1 /* $NetBSD: elinkxlreg.h,v 1.11 2002/11/09 11:45:19 enami Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file defines the registers specific to the EtherLink XL family 41 * of NICs. 42 */ 43 44 #define EEPROM_SOFTINFO3 0x15 /* Software info #3 */ 45 #define EEPROM_SUBVENDOR_ELXL 0x17 /* Subsys vendor id */ 46 #define EEPROM_SUBSYSID 0x18 /* Subsys id */ 47 #define EEPROM_MEDIA 0x19 /* Media options (90xB) */ 48 #define EEPROM_CHECKSUM_ELXL 0x20 /* EEPROM checksum */ 49 50 #define READ_EEPROM8 0x0200 /* 8 bit EEPROM read command */ 51 52 /* 53 * Flat address space registers (outside the windows) 54 */ 55 56 #define ELINK_TXPKTID 0x18 /* 90xB only */ 57 #define ELINK_TIMER 0x1a 58 #define ELINK_TXSTATUS 0x1b 59 #define ELINK_INTSTATUSAUTO 0x1e 60 #define ELINK_DMACTRL 0x20 61 # define ELINK_DMAC_DNCMPLREQ 0x00000002 62 # define ELINK_DMAC_DNSTALLED 0x00000004 63 # define ELINK_DMAC_UPCOMPLETE 0x00000008 64 # define ELINK_DMAC_DNCOMPLETE 0x00000010 65 # define ELINK_DMAC_UPRXEAREN 0x00000020 66 # define ELINK_DMAC_ARNCNTDN 0x00000040 67 # define ELINK_DMAC_DNINPROG 0x00000080 68 # define ELINK_DMAC_CNTSPEED 0x00000100 69 # define ELINK_DMAC_CNTDNMODE 0x00000200 70 # define ELINK_DMAC_ALTSEQDIS 0x00010000 71 # define ELINK_DMAC_DEFEATMWI 0x00100000 72 # define ELINK_DMAC_DEFEATMRL 0x00200000 73 # define ELINK_DMAC_UPOVERDIS 0x00400000 74 # define ELINK_DMAC_TARGABORT 0x40000000 75 # define ELINK_DMAC_MSTRABORT 0x80000000 76 #define ELINK_DNLISTPTR 0x24 77 #define ELINK_DNBURSTTHRESH 0x2a /* 90xB only */ 78 #define ELINK_DNPRIOTHRESH 0x2c /* 90xB only */ 79 #define ELINK_DNPOLL 0x2d /* 90xB only */ 80 #define ELINK_TXFREETHRESH 0x2f /* 90x only */ 81 #define ELINK_UPPKTSTATUS 0x30 82 #define ELINK_FREETIMER 0x34 83 #define ELINK_COUNTDOWN 0x36 84 #define ELINK_UPLISTPTR 0x38 85 #define ELINK_UPPRIOTHRESH 0x3c /* 90xB only */ 86 #define ELINK_UPPOLL 0x3d /* 90xB only */ 87 #define ELINK_UPBURSTTHRESH 0x3e /* 90xB only */ 88 #define ELINK_REALTIMECNT 0x40 /* 90xB only */ 89 #define ELINK_DNMAXBURST 0x78 /* 90xB only */ 90 #define ELINK_UPMAXBURST 0x7a /* 90xB only */ 91 92 /* 93 * This is reset options for the other cards, media options for 94 * the 90xB NICs. Reset options are in a separate register for 95 * the 90xB. 96 */ 97 #define ELINK_W3_MEDIA_OPTIONS 0x08 98 # define ELINK_MEDIACAP_100BASET4 0x0001 99 # define ELINK_MEDIACAP_100BASETX 0x0002 100 # define ELINK_MEDIACAP_100BASEFX 0x0004 101 # define ELINK_MEDIACAP_10BASET 0x0008 102 # define ELINK_MEDIACAP_10BASE2 0x0010 103 # define ELINK_MEDIACAP_10BASE5 0x0020 104 # define ELINK_MEDIACAP_MII 0x0040 105 # define ELINK_MEDIACAP_10BASEFL 0x0080 106 107 /* 108 * Reset options for the 90xB 109 */ 110 #define ELINK_W2_RESET_OPTIONS 0x0c 111 # define ELINK_RESET_OPT_LEDPOLAR 0x0010 112 # define ELINK_RESET_OPT_PHYPOWER 0x4000 113 114 /* 115 * Window 4, offset 8 is defined for MII/PHY access for EtherLink XL 116 * cards. 117 */ 118 #define ELINK_W4_PHYSMGMT 0x08 119 # define ELINK_PHY_CLK 0x0001 120 # define ELINK_PHY_DATA 0x0002 121 # define ELINK_PHY_DIR 0x0004 122 123 /* 124 * Counter in window 4 for packets with a bad start-of-stream delimiter/ 125 */ 126 #define ELINK_W4_BADSSD 0x0c 127 #define ELINK_W4_UBYTESOK 0x0d 128 129 /* 130 * Define for extra multicast hash filter bit implemented in the 90xB 131 */ 132 #define FIL_MULTIHASH 0x10 133 134 /* 135 * Defines for the interrupt status register, only for the 90x[B] 136 */ 137 #define HOST_ERROR 0x0002 138 #define LINK_EVENT 0x0100 139 #define DN_COMPLETE 0x0200 140 #define UP_COMPLETE 0x0400 141 142 #define XL_WATCHED_INTERRUPTS \ 143 (HOST_ERROR | TX_COMPLETE | UPD_STATS | DN_COMPLETE | UP_COMPLETE) 144 145 146 /* 147 * Window 7 registers. These are different for 90x and 90xB than 148 * for the EtherLink III / Fast EtherLink cards. 149 */ 150 151 #define ELINK_W7_VLANMASK 0x00 /* 90xB only */ 152 #define ELINK_W7_VLANTYPE 0x04 /* 90xB only */ 153 #define ELINK_W7_TIMER 0x0a /* 90x only */ 154 #define ELINK_W7_TX_STATUS 0x0b /* 90x only */ 155 #define ELINK_W7_POWEREVENT 0x0c /* 90xB only */ 156 #define ELINK_W7_INTSTATUS 0x0e 157 158 /* 159 * Command definitions. 160 */ 161 #define ELINK_UPSTALL 0x3000 162 #define ELINK_UPUNSTALL 0x3001 163 #define ELINK_DNSTALL 0x3002 164 #define ELINK_DNUNSTALL 0x3003 165 #define ELINK_TXRECLTHRESH 0xc000 166 #define ELINK_TXSTARTTHRESH 0x9800 167 #define ELINK_CLEARHASHFILBIT 0xc800 168 #define ELINK_SETHASHFILBIT 0xcc00 169 170 /* 171 * The Internal Config register is different on 90xB cards. The 172 * different masks / shifts are defined here. 173 */ 174 175 /* 176 * Lower 16 bits. 177 */ 178 #define CONFIG_TXLARGE (u_int16_t) 0x4000 179 #define CONFIG_TXLARGE_SHIFT 14 180 181 #define CONFIG_RXLARGE (u_int16_t) 0x8000 182 #define CONFIG_RXLARGE_SHIFT 15 183 184 /* 185 * Upper 16 bits. 186 */ 187 #define CONFIG_XCVR_SEL (u_int16_t) 0x00f0 188 #define CONFIG_XCVR_SEL_SHIFT 4 189 190 #define ELINKMEDIA_AUTO 8 191 192 #define CONFIG_AUTOSEL (u_int16_t) 0x0100 193 #define CONFIG_AUTOSEL_SHIFT 8 194 195 #define CONFIG_DISABLEROM (u_int16_t) 0x0200 196 #define CONFIG_DISABLEROM_SHIFT 9 197 198 /* 199 * ID of internal PHY. 200 */ 201 202 #define ELINK_INTPHY_ID 24 203 204 /* 205 * Fragment header as laid out in memory for DMA access. 206 */ 207 208 struct ex_fraghdr { 209 volatile u_int32_t fr_addr; /* phys addr of frag */ 210 volatile u_int32_t fr_len; /* length of frag */ 211 }; 212 213 #define EX_FR_LENMASK 0x00001fff /* mask for length in fr_len field */ 214 #define EX_FR_LAST 0x80000000 /* indicates last fragment */ 215 216 #define EX_NDPD 256 217 #define EX_NUPD 128 218 219 /* 220 * Note: the number of receive fragments in an UPD is 1, since we're 221 * receiving into one contiguous mbuf. 222 */ 223 #define EX_NRFRAGS 1 /* # fragments in rcv pkt (< 64) */ 224 #define EX_NTFRAGS 32 /* # fragments in tx pkt (< 64) */ 225 226 /* 227 * Type 0 Download Packet Descriptor (DPD). 228 */ 229 struct ex_dpd { 230 volatile u_int32_t dpd_nextptr; /* prt to next fragheader */ 231 volatile u_int32_t dpd_fsh; /* frame start header */ 232 volatile struct ex_fraghdr dpd_frags[EX_NTFRAGS]; 233 }; 234 235 /* 236 * Type 1 DPD, supported by 90xB. 237 */ 238 struct ex_dpd1 { 239 volatile u_int32_t dpd_nextptr; 240 volatile u_int32_t dpd_schedtime; /* time to download */ 241 volatile u_int32_t dpd_fsh; 242 volatile struct ex_fraghdr dpd_frags[EX_NTFRAGS]; 243 }; 244 245 struct ex_upd { 246 volatile u_int32_t upd_nextptr; 247 volatile u_int32_t upd_pktstatus; 248 volatile struct ex_fraghdr upd_frags[EX_NRFRAGS]; 249 }; 250 251 /* 252 * Higher level linked list of upload packet descriptors. 253 */ 254 struct ex_rxdesc { 255 struct ex_rxdesc *rx_next; 256 struct mbuf *rx_mbhead; 257 bus_dmamap_t rx_dmamap; 258 struct ex_upd *rx_upd; 259 }; 260 261 /* 262 * .. and for download packet descriptors. 263 */ 264 struct ex_txdesc { 265 struct ex_txdesc *tx_next; 266 struct mbuf *tx_mbhead; 267 bus_dmamap_t tx_dmamap; 268 struct ex_dpd *tx_dpd; 269 }; 270 271 #define DPD_DMADDR(s,t) \ 272 ((s)->sc_dpddma + ((caddr_t)((t)->tx_dpd) - (caddr_t)((s)->sc_dpd))) 273 274 /* 275 * Frame Start Header bitfields. 276 */ 277 278 #define EX_DPD_DNIND 0x80000000 /* intr on download done */ 279 #define EX_DPD_TXIND 0x00008000 /* intr on tx done */ 280 #define EX_DPD_NOCRC 0x00002000 /* no CRC append */ 281 282 /* 283 * Lower 12 bits are the tx length for the 90x family. The 90xB 284 * assumes that the tx length is the sum of all frame lengths, 285 * and uses the bits as below. It also defines some more bits in 286 * the upper part. 287 */ 288 #define EX_DPD_EMPTY 0x20000000 /* no data in this DPD */ 289 #define EX_DPD_UPDEFEAT 0x10000000 /* don't round tx lengths up */ 290 #define EX_DPD_UDPCKSUM 0x08000000 /* do hardware UDP checksum */ 291 #define EX_DPD_TCPCKSUM 0x04000000 /* do hardware TCP checksum */ 292 #define EX_DPD_IPCKSUM 0x02000000 /* do hardware IP checksum */ 293 #define EX_DPD_DNCMPLT 0x01000000 /* packet has been downloaded */ 294 #define EX_DPD_IDMASK 0x000003fc /* mask for packet id */ 295 # define EX_DPD_IDSHIFT 2 296 #define EX_DPD_RNDMASK 0x00000003 /* mask for rounding */ 297 /* 0 -> dword, 2 -> word, 1,3 -> none */ 298 299 /* 300 * Schedtime bitfields. 301 */ 302 #define EX_SCHED_TIMEVALID 0x20000000 /* field contains value */ 303 #define EX_SCHED_LDCOUNT 0x10000000 /* load schedtime onto NIC */ 304 #define EX_SCHED_TIMEMASK 0x00ffffff 305 306 /* 307 * upd_pktstatus bitfields. 308 * The *CKSUMERR fields are only valid if the matching *CHECKED field 309 * is set. 310 */ 311 #define EX_UPD_PKTLENMASK 0x00001fff /* 12:0 -> packet length */ 312 #define EX_UPD_ERROR 0x00004000 /* rcv error */ 313 #define EX_UPD_COMPLETE 0x00008000 /* rcv complete */ 314 #define EX_UPD_OVERRUN 0x00010000 /* rcv overrun */ 315 #define EX_UPD_RUNT 0x00020000 /* pkt < 60 bytes */ 316 #define EX_UPD_ALIGNERR 0x00040000 /* alignment error */ 317 #define EX_UPD_CRCERR 0x00080000 /* CRC error */ 318 #define EX_UPD_OVERSIZED 0x00100000 /* oversize frame */ 319 #define EX_UPD_DRIBBLEBITS 0x00800000 /* pkt had dribble bits */ 320 #define EX_UPD_OVERFLOW 0x01000000 /* insufficient space for pkt */ 321 #define EX_UPD_IPCKSUMERR 0x02000000 /* IP cksum error (90xB) */ 322 #define EX_UPD_TCPCKSUMERR 0x04000000 /* TCP cksum error (90xB) */ 323 #define EX_UPD_UDPCKSUMERR 0x08000000 /* UDP cksum error (90xB) */ 324 #define EX_UPD_IPCHECKED 0x20000000 /* IP cksum done */ 325 #define EX_UPD_TCPCHECKED 0x40000000 /* TCP cksum done */ 326 #define EX_UPD_UDPCHECKED 0x80000000 /* UDP cksum done */ 327 328 #define EX_UPD_ERR 0x001f4000 /* Errors we check for */ 329 #define EX_UPD_ERR_VLAN 0x000f0000 /* same for 802.1q */ 330