1 /* $NetBSD: gemvar.h,v 1.9 2002/05/15 21:05:23 matt Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 #ifndef _IF_GEMVAR_H 33 #define _IF_GEMVAR_H 34 35 36 #include "rnd.h" 37 38 #include <sys/queue.h> 39 #include <sys/callout.h> 40 41 #if NRND > 0 42 #include <sys/rnd.h> 43 #endif 44 45 /* 46 * Misc. definitions for the Sun ``Gem'' Ethernet controller family driver. 47 */ 48 49 /* 50 * Transmit descriptor list size. This is arbitrary, but allocate 51 * enough descriptors for 64 pending transmissions and 16 segments 52 * per packet. 53 */ 54 #define GEM_NTXSEGS 16 55 56 #define GEM_TXQUEUELEN 64 57 #define GEM_NTXDESC (GEM_TXQUEUELEN * GEM_NTXSEGS) 58 #define GEM_NTXDESC_MASK (GEM_NTXDESC - 1) 59 #define GEM_NEXTTX(x) ((x + 1) & GEM_NTXDESC_MASK) 60 61 /* 62 * Receive descriptor list size. We have one Rx buffer per incoming 63 * packet, so this logic is a little simpler. 64 */ 65 #define GEM_NRXDESC 128 66 #define GEM_NRXDESC_MASK (GEM_NRXDESC - 1) 67 #define GEM_PREVRX(x) ((x - 1) & GEM_NRXDESC_MASK) 68 #define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK) 69 70 /* 71 * Control structures are DMA'd to the GEM chip. We allocate them in 72 * a single clump that maps to a single DMA segment to make several things 73 * easier. 74 */ 75 struct gem_control_data { 76 /* 77 * The transmit descriptors. 78 */ 79 struct gem_desc gcd_txdescs[GEM_NTXDESC]; 80 81 /* 82 * The receive descriptors. 83 */ 84 struct gem_desc gcd_rxdescs[GEM_NRXDESC]; 85 }; 86 87 #define GEM_CDOFF(x) offsetof(struct gem_control_data, x) 88 #define GEM_CDTXOFF(x) GEM_CDOFF(gcd_txdescs[(x)]) 89 #define GEM_CDRXOFF(x) GEM_CDOFF(gcd_rxdescs[(x)]) 90 91 /* 92 * Software state for transmit jobs. 93 */ 94 struct gem_txsoft { 95 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 96 bus_dmamap_t txs_dmamap; /* our DMA map */ 97 int txs_firstdesc; /* first descriptor in packet */ 98 int txs_lastdesc; /* last descriptor in packet */ 99 int txs_ndescs; /* number of descriptors */ 100 SIMPLEQ_ENTRY(gem_txsoft) txs_q; 101 }; 102 103 SIMPLEQ_HEAD(gem_txsq, gem_txsoft); 104 105 /* 106 * Software state for receive jobs. 107 */ 108 struct gem_rxsoft { 109 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 110 bus_dmamap_t rxs_dmamap; /* our DMA map */ 111 }; 112 113 /* 114 * Software state per device. 115 */ 116 struct gem_softc { 117 struct device sc_dev; /* generic device information */ 118 struct ethercom sc_ethercom; /* ethernet common data */ 119 struct mii_data sc_mii; /* MII media control */ 120 #define sc_media sc_mii.mii_media/* shorthand */ 121 struct callout sc_tick_ch; /* tick callout */ 122 123 /* The following bus handles are to be provided by the bus front-end */ 124 bus_space_tag_t sc_bustag; /* bus tag */ 125 bus_dma_tag_t sc_dmatag; /* bus dma tag */ 126 bus_dmamap_t sc_dmamap; /* bus dma handle */ 127 bus_space_handle_t sc_h; /* bus space handle for all regs */ 128 129 int sc_phys[2]; /* MII instance -> PHY map */ 130 131 int sc_mif_config; /* Selected MII reg setting */ 132 133 int sc_pci; /* XXXXX -- PCI buses are LE. */ 134 u_int sc_variant; /* which GEM are we dealing with? */ 135 #define GEM_UNKNOWN 0 /* don't know */ 136 #define GEM_SUN_GEM 1 /* Sun GEM variant */ 137 #define GEM_APPLE_GMAC 2 /* Apple GMAC variant */ 138 139 u_int sc_flags; /* */ 140 #define GEM_GIGABIT 0x0001 /* has a gigabit PHY */ 141 142 void *sc_sdhook; /* shutdown hook */ 143 void *sc_powerhook; /* power management hook */ 144 145 /* 146 * Ring buffer DMA stuff. 147 */ 148 bus_dma_segment_t sc_cdseg; /* control data memory */ 149 int sc_cdnseg; /* number of segments */ 150 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 151 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 152 153 /* 154 * Software state for transmit and receive descriptors. 155 */ 156 struct gem_txsoft sc_txsoft[GEM_TXQUEUELEN]; 157 struct gem_rxsoft sc_rxsoft[GEM_NRXDESC]; 158 159 /* 160 * Control data structures. 161 */ 162 struct gem_control_data *sc_control_data; 163 #define sc_txdescs sc_control_data->gcd_txdescs 164 #define sc_rxdescs sc_control_data->gcd_rxdescs 165 166 int sc_txfree; /* number of free Tx descriptors */ 167 int sc_txnext; /* next ready Tx descriptor */ 168 int sc_txwin; /* Tx descriptors since last Tx int */ 169 170 struct gem_txsq sc_txfreeq; /* free Tx descsofts */ 171 struct gem_txsq sc_txdirtyq; /* dirty Tx descsofts */ 172 173 int sc_rxptr; /* next ready RX descriptor/descsoft */ 174 int sc_rxfifosize; /* Rx FIFO size (bytes) */ 175 176 /* ========== */ 177 int sc_inited; 178 int sc_debug; 179 void *sc_sh; /* shutdownhook cookie */ 180 181 /* Special hardware hooks */ 182 void (*sc_hwreset) __P((struct gem_softc *)); 183 void (*sc_hwinit) __P((struct gem_softc *)); 184 185 #if NRND > 0 186 rndsource_element_t rnd_source; 187 #endif 188 189 struct evcnt sc_ev_intr; 190 #ifdef GEM_COUNTERS 191 struct evcnt sc_ev_txint; 192 struct evcnt sc_ev_rxint; 193 struct evcnt sc_ev_rxnobuf; 194 struct evcnt sc_ev_rxfull; 195 struct evcnt sc_ev_rxhist[9]; 196 #endif 197 }; 198 199 #ifdef GEM_COUNTERS 200 #define GEM_COUNTER_INCR(sc, ctr) ((void) (sc->ctr.ev_count++)) 201 #else 202 #define GEM_COUNTER_INCR(sc, ctr) ((void) sc) 203 #endif 204 205 206 #define GEM_DMA_READ(sc, v) (((sc)->sc_pci) ? le64toh(v) : be64toh(v)) 207 #define GEM_DMA_WRITE(sc, v) (((sc)->sc_pci) ? htole64(v) : htobe64(v)) 208 209 #define GEM_CDTXADDR(sc, x) ((sc)->sc_cddma + GEM_CDTXOFF((x))) 210 #define GEM_CDRXADDR(sc, x) ((sc)->sc_cddma + GEM_CDRXOFF((x))) 211 212 #define GEM_CDSPADDR(sc) ((sc)->sc_cddma + GEM_CDSPOFF) 213 214 #define GEM_CDTXSYNC(sc, x, n, ops) \ 215 do { \ 216 int __x, __n; \ 217 \ 218 __x = (x); \ 219 __n = (n); \ 220 \ 221 /* If it will wrap around, sync to the end of the ring. */ \ 222 if ((__x + __n) > GEM_NTXDESC) { \ 223 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 224 GEM_CDTXOFF(__x), sizeof(struct gem_desc) * \ 225 (GEM_NTXDESC - __x), (ops)); \ 226 __n -= (GEM_NTXDESC - __x); \ 227 __x = 0; \ 228 } \ 229 \ 230 /* Now sync whatever is left. */ \ 231 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 232 GEM_CDTXOFF(__x), sizeof(struct gem_desc) * __n, (ops)); \ 233 } while (0) 234 235 #define GEM_CDRXSYNC(sc, x, ops) \ 236 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 237 GEM_CDRXOFF((x)), sizeof(struct gem_desc), (ops)) 238 239 #define GEM_CDSPSYNC(sc, ops) \ 240 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 241 GEM_CDSPOFF, GEM_SETUP_PACKET_LEN, (ops)) 242 243 #define GEM_INIT_RXDESC(sc, x) \ 244 do { \ 245 struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \ 246 struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \ 247 struct mbuf *__m = __rxs->rxs_mbuf; \ 248 \ 249 __m->m_data = __m->m_ext.ext_buf; \ 250 __rxd->gd_addr = \ 251 GEM_DMA_WRITE((sc), __rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 252 __rxd->gd_flags = \ 253 GEM_DMA_WRITE((sc), \ 254 (((__m->m_ext.ext_size)<<GEM_RD_BUFSHIFT) \ 255 & GEM_RD_BUFSIZE) | GEM_RD_OWN); \ 256 GEM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 257 } while (0) 258 259 #ifdef _KERNEL 260 void gem_attach __P((struct gem_softc *, const uint8_t *)); 261 int gem_intr __P((void *)); 262 263 void gem_reset __P((struct gem_softc *)); 264 #endif /* _KERNEL */ 265 266 267 #endif 268