1 /* $NetBSD: hme.c,v 1.29 2002/05/05 03:02:38 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * HME Ethernet module driver. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: hme.c,v 1.29 2002/05/05 03:02:38 thorpej Exp $"); 45 46 #define HMEDEBUG 47 48 #include "opt_inet.h" 49 #include "opt_ns.h" 50 #include "bpfilter.h" 51 #include "rnd.h" 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/kernel.h> 56 #include <sys/mbuf.h> 57 #include <sys/syslog.h> 58 #include <sys/socket.h> 59 #include <sys/device.h> 60 #include <sys/malloc.h> 61 #include <sys/ioctl.h> 62 #include <sys/errno.h> 63 #if NRND > 0 64 #include <sys/rnd.h> 65 #endif 66 67 #include <net/if.h> 68 #include <net/if_dl.h> 69 #include <net/if_ether.h> 70 #include <net/if_media.h> 71 72 #ifdef INET 73 #include <netinet/in.h> 74 #include <netinet/if_inarp.h> 75 #include <netinet/in_systm.h> 76 #include <netinet/in_var.h> 77 #include <netinet/ip.h> 78 #endif 79 80 #ifdef NS 81 #include <netns/ns.h> 82 #include <netns/ns_if.h> 83 #endif 84 85 #if NBPFILTER > 0 86 #include <net/bpf.h> 87 #include <net/bpfdesc.h> 88 #endif 89 90 #include <dev/mii/mii.h> 91 #include <dev/mii/miivar.h> 92 93 #include <machine/bus.h> 94 95 #include <dev/ic/hmereg.h> 96 #include <dev/ic/hmevar.h> 97 98 void hme_start __P((struct ifnet *)); 99 void hme_stop __P((struct hme_softc *)); 100 int hme_ioctl __P((struct ifnet *, u_long, caddr_t)); 101 void hme_tick __P((void *)); 102 void hme_watchdog __P((struct ifnet *)); 103 void hme_shutdown __P((void *)); 104 void hme_init __P((struct hme_softc *)); 105 void hme_meminit __P((struct hme_softc *)); 106 void hme_mifinit __P((struct hme_softc *)); 107 void hme_reset __P((struct hme_softc *)); 108 void hme_setladrf __P((struct hme_softc *)); 109 110 /* MII methods & callbacks */ 111 static int hme_mii_readreg __P((struct device *, int, int)); 112 static void hme_mii_writereg __P((struct device *, int, int, int)); 113 static void hme_mii_statchg __P((struct device *)); 114 115 int hme_mediachange __P((struct ifnet *)); 116 void hme_mediastatus __P((struct ifnet *, struct ifmediareq *)); 117 118 struct mbuf *hme_get __P((struct hme_softc *, int, int)); 119 int hme_put __P((struct hme_softc *, int, struct mbuf *)); 120 void hme_read __P((struct hme_softc *, int, int)); 121 int hme_eint __P((struct hme_softc *, u_int)); 122 int hme_rint __P((struct hme_softc *)); 123 int hme_tint __P((struct hme_softc *)); 124 125 static int ether_cmp __P((u_char *, u_char *)); 126 127 /* Default buffer copy routines */ 128 void hme_copytobuf_contig __P((struct hme_softc *, void *, int, int)); 129 void hme_copyfrombuf_contig __P((struct hme_softc *, void *, int, int)); 130 void hme_zerobuf_contig __P((struct hme_softc *, int, int)); 131 132 133 void 134 hme_config(sc) 135 struct hme_softc *sc; 136 { 137 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 138 struct mii_data *mii = &sc->sc_mii; 139 struct mii_softc *child; 140 bus_dma_tag_t dmatag = sc->sc_dmatag; 141 bus_dma_segment_t seg; 142 bus_size_t size; 143 int rseg, error; 144 145 /* 146 * HME common initialization. 147 * 148 * hme_softc fields that must be initialized by the front-end: 149 * 150 * the bus tag: 151 * sc_bustag 152 * 153 * the dma bus tag: 154 * sc_dmatag 155 * 156 * the bus handles: 157 * sc_seb (Shared Ethernet Block registers) 158 * sc_erx (Receiver Unit registers) 159 * sc_etx (Transmitter Unit registers) 160 * sc_mac (MAC registers) 161 * sc_mif (Managment Interface registers) 162 * 163 * the maximum bus burst size: 164 * sc_burst 165 * 166 * (notyet:DMA capable memory for the ring descriptors & packet buffers: 167 * rb_membase, rb_dmabase) 168 * 169 * the local Ethernet address: 170 * sc_enaddr 171 * 172 */ 173 174 /* Make sure the chip is stopped. */ 175 hme_stop(sc); 176 177 178 /* 179 * Allocate descriptors and buffers 180 * XXX - do all this differently.. and more configurably, 181 * eg. use things as `dma_load_mbuf()' on transmit, 182 * and a pool of `EXTMEM' mbufs (with buffers DMA-mapped 183 * all the time) on the reveiver side. 184 * 185 * Note: receive buffers must be 64-byte aligned. 186 * Also, apparently, the buffers must extend to a DMA burst 187 * boundary beyond the maximum packet size. 188 */ 189 #define _HME_NDESC 128 190 #define _HME_BUFSZ 1600 191 192 /* Note: the # of descriptors must be a multiple of 16 */ 193 sc->sc_rb.rb_ntbuf = _HME_NDESC; 194 sc->sc_rb.rb_nrbuf = _HME_NDESC; 195 196 /* 197 * Allocate DMA capable memory 198 * Buffer descriptors must be aligned on a 2048 byte boundary; 199 * take this into account when calculating the size. Note that 200 * the maximum number of descriptors (256) occupies 2048 bytes, 201 * so we allocate that much regardless of _HME_NDESC. 202 */ 203 size = 2048 + /* TX descriptors */ 204 2048 + /* RX descriptors */ 205 sc->sc_rb.rb_ntbuf * _HME_BUFSZ + /* TX buffers */ 206 sc->sc_rb.rb_nrbuf * _HME_BUFSZ; /* TX buffers */ 207 208 /* Allocate DMA buffer */ 209 if ((error = bus_dmamem_alloc(dmatag, size, 210 2048, 0, 211 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 212 printf("%s: DMA buffer alloc error %d\n", 213 sc->sc_dev.dv_xname, error); 214 return; 215 } 216 217 /* Map DMA memory in CPU addressable space */ 218 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 219 &sc->sc_rb.rb_membase, 220 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 221 printf("%s: DMA buffer map error %d\n", 222 sc->sc_dev.dv_xname, error); 223 bus_dmamap_unload(dmatag, sc->sc_dmamap); 224 bus_dmamem_free(dmatag, &seg, rseg); 225 return; 226 } 227 228 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 229 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 230 printf("%s: DMA map create error %d\n", 231 sc->sc_dev.dv_xname, error); 232 return; 233 } 234 235 /* Load the buffer */ 236 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 237 sc->sc_rb.rb_membase, size, NULL, 238 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 239 printf("%s: DMA buffer map load error %d\n", 240 sc->sc_dev.dv_xname, error); 241 bus_dmamem_free(dmatag, &seg, rseg); 242 return; 243 } 244 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 245 246 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 247 ether_sprintf(sc->sc_enaddr)); 248 249 /* Initialize ifnet structure. */ 250 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 251 ifp->if_softc = sc; 252 ifp->if_start = hme_start; 253 ifp->if_ioctl = hme_ioctl; 254 ifp->if_watchdog = hme_watchdog; 255 ifp->if_flags = 256 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 257 IFQ_SET_READY(&ifp->if_snd); 258 259 /* Initialize ifmedia structures and MII info */ 260 mii->mii_ifp = ifp; 261 mii->mii_readreg = hme_mii_readreg; 262 mii->mii_writereg = hme_mii_writereg; 263 mii->mii_statchg = hme_mii_statchg; 264 265 ifmedia_init(&mii->mii_media, 0, hme_mediachange, hme_mediastatus); 266 267 hme_mifinit(sc); 268 269 mii_attach(&sc->sc_dev, mii, 0xffffffff, 270 MII_PHY_ANY, MII_OFFSET_ANY, 0); 271 272 child = LIST_FIRST(&mii->mii_phys); 273 if (child == NULL) { 274 /* No PHY attached */ 275 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 276 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 277 } else { 278 /* 279 * Walk along the list of attached MII devices and 280 * establish an `MII instance' to `phy number' 281 * mapping. We'll use this mapping in media change 282 * requests to determine which phy to use to program 283 * the MIF configuration register. 284 */ 285 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 286 /* 287 * Note: we support just two PHYs: the built-in 288 * internal device and an external on the MII 289 * connector. 290 */ 291 if (child->mii_phy > 1 || child->mii_inst > 1) { 292 printf("%s: cannot accomodate MII device %s" 293 " at phy %d, instance %d\n", 294 sc->sc_dev.dv_xname, 295 child->mii_dev.dv_xname, 296 child->mii_phy, child->mii_inst); 297 continue; 298 } 299 300 sc->sc_phys[child->mii_inst] = child->mii_phy; 301 } 302 303 /* 304 * XXX - we can really do the following ONLY if the 305 * phy indeed has the auto negotiation capability!! 306 */ 307 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 308 } 309 310 /* claim 802.1q capability */ 311 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 312 313 /* Attach the interface. */ 314 if_attach(ifp); 315 ether_ifattach(ifp, sc->sc_enaddr); 316 317 sc->sc_sh = shutdownhook_establish(hme_shutdown, sc); 318 if (sc->sc_sh == NULL) 319 panic("hme_config: can't establish shutdownhook"); 320 321 #if 0 322 printf("%s: %d receive buffers, %d transmit buffers\n", 323 sc->sc_dev.dv_xname, sc->sc_nrbuf, sc->sc_ntbuf); 324 sc->sc_rbufaddr = malloc(sc->sc_nrbuf * sizeof(int), M_DEVBUF, 325 M_WAITOK); 326 sc->sc_tbufaddr = malloc(sc->sc_ntbuf * sizeof(int), M_DEVBUF, 327 M_WAITOK); 328 #endif 329 330 #if NRND > 0 331 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 332 RND_TYPE_NET, 0); 333 #endif 334 335 callout_init(&sc->sc_tick_ch); 336 } 337 338 void 339 hme_tick(arg) 340 void *arg; 341 { 342 struct hme_softc *sc = arg; 343 int s; 344 345 s = splnet(); 346 mii_tick(&sc->sc_mii); 347 splx(s); 348 349 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 350 } 351 352 void 353 hme_reset(sc) 354 struct hme_softc *sc; 355 { 356 int s; 357 358 s = splnet(); 359 hme_init(sc); 360 splx(s); 361 } 362 363 void 364 hme_stop(sc) 365 struct hme_softc *sc; 366 { 367 bus_space_tag_t t = sc->sc_bustag; 368 bus_space_handle_t seb = sc->sc_seb; 369 int n; 370 371 callout_stop(&sc->sc_tick_ch); 372 mii_down(&sc->sc_mii); 373 374 /* Reset transmitter and receiver */ 375 bus_space_write_4(t, seb, HME_SEBI_RESET, 376 (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)); 377 378 for (n = 0; n < 20; n++) { 379 u_int32_t v = bus_space_read_4(t, seb, HME_SEBI_RESET); 380 if ((v & (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)) == 0) 381 return; 382 DELAY(20); 383 } 384 385 printf("%s: hme_stop: reset failed\n", sc->sc_dev.dv_xname); 386 } 387 388 void 389 hme_meminit(sc) 390 struct hme_softc *sc; 391 { 392 bus_addr_t txbufdma, rxbufdma; 393 bus_addr_t dma; 394 caddr_t p; 395 unsigned int ntbuf, nrbuf, i; 396 struct hme_ring *hr = &sc->sc_rb; 397 398 p = hr->rb_membase; 399 dma = hr->rb_dmabase; 400 401 ntbuf = hr->rb_ntbuf; 402 nrbuf = hr->rb_nrbuf; 403 404 /* 405 * Allocate transmit descriptors 406 */ 407 hr->rb_txd = p; 408 hr->rb_txddma = dma; 409 p += ntbuf * HME_XD_SIZE; 410 dma += ntbuf * HME_XD_SIZE; 411 /* We have reserved descriptor space until the next 2048 byte boundary.*/ 412 dma = (bus_addr_t)roundup((u_long)dma, 2048); 413 p = (caddr_t)roundup((u_long)p, 2048); 414 415 /* 416 * Allocate receive descriptors 417 */ 418 hr->rb_rxd = p; 419 hr->rb_rxddma = dma; 420 p += nrbuf * HME_XD_SIZE; 421 dma += nrbuf * HME_XD_SIZE; 422 /* Again move forward to the next 2048 byte boundary.*/ 423 dma = (bus_addr_t)roundup((u_long)dma, 2048); 424 p = (caddr_t)roundup((u_long)p, 2048); 425 426 427 /* 428 * Allocate transmit buffers 429 */ 430 hr->rb_txbuf = p; 431 txbufdma = dma; 432 p += ntbuf * _HME_BUFSZ; 433 dma += ntbuf * _HME_BUFSZ; 434 435 /* 436 * Allocate receive buffers 437 */ 438 hr->rb_rxbuf = p; 439 rxbufdma = dma; 440 p += nrbuf * _HME_BUFSZ; 441 dma += nrbuf * _HME_BUFSZ; 442 443 /* 444 * Initialize transmit buffer descriptors 445 */ 446 for (i = 0; i < ntbuf; i++) { 447 HME_XD_SETADDR(sc->sc_pci, hr->rb_txd, i, txbufdma + i * _HME_BUFSZ); 448 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, i, 0); 449 } 450 451 /* 452 * Initialize receive buffer descriptors 453 */ 454 for (i = 0; i < nrbuf; i++) { 455 HME_XD_SETADDR(sc->sc_pci, hr->rb_rxd, i, rxbufdma + i * _HME_BUFSZ); 456 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_rxd, i, 457 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 458 } 459 460 hr->rb_tdhead = hr->rb_tdtail = 0; 461 hr->rb_td_nbusy = 0; 462 hr->rb_rdtail = 0; 463 } 464 465 /* 466 * Initialization of interface; set up initialization block 467 * and transmit/receive descriptor rings. 468 */ 469 void 470 hme_init(sc) 471 struct hme_softc *sc; 472 { 473 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 474 bus_space_tag_t t = sc->sc_bustag; 475 bus_space_handle_t seb = sc->sc_seb; 476 bus_space_handle_t etx = sc->sc_etx; 477 bus_space_handle_t erx = sc->sc_erx; 478 bus_space_handle_t mac = sc->sc_mac; 479 bus_space_handle_t mif = sc->sc_mif; 480 u_int8_t *ea; 481 u_int32_t v; 482 483 /* 484 * Initialization sequence. The numbered steps below correspond 485 * to the sequence outlined in section 6.3.5.1 in the Ethernet 486 * Channel Engine manual (part of the PCIO manual). 487 * See also the STP2002-STQ document from Sun Microsystems. 488 */ 489 490 /* step 1 & 2. Reset the Ethernet Channel */ 491 hme_stop(sc); 492 493 /* Re-initialize the MIF */ 494 hme_mifinit(sc); 495 496 /* Call MI reset function if any */ 497 if (sc->sc_hwreset) 498 (*sc->sc_hwreset)(sc); 499 500 #if 0 501 /* Mask all MIF interrupts, just in case */ 502 bus_space_write_4(t, mif, HME_MIFI_IMASK, 0xffff); 503 #endif 504 505 /* step 3. Setup data structures in host memory */ 506 hme_meminit(sc); 507 508 /* step 4. TX MAC registers & counters */ 509 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 510 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 511 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 512 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 513 bus_space_write_4(t, mac, HME_MACI_TXSIZE, 514 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 515 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : 516 ETHER_MAX_LEN); 517 518 /* Load station MAC address */ 519 ea = sc->sc_enaddr; 520 bus_space_write_4(t, mac, HME_MACI_MACADDR0, (ea[0] << 8) | ea[1]); 521 bus_space_write_4(t, mac, HME_MACI_MACADDR1, (ea[2] << 8) | ea[3]); 522 bus_space_write_4(t, mac, HME_MACI_MACADDR2, (ea[4] << 8) | ea[5]); 523 524 /* 525 * Init seed for backoff 526 * (source suggested by manual: low 10 bits of MAC address) 527 */ 528 v = ((ea[4] << 8) | ea[5]) & 0x3fff; 529 bus_space_write_4(t, mac, HME_MACI_RANDSEED, v); 530 531 532 /* Note: Accepting power-on default for other MAC registers here.. */ 533 534 535 /* step 5. RX MAC registers & counters */ 536 hme_setladrf(sc); 537 538 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 539 bus_space_write_4(t, etx, HME_ETXI_RING, sc->sc_rb.rb_txddma); 540 bus_space_write_4(t, etx, HME_ETXI_RSIZE, sc->sc_rb.rb_ntbuf); 541 542 bus_space_write_4(t, erx, HME_ERXI_RING, sc->sc_rb.rb_rxddma); 543 bus_space_write_4(t, mac, HME_MACI_RXSIZE, 544 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 545 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : 546 ETHER_MAX_LEN); 547 548 549 /* step 8. Global Configuration & Interrupt Mask */ 550 bus_space_write_4(t, seb, HME_SEBI_IMASK, 551 ~( 552 /*HME_SEB_STAT_GOTFRAME | HME_SEB_STAT_SENTFRAME |*/ 553 HME_SEB_STAT_HOSTTOTX | 554 HME_SEB_STAT_RXTOHOST | 555 HME_SEB_STAT_TXALL | 556 HME_SEB_STAT_TXPERR | 557 HME_SEB_STAT_RCNTEXP | 558 HME_SEB_STAT_ALL_ERRORS )); 559 560 switch (sc->sc_burst) { 561 default: 562 v = 0; 563 break; 564 case 16: 565 v = HME_SEB_CFG_BURST16; 566 break; 567 case 32: 568 v = HME_SEB_CFG_BURST32; 569 break; 570 case 64: 571 v = HME_SEB_CFG_BURST64; 572 break; 573 } 574 bus_space_write_4(t, seb, HME_SEBI_CFG, v); 575 576 /* step 9. ETX Configuration: use mostly default values */ 577 578 /* Enable DMA */ 579 v = bus_space_read_4(t, etx, HME_ETXI_CFG); 580 v |= HME_ETX_CFG_DMAENABLE; 581 bus_space_write_4(t, etx, HME_ETXI_CFG, v); 582 583 /* Transmit Descriptor ring size: in increments of 16 */ 584 bus_space_write_4(t, etx, HME_ETXI_RSIZE, _HME_NDESC / 16 - 1); 585 586 587 /* step 10. ERX Configuration */ 588 v = bus_space_read_4(t, erx, HME_ERXI_CFG); 589 590 /* Encode Receive Descriptor ring size: four possible values */ 591 switch (_HME_NDESC /*XXX*/) { 592 case 32: 593 v |= HME_ERX_CFG_RINGSIZE32; 594 break; 595 case 64: 596 v |= HME_ERX_CFG_RINGSIZE64; 597 break; 598 case 128: 599 v |= HME_ERX_CFG_RINGSIZE128; 600 break; 601 case 256: 602 v |= HME_ERX_CFG_RINGSIZE256; 603 break; 604 default: 605 printf("hme: invalid Receive Descriptor ring size\n"); 606 break; 607 } 608 609 /* Enable DMA */ 610 v |= HME_ERX_CFG_DMAENABLE; 611 bus_space_write_4(t, erx, HME_ERXI_CFG, v); 612 613 /* step 11. XIF Configuration */ 614 v = bus_space_read_4(t, mac, HME_MACI_XIF); 615 v |= HME_MAC_XIF_OE; 616 /* If an external transceiver is connected, enable its MII drivers */ 617 if ((bus_space_read_4(t, mif, HME_MIFI_CFG) & HME_MIF_CFG_MDI1) != 0) 618 v |= HME_MAC_XIF_MIIENABLE; 619 bus_space_write_4(t, mac, HME_MACI_XIF, v); 620 621 622 /* step 12. RX_MAC Configuration Register */ 623 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 624 v |= HME_MAC_RXCFG_ENABLE; 625 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 626 627 /* step 13. TX_MAC Configuration Register */ 628 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 629 v |= (HME_MAC_TXCFG_ENABLE | HME_MAC_TXCFG_DGIVEUP); 630 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 631 632 /* step 14. Issue Transmit Pending command */ 633 634 /* Call MI initialization function if any */ 635 if (sc->sc_hwinit) 636 (*sc->sc_hwinit)(sc); 637 638 /* Set the current media. */ 639 mii_mediachg(&sc->sc_mii); 640 641 /* Start the one second timer. */ 642 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 643 644 ifp->if_flags |= IFF_RUNNING; 645 ifp->if_flags &= ~IFF_OACTIVE; 646 ifp->if_timer = 0; 647 hme_start(ifp); 648 } 649 650 /* 651 * Compare two Ether/802 addresses for equality, inlined and unrolled for 652 * speed. 653 */ 654 static __inline__ int 655 ether_cmp(a, b) 656 u_char *a, *b; 657 { 658 659 if (a[5] != b[5] || a[4] != b[4] || a[3] != b[3] || 660 a[2] != b[2] || a[1] != b[1] || a[0] != b[0]) 661 return (0); 662 return (1); 663 } 664 665 666 /* 667 * Routine to copy from mbuf chain to transmit buffer in 668 * network buffer memory. 669 * Returns the amount of data copied. 670 */ 671 int 672 hme_put(sc, ri, m) 673 struct hme_softc *sc; 674 int ri; /* Ring index */ 675 struct mbuf *m; 676 { 677 struct mbuf *n; 678 int len, tlen = 0; 679 caddr_t bp; 680 681 bp = sc->sc_rb.rb_txbuf + (ri % sc->sc_rb.rb_ntbuf) * _HME_BUFSZ; 682 for (; m; m = n) { 683 len = m->m_len; 684 if (len == 0) { 685 MFREE(m, n); 686 continue; 687 } 688 memcpy(bp, mtod(m, caddr_t), len); 689 bp += len; 690 tlen += len; 691 MFREE(m, n); 692 } 693 return (tlen); 694 } 695 696 /* 697 * Pull data off an interface. 698 * Len is length of data, with local net header stripped. 699 * We copy the data into mbufs. When full cluster sized units are present 700 * we copy into clusters. 701 */ 702 struct mbuf * 703 hme_get(sc, ri, totlen) 704 struct hme_softc *sc; 705 int ri, totlen; 706 { 707 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 708 struct mbuf *m, *m0, *newm; 709 caddr_t bp; 710 int len; 711 712 MGETHDR(m0, M_DONTWAIT, MT_DATA); 713 if (m0 == 0) 714 return (0); 715 m0->m_pkthdr.rcvif = ifp; 716 m0->m_pkthdr.len = totlen; 717 len = MHLEN; 718 m = m0; 719 720 bp = sc->sc_rb.rb_rxbuf + (ri % sc->sc_rb.rb_nrbuf) * _HME_BUFSZ; 721 722 while (totlen > 0) { 723 if (totlen >= MINCLSIZE) { 724 MCLGET(m, M_DONTWAIT); 725 if ((m->m_flags & M_EXT) == 0) 726 goto bad; 727 len = MCLBYTES; 728 } 729 730 if (m == m0) { 731 caddr_t newdata = (caddr_t) 732 ALIGN(m->m_data + sizeof(struct ether_header)) - 733 sizeof(struct ether_header); 734 len -= newdata - m->m_data; 735 m->m_data = newdata; 736 } 737 738 m->m_len = len = min(totlen, len); 739 memcpy(mtod(m, caddr_t), bp, len); 740 bp += len; 741 742 totlen -= len; 743 if (totlen > 0) { 744 MGET(newm, M_DONTWAIT, MT_DATA); 745 if (newm == 0) 746 goto bad; 747 len = MLEN; 748 m = m->m_next = newm; 749 } 750 } 751 752 return (m0); 753 754 bad: 755 m_freem(m0); 756 return (0); 757 } 758 759 /* 760 * Pass a packet to the higher levels. 761 */ 762 void 763 hme_read(sc, ix, len) 764 struct hme_softc *sc; 765 int ix, len; 766 { 767 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 768 struct mbuf *m; 769 770 if (len <= sizeof(struct ether_header) || 771 len > ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 772 ETHER_VLAN_ENCAP_LEN + ETHERMTU + sizeof(struct ether_header) : 773 ETHERMTU + sizeof(struct ether_header))) { 774 #ifdef HMEDEBUG 775 printf("%s: invalid packet size %d; dropping\n", 776 sc->sc_dev.dv_xname, len); 777 #endif 778 ifp->if_ierrors++; 779 return; 780 } 781 782 /* Pull packet off interface. */ 783 m = hme_get(sc, ix, len); 784 if (m == 0) { 785 ifp->if_ierrors++; 786 return; 787 } 788 789 ifp->if_ipackets++; 790 791 #if NBPFILTER > 0 792 /* 793 * Check if there's a BPF listener on this interface. 794 * If so, hand off the raw packet to BPF. 795 */ 796 if (ifp->if_bpf) 797 bpf_mtap(ifp->if_bpf, m); 798 #endif 799 800 /* Pass the packet up. */ 801 (*ifp->if_input)(ifp, m); 802 } 803 804 void 805 hme_start(ifp) 806 struct ifnet *ifp; 807 { 808 struct hme_softc *sc = (struct hme_softc *)ifp->if_softc; 809 caddr_t txd = sc->sc_rb.rb_txd; 810 struct mbuf *m; 811 unsigned int ri, len; 812 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 813 814 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 815 return; 816 817 ri = sc->sc_rb.rb_tdhead; 818 819 for (;;) { 820 IFQ_DEQUEUE(&ifp->if_snd, m); 821 if (m == 0) 822 break; 823 824 #if NBPFILTER > 0 825 /* 826 * If BPF is listening on this interface, let it see the 827 * packet before we commit it to the wire. 828 */ 829 if (ifp->if_bpf) 830 bpf_mtap(ifp->if_bpf, m); 831 #endif 832 833 /* 834 * Copy the mbuf chain into the transmit buffer. 835 */ 836 len = hme_put(sc, ri, m); 837 838 /* 839 * Initialize transmit registers and start transmission 840 */ 841 HME_XD_SETFLAGS(sc->sc_pci, txd, ri, 842 HME_XD_OWN | HME_XD_SOP | HME_XD_EOP | 843 HME_XD_ENCODE_TSIZE(len)); 844 845 /*if (sc->sc_rb.rb_td_nbusy <= 0)*/ 846 bus_space_write_4(sc->sc_bustag, sc->sc_etx, HME_ETXI_PENDING, 847 HME_ETX_TP_DMAWAKEUP); 848 849 if (++ri == ntbuf) 850 ri = 0; 851 852 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 853 ifp->if_flags |= IFF_OACTIVE; 854 break; 855 } 856 } 857 858 sc->sc_rb.rb_tdhead = ri; 859 } 860 861 /* 862 * Transmit interrupt. 863 */ 864 int 865 hme_tint(sc) 866 struct hme_softc *sc; 867 { 868 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 869 bus_space_tag_t t = sc->sc_bustag; 870 bus_space_handle_t mac = sc->sc_mac; 871 unsigned int ri, txflags; 872 873 /* 874 * Unload collision counters 875 */ 876 ifp->if_collisions += 877 bus_space_read_4(t, mac, HME_MACI_NCCNT) + 878 bus_space_read_4(t, mac, HME_MACI_FCCNT) + 879 bus_space_read_4(t, mac, HME_MACI_EXCNT) + 880 bus_space_read_4(t, mac, HME_MACI_LTCNT); 881 882 /* 883 * then clear the hardware counters. 884 */ 885 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 886 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 887 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 888 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 889 890 /* Fetch current position in the transmit ring */ 891 ri = sc->sc_rb.rb_tdtail; 892 893 for (;;) { 894 if (sc->sc_rb.rb_td_nbusy <= 0) 895 break; 896 897 txflags = HME_XD_GETFLAGS(sc->sc_pci, sc->sc_rb.rb_txd, ri); 898 899 if (txflags & HME_XD_OWN) 900 break; 901 902 ifp->if_flags &= ~IFF_OACTIVE; 903 ifp->if_opackets++; 904 905 if (++ri == sc->sc_rb.rb_ntbuf) 906 ri = 0; 907 908 --sc->sc_rb.rb_td_nbusy; 909 } 910 911 /* Update ring */ 912 sc->sc_rb.rb_tdtail = ri; 913 914 hme_start(ifp); 915 916 if (sc->sc_rb.rb_td_nbusy == 0) 917 ifp->if_timer = 0; 918 919 return (1); 920 } 921 922 /* 923 * Receive interrupt. 924 */ 925 int 926 hme_rint(sc) 927 struct hme_softc *sc; 928 { 929 caddr_t xdr = sc->sc_rb.rb_rxd; 930 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 931 unsigned int ri, len; 932 u_int32_t flags; 933 934 ri = sc->sc_rb.rb_rdtail; 935 936 /* 937 * Process all buffers with valid data. 938 */ 939 for (;;) { 940 flags = HME_XD_GETFLAGS(sc->sc_pci, xdr, ri); 941 if (flags & HME_XD_OWN) 942 break; 943 944 if (flags & HME_XD_OFL) { 945 printf("%s: buffer overflow, ri=%d; flags=0x%x\n", 946 sc->sc_dev.dv_xname, ri, flags); 947 } else { 948 len = HME_XD_DECODE_RSIZE(flags); 949 hme_read(sc, ri, len); 950 } 951 952 /* This buffer can be used by the hardware again */ 953 HME_XD_SETFLAGS(sc->sc_pci, xdr, ri, 954 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 955 956 if (++ri == nrbuf) 957 ri = 0; 958 } 959 960 sc->sc_rb.rb_rdtail = ri; 961 962 return (1); 963 } 964 965 int 966 hme_eint(sc, status) 967 struct hme_softc *sc; 968 u_int status; 969 { 970 char bits[128]; 971 972 if ((status & HME_SEB_STAT_MIFIRQ) != 0) { 973 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 974 return (1); 975 } 976 977 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 978 bitmask_snprintf(status, HME_SEB_STAT_BITS, bits,sizeof(bits))); 979 return (1); 980 } 981 982 int 983 hme_intr(v) 984 void *v; 985 { 986 struct hme_softc *sc = (struct hme_softc *)v; 987 bus_space_tag_t t = sc->sc_bustag; 988 bus_space_handle_t seb = sc->sc_seb; 989 u_int32_t status; 990 int r = 0; 991 992 status = bus_space_read_4(t, seb, HME_SEBI_STAT); 993 994 if ((status & HME_SEB_STAT_ALL_ERRORS) != 0) 995 r |= hme_eint(sc, status); 996 997 if ((status & (HME_SEB_STAT_TXALL | HME_SEB_STAT_HOSTTOTX)) != 0) 998 r |= hme_tint(sc); 999 1000 if ((status & HME_SEB_STAT_RXTOHOST) != 0) 1001 r |= hme_rint(sc); 1002 1003 return (r); 1004 } 1005 1006 1007 void 1008 hme_watchdog(ifp) 1009 struct ifnet *ifp; 1010 { 1011 struct hme_softc *sc = ifp->if_softc; 1012 1013 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1014 ++ifp->if_oerrors; 1015 1016 hme_reset(sc); 1017 } 1018 1019 /* 1020 * Initialize the MII Management Interface 1021 */ 1022 void 1023 hme_mifinit(sc) 1024 struct hme_softc *sc; 1025 { 1026 bus_space_tag_t t = sc->sc_bustag; 1027 bus_space_handle_t mif = sc->sc_mif; 1028 u_int32_t v; 1029 1030 /* Configure the MIF in frame mode */ 1031 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1032 v &= ~HME_MIF_CFG_BBMODE; 1033 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1034 } 1035 1036 /* 1037 * MII interface 1038 */ 1039 static int 1040 hme_mii_readreg(self, phy, reg) 1041 struct device *self; 1042 int phy, reg; 1043 { 1044 struct hme_softc *sc = (void *)self; 1045 bus_space_tag_t t = sc->sc_bustag; 1046 bus_space_handle_t mif = sc->sc_mif; 1047 int n; 1048 u_int32_t v; 1049 1050 /* Select the desired PHY in the MIF configuration register */ 1051 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1052 /* Clear PHY select bit */ 1053 v &= ~HME_MIF_CFG_PHY; 1054 if (phy == HME_PHYAD_EXTERNAL) 1055 /* Set PHY select bit to get at external device */ 1056 v |= HME_MIF_CFG_PHY; 1057 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1058 1059 /* Construct the frame command */ 1060 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1061 HME_MIF_FO_TAMSB | 1062 (MII_COMMAND_READ << HME_MIF_FO_OPC_SHIFT) | 1063 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1064 (reg << HME_MIF_FO_REGAD_SHIFT); 1065 1066 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1067 for (n = 0; n < 100; n++) { 1068 DELAY(1); 1069 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1070 if (v & HME_MIF_FO_TALSB) 1071 return (v & HME_MIF_FO_DATA); 1072 } 1073 1074 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1075 return (0); 1076 } 1077 1078 static void 1079 hme_mii_writereg(self, phy, reg, val) 1080 struct device *self; 1081 int phy, reg, val; 1082 { 1083 struct hme_softc *sc = (void *)self; 1084 bus_space_tag_t t = sc->sc_bustag; 1085 bus_space_handle_t mif = sc->sc_mif; 1086 int n; 1087 u_int32_t v; 1088 1089 /* Select the desired PHY in the MIF configuration register */ 1090 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1091 /* Clear PHY select bit */ 1092 v &= ~HME_MIF_CFG_PHY; 1093 if (phy == HME_PHYAD_EXTERNAL) 1094 /* Set PHY select bit to get at external device */ 1095 v |= HME_MIF_CFG_PHY; 1096 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1097 1098 /* Construct the frame command */ 1099 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1100 HME_MIF_FO_TAMSB | 1101 (MII_COMMAND_WRITE << HME_MIF_FO_OPC_SHIFT) | 1102 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1103 (reg << HME_MIF_FO_REGAD_SHIFT) | 1104 (val & HME_MIF_FO_DATA); 1105 1106 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1107 for (n = 0; n < 100; n++) { 1108 DELAY(1); 1109 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1110 if (v & HME_MIF_FO_TALSB) 1111 return; 1112 } 1113 1114 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1115 } 1116 1117 static void 1118 hme_mii_statchg(dev) 1119 struct device *dev; 1120 { 1121 struct hme_softc *sc = (void *)dev; 1122 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1123 int phy = sc->sc_phys[instance]; 1124 bus_space_tag_t t = sc->sc_bustag; 1125 bus_space_handle_t mif = sc->sc_mif; 1126 bus_space_handle_t mac = sc->sc_mac; 1127 u_int32_t v; 1128 1129 #ifdef HMEDEBUG 1130 if (sc->sc_debug) 1131 printf("hme_mii_statchg: status change: phy = %d\n", phy); 1132 #endif 1133 1134 /* Select the current PHY in the MIF configuration register */ 1135 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1136 v &= ~HME_MIF_CFG_PHY; 1137 if (phy == HME_PHYAD_EXTERNAL) 1138 v |= HME_MIF_CFG_PHY; 1139 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1140 1141 /* Set the MAC Full Duplex bit appropriately */ 1142 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 1143 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1144 v |= HME_MAC_TXCFG_FULLDPLX; 1145 else 1146 v &= ~HME_MAC_TXCFG_FULLDPLX; 1147 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 1148 1149 /* If an external transceiver is selected, enable its MII drivers */ 1150 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1151 v &= ~HME_MAC_XIF_MIIENABLE; 1152 if (phy == HME_PHYAD_EXTERNAL) 1153 v |= HME_MAC_XIF_MIIENABLE; 1154 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1155 } 1156 1157 int 1158 hme_mediachange(ifp) 1159 struct ifnet *ifp; 1160 { 1161 struct hme_softc *sc = ifp->if_softc; 1162 1163 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 1164 return (EINVAL); 1165 1166 return (mii_mediachg(&sc->sc_mii)); 1167 } 1168 1169 void 1170 hme_mediastatus(ifp, ifmr) 1171 struct ifnet *ifp; 1172 struct ifmediareq *ifmr; 1173 { 1174 struct hme_softc *sc = ifp->if_softc; 1175 1176 if ((ifp->if_flags & IFF_UP) == 0) 1177 return; 1178 1179 mii_pollstat(&sc->sc_mii); 1180 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1181 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1182 } 1183 1184 /* 1185 * Process an ioctl request. 1186 */ 1187 int 1188 hme_ioctl(ifp, cmd, data) 1189 struct ifnet *ifp; 1190 u_long cmd; 1191 caddr_t data; 1192 { 1193 struct hme_softc *sc = ifp->if_softc; 1194 struct ifaddr *ifa = (struct ifaddr *)data; 1195 struct ifreq *ifr = (struct ifreq *)data; 1196 int s, error = 0; 1197 1198 s = splnet(); 1199 1200 switch (cmd) { 1201 1202 case SIOCSIFADDR: 1203 ifp->if_flags |= IFF_UP; 1204 1205 switch (ifa->ifa_addr->sa_family) { 1206 #ifdef INET 1207 case AF_INET: 1208 hme_init(sc); 1209 arp_ifinit(ifp, ifa); 1210 break; 1211 #endif 1212 #ifdef NS 1213 case AF_NS: 1214 { 1215 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1216 1217 if (ns_nullhost(*ina)) 1218 ina->x_host = 1219 *(union ns_host *)LLADDR(ifp->if_sadl); 1220 else { 1221 memcpy(LLADDR(ifp->if_sadl), 1222 ina->x_host.c_host, sizeof(sc->sc_enaddr)); 1223 } 1224 /* Set new address. */ 1225 hme_init(sc); 1226 break; 1227 } 1228 #endif 1229 default: 1230 hme_init(sc); 1231 break; 1232 } 1233 break; 1234 1235 case SIOCSIFFLAGS: 1236 if ((ifp->if_flags & IFF_UP) == 0 && 1237 (ifp->if_flags & IFF_RUNNING) != 0) { 1238 /* 1239 * If interface is marked down and it is running, then 1240 * stop it. 1241 */ 1242 hme_stop(sc); 1243 ifp->if_flags &= ~IFF_RUNNING; 1244 } else if ((ifp->if_flags & IFF_UP) != 0 && 1245 (ifp->if_flags & IFF_RUNNING) == 0) { 1246 /* 1247 * If interface is marked up and it is stopped, then 1248 * start it. 1249 */ 1250 hme_init(sc); 1251 } else if ((ifp->if_flags & IFF_UP) != 0) { 1252 /* 1253 * Reset the interface to pick up changes in any other 1254 * flags that affect hardware registers. 1255 */ 1256 /*hme_stop(sc);*/ 1257 hme_init(sc); 1258 } 1259 #ifdef HMEDEBUG 1260 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 1261 #endif 1262 break; 1263 1264 case SIOCADDMULTI: 1265 case SIOCDELMULTI: 1266 error = (cmd == SIOCADDMULTI) ? 1267 ether_addmulti(ifr, &sc->sc_ethercom) : 1268 ether_delmulti(ifr, &sc->sc_ethercom); 1269 1270 if (error == ENETRESET) { 1271 /* 1272 * Multicast list has changed; set the hardware filter 1273 * accordingly. 1274 */ 1275 hme_setladrf(sc); 1276 error = 0; 1277 } 1278 break; 1279 1280 case SIOCGIFMEDIA: 1281 case SIOCSIFMEDIA: 1282 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1283 break; 1284 1285 default: 1286 error = EINVAL; 1287 break; 1288 } 1289 1290 splx(s); 1291 return (error); 1292 } 1293 1294 void 1295 hme_shutdown(arg) 1296 void *arg; 1297 { 1298 1299 hme_stop((struct hme_softc *)arg); 1300 } 1301 1302 /* 1303 * Set up the logical address filter. 1304 */ 1305 void 1306 hme_setladrf(sc) 1307 struct hme_softc *sc; 1308 { 1309 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1310 struct ether_multi *enm; 1311 struct ether_multistep step; 1312 struct ethercom *ec = &sc->sc_ethercom; 1313 bus_space_tag_t t = sc->sc_bustag; 1314 bus_space_handle_t mac = sc->sc_mac; 1315 u_char *cp; 1316 u_int32_t crc; 1317 u_int32_t hash[4]; 1318 u_int32_t v; 1319 int len; 1320 1321 /* Clear hash table */ 1322 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1323 1324 /* Get current RX configuration */ 1325 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 1326 1327 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1328 /* Turn on promiscuous mode; turn off the hash filter */ 1329 v |= HME_MAC_RXCFG_PMISC; 1330 v &= ~HME_MAC_RXCFG_HENABLE; 1331 ifp->if_flags |= IFF_ALLMULTI; 1332 goto chipit; 1333 } 1334 1335 /* Turn off promiscuous mode; turn on the hash filter */ 1336 v &= ~HME_MAC_RXCFG_PMISC; 1337 v |= HME_MAC_RXCFG_HENABLE; 1338 1339 /* 1340 * Set up multicast address filter by passing all multicast addresses 1341 * through a crc generator, and then using the high order 6 bits as an 1342 * index into the 64 bit logical address filter. The high order bit 1343 * selects the word, while the rest of the bits select the bit within 1344 * the word. 1345 */ 1346 1347 ETHER_FIRST_MULTI(step, ec, enm); 1348 while (enm != NULL) { 1349 if (ether_cmp(enm->enm_addrlo, enm->enm_addrhi)) { 1350 /* 1351 * We must listen to a range of multicast addresses. 1352 * For now, just accept all multicasts, rather than 1353 * trying to set only those filter bits needed to match 1354 * the range. (At this time, the only use of address 1355 * ranges is for IP multicast routing, for which the 1356 * range is big enough to require all bits set.) 1357 */ 1358 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1359 ifp->if_flags |= IFF_ALLMULTI; 1360 goto chipit; 1361 } 1362 1363 cp = enm->enm_addrlo; 1364 crc = 0xffffffff; 1365 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1366 int octet = *cp++; 1367 int i; 1368 1369 #define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */ 1370 for (i = 0; i < 8; i++) { 1371 if ((crc & 1) ^ (octet & 1)) { 1372 crc >>= 1; 1373 crc ^= MC_POLY_LE; 1374 } else { 1375 crc >>= 1; 1376 } 1377 octet >>= 1; 1378 } 1379 } 1380 /* Just want the 6 most significant bits. */ 1381 crc >>= 26; 1382 1383 /* Set the corresponding bit in the filter. */ 1384 hash[crc >> 4] |= 1 << (crc & 0xf); 1385 1386 ETHER_NEXT_MULTI(step, enm); 1387 } 1388 1389 ifp->if_flags &= ~IFF_ALLMULTI; 1390 1391 chipit: 1392 /* Now load the hash table into the chip */ 1393 bus_space_write_4(t, mac, HME_MACI_HASHTAB0, hash[0]); 1394 bus_space_write_4(t, mac, HME_MACI_HASHTAB1, hash[1]); 1395 bus_space_write_4(t, mac, HME_MACI_HASHTAB2, hash[2]); 1396 bus_space_write_4(t, mac, HME_MACI_HASHTAB3, hash[3]); 1397 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 1398 } 1399 1400 /* 1401 * Routines for accessing the transmit and receive buffers. 1402 * The various CPU and adapter configurations supported by this 1403 * driver require three different access methods for buffers 1404 * and descriptors: 1405 * (1) contig (contiguous data; no padding), 1406 * (2) gap2 (two bytes of data followed by two bytes of padding), 1407 * (3) gap16 (16 bytes of data followed by 16 bytes of padding). 1408 */ 1409 1410 #if 0 1411 /* 1412 * contig: contiguous data with no padding. 1413 * 1414 * Buffers may have any alignment. 1415 */ 1416 1417 void 1418 hme_copytobuf_contig(sc, from, ri, len) 1419 struct hme_softc *sc; 1420 void *from; 1421 int ri, len; 1422 { 1423 volatile caddr_t buf = sc->sc_rb.rb_txbuf + (ri * _HME_BUFSZ); 1424 1425 /* 1426 * Just call memcpy() to do the work. 1427 */ 1428 memcpy(buf, from, len); 1429 } 1430 1431 void 1432 hme_copyfrombuf_contig(sc, to, boff, len) 1433 struct hme_softc *sc; 1434 void *to; 1435 int boff, len; 1436 { 1437 volatile caddr_t buf = sc->sc_rb.rb_rxbuf + (ri * _HME_BUFSZ); 1438 1439 /* 1440 * Just call memcpy() to do the work. 1441 */ 1442 memcpy(to, buf, len); 1443 } 1444 #endif 1445