1 /* $NetBSD: i82365.c,v 1.113 2010/04/19 18:24:26 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Charles M. Hannum. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 */ 20 21 /* 22 * Copyright (c) 2000 Christian E. Hopps. All rights reserved. 23 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 24 * 25 * Redistribution and use in source and binary forms, with or without 26 * modification, are permitted provided that the following conditions 27 * are met: 28 * 1. Redistributions of source code must retain the above copyright 29 * notice, this list of conditions and the following disclaimer. 30 * 2. Redistributions in binary form must reproduce the above copyright 31 * notice, this list of conditions and the following disclaimer in the 32 * documentation and/or other materials provided with the distribution. 33 * 3. All advertising materials mentioning features or use of this software 34 * must display the following acknowledgement: 35 * This product includes software developed by Marc Horowitz. 36 * 4. The name of the author may not be used to endorse or promote products 37 * derived from this software without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 40 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 41 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 42 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 43 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 44 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 45 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 46 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 47 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 48 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: i82365.c,v 1.113 2010/04/19 18:24:26 dyoung Exp $"); 53 54 #define PCICDEBUG 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/device.h> 59 #include <sys/extent.h> 60 #include <sys/kernel.h> 61 #include <sys/malloc.h> 62 #include <sys/kthread.h> 63 64 #include <sys/bus.h> 65 #include <sys/intr.h> 66 67 #include <dev/pcmcia/pcmciareg.h> 68 #include <dev/pcmcia/pcmciavar.h> 69 70 #include <dev/ic/i82365reg.h> 71 #include <dev/ic/i82365var.h> 72 73 #include "locators.h" 74 75 #ifdef PCICDEBUG 76 int pcic_debug = 0; 77 #define DPRINTF(arg) if (pcic_debug) printf arg; 78 #else 79 #define DPRINTF(arg) 80 #endif 81 82 /* 83 * Individual drivers will allocate their own memory and io regions. Memory 84 * regions must be a multiple of 4k, aligned on a 4k boundary. 85 */ 86 87 #define PCIC_MEM_ALIGN PCIC_MEM_PAGESIZE 88 89 void pcic_attach_socket(struct pcic_handle *); 90 void pcic_attach_socket_finish(struct pcic_handle *); 91 92 int pcic_print (void *arg, const char *pnp); 93 int pcic_intr_socket(struct pcic_handle *); 94 void pcic_poll_intr(void *); 95 96 void pcic_attach_card(struct pcic_handle *); 97 void pcic_detach_card(struct pcic_handle *, int); 98 void pcic_deactivate_card(struct pcic_handle *); 99 100 void pcic_chip_do_mem_map(struct pcic_handle *, int); 101 void pcic_chip_do_io_map(struct pcic_handle *, int); 102 103 void pcic_event_thread(void *); 104 105 void pcic_queue_event(struct pcic_handle *, int); 106 void pcic_power(int, void *); 107 108 static int pcic_wait_ready(struct pcic_handle *); 109 static void pcic_delay(struct pcic_handle *, int, const char *); 110 111 static uint8_t st_pcic_read(struct pcic_handle *, int); 112 static void st_pcic_write(struct pcic_handle *, int, uint8_t); 113 114 int 115 pcic_ident_ok(int ident) 116 { 117 118 /* this is very empirical and heuristic */ 119 120 if ((ident == 0) || (ident == 0xff) || (ident & PCIC_IDENT_ZERO)) 121 return 0; 122 123 if ((ident & PCIC_IDENT_REV_MASK) == 0) 124 return 0; 125 126 if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) { 127 #ifdef DIAGNOSTIC 128 printf("pcic: does not support memory and I/O cards, " 129 "ignored (ident=%0x)\n", ident); 130 #endif 131 return 0; 132 } 133 134 return 1; 135 } 136 137 int 138 pcic_vendor(struct pcic_handle *h) 139 { 140 int reg; 141 int vendor; 142 143 reg = pcic_read(h, PCIC_IDENT); 144 145 if ((reg & PCIC_IDENT_REV_MASK) == 0) 146 return PCIC_VENDOR_NONE; 147 148 switch (reg) { 149 case 0x00: 150 case 0xff: 151 return PCIC_VENDOR_NONE; 152 case PCIC_IDENT_ID_INTEL0: 153 vendor = PCIC_VENDOR_I82365SLR0; 154 break; 155 case PCIC_IDENT_ID_INTEL1: 156 vendor = PCIC_VENDOR_I82365SLR1; 157 break; 158 case PCIC_IDENT_ID_INTEL2: 159 vendor = PCIC_VENDOR_I82365SL_DF; 160 break; 161 case PCIC_IDENT_ID_IBM1: 162 case PCIC_IDENT_ID_IBM2: 163 vendor = PCIC_VENDOR_IBM; 164 break; 165 case PCIC_IDENT_ID_IBM3: 166 vendor = PCIC_VENDOR_IBM_KING; 167 break; 168 default: 169 vendor = PCIC_VENDOR_UNKNOWN; 170 break; 171 } 172 173 if (vendor == PCIC_VENDOR_I82365SLR0 || 174 vendor == PCIC_VENDOR_I82365SLR1) { 175 /* 176 * Check for Cirrus PD67xx. 177 * the chip_id of the cirrus toggles between 11 and 00 after a 178 * write. weird. 179 */ 180 pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0); 181 reg = pcic_read(h, -1); 182 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 183 PCIC_CIRRUS_CHIP_INFO_CHIP_ID) { 184 reg = pcic_read(h, -1); 185 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) 186 return PCIC_VENDOR_CIRRUS_PD67XX; 187 } 188 189 /* 190 * check for Ricoh RF5C[23]96 191 */ 192 reg = pcic_read(h, PCIC_RICOH_REG_CHIP_ID); 193 switch (reg) { 194 case PCIC_RICOH_CHIP_ID_5C296: 195 return PCIC_VENDOR_RICOH_5C296; 196 case PCIC_RICOH_CHIP_ID_5C396: 197 return PCIC_VENDOR_RICOH_5C396; 198 } 199 } 200 201 return vendor; 202 } 203 204 const char * 205 pcic_vendor_to_string(int vendor) 206 { 207 208 switch (vendor) { 209 case PCIC_VENDOR_I82365SLR0: 210 return "Intel 82365SL Revision 0"; 211 case PCIC_VENDOR_I82365SLR1: 212 return "Intel 82365SL Revision 1"; 213 case PCIC_VENDOR_CIRRUS_PD67XX: 214 return "Cirrus PD6710/2X"; 215 case PCIC_VENDOR_I82365SL_DF: 216 return "Intel 82365SL-DF"; 217 case PCIC_VENDOR_RICOH_5C296: 218 return "Ricoh RF5C296"; 219 case PCIC_VENDOR_RICOH_5C396: 220 return "Ricoh RF5C396"; 221 case PCIC_VENDOR_IBM: 222 return "IBM PCIC"; 223 case PCIC_VENDOR_IBM_KING: 224 return "IBM KING"; 225 } 226 227 return "Unknown controller"; 228 } 229 230 void 231 pcic_attach(struct pcic_softc *sc) 232 { 233 int i, reg, chip, socket; 234 struct pcic_handle *h; 235 device_t self; 236 237 DPRINTF(("pcic ident regs:")); 238 239 self = &sc->dev; 240 mutex_init(&sc->sc_pcic_lock, MUTEX_DEFAULT, IPL_NONE); 241 242 /* find and configure for the available sockets */ 243 for (i = 0; i < __arraycount(sc->handle); i++) { 244 h = &sc->handle[i]; 245 chip = i / 2; 246 socket = i % 2; 247 248 h->ph_parent = self; 249 h->chip = chip; 250 h->socket = socket; 251 h->sock = chip * PCIC_CHIP_OFFSET + socket * PCIC_SOCKET_OFFSET; 252 h->laststate = PCIC_LASTSTATE_EMPTY; 253 /* initialize pcic_read and pcic_write functions */ 254 h->ph_read = st_pcic_read; 255 h->ph_write = st_pcic_write; 256 h->ph_bus_t = sc->iot; 257 h->ph_bus_h = sc->ioh; 258 h->flags = 0; 259 260 /* need to read vendor -- for cirrus to report no xtra chip */ 261 if (socket == 0) { 262 h->vendor = pcic_vendor(h); 263 if (i < __arraycount(sc->handle) - 1) 264 (h + 1)->vendor = h->vendor; 265 } 266 267 switch (h->vendor) { 268 case PCIC_VENDOR_NONE: 269 /* no chip */ 270 continue; 271 case PCIC_VENDOR_CIRRUS_PD67XX: 272 reg = pcic_read(h, PCIC_CIRRUS_CHIP_INFO); 273 if (socket == 0 || 274 (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS)) 275 h->flags = PCIC_FLAG_SOCKETP; 276 break; 277 default: 278 /* 279 * During the socket probe, read the ident register 280 * twice. I don't understand why, but sometimes the 281 * clone chips in hpcmips boxes read all-0s the first 282 * time. -- mycroft 283 */ 284 reg = pcic_read(h, PCIC_IDENT); 285 DPRINTF(("socket %d ident reg 0x%02x\n", i, reg)); 286 reg = pcic_read(h, PCIC_IDENT); 287 DPRINTF(("socket %d ident reg 0x%02x\n", i, reg)); 288 if (pcic_ident_ok(reg)) 289 h->flags = PCIC_FLAG_SOCKETP; 290 break; 291 } 292 } 293 294 for (i = 0; i < __arraycount(sc->handle); i++) { 295 h = &sc->handle[i]; 296 297 if (h->flags & PCIC_FLAG_SOCKETP) { 298 SIMPLEQ_INIT(&h->events); 299 300 /* disable interrupts and leave socket in reset */ 301 pcic_write(h, PCIC_INTR, 0); 302 303 /* zero out the address windows */ 304 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 305 306 /* power down the socket */ 307 pcic_write(h, PCIC_PWRCTL, 0); 308 309 pcic_write(h, PCIC_CSC_INTR, 0); 310 (void) pcic_read(h, PCIC_CSC); 311 } 312 } 313 314 /* print detected info */ 315 for (i = 0; i < __arraycount(sc->handle) - 1; i += 2) { 316 h = &sc->handle[i]; 317 chip = i / 2; 318 319 if (h->vendor == PCIC_VENDOR_NONE) 320 continue; 321 322 aprint_normal_dev(self, "controller %d (%s) has ", 323 chip, pcic_vendor_to_string(sc->handle[i].vendor)); 324 325 if ((h->flags & PCIC_FLAG_SOCKETP) && 326 ((h + 1)->flags & PCIC_FLAG_SOCKETP)) 327 aprint_normal("sockets A and B\n"); 328 else if (h->flags & PCIC_FLAG_SOCKETP) 329 aprint_normal("socket A only\n"); 330 else if ((h + 1)->flags & PCIC_FLAG_SOCKETP) 331 aprint_normal("socket B only\n"); 332 else 333 aprint_normal("no sockets\n"); 334 } 335 } 336 337 /* 338 * attach the sockets before we know what interrupts we have 339 */ 340 void 341 pcic_attach_sockets(struct pcic_softc *sc) 342 { 343 int i; 344 345 for (i = 0; i < __arraycount(sc->handle); i++) 346 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 347 pcic_attach_socket(&sc->handle[i]); 348 } 349 350 void 351 pcic_power(int why, void *arg) 352 { 353 struct pcic_handle *h = arg; 354 struct pcic_softc *sc = device_private(h->ph_parent); 355 int reg; 356 357 DPRINTF(("%s: power: why %d\n", device_xname(h->ph_parent), why)); 358 359 if (h->flags & PCIC_FLAG_SOCKETP) { 360 if ((why == PWR_RESUME) && 361 (pcic_read(h, PCIC_CSC_INTR) == 0)) { 362 #ifdef PCICDEBUG 363 char bitbuf[64]; 364 #endif 365 reg = PCIC_CSC_INTR_CD_ENABLE; 366 if (sc->irq != -1) 367 reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT; 368 pcic_write(h, PCIC_CSC_INTR, reg); 369 #ifdef PCICDEBUG 370 snprintb(bitbuf, sizeof(bitbuf), PCIC_CSC_INTR_FORMAT, 371 pcic_read(h, PCIC_CSC_INTR)); 372 #endif 373 DPRINTF(("%s: CSC_INTR was zero; reset to %s\n", 374 device_xname(&sc->dev), bitbuf)); 375 } 376 377 /* 378 * check for card insertion or removal during suspend period. 379 * XXX: the code can't cope with card swap (remove then insert). 380 * how can we detect such situation? 381 */ 382 if (why == PWR_RESUME) 383 (void)pcic_intr_socket(h); 384 } 385 } 386 387 388 /* 389 * attach a socket -- we don't know about irqs yet 390 */ 391 void 392 pcic_attach_socket(struct pcic_handle *h) 393 { 394 struct pcmciabus_attach_args paa; 395 struct pcic_softc *sc = device_private(h->ph_parent); 396 int locs[PCMCIABUSCF_NLOCS]; 397 398 /* initialize the rest of the handle */ 399 400 h->shutdown = 0; 401 h->memalloc = 0; 402 h->ioalloc = 0; 403 h->ih_irq = 0; 404 405 /* now, config one pcmcia device per socket */ 406 407 paa.paa_busname = "pcmcia"; 408 paa.pct = (pcmcia_chipset_tag_t) sc->pct; 409 paa.pch = (pcmcia_chipset_handle_t) h; 410 paa.iobase = sc->iobase; 411 paa.iosize = sc->iosize; 412 413 locs[PCMCIABUSCF_CONTROLLER] = h->chip; 414 locs[PCMCIABUSCF_SOCKET] = h->socket; 415 416 h->pcmcia = config_found_sm_loc(&sc->dev, "pcmciabus", locs, &paa, 417 pcic_print, config_stdsubmatch); 418 if (h->pcmcia == NULL) { 419 h->flags &= ~PCIC_FLAG_SOCKETP; 420 return; 421 } 422 423 } 424 425 /* 426 * now finish attaching the sockets, we are ready to allocate 427 * interrupts 428 */ 429 void 430 pcic_attach_sockets_finish(struct pcic_softc *sc) 431 { 432 int i; 433 434 for (i = 0; i < __arraycount(sc->handle); i++) 435 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 436 pcic_attach_socket_finish(&sc->handle[i]); 437 } 438 439 /* 440 * finishing attaching the socket. Interrupts may now be on 441 * if so expects the pcic interrupt to be blocked 442 */ 443 void 444 pcic_attach_socket_finish(struct pcic_handle *h) 445 { 446 struct pcic_softc *sc = device_private(h->ph_parent); 447 int reg; 448 char cs[4]; 449 450 DPRINTF(("%s: attach finish socket %ld\n", device_xname(h->ph_parent), 451 (long) (h - &sc->handle[0]))); 452 453 /* 454 * Set up a powerhook to ensure it continues to interrupt on 455 * card detect even after suspend. 456 * (this works around a bug seen in suspend-to-disk on the 457 * Sony VAIO Z505; on resume, the CSC_INTR state is not preserved). 458 */ 459 powerhook_establish(device_xname(h->ph_parent), pcic_power, h); 460 461 /* enable interrupts on card detect, poll for them if no irq avail */ 462 reg = PCIC_CSC_INTR_CD_ENABLE; 463 if (sc->irq == -1) { 464 if (sc->poll_established == 0) { 465 callout_init(&sc->poll_ch, 0); 466 callout_reset(&sc->poll_ch, hz / 2, pcic_poll_intr, sc); 467 sc->poll_established = 1; 468 } 469 } else 470 reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT; 471 pcic_write(h, PCIC_CSC_INTR, reg); 472 473 /* steer above mgmt interrupt to configured place */ 474 if (sc->irq == 0) 475 pcic_write(h, PCIC_INTR, PCIC_INTR_ENABLE); 476 477 /* clear possible card detect interrupt */ 478 (void) pcic_read(h, PCIC_CSC); 479 480 DPRINTF(("%s: attach finish vendor 0x%02x\n", 481 device_xname(h->ph_parent), h->vendor)); 482 483 /* unsleep the cirrus controller */ 484 if (h->vendor == PCIC_VENDOR_CIRRUS_PD67XX) { 485 reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2); 486 if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) { 487 DPRINTF(("%s: socket %02x was suspended\n", 488 device_xname(h->ph_parent), h->sock)); 489 reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND; 490 pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg); 491 } 492 } 493 494 /* if there's a card there, then attach it. */ 495 reg = pcic_read(h, PCIC_IF_STATUS); 496 if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) == 497 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 498 pcic_queue_event(h, PCIC_EVENT_INSERTION); 499 h->laststate = PCIC_LASTSTATE_PRESENT; 500 } else { 501 h->laststate = PCIC_LASTSTATE_EMPTY; 502 } 503 504 /* 505 * queue creation of a kernel thread to handle insert/removal events. 506 */ 507 #ifdef DIAGNOSTIC 508 if (h->event_thread != NULL) 509 panic("pcic_attach_socket: event thread"); 510 #endif 511 config_pending_incr(); 512 snprintf(cs, sizeof(cs), "%d,%d", h->chip, h->socket); 513 514 if (kthread_create(PRI_NONE, 0, NULL, pcic_event_thread, h, 515 &h->event_thread, "%s,%s", device_xname(h->ph_parent), cs)) { 516 aprint_error_dev(h->ph_parent, 517 "unable to create event thread for sock 0x%02x\n", h->sock); 518 panic("pcic_attach_socket"); 519 } 520 } 521 522 void 523 pcic_event_thread(void *arg) 524 { 525 struct pcic_handle *h = arg; 526 struct pcic_event *pe; 527 int s, first = 1; 528 struct pcic_softc *sc = device_private(h->ph_parent); 529 530 while (h->shutdown == 0) { 531 /* 532 * Serialize event processing on the PCIC. We may 533 * sleep while we hold this lock. 534 */ 535 mutex_enter(&sc->sc_pcic_lock); 536 537 s = splhigh(); 538 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 539 splx(s); 540 if (first) { 541 first = 0; 542 config_pending_decr(); 543 } 544 /* 545 * No events to process; release the PCIC lock. 546 */ 547 (void) mutex_exit(&sc->sc_pcic_lock); 548 (void) tsleep(&h->events, PWAIT, "pcicev", 0); 549 continue; 550 } else { 551 splx(s); 552 /* sleep .25s to be enqueued chatterling interrupts */ 553 (void) tsleep((void *)pcic_event_thread, PWAIT, 554 "pcicss", hz / 4); 555 } 556 s = splhigh(); 557 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 558 splx(s); 559 560 switch (pe->pe_type) { 561 case PCIC_EVENT_INSERTION: 562 s = splhigh(); 563 for (;;) { 564 struct pcic_event *pe1, *pe2; 565 566 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 567 break; 568 if (pe1->pe_type != PCIC_EVENT_REMOVAL) 569 break; 570 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 571 break; 572 if (pe2->pe_type == PCIC_EVENT_INSERTION) { 573 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 574 free(pe1, M_TEMP); 575 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 576 free(pe2, M_TEMP); 577 } 578 } 579 splx(s); 580 581 DPRINTF(("%s: insertion event\n", 582 device_xname(h->ph_parent))); 583 pcic_attach_card(h); 584 break; 585 586 case PCIC_EVENT_REMOVAL: 587 s = splhigh(); 588 for (;;) { 589 struct pcic_event *pe1, *pe2; 590 591 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 592 break; 593 if (pe1->pe_type != PCIC_EVENT_INSERTION) 594 break; 595 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 596 break; 597 if (pe2->pe_type == PCIC_EVENT_REMOVAL) { 598 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 599 free(pe1, M_TEMP); 600 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 601 free(pe2, M_TEMP); 602 } 603 } 604 splx(s); 605 606 DPRINTF(("%s: removal event\n", 607 device_xname(h->ph_parent))); 608 pcic_detach_card(h, DETACH_FORCE); 609 break; 610 611 default: 612 panic("pcic_event_thread: unknown event %d", 613 pe->pe_type); 614 } 615 free(pe, M_TEMP); 616 617 mutex_exit(&sc->sc_pcic_lock); 618 } 619 620 h->event_thread = NULL; 621 622 /* In case parent is waiting for us to exit. */ 623 wakeup(sc); 624 625 kthread_exit(0); 626 } 627 628 int 629 pcic_print(void *arg, const char *pnp) 630 { 631 struct pcmciabus_attach_args *paa = arg; 632 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 633 634 /* Only "pcmcia"s can attach to "pcic"s... easy. */ 635 if (pnp) 636 aprint_normal("pcmcia at %s", pnp); 637 638 aprint_normal(" controller %d socket %d", h->chip, h->socket); 639 640 return UNCONF; 641 } 642 643 void 644 pcic_poll_intr(void *arg) 645 { 646 struct pcic_softc *sc; 647 int i, s; 648 649 s = spltty(); 650 sc = arg; 651 for (i = 0; i < __arraycount(sc->handle); i++) 652 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 653 (void)pcic_intr_socket(&sc->handle[i]); 654 callout_reset(&sc->poll_ch, hz / 2, pcic_poll_intr, sc); 655 splx(s); 656 } 657 658 int 659 pcic_intr(void *arg) 660 { 661 struct pcic_softc *sc = arg; 662 int i, ret = 0; 663 664 DPRINTF(("%s: intr\n", device_xname(&sc->dev))); 665 666 for (i = 0; i < __arraycount(sc->handle); i++) 667 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 668 ret += pcic_intr_socket(&sc->handle[i]); 669 670 return ret ? 1 : 0; 671 } 672 673 int 674 pcic_intr_socket(struct pcic_handle *h) 675 { 676 int cscreg; 677 678 cscreg = pcic_read(h, PCIC_CSC); 679 680 cscreg &= (PCIC_CSC_GPI | 681 PCIC_CSC_CD | 682 PCIC_CSC_READY | 683 PCIC_CSC_BATTWARN | 684 PCIC_CSC_BATTDEAD); 685 686 if (cscreg & PCIC_CSC_GPI) { 687 DPRINTF(("%s: %02x GPI\n", 688 device_xname(h->ph_parent), h->sock)); 689 } 690 if (cscreg & PCIC_CSC_CD) { 691 int statreg; 692 693 statreg = pcic_read(h, PCIC_IF_STATUS); 694 695 DPRINTF(("%s: %02x CD %x\n", device_xname(h->ph_parent), 696 h->sock, statreg)); 697 698 if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 699 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 700 if (h->laststate != PCIC_LASTSTATE_PRESENT) { 701 DPRINTF(("%s: enqueing INSERTION event\n", 702 device_xname(h->ph_parent))); 703 pcic_queue_event(h, PCIC_EVENT_INSERTION); 704 } 705 h->laststate = PCIC_LASTSTATE_PRESENT; 706 } else { 707 if (h->laststate == PCIC_LASTSTATE_PRESENT) { 708 /* Deactivate the card now. */ 709 DPRINTF(("%s: deactivating card\n", 710 device_xname(h->ph_parent))); 711 pcic_deactivate_card(h); 712 713 DPRINTF(("%s: enqueing REMOVAL event\n", 714 device_xname(h->ph_parent))); 715 pcic_queue_event(h, PCIC_EVENT_REMOVAL); 716 } 717 h->laststate = PCIC_LASTSTATE_EMPTY; 718 } 719 } 720 if (cscreg & PCIC_CSC_READY) { 721 DPRINTF(("%s: %02x READY\n", device_xname(h->ph_parent), 722 h->sock)); 723 /* shouldn't happen */ 724 } 725 if (cscreg & PCIC_CSC_BATTWARN) { 726 DPRINTF(("%s: %02x BATTWARN\n", device_xname(h->ph_parent), 727 h->sock)); 728 } 729 if (cscreg & PCIC_CSC_BATTDEAD) { 730 DPRINTF(("%s: %02x BATTDEAD\n", device_xname(h->ph_parent), 731 h->sock)); 732 } 733 return cscreg ? 1 : 0; 734 } 735 736 void 737 pcic_queue_event(struct pcic_handle *h, int event) 738 { 739 struct pcic_event *pe; 740 int s; 741 742 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 743 if (pe == NULL) 744 panic("pcic_queue_event: can't allocate event"); 745 746 pe->pe_type = event; 747 s = splhigh(); 748 SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 749 splx(s); 750 wakeup(&h->events); 751 } 752 753 void 754 pcic_attach_card(struct pcic_handle *h) 755 { 756 757 if ((h->flags & PCIC_FLAG_CARDP) == 0) { 758 /* call the MI attach function */ 759 pcmcia_card_attach(h->pcmcia); 760 761 h->flags |= PCIC_FLAG_CARDP; 762 } else { 763 DPRINTF(("pcic_attach_card: already attached")); 764 } 765 } 766 767 void 768 pcic_detach_card(struct pcic_handle *h, int flags) 769 /* flags: DETACH_* */ 770 { 771 772 if (h->flags & PCIC_FLAG_CARDP) { 773 h->flags &= ~PCIC_FLAG_CARDP; 774 775 /* call the MI detach function */ 776 pcmcia_card_detach(h->pcmcia, flags); 777 } else { 778 DPRINTF(("pcic_detach_card: already detached")); 779 } 780 } 781 782 void 783 pcic_deactivate_card(struct pcic_handle *h) 784 { 785 int intr; 786 787 /* call the MI deactivate function */ 788 pcmcia_card_deactivate(h->pcmcia); 789 790 /* reset the socket */ 791 intr = pcic_read(h, PCIC_INTR); 792 intr &= PCIC_INTR_ENABLE; 793 pcic_write(h, PCIC_INTR, intr); 794 795 /* power down the socket */ 796 pcic_write(h, PCIC_PWRCTL, 0); 797 } 798 799 int 800 pcic_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 801 struct pcmcia_mem_handle *pcmhp) 802 { 803 struct pcic_handle *h = (struct pcic_handle *) pch; 804 bus_space_handle_t memh; 805 bus_addr_t addr; 806 bus_size_t sizepg; 807 int i, mask, mhandle; 808 struct pcic_softc *sc = device_private(h->ph_parent); 809 810 /* out of sc->memh, allocate as many pages as necessary */ 811 812 /* convert size to PCIC pages */ 813 sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN; 814 if (sizepg > PCIC_MAX_MEM_PAGES) 815 return 1; 816 817 mask = (1 << sizepg) - 1; 818 819 addr = 0; /* XXX gcc -Wuninitialized */ 820 mhandle = 0; /* XXX gcc -Wuninitialized */ 821 822 for (i = 0; i <= PCIC_MAX_MEM_PAGES - sizepg; i++) { 823 if ((sc->subregionmask & (mask << i)) == (mask << i)) { 824 if (bus_space_subregion(sc->memt, sc->memh, 825 i * PCIC_MEM_PAGESIZE, 826 sizepg * PCIC_MEM_PAGESIZE, &memh)) 827 return 1; 828 mhandle = mask << i; 829 addr = sc->membase + (i * PCIC_MEM_PAGESIZE); 830 sc->subregionmask &= ~(mhandle); 831 pcmhp->memt = sc->memt; 832 pcmhp->memh = memh; 833 pcmhp->addr = addr; 834 pcmhp->size = size; 835 pcmhp->mhandle = mhandle; 836 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 837 return 0; 838 } 839 } 840 841 return 1; 842 } 843 844 void 845 pcic_chip_mem_free(pcmcia_chipset_handle_t pch, struct pcmcia_mem_handle *pcmhp) 846 { 847 struct pcic_handle *h = (struct pcic_handle *) pch; 848 struct pcic_softc *sc = device_private(h->ph_parent); 849 850 sc->subregionmask |= pcmhp->mhandle; 851 } 852 853 static const struct mem_map_index_st { 854 int sysmem_start_lsb; 855 int sysmem_start_msb; 856 int sysmem_stop_lsb; 857 int sysmem_stop_msb; 858 int cardmem_lsb; 859 int cardmem_msb; 860 int memenable; 861 } mem_map_index[] = { 862 { 863 PCIC_SYSMEM_ADDR0_START_LSB, 864 PCIC_SYSMEM_ADDR0_START_MSB, 865 PCIC_SYSMEM_ADDR0_STOP_LSB, 866 PCIC_SYSMEM_ADDR0_STOP_MSB, 867 PCIC_CARDMEM_ADDR0_LSB, 868 PCIC_CARDMEM_ADDR0_MSB, 869 PCIC_ADDRWIN_ENABLE_MEM0, 870 }, 871 { 872 PCIC_SYSMEM_ADDR1_START_LSB, 873 PCIC_SYSMEM_ADDR1_START_MSB, 874 PCIC_SYSMEM_ADDR1_STOP_LSB, 875 PCIC_SYSMEM_ADDR1_STOP_MSB, 876 PCIC_CARDMEM_ADDR1_LSB, 877 PCIC_CARDMEM_ADDR1_MSB, 878 PCIC_ADDRWIN_ENABLE_MEM1, 879 }, 880 { 881 PCIC_SYSMEM_ADDR2_START_LSB, 882 PCIC_SYSMEM_ADDR2_START_MSB, 883 PCIC_SYSMEM_ADDR2_STOP_LSB, 884 PCIC_SYSMEM_ADDR2_STOP_MSB, 885 PCIC_CARDMEM_ADDR2_LSB, 886 PCIC_CARDMEM_ADDR2_MSB, 887 PCIC_ADDRWIN_ENABLE_MEM2, 888 }, 889 { 890 PCIC_SYSMEM_ADDR3_START_LSB, 891 PCIC_SYSMEM_ADDR3_START_MSB, 892 PCIC_SYSMEM_ADDR3_STOP_LSB, 893 PCIC_SYSMEM_ADDR3_STOP_MSB, 894 PCIC_CARDMEM_ADDR3_LSB, 895 PCIC_CARDMEM_ADDR3_MSB, 896 PCIC_ADDRWIN_ENABLE_MEM3, 897 }, 898 { 899 PCIC_SYSMEM_ADDR4_START_LSB, 900 PCIC_SYSMEM_ADDR4_START_MSB, 901 PCIC_SYSMEM_ADDR4_STOP_LSB, 902 PCIC_SYSMEM_ADDR4_STOP_MSB, 903 PCIC_CARDMEM_ADDR4_LSB, 904 PCIC_CARDMEM_ADDR4_MSB, 905 PCIC_ADDRWIN_ENABLE_MEM4, 906 }, 907 }; 908 909 void 910 pcic_chip_do_mem_map(struct pcic_handle *h, int win) 911 { 912 int reg; 913 int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 914 int mem8 = 915 (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 916 || (kind == PCMCIA_MEM_ATTR); 917 918 DPRINTF(("mem8 %d\n", mem8)); 919 /* mem8 = 1; */ 920 921 pcic_write(h, mem_map_index[win].sysmem_start_lsb, 922 (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 923 pcic_write(h, mem_map_index[win].sysmem_start_msb, 924 ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 925 PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK) | 926 (mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT)); 927 928 pcic_write(h, mem_map_index[win].sysmem_stop_lsb, 929 ((h->mem[win].addr + h->mem[win].size) >> 930 PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 931 pcic_write(h, mem_map_index[win].sysmem_stop_msb, 932 (((h->mem[win].addr + h->mem[win].size) >> 933 (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 934 PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) | 935 PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2); 936 937 pcic_write(h, mem_map_index[win].cardmem_lsb, 938 (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff); 939 pcic_write(h, mem_map_index[win].cardmem_msb, 940 ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) & 941 PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) | 942 ((kind == PCMCIA_MEM_ATTR) ? 943 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0)); 944 945 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 946 reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16); 947 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 948 949 delay(100); 950 951 #ifdef PCICDEBUG 952 { 953 int r1, r2, r3, r4, r5, r6; 954 955 r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb); 956 r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb); 957 r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb); 958 r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb); 959 r5 = pcic_read(h, mem_map_index[win].cardmem_msb); 960 r6 = pcic_read(h, mem_map_index[win].cardmem_lsb); 961 962 DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x " 963 "%02x%02x\n", win, r1, r2, r3, r4, r5, r6)); 964 } 965 #endif 966 } 967 968 int 969 pcic_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, bus_addr_t card_addr, 970 bus_size_t size, struct pcmcia_mem_handle *pcmhp, bus_size_t *offsetp, 971 int *windowp) 972 { 973 struct pcic_handle *h = (struct pcic_handle *) pch; 974 bus_addr_t busaddr; 975 long card_offset; 976 int i, win; 977 978 win = -1; 979 for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0])); 980 i++) { 981 if ((h->memalloc & (1 << i)) == 0) { 982 win = i; 983 h->memalloc |= (1 << i); 984 break; 985 } 986 } 987 988 if (win == -1) 989 return 1; 990 991 *windowp = win; 992 993 /* XXX this is pretty gross */ 994 995 { 996 struct pcic_softc *sc = device_private(h->ph_parent); 997 if (!bus_space_is_equal(sc->memt, pcmhp->memt)) 998 panic("pcic_chip_mem_map memt is bogus"); 999 } 1000 1001 busaddr = pcmhp->addr; 1002 1003 /* 1004 * compute the address offset to the pcmcia address space for the 1005 * pcic. this is intentionally signed. The masks and shifts below 1006 * will cause TRT to happen in the pcic registers. Deal with making 1007 * sure the address is aligned, and return the alignment offset. 1008 */ 1009 1010 *offsetp = card_addr % PCIC_MEM_ALIGN; 1011 card_addr -= *offsetp; 1012 1013 DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 1014 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 1015 (u_long) card_addr)); 1016 1017 /* 1018 * include the offset in the size, and decrement size by one, since 1019 * the hw wants start/stop 1020 */ 1021 size += *offsetp - 1; 1022 1023 card_offset = (((long) card_addr) - ((long) busaddr)); 1024 1025 h->mem[win].addr = busaddr; 1026 h->mem[win].size = size; 1027 h->mem[win].offset = card_offset; 1028 h->mem[win].kind = kind; 1029 1030 pcic_chip_do_mem_map(h, win); 1031 1032 return 0; 1033 } 1034 1035 void 1036 pcic_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 1037 { 1038 struct pcic_handle *h = (struct pcic_handle *) pch; 1039 int reg; 1040 1041 if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0]))) 1042 panic("pcic_chip_mem_unmap: window out of range"); 1043 1044 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1045 reg &= ~mem_map_index[window].memenable; 1046 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1047 1048 h->memalloc &= ~(1 << window); 1049 } 1050 1051 int 1052 pcic_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1053 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1054 { 1055 struct pcic_handle *h = (struct pcic_handle *) pch; 1056 bus_space_tag_t iot; 1057 bus_space_handle_t ioh; 1058 bus_addr_t ioaddr; 1059 int flags = 0; 1060 struct pcic_softc *sc = device_private(h->ph_parent); 1061 1062 /* 1063 * Allocate some arbitrary I/O space. 1064 */ 1065 1066 iot = sc->iot; 1067 1068 if (start) { 1069 ioaddr = start; 1070 if (bus_space_map(iot, start, size, 0, &ioh)) 1071 return 1; 1072 DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n", 1073 (u_long) ioaddr, (u_long) size)); 1074 } else { 1075 flags |= PCMCIA_IO_ALLOCATED; 1076 if (bus_space_alloc(iot, sc->iobase, 1077 sc->iobase + sc->iosize, size, align, 0, 0, 1078 &ioaddr, &ioh)) 1079 return 1; 1080 DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n", 1081 (u_long) ioaddr, (u_long) size)); 1082 } 1083 1084 pcihp->iot = iot; 1085 pcihp->ioh = ioh; 1086 pcihp->addr = ioaddr; 1087 pcihp->size = size; 1088 pcihp->flags = flags; 1089 1090 return 0; 1091 } 1092 1093 void 1094 pcic_chip_io_free(pcmcia_chipset_handle_t pch, struct pcmcia_io_handle *pcihp) 1095 { 1096 bus_space_tag_t iot = pcihp->iot; 1097 bus_space_handle_t ioh = pcihp->ioh; 1098 bus_size_t size = pcihp->size; 1099 1100 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1101 bus_space_free(iot, ioh, size); 1102 else 1103 bus_space_unmap(iot, ioh, size); 1104 } 1105 1106 1107 static const struct io_map_index_st { 1108 int start_lsb; 1109 int start_msb; 1110 int stop_lsb; 1111 int stop_msb; 1112 int ioenable; 1113 int ioctlmask; 1114 int ioctlbits[3]; /* indexed by PCMCIA_WIDTH_* */ 1115 } io_map_index[] = { 1116 { 1117 PCIC_IOADDR0_START_LSB, 1118 PCIC_IOADDR0_START_MSB, 1119 PCIC_IOADDR0_STOP_LSB, 1120 PCIC_IOADDR0_STOP_MSB, 1121 PCIC_ADDRWIN_ENABLE_IO0, 1122 PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1123 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK, 1124 { 1125 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1126 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1127 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1128 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1129 PCIC_IOCTL_IO0_DATASIZE_16BIT, 1130 }, 1131 }, 1132 { 1133 PCIC_IOADDR1_START_LSB, 1134 PCIC_IOADDR1_START_MSB, 1135 PCIC_IOADDR1_STOP_LSB, 1136 PCIC_IOADDR1_STOP_MSB, 1137 PCIC_ADDRWIN_ENABLE_IO1, 1138 PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1139 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK, 1140 { 1141 PCIC_IOCTL_IO1_IOCS16SRC_CARD, 1142 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1143 PCIC_IOCTL_IO1_DATASIZE_8BIT, 1144 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1145 PCIC_IOCTL_IO1_DATASIZE_16BIT, 1146 }, 1147 }, 1148 }; 1149 1150 void 1151 pcic_chip_do_io_map(struct pcic_handle *h, int win) 1152 { 1153 int reg; 1154 1155 DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1156 win, (long) h->io[win].addr, (long) h->io[win].size, 1157 h->io[win].width * 8)); 1158 1159 pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff); 1160 pcic_write(h, io_map_index[win].start_msb, 1161 (h->io[win].addr >> 8) & 0xff); 1162 1163 pcic_write(h, io_map_index[win].stop_lsb, 1164 (h->io[win].addr + h->io[win].size - 1) & 0xff); 1165 pcic_write(h, io_map_index[win].stop_msb, 1166 ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff); 1167 1168 reg = pcic_read(h, PCIC_IOCTL); 1169 reg &= ~io_map_index[win].ioctlmask; 1170 reg |= io_map_index[win].ioctlbits[h->io[win].width]; 1171 pcic_write(h, PCIC_IOCTL, reg); 1172 1173 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1174 reg |= io_map_index[win].ioenable; 1175 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1176 } 1177 1178 int 1179 pcic_chip_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 1180 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 1181 { 1182 struct pcic_handle *h = (struct pcic_handle *) pch; 1183 bus_addr_t ioaddr = pcihp->addr + offset; 1184 int i, win; 1185 #ifdef PCICDEBUG 1186 static const char *width_names[] = { "auto", "io8", "io16" }; 1187 #endif 1188 struct pcic_softc *sc = device_private(h->ph_parent); 1189 1190 /* XXX Sanity check offset/size. */ 1191 1192 win = -1; 1193 for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) { 1194 if ((h->ioalloc & (1 << i)) == 0) { 1195 win = i; 1196 h->ioalloc |= (1 << i); 1197 break; 1198 } 1199 } 1200 1201 if (win == -1) 1202 return 1; 1203 1204 *windowp = win; 1205 1206 /* XXX this is pretty gross */ 1207 1208 if (!bus_space_is_equal(sc->iot, pcihp->iot)) 1209 panic("pcic_chip_io_map iot is bogus"); 1210 1211 DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n", 1212 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1213 1214 /* XXX wtf is this doing here? */ 1215 1216 printf("%s: port 0x%lx", device_xname(&sc->dev), (u_long) ioaddr); 1217 if (size > 1) 1218 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1219 printf("\n"); 1220 1221 h->io[win].addr = ioaddr; 1222 h->io[win].size = size; 1223 h->io[win].width = width; 1224 1225 pcic_chip_do_io_map(h, win); 1226 1227 return 0; 1228 } 1229 1230 void 1231 pcic_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 1232 { 1233 struct pcic_handle *h = (struct pcic_handle *) pch; 1234 int reg; 1235 1236 if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0]))) 1237 panic("pcic_chip_io_unmap: window out of range"); 1238 1239 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1240 reg &= ~io_map_index[window].ioenable; 1241 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1242 1243 h->ioalloc &= ~(1 << window); 1244 } 1245 1246 static int 1247 pcic_wait_ready(struct pcic_handle *h) 1248 { 1249 uint8_t stat; 1250 int i; 1251 1252 /* wait an initial 10ms for quick cards */ 1253 stat = pcic_read(h, PCIC_IF_STATUS); 1254 if (stat & PCIC_IF_STATUS_READY) 1255 return 0; 1256 pcic_delay(h, 10, "pccwr0"); 1257 for (i = 0; i < 50; i++) { 1258 stat = pcic_read(h, PCIC_IF_STATUS); 1259 if (stat & PCIC_IF_STATUS_READY) 1260 return 0; 1261 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 1262 PCIC_IF_STATUS_CARDDETECT_PRESENT) 1263 return ENXIO; 1264 /* wait .1s (100ms) each iteration now */ 1265 pcic_delay(h, 100, "pccwr1"); 1266 } 1267 1268 printf("pcic_wait_ready: ready never happened, status=%02x\n", stat); 1269 return EWOULDBLOCK; 1270 } 1271 1272 /* 1273 * Perform long (msec order) delay. 1274 */ 1275 static void 1276 pcic_delay(struct pcic_handle *h, int timo, const char *wmesg) 1277 /* timo: in ms. must not be zero */ 1278 { 1279 1280 #ifdef DIAGNOSTIC 1281 if (timo <= 0) 1282 panic("pcic_delay: called with timeout %d", timo); 1283 if (!curlwp) 1284 panic("pcic_delay: called in interrupt context"); 1285 if (!h->event_thread) 1286 panic("pcic_delay: no event thread"); 1287 #endif 1288 DPRINTF(("pcic_delay: \"%s\" %p, sleep %d ms\n", 1289 wmesg, h->event_thread, timo)); 1290 if (doing_shutdown) 1291 delay(timo * 1000); 1292 else 1293 tsleep(pcic_delay, PWAIT, wmesg, 1294 roundup(timo * hz, 1000) / 1000); 1295 } 1296 1297 void 1298 pcic_chip_socket_enable(pcmcia_chipset_handle_t pch) 1299 { 1300 struct pcic_handle *h = (struct pcic_handle *) pch; 1301 int win; 1302 uint8_t power, intr; 1303 #ifdef DIAGNOSTIC 1304 int reg; 1305 #endif 1306 1307 #ifdef DIAGNOSTIC 1308 if (h->flags & PCIC_FLAG_ENABLED) 1309 printf("pcic_chip_socket_enable: enabling twice\n"); 1310 #endif 1311 1312 /* disable interrupts; assert RESET */ 1313 intr = pcic_read(h, PCIC_INTR); 1314 intr &= PCIC_INTR_ENABLE; 1315 pcic_write(h, PCIC_INTR, intr); 1316 1317 /* zero out the address windows */ 1318 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1319 1320 /* power off; assert output enable bit */ 1321 power = PCIC_PWRCTL_OE; 1322 pcic_write(h, PCIC_PWRCTL, power); 1323 1324 /* 1325 * power hack for RICOH RF5C[23]96 1326 */ 1327 switch (h->vendor) { 1328 case PCIC_VENDOR_RICOH_5C296: 1329 case PCIC_VENDOR_RICOH_5C396: 1330 { 1331 int regtmp; 1332 regtmp = pcic_read(h, PCIC_RICOH_REG_MCR2); 1333 #ifdef RICOH_POWER_HACK 1334 regtmp |= PCIC_RICOH_MCR2_VCC_DIRECT; 1335 #else 1336 regtmp &= 1337 ~(PCIC_RICOH_MCR2_VCC_DIRECT|PCIC_RICOH_MCR2_VCC_SEL_3V); 1338 #endif 1339 pcic_write(h, PCIC_RICOH_REG_MCR2, regtmp); 1340 } 1341 break; 1342 default: 1343 break; 1344 } 1345 1346 #ifdef VADEM_POWER_HACK 1347 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x0e); 1348 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x37); 1349 printf("prcr = %02x\n", pcic_read(h, 0x02)); 1350 printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1351 printf("DANGER WILL ROBINSON! Changing voltage select!\n"); 1352 pcic_write(h, 0x2f, pcic_read(h, 0x2f) & ~0x03); 1353 printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1354 #endif 1355 1356 /* power up the socket */ 1357 power |= PCIC_PWRCTL_PWR_ENABLE | PCIC_PWRCTL_VPP1_VCC; 1358 pcic_write(h, PCIC_PWRCTL, power); 1359 1360 /* 1361 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 1362 * Vcc Rising Time (Tpr) = 100ms 1363 * RESET Width (Th (Hi-z RESET)) = 1ms 1364 * RESET Width (Tw (RESET)) = 10us 1365 * 1366 * some machines require some more time to be settled 1367 * (100ms is added here). 1368 */ 1369 pcic_delay(h, 200 + 1, "pccen1"); 1370 1371 /* negate RESET */ 1372 intr |= PCIC_INTR_RESET; 1373 pcic_write(h, PCIC_INTR, intr); 1374 1375 /* 1376 * RESET Setup Time (Tsu (RESET)) = 20ms 1377 */ 1378 pcic_delay(h, 20, "pccen2"); 1379 1380 #ifdef DIAGNOSTIC 1381 reg = pcic_read(h, PCIC_IF_STATUS); 1382 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 1383 printf("pcic_chip_socket_enable: no power, status=%x\n", reg); 1384 #endif 1385 1386 /* wait for the chip to finish initializing */ 1387 if (pcic_wait_ready(h)) { 1388 /* XXX return a failure status?? */ 1389 pcic_write(h, PCIC_PWRCTL, 0); 1390 return; 1391 } 1392 1393 /* reinstall all the memory and io mappings */ 1394 for (win = 0; win < PCIC_MEM_WINS; win++) 1395 if (h->memalloc & (1 << win)) 1396 pcic_chip_do_mem_map(h, win); 1397 for (win = 0; win < PCIC_IO_WINS; win++) 1398 if (h->ioalloc & (1 << win)) 1399 pcic_chip_do_io_map(h, win); 1400 1401 h->flags |= PCIC_FLAG_ENABLED; 1402 } 1403 1404 void 1405 pcic_chip_socket_disable(pcmcia_chipset_handle_t pch) 1406 { 1407 struct pcic_handle *h = (struct pcic_handle *) pch; 1408 uint8_t intr; 1409 1410 DPRINTF(("pcic_chip_socket_disable\n")); 1411 1412 /* disable interrupts; assert RESET */ 1413 intr = pcic_read(h, PCIC_INTR); 1414 intr &= PCIC_INTR_ENABLE; 1415 pcic_write(h, PCIC_INTR, intr); 1416 1417 /* zero out the address windows */ 1418 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1419 1420 /* disable socket: negate output enable bit and power off */ 1421 pcic_write(h, PCIC_PWRCTL, 0); 1422 1423 /* 1424 * Vcc Falling Time (Tpf) = 300ms 1425 */ 1426 pcic_delay(h, 300, "pccwr1"); 1427 1428 h->flags &= ~PCIC_FLAG_ENABLED; 1429 } 1430 1431 void 1432 pcic_chip_socket_settype(pcmcia_chipset_handle_t pch, int type) 1433 { 1434 struct pcic_handle *h = (struct pcic_handle *) pch; 1435 int intr; 1436 1437 intr = pcic_read(h, PCIC_INTR); 1438 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 1439 if (type == PCMCIA_IFTYPE_IO) { 1440 intr |= PCIC_INTR_CARDTYPE_IO; 1441 intr |= h->ih_irq << PCIC_INTR_IRQ_SHIFT; 1442 } else 1443 intr |= PCIC_INTR_CARDTYPE_MEM; 1444 pcic_write(h, PCIC_INTR, intr); 1445 1446 DPRINTF(("%s: pcic_chip_socket_settype %02x type %s %02x\n", 1447 device_xname(h->ph_parent), h->sock, 1448 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 1449 } 1450 1451 static uint8_t 1452 st_pcic_read(struct pcic_handle *h, int idx) 1453 { 1454 1455 if (idx != -1) 1456 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1457 h->sock + idx); 1458 return bus_space_read_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA); 1459 } 1460 1461 static void 1462 st_pcic_write(struct pcic_handle *h, int idx, uint8_t data) 1463 { 1464 1465 if (idx != -1) 1466 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1467 h->sock + idx); 1468 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA, data); 1469 } 1470