1 /* $NetBSD: i82365.c,v 1.69 2002/11/24 02:46:55 takemura Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Christian E. Hopps. All rights reserved. 5 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Marc Horowitz. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: i82365.c,v 1.69 2002/11/24 02:46:55 takemura Exp $"); 35 36 #define PCICDEBUG 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <sys/extent.h> 42 #include <sys/kernel.h> 43 #include <sys/malloc.h> 44 #include <sys/kthread.h> 45 46 #include <machine/bus.h> 47 #include <machine/intr.h> 48 49 #include <dev/pcmcia/pcmciareg.h> 50 #include <dev/pcmcia/pcmciavar.h> 51 52 #include <dev/ic/i82365reg.h> 53 #include <dev/ic/i82365var.h> 54 55 #include "locators.h" 56 57 #ifdef PCICDEBUG 58 int pcic_debug = 0; 59 #define DPRINTF(arg) if (pcic_debug) printf arg; 60 #else 61 #define DPRINTF(arg) 62 #endif 63 64 /* 65 * Individual drivers will allocate their own memory and io regions. Memory 66 * regions must be a multiple of 4k, aligned on a 4k boundary. 67 */ 68 69 #define PCIC_MEM_ALIGN PCIC_MEM_PAGESIZE 70 71 void pcic_attach_socket __P((struct pcic_handle *)); 72 void pcic_attach_socket_finish __P((struct pcic_handle *)); 73 74 int pcic_submatch __P((struct device *, struct cfdata *, void *)); 75 int pcic_print __P((void *arg, const char *pnp)); 76 int pcic_intr_socket __P((struct pcic_handle *)); 77 void pcic_poll_intr __P((void *)); 78 79 void pcic_attach_card __P((struct pcic_handle *)); 80 void pcic_detach_card __P((struct pcic_handle *, int)); 81 void pcic_deactivate_card __P((struct pcic_handle *)); 82 83 void pcic_chip_do_mem_map __P((struct pcic_handle *, int)); 84 void pcic_chip_do_io_map __P((struct pcic_handle *, int)); 85 86 void pcic_create_event_thread __P((void *)); 87 void pcic_event_thread __P((void *)); 88 89 void pcic_queue_event __P((struct pcic_handle *, int)); 90 void pcic_power __P((int, void *)); 91 92 static void pcic_wait_ready __P((struct pcic_handle *)); 93 static void pcic_delay __P((struct pcic_handle *, int, const char *)); 94 95 static u_int8_t st_pcic_read __P((struct pcic_handle *, int)); 96 static void st_pcic_write __P((struct pcic_handle *, int, u_int8_t)); 97 98 int 99 pcic_ident_ok(ident) 100 int ident; 101 { 102 /* this is very empirical and heuristic */ 103 104 if ((ident == 0) || (ident == 0xff) || (ident & PCIC_IDENT_ZERO)) 105 return (0); 106 107 if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) { 108 #ifdef DIAGNOSTIC 109 printf("pcic: does not support memory and I/O cards, " 110 "ignored (ident=%0x)\n", ident); 111 #endif 112 return (0); 113 } 114 return (1); 115 } 116 117 int 118 pcic_vendor(h) 119 struct pcic_handle *h; 120 { 121 int reg; 122 int vendor; 123 124 /* 125 * the chip_id of the cirrus toggles between 11 and 00 after a write. 126 * weird. 127 */ 128 129 pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0); 130 reg = pcic_read(h, -1); 131 132 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 133 PCIC_CIRRUS_CHIP_INFO_CHIP_ID) { 134 reg = pcic_read(h, -1); 135 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) { 136 if (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS) 137 return (PCIC_VENDOR_CIRRUS_PD672X); 138 else 139 return (PCIC_VENDOR_CIRRUS_PD6710); 140 } 141 } 142 143 reg = pcic_read(h, PCIC_IDENT); 144 145 switch (reg) { 146 case PCIC_IDENT_ID_INTEL0: 147 vendor = PCIC_VENDOR_I82365SLR0; 148 break; 149 case PCIC_IDENT_ID_INTEL1: 150 vendor = PCIC_VENDOR_I82365SLR1; 151 break; 152 case PCIC_IDENT_ID_INTEL2: 153 vendor = PCIC_VENDOR_I82365SL_DF; 154 break; 155 case PCIC_IDENT_ID_IBM1: 156 case PCIC_IDENT_ID_IBM2: 157 vendor = PCIC_VENDOR_IBM; 158 break; 159 case PCIC_IDENT_ID_IBM3: 160 vendor = PCIC_VENDOR_IBM_KING; 161 break; 162 default: 163 vendor = PCIC_VENDOR_UNKNOWN; 164 break; 165 } 166 167 if (vendor == PCIC_VENDOR_I82365SLR0 || 168 vendor == PCIC_VENDOR_I82365SLR1) { 169 /* 170 * check for Ricoh RF5C[23]96 171 */ 172 reg = pcic_read(h, PCIC_RICOH_REG_CHIP_ID); 173 switch (reg) { 174 case PCIC_RICOH_CHIP_ID_5C296: 175 vendor = PCIC_VENDOR_RICOH_5C296; 176 break; 177 case PCIC_RICOH_CHIP_ID_5C396: 178 vendor = PCIC_VENDOR_RICOH_5C396; 179 break; 180 default: 181 break; 182 } 183 } 184 185 return ( vendor ); 186 } 187 188 char * 189 pcic_vendor_to_string(vendor) 190 int vendor; 191 { 192 switch (vendor) { 193 case PCIC_VENDOR_I82365SLR0: 194 return ("Intel 82365SL Revision 0"); 195 case PCIC_VENDOR_I82365SLR1: 196 return ("Intel 82365SL Revision 1"); 197 case PCIC_VENDOR_CIRRUS_PD6710: 198 return ("Cirrus PD6710"); 199 case PCIC_VENDOR_CIRRUS_PD672X: 200 return ("Cirrus PD672X"); 201 case PCIC_VENDOR_I82365SL_DF: 202 return ("Intel 82365SL-DF"); 203 case PCIC_VENDOR_RICOH_5C296: 204 return ("Ricoh RF5C296"); 205 case PCIC_VENDOR_RICOH_5C396: 206 return ("Ricoh RF5C396"); 207 case PCIC_VENDOR_IBM: 208 return ("IBM PCIC"); 209 case PCIC_VENDOR_IBM_KING: 210 return ("IBM KING"); 211 } 212 213 return ("Unknown controller"); 214 } 215 216 void 217 pcic_attach(sc) 218 struct pcic_softc *sc; 219 { 220 int i, reg, chip, socket, intr; 221 struct pcic_handle *h; 222 223 DPRINTF(("pcic ident regs:")); 224 225 lockinit(&sc->sc_pcic_lock, PWAIT, "pciclk", 0, 0); 226 227 /* find and configure for the available sockets */ 228 for (i = 0; i < PCIC_NSLOTS; i++) { 229 h = &sc->handle[i]; 230 chip = i / 2; 231 socket = i % 2; 232 233 h->ph_parent = (struct device *)sc; 234 h->chip = chip; 235 h->sock = chip * PCIC_CHIP_OFFSET + socket * PCIC_SOCKET_OFFSET; 236 h->laststate = PCIC_LASTSTATE_EMPTY; 237 /* initialize pcic_read and pcic_write functions */ 238 h->ph_read = st_pcic_read; 239 h->ph_write = st_pcic_write; 240 h->ph_bus_t = sc->iot; 241 h->ph_bus_h = sc->ioh; 242 243 /* need to read vendor -- for cirrus to report no xtra chip */ 244 if (socket == 0) 245 h->vendor = (h+1)->vendor = pcic_vendor(h); 246 247 /* 248 * During the socket probe, read the ident register twice. 249 * I don't understand why, but sometimes the clone chips 250 * in hpcmips boxes read all-0s the first time. -- mycroft 251 */ 252 reg = pcic_read(h, PCIC_IDENT); 253 reg = pcic_read(h, PCIC_IDENT); 254 DPRINTF(("ident reg 0x%02x\n", reg)); 255 if (pcic_ident_ok(reg)) 256 h->flags = PCIC_FLAG_SOCKETP; 257 else 258 h->flags = 0; 259 } 260 261 for (i = 0; i < PCIC_NSLOTS; i++) { 262 h = &sc->handle[i]; 263 264 if (h->flags & PCIC_FLAG_SOCKETP) { 265 SIMPLEQ_INIT(&h->events); 266 267 /* disable interrupts -- for now */ 268 pcic_write(h, PCIC_CSC_INTR, 0); 269 intr = pcic_read(h, PCIC_INTR); 270 DPRINTF(("intr was 0x%02x\n", intr)); 271 intr &= ~(PCIC_INTR_RI_ENABLE | PCIC_INTR_ENABLE | 272 PCIC_INTR_IRQ_MASK); 273 pcic_write(h, PCIC_INTR, intr); 274 (void) pcic_read(h, PCIC_CSC); 275 } 276 } 277 278 /* print detected info */ 279 for (i = 0; i < PCIC_NSLOTS; i += 2) { 280 h = &sc->handle[i]; 281 chip = i / 2; 282 283 printf("%s: controller %d (%s) has ", sc->dev.dv_xname, chip, 284 pcic_vendor_to_string(sc->handle[i].vendor)); 285 286 if ((h->flags & PCIC_FLAG_SOCKETP) && 287 ((h+1)->flags & PCIC_FLAG_SOCKETP)) 288 printf("sockets A and B\n"); 289 else if (h->flags & PCIC_FLAG_SOCKETP) 290 printf("socket A only\n"); 291 else if ((h+1)->flags & PCIC_FLAG_SOCKETP) 292 printf("socket B only\n"); 293 else 294 printf("no sockets\n"); 295 } 296 } 297 298 /* 299 * attach the sockets before we know what interrupts we have 300 */ 301 void 302 pcic_attach_sockets(sc) 303 struct pcic_softc *sc; 304 { 305 int i; 306 307 for (i = 0; i < PCIC_NSLOTS; i++) 308 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 309 pcic_attach_socket(&sc->handle[i]); 310 } 311 312 void 313 pcic_power(why, arg) 314 int why; 315 void *arg; 316 { 317 struct pcic_handle *h = (struct pcic_handle *)arg; 318 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 319 int reg; 320 321 DPRINTF(("%s: power: why %d\n", h->ph_parent->dv_xname, why)); 322 323 if (h->flags & PCIC_FLAG_SOCKETP) { 324 if ((why == PWR_RESUME) && 325 (pcic_read(h, PCIC_CSC_INTR) == 0)) { 326 #ifdef PCICDEBUG 327 char bitbuf[64]; 328 #endif 329 reg = PCIC_CSC_INTR_CD_ENABLE; 330 if (sc->irq != -1) 331 reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT; 332 pcic_write(h, PCIC_CSC_INTR, reg); 333 DPRINTF(("%s: CSC_INTR was zero; reset to %s\n", 334 sc->dev.dv_xname, 335 bitmask_snprintf(pcic_read(h, PCIC_CSC_INTR), 336 PCIC_CSC_INTR_FORMAT, 337 bitbuf, sizeof(bitbuf)))); 338 } 339 340 /* 341 * check for card insertion or removal during suspend period. 342 * XXX: the code can't cope with card swap (remove then insert). 343 * how can we detect such situation? 344 */ 345 if (why == PWR_RESUME) 346 (void)pcic_intr_socket(h); 347 } 348 } 349 350 351 /* 352 * attach a socket -- we don't know about irqs yet 353 */ 354 void 355 pcic_attach_socket(h) 356 struct pcic_handle *h; 357 { 358 struct pcmciabus_attach_args paa; 359 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 360 361 /* initialize the rest of the handle */ 362 363 h->shutdown = 0; 364 h->memalloc = 0; 365 h->ioalloc = 0; 366 h->ih_irq = 0; 367 368 /* now, config one pcmcia device per socket */ 369 370 paa.paa_busname = "pcmcia"; 371 paa.pct = (pcmcia_chipset_tag_t) sc->pct; 372 paa.pch = (pcmcia_chipset_handle_t) h; 373 paa.iobase = sc->iobase; 374 paa.iosize = sc->iosize; 375 376 h->pcmcia = config_found_sm(&sc->dev, &paa, pcic_print, pcic_submatch); 377 if (h->pcmcia == NULL) { 378 h->flags &= ~PCIC_FLAG_SOCKETP; 379 return; 380 } 381 382 /* 383 * queue creation of a kernel thread to handle insert/removal events. 384 */ 385 #ifdef DIAGNOSTIC 386 if (h->event_thread != NULL) 387 panic("pcic_attach_socket: event thread"); 388 #endif 389 config_pending_incr(); 390 kthread_create(pcic_create_event_thread, h); 391 } 392 393 /* 394 * now finish attaching the sockets, we are ready to allocate 395 * interrupts 396 */ 397 void 398 pcic_attach_sockets_finish(sc) 399 struct pcic_softc *sc; 400 { 401 int i; 402 403 for (i = 0; i < PCIC_NSLOTS; i++) 404 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 405 pcic_attach_socket_finish(&sc->handle[i]); 406 } 407 408 /* 409 * finishing attaching the socket. Interrupts may now be on 410 * if so expects the pcic interrupt to be blocked 411 */ 412 void 413 pcic_attach_socket_finish(h) 414 struct pcic_handle *h; 415 { 416 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 417 int reg, intr; 418 419 DPRINTF(("%s: attach finish socket %ld\n", h->ph_parent->dv_xname, 420 (long) (h - &sc->handle[0]))); 421 422 /* 423 * Set up a powerhook to ensure it continues to interrupt on 424 * card detect even after suspend. 425 * (this works around a bug seen in suspend-to-disk on the 426 * Sony VAIO Z505; on resume, the CSC_INTR state is not preserved). 427 */ 428 powerhook_establish(pcic_power, h); 429 430 /* enable interrupts on card detect, poll for them if no irq avail */ 431 reg = PCIC_CSC_INTR_CD_ENABLE; 432 if (sc->irq == -1) { 433 if (sc->poll_established == 0) { 434 callout_init(&sc->poll_ch); 435 callout_reset(&sc->poll_ch, hz / 2, pcic_poll_intr, sc); 436 sc->poll_established = 1; 437 } 438 } else 439 reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT; 440 pcic_write(h, PCIC_CSC_INTR, reg); 441 442 /* steer above mgmt interrupt to configured place */ 443 intr = pcic_read(h, PCIC_INTR); 444 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE); 445 pcic_write(h, PCIC_INTR, intr); 446 447 /* power down the socket */ 448 pcic_write(h, PCIC_PWRCTL, 0); 449 450 /* zero out the address windows */ 451 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 452 453 /* clear possible card detect interrupt */ 454 pcic_read(h, PCIC_CSC); 455 456 DPRINTF(("%s: attach finish vendor 0x%02x\n", h->ph_parent->dv_xname, 457 h->vendor)); 458 459 /* unsleep the cirrus controller */ 460 if ((h->vendor == PCIC_VENDOR_CIRRUS_PD6710) || 461 (h->vendor == PCIC_VENDOR_CIRRUS_PD672X)) { 462 reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2); 463 if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) { 464 DPRINTF(("%s: socket %02x was suspended\n", 465 h->ph_parent->dv_xname, h->sock)); 466 reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND; 467 pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg); 468 } 469 } 470 471 /* if there's a card there, then attach it. */ 472 reg = pcic_read(h, PCIC_IF_STATUS); 473 if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) == 474 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 475 pcic_queue_event(h, PCIC_EVENT_INSERTION); 476 h->laststate = PCIC_LASTSTATE_PRESENT; 477 } else { 478 h->laststate = PCIC_LASTSTATE_EMPTY; 479 } 480 } 481 482 void 483 pcic_create_event_thread(arg) 484 void *arg; 485 { 486 struct pcic_handle *h = arg; 487 const char *cs; 488 489 switch (h->sock) { 490 case C0SA: 491 cs = "0,0"; 492 break; 493 case C0SB: 494 cs = "0,1"; 495 break; 496 case C1SA: 497 cs = "1,0"; 498 break; 499 case C1SB: 500 cs = "1,1"; 501 break; 502 default: 503 panic("pcic_create_event_thread: unknown pcic socket"); 504 } 505 506 if (kthread_create1(pcic_event_thread, h, &h->event_thread, 507 "%s,%s", h->ph_parent->dv_xname, cs)) { 508 printf("%s: unable to create event thread for sock 0x%02x\n", 509 h->ph_parent->dv_xname, h->sock); 510 panic("pcic_create_event_thread"); 511 } 512 } 513 514 void 515 pcic_event_thread(arg) 516 void *arg; 517 { 518 struct pcic_handle *h = arg; 519 struct pcic_event *pe; 520 int s, first = 1; 521 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 522 523 while (h->shutdown == 0) { 524 /* 525 * Serialize event processing on the PCIC. We may 526 * sleep while we hold this lock. 527 */ 528 (void) lockmgr(&sc->sc_pcic_lock, LK_EXCLUSIVE, NULL); 529 530 s = splhigh(); 531 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 532 splx(s); 533 if (first) { 534 first = 0; 535 config_pending_decr(); 536 } 537 /* 538 * No events to process; release the PCIC lock. 539 */ 540 (void) lockmgr(&sc->sc_pcic_lock, LK_RELEASE, NULL); 541 (void) tsleep(&h->events, PWAIT, "pcicev", 0); 542 continue; 543 } else { 544 splx(s); 545 /* sleep .25s to be enqueued chatterling interrupts */ 546 (void) tsleep((caddr_t)pcic_event_thread, PWAIT, 547 "pcicss", hz/4); 548 } 549 s = splhigh(); 550 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 551 splx(s); 552 553 switch (pe->pe_type) { 554 case PCIC_EVENT_INSERTION: 555 s = splhigh(); 556 while (1) { 557 struct pcic_event *pe1, *pe2; 558 559 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 560 break; 561 if (pe1->pe_type != PCIC_EVENT_REMOVAL) 562 break; 563 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 564 break; 565 if (pe2->pe_type == PCIC_EVENT_INSERTION) { 566 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 567 free(pe1, M_TEMP); 568 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 569 free(pe2, M_TEMP); 570 } 571 } 572 splx(s); 573 574 DPRINTF(("%s: insertion event\n", 575 h->ph_parent->dv_xname)); 576 pcic_attach_card(h); 577 break; 578 579 case PCIC_EVENT_REMOVAL: 580 s = splhigh(); 581 while (1) { 582 struct pcic_event *pe1, *pe2; 583 584 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 585 break; 586 if (pe1->pe_type != PCIC_EVENT_INSERTION) 587 break; 588 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 589 break; 590 if (pe2->pe_type == PCIC_EVENT_REMOVAL) { 591 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 592 free(pe1, M_TEMP); 593 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 594 free(pe2, M_TEMP); 595 } 596 } 597 splx(s); 598 599 DPRINTF(("%s: removal event\n", 600 h->ph_parent->dv_xname)); 601 pcic_detach_card(h, DETACH_FORCE); 602 break; 603 604 default: 605 panic("pcic_event_thread: unknown event %d", 606 pe->pe_type); 607 } 608 free(pe, M_TEMP); 609 610 (void) lockmgr(&sc->sc_pcic_lock, LK_RELEASE, NULL); 611 } 612 613 h->event_thread = NULL; 614 615 /* In case parent is waiting for us to exit. */ 616 wakeup(sc); 617 618 kthread_exit(0); 619 } 620 621 int 622 pcic_submatch(parent, cf, aux) 623 struct device *parent; 624 struct cfdata *cf; 625 void *aux; 626 { 627 628 struct pcmciabus_attach_args *paa = aux; 629 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 630 631 switch (h->sock) { 632 case C0SA: 633 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 634 PCMCIABUSCF_CONTROLLER_DEFAULT && 635 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 636 return 0; 637 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 638 PCMCIABUSCF_SOCKET_DEFAULT && 639 cf->cf_loc[PCMCIABUSCF_SOCKET] != 0) 640 return 0; 641 642 break; 643 case C0SB: 644 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 645 PCMCIABUSCF_CONTROLLER_DEFAULT && 646 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 647 return 0; 648 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 649 PCMCIABUSCF_SOCKET_DEFAULT && 650 cf->cf_loc[PCMCIABUSCF_SOCKET] != 1) 651 return 0; 652 653 break; 654 case C1SA: 655 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 656 PCMCIABUSCF_CONTROLLER_DEFAULT && 657 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 658 return 0; 659 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 660 PCMCIABUSCF_SOCKET_DEFAULT && 661 cf->cf_loc[PCMCIABUSCF_SOCKET] != 0) 662 return 0; 663 664 break; 665 case C1SB: 666 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 667 PCMCIABUSCF_CONTROLLER_DEFAULT && 668 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 669 return 0; 670 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 671 PCMCIABUSCF_SOCKET_DEFAULT && 672 cf->cf_loc[PCMCIABUSCF_SOCKET] != 1) 673 return 0; 674 675 break; 676 default: 677 panic("unknown pcic socket"); 678 } 679 680 return (config_match(parent, cf, aux)); 681 } 682 683 int 684 pcic_print(arg, pnp) 685 void *arg; 686 const char *pnp; 687 { 688 struct pcmciabus_attach_args *paa = arg; 689 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 690 691 /* Only "pcmcia"s can attach to "pcic"s... easy. */ 692 if (pnp) 693 printf("pcmcia at %s", pnp); 694 695 switch (h->sock) { 696 case C0SA: 697 printf(" controller 0 socket 0"); 698 break; 699 case C0SB: 700 printf(" controller 0 socket 1"); 701 break; 702 case C1SA: 703 printf(" controller 1 socket 0"); 704 break; 705 case C1SB: 706 printf(" controller 1 socket 1"); 707 break; 708 default: 709 panic("unknown pcic socket"); 710 } 711 712 return (UNCONF); 713 } 714 715 void 716 pcic_poll_intr(arg) 717 void *arg; 718 { 719 struct pcic_softc *sc; 720 int i, s; 721 722 s = spltty(); 723 sc = arg; 724 for (i = 0; i < PCIC_NSLOTS; i++) 725 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 726 (void)pcic_intr_socket(&sc->handle[i]); 727 callout_reset(&sc->poll_ch, hz / 2, pcic_poll_intr, sc); 728 splx(s); 729 } 730 731 int 732 pcic_intr(arg) 733 void *arg; 734 { 735 struct pcic_softc *sc = arg; 736 int i, ret = 0; 737 738 DPRINTF(("%s: intr\n", sc->dev.dv_xname)); 739 740 for (i = 0; i < PCIC_NSLOTS; i++) 741 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 742 ret += pcic_intr_socket(&sc->handle[i]); 743 744 return (ret ? 1 : 0); 745 } 746 747 int 748 pcic_intr_socket(h) 749 struct pcic_handle *h; 750 { 751 int cscreg; 752 753 cscreg = pcic_read(h, PCIC_CSC); 754 755 cscreg &= (PCIC_CSC_GPI | 756 PCIC_CSC_CD | 757 PCIC_CSC_READY | 758 PCIC_CSC_BATTWARN | 759 PCIC_CSC_BATTDEAD); 760 761 if (cscreg & PCIC_CSC_GPI) { 762 DPRINTF(("%s: %02x GPI\n", h->ph_parent->dv_xname, h->sock)); 763 } 764 if (cscreg & PCIC_CSC_CD) { 765 int statreg; 766 767 statreg = pcic_read(h, PCIC_IF_STATUS); 768 769 DPRINTF(("%s: %02x CD %x\n", h->ph_parent->dv_xname, h->sock, 770 statreg)); 771 772 if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 773 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 774 if (h->laststate != PCIC_LASTSTATE_PRESENT) { 775 DPRINTF(("%s: enqueing INSERTION event\n", 776 h->ph_parent->dv_xname)); 777 pcic_queue_event(h, PCIC_EVENT_INSERTION); 778 } 779 h->laststate = PCIC_LASTSTATE_PRESENT; 780 } else { 781 if (h->laststate == PCIC_LASTSTATE_PRESENT) { 782 /* Deactivate the card now. */ 783 DPRINTF(("%s: deactivating card\n", 784 h->ph_parent->dv_xname)); 785 pcic_deactivate_card(h); 786 787 DPRINTF(("%s: enqueing REMOVAL event\n", 788 h->ph_parent->dv_xname)); 789 pcic_queue_event(h, PCIC_EVENT_REMOVAL); 790 } 791 h->laststate = 792 ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 0) ? 793 PCIC_LASTSTATE_EMPTY : PCIC_LASTSTATE_HALF; 794 } 795 } 796 if (cscreg & PCIC_CSC_READY) { 797 DPRINTF(("%s: %02x READY\n", h->ph_parent->dv_xname, h->sock)); 798 /* shouldn't happen */ 799 } 800 if (cscreg & PCIC_CSC_BATTWARN) { 801 DPRINTF(("%s: %02x BATTWARN\n", h->ph_parent->dv_xname, 802 h->sock)); 803 } 804 if (cscreg & PCIC_CSC_BATTDEAD) { 805 DPRINTF(("%s: %02x BATTDEAD\n", h->ph_parent->dv_xname, 806 h->sock)); 807 } 808 return (cscreg ? 1 : 0); 809 } 810 811 void 812 pcic_queue_event(h, event) 813 struct pcic_handle *h; 814 int event; 815 { 816 struct pcic_event *pe; 817 int s; 818 819 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 820 if (pe == NULL) 821 panic("pcic_queue_event: can't allocate event"); 822 823 pe->pe_type = event; 824 s = splhigh(); 825 SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 826 splx(s); 827 wakeup(&h->events); 828 } 829 830 void 831 pcic_attach_card(h) 832 struct pcic_handle *h; 833 { 834 835 if (!(h->flags & PCIC_FLAG_CARDP)) { 836 /* call the MI attach function */ 837 pcmcia_card_attach(h->pcmcia); 838 839 h->flags |= PCIC_FLAG_CARDP; 840 } else { 841 DPRINTF(("pcic_attach_card: already attached")); 842 } 843 } 844 845 void 846 pcic_detach_card(h, flags) 847 struct pcic_handle *h; 848 int flags; /* DETACH_* */ 849 { 850 851 if (h->flags & PCIC_FLAG_CARDP) { 852 h->flags &= ~PCIC_FLAG_CARDP; 853 854 /* call the MI detach function */ 855 pcmcia_card_detach(h->pcmcia, flags); 856 } else { 857 DPRINTF(("pcic_detach_card: already detached")); 858 } 859 } 860 861 void 862 pcic_deactivate_card(h) 863 struct pcic_handle *h; 864 { 865 866 /* call the MI deactivate function */ 867 pcmcia_card_deactivate(h->pcmcia); 868 869 /* power down the socket */ 870 pcic_write(h, PCIC_PWRCTL, 0); 871 872 /* reset the socket */ 873 pcic_write(h, PCIC_INTR, 0); 874 } 875 876 int 877 pcic_chip_mem_alloc(pch, size, pcmhp) 878 pcmcia_chipset_handle_t pch; 879 bus_size_t size; 880 struct pcmcia_mem_handle *pcmhp; 881 { 882 struct pcic_handle *h = (struct pcic_handle *) pch; 883 bus_space_handle_t memh; 884 bus_addr_t addr; 885 bus_size_t sizepg; 886 int i, mask, mhandle; 887 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 888 889 /* out of sc->memh, allocate as many pages as necessary */ 890 891 /* convert size to PCIC pages */ 892 sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN; 893 if (sizepg > PCIC_MAX_MEM_PAGES) 894 return (1); 895 896 mask = (1 << sizepg) - 1; 897 898 addr = 0; /* XXX gcc -Wuninitialized */ 899 mhandle = 0; /* XXX gcc -Wuninitialized */ 900 901 for (i = 0; i <= PCIC_MAX_MEM_PAGES - sizepg; i++) { 902 if ((sc->subregionmask & (mask << i)) == (mask << i)) { 903 if (bus_space_subregion(sc->memt, sc->memh, 904 i * PCIC_MEM_PAGESIZE, 905 sizepg * PCIC_MEM_PAGESIZE, &memh)) 906 return (1); 907 mhandle = mask << i; 908 addr = sc->membase + (i * PCIC_MEM_PAGESIZE); 909 sc->subregionmask &= ~(mhandle); 910 pcmhp->memt = sc->memt; 911 pcmhp->memh = memh; 912 pcmhp->addr = addr; 913 pcmhp->size = size; 914 pcmhp->mhandle = mhandle; 915 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 916 return (0); 917 } 918 } 919 920 return (1); 921 } 922 923 void 924 pcic_chip_mem_free(pch, pcmhp) 925 pcmcia_chipset_handle_t pch; 926 struct pcmcia_mem_handle *pcmhp; 927 { 928 struct pcic_handle *h = (struct pcic_handle *) pch; 929 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 930 931 sc->subregionmask |= pcmhp->mhandle; 932 } 933 934 static const struct mem_map_index_st { 935 int sysmem_start_lsb; 936 int sysmem_start_msb; 937 int sysmem_stop_lsb; 938 int sysmem_stop_msb; 939 int cardmem_lsb; 940 int cardmem_msb; 941 int memenable; 942 } mem_map_index[] = { 943 { 944 PCIC_SYSMEM_ADDR0_START_LSB, 945 PCIC_SYSMEM_ADDR0_START_MSB, 946 PCIC_SYSMEM_ADDR0_STOP_LSB, 947 PCIC_SYSMEM_ADDR0_STOP_MSB, 948 PCIC_CARDMEM_ADDR0_LSB, 949 PCIC_CARDMEM_ADDR0_MSB, 950 PCIC_ADDRWIN_ENABLE_MEM0, 951 }, 952 { 953 PCIC_SYSMEM_ADDR1_START_LSB, 954 PCIC_SYSMEM_ADDR1_START_MSB, 955 PCIC_SYSMEM_ADDR1_STOP_LSB, 956 PCIC_SYSMEM_ADDR1_STOP_MSB, 957 PCIC_CARDMEM_ADDR1_LSB, 958 PCIC_CARDMEM_ADDR1_MSB, 959 PCIC_ADDRWIN_ENABLE_MEM1, 960 }, 961 { 962 PCIC_SYSMEM_ADDR2_START_LSB, 963 PCIC_SYSMEM_ADDR2_START_MSB, 964 PCIC_SYSMEM_ADDR2_STOP_LSB, 965 PCIC_SYSMEM_ADDR2_STOP_MSB, 966 PCIC_CARDMEM_ADDR2_LSB, 967 PCIC_CARDMEM_ADDR2_MSB, 968 PCIC_ADDRWIN_ENABLE_MEM2, 969 }, 970 { 971 PCIC_SYSMEM_ADDR3_START_LSB, 972 PCIC_SYSMEM_ADDR3_START_MSB, 973 PCIC_SYSMEM_ADDR3_STOP_LSB, 974 PCIC_SYSMEM_ADDR3_STOP_MSB, 975 PCIC_CARDMEM_ADDR3_LSB, 976 PCIC_CARDMEM_ADDR3_MSB, 977 PCIC_ADDRWIN_ENABLE_MEM3, 978 }, 979 { 980 PCIC_SYSMEM_ADDR4_START_LSB, 981 PCIC_SYSMEM_ADDR4_START_MSB, 982 PCIC_SYSMEM_ADDR4_STOP_LSB, 983 PCIC_SYSMEM_ADDR4_STOP_MSB, 984 PCIC_CARDMEM_ADDR4_LSB, 985 PCIC_CARDMEM_ADDR4_MSB, 986 PCIC_ADDRWIN_ENABLE_MEM4, 987 }, 988 }; 989 990 void 991 pcic_chip_do_mem_map(h, win) 992 struct pcic_handle *h; 993 int win; 994 { 995 int reg; 996 int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 997 int mem8 = 998 (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 999 || (kind == PCMCIA_MEM_ATTR); 1000 1001 DPRINTF(("mem8 %d\n", mem8)); 1002 /* mem8 = 1; */ 1003 1004 pcic_write(h, mem_map_index[win].sysmem_start_lsb, 1005 (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 1006 pcic_write(h, mem_map_index[win].sysmem_start_msb, 1007 ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 1008 PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK) | 1009 (mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT)); 1010 1011 pcic_write(h, mem_map_index[win].sysmem_stop_lsb, 1012 ((h->mem[win].addr + h->mem[win].size) >> 1013 PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 1014 pcic_write(h, mem_map_index[win].sysmem_stop_msb, 1015 (((h->mem[win].addr + h->mem[win].size) >> 1016 (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 1017 PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) | 1018 PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2); 1019 1020 pcic_write(h, mem_map_index[win].cardmem_lsb, 1021 (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff); 1022 pcic_write(h, mem_map_index[win].cardmem_msb, 1023 ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) & 1024 PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) | 1025 ((kind == PCMCIA_MEM_ATTR) ? 1026 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0)); 1027 1028 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1029 reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16); 1030 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1031 1032 delay(100); 1033 1034 #ifdef PCICDEBUG 1035 { 1036 int r1, r2, r3, r4, r5, r6; 1037 1038 r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb); 1039 r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb); 1040 r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb); 1041 r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb); 1042 r5 = pcic_read(h, mem_map_index[win].cardmem_msb); 1043 r6 = pcic_read(h, mem_map_index[win].cardmem_lsb); 1044 1045 DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x " 1046 "%02x%02x\n", win, r1, r2, r3, r4, r5, r6)); 1047 } 1048 #endif 1049 } 1050 1051 int 1052 pcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 1053 pcmcia_chipset_handle_t pch; 1054 int kind; 1055 bus_addr_t card_addr; 1056 bus_size_t size; 1057 struct pcmcia_mem_handle *pcmhp; 1058 bus_size_t *offsetp; 1059 int *windowp; 1060 { 1061 struct pcic_handle *h = (struct pcic_handle *) pch; 1062 bus_addr_t busaddr; 1063 long card_offset; 1064 int i, win; 1065 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1066 1067 win = -1; 1068 for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0])); 1069 i++) { 1070 if ((h->memalloc & (1 << i)) == 0) { 1071 win = i; 1072 h->memalloc |= (1 << i); 1073 break; 1074 } 1075 } 1076 1077 if (win == -1) 1078 return (1); 1079 1080 *windowp = win; 1081 1082 /* XXX this is pretty gross */ 1083 1084 if (sc->memt != pcmhp->memt) 1085 panic("pcic_chip_mem_map memt is bogus"); 1086 1087 busaddr = pcmhp->addr; 1088 1089 /* 1090 * compute the address offset to the pcmcia address space for the 1091 * pcic. this is intentionally signed. The masks and shifts below 1092 * will cause TRT to happen in the pcic registers. Deal with making 1093 * sure the address is aligned, and return the alignment offset. 1094 */ 1095 1096 *offsetp = card_addr % PCIC_MEM_ALIGN; 1097 card_addr -= *offsetp; 1098 1099 DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 1100 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 1101 (u_long) card_addr)); 1102 1103 /* 1104 * include the offset in the size, and decrement size by one, since 1105 * the hw wants start/stop 1106 */ 1107 size += *offsetp - 1; 1108 1109 card_offset = (((long) card_addr) - ((long) busaddr)); 1110 1111 h->mem[win].addr = busaddr; 1112 h->mem[win].size = size; 1113 h->mem[win].offset = card_offset; 1114 h->mem[win].kind = kind; 1115 1116 pcic_chip_do_mem_map(h, win); 1117 1118 return (0); 1119 } 1120 1121 void 1122 pcic_chip_mem_unmap(pch, window) 1123 pcmcia_chipset_handle_t pch; 1124 int window; 1125 { 1126 struct pcic_handle *h = (struct pcic_handle *) pch; 1127 int reg; 1128 1129 if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0]))) 1130 panic("pcic_chip_mem_unmap: window out of range"); 1131 1132 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1133 reg &= ~mem_map_index[window].memenable; 1134 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1135 1136 h->memalloc &= ~(1 << window); 1137 } 1138 1139 int 1140 pcic_chip_io_alloc(pch, start, size, align, pcihp) 1141 pcmcia_chipset_handle_t pch; 1142 bus_addr_t start; 1143 bus_size_t size; 1144 bus_size_t align; 1145 struct pcmcia_io_handle *pcihp; 1146 { 1147 struct pcic_handle *h = (struct pcic_handle *) pch; 1148 bus_space_tag_t iot; 1149 bus_space_handle_t ioh; 1150 bus_addr_t ioaddr; 1151 int flags = 0; 1152 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1153 1154 /* 1155 * Allocate some arbitrary I/O space. 1156 */ 1157 1158 iot = sc->iot; 1159 1160 if (start) { 1161 ioaddr = start; 1162 if (bus_space_map(iot, start, size, 0, &ioh)) 1163 return (1); 1164 DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n", 1165 (u_long) ioaddr, (u_long) size)); 1166 } else { 1167 flags |= PCMCIA_IO_ALLOCATED; 1168 if (bus_space_alloc(iot, sc->iobase, 1169 sc->iobase + sc->iosize, size, align, 0, 0, 1170 &ioaddr, &ioh)) 1171 return (1); 1172 DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n", 1173 (u_long) ioaddr, (u_long) size)); 1174 } 1175 1176 pcihp->iot = iot; 1177 pcihp->ioh = ioh; 1178 pcihp->addr = ioaddr; 1179 pcihp->size = size; 1180 pcihp->flags = flags; 1181 1182 return (0); 1183 } 1184 1185 void 1186 pcic_chip_io_free(pch, pcihp) 1187 pcmcia_chipset_handle_t pch; 1188 struct pcmcia_io_handle *pcihp; 1189 { 1190 bus_space_tag_t iot = pcihp->iot; 1191 bus_space_handle_t ioh = pcihp->ioh; 1192 bus_size_t size = pcihp->size; 1193 1194 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1195 bus_space_free(iot, ioh, size); 1196 else 1197 bus_space_unmap(iot, ioh, size); 1198 } 1199 1200 1201 static const struct io_map_index_st { 1202 int start_lsb; 1203 int start_msb; 1204 int stop_lsb; 1205 int stop_msb; 1206 int ioenable; 1207 int ioctlmask; 1208 int ioctlbits[3]; /* indexed by PCMCIA_WIDTH_* */ 1209 } io_map_index[] = { 1210 { 1211 PCIC_IOADDR0_START_LSB, 1212 PCIC_IOADDR0_START_MSB, 1213 PCIC_IOADDR0_STOP_LSB, 1214 PCIC_IOADDR0_STOP_MSB, 1215 PCIC_ADDRWIN_ENABLE_IO0, 1216 PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1217 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK, 1218 { 1219 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1220 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1221 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1222 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1223 PCIC_IOCTL_IO0_DATASIZE_16BIT, 1224 }, 1225 }, 1226 { 1227 PCIC_IOADDR1_START_LSB, 1228 PCIC_IOADDR1_START_MSB, 1229 PCIC_IOADDR1_STOP_LSB, 1230 PCIC_IOADDR1_STOP_MSB, 1231 PCIC_ADDRWIN_ENABLE_IO1, 1232 PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1233 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK, 1234 { 1235 PCIC_IOCTL_IO1_IOCS16SRC_CARD, 1236 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1237 PCIC_IOCTL_IO1_DATASIZE_8BIT, 1238 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1239 PCIC_IOCTL_IO1_DATASIZE_16BIT, 1240 }, 1241 }, 1242 }; 1243 1244 void 1245 pcic_chip_do_io_map(h, win) 1246 struct pcic_handle *h; 1247 int win; 1248 { 1249 int reg; 1250 1251 DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1252 win, (long) h->io[win].addr, (long) h->io[win].size, 1253 h->io[win].width * 8)); 1254 1255 pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff); 1256 pcic_write(h, io_map_index[win].start_msb, 1257 (h->io[win].addr >> 8) & 0xff); 1258 1259 pcic_write(h, io_map_index[win].stop_lsb, 1260 (h->io[win].addr + h->io[win].size - 1) & 0xff); 1261 pcic_write(h, io_map_index[win].stop_msb, 1262 ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff); 1263 1264 reg = pcic_read(h, PCIC_IOCTL); 1265 reg &= ~io_map_index[win].ioctlmask; 1266 reg |= io_map_index[win].ioctlbits[h->io[win].width]; 1267 pcic_write(h, PCIC_IOCTL, reg); 1268 1269 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1270 reg |= io_map_index[win].ioenable; 1271 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1272 } 1273 1274 int 1275 pcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 1276 pcmcia_chipset_handle_t pch; 1277 int width; 1278 bus_addr_t offset; 1279 bus_size_t size; 1280 struct pcmcia_io_handle *pcihp; 1281 int *windowp; 1282 { 1283 struct pcic_handle *h = (struct pcic_handle *) pch; 1284 bus_addr_t ioaddr = pcihp->addr + offset; 1285 int i, win; 1286 #ifdef PCICDEBUG 1287 static char *width_names[] = { "auto", "io8", "io16" }; 1288 #endif 1289 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1290 1291 /* XXX Sanity check offset/size. */ 1292 1293 win = -1; 1294 for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) { 1295 if ((h->ioalloc & (1 << i)) == 0) { 1296 win = i; 1297 h->ioalloc |= (1 << i); 1298 break; 1299 } 1300 } 1301 1302 if (win == -1) 1303 return (1); 1304 1305 *windowp = win; 1306 1307 /* XXX this is pretty gross */ 1308 1309 if (sc->iot != pcihp->iot) 1310 panic("pcic_chip_io_map iot is bogus"); 1311 1312 DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n", 1313 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1314 1315 /* XXX wtf is this doing here? */ 1316 1317 printf(" port 0x%lx", (u_long) ioaddr); 1318 if (size > 1) 1319 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1320 1321 h->io[win].addr = ioaddr; 1322 h->io[win].size = size; 1323 h->io[win].width = width; 1324 1325 pcic_chip_do_io_map(h, win); 1326 1327 return (0); 1328 } 1329 1330 void 1331 pcic_chip_io_unmap(pch, window) 1332 pcmcia_chipset_handle_t pch; 1333 int window; 1334 { 1335 struct pcic_handle *h = (struct pcic_handle *) pch; 1336 int reg; 1337 1338 if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0]))) 1339 panic("pcic_chip_io_unmap: window out of range"); 1340 1341 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1342 reg &= ~io_map_index[window].ioenable; 1343 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1344 1345 h->ioalloc &= ~(1 << window); 1346 } 1347 1348 static void 1349 pcic_wait_ready(h) 1350 struct pcic_handle *h; 1351 { 1352 int i; 1353 1354 /* wait an initial 10ms for quick cards */ 1355 if (pcic_read(h, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) 1356 return; 1357 pcic_delay(h, 10, "pccwr0"); 1358 for (i = 0; i < 50; i++) { 1359 if (pcic_read(h, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) 1360 return; 1361 /* wait .1s (100ms) each iteration now */ 1362 pcic_delay(h, 100, "pccwr1"); 1363 #ifdef PCICDEBUG 1364 if (pcic_debug) { 1365 if ((i > 20) && (i % 100 == 99)) 1366 printf("."); 1367 } 1368 #endif 1369 } 1370 1371 #ifdef DIAGNOSTIC 1372 printf("pcic_wait_ready: ready never happened, status = %02x\n", 1373 pcic_read(h, PCIC_IF_STATUS)); 1374 #endif 1375 } 1376 1377 /* 1378 * Perform long (msec order) delay. 1379 */ 1380 static void 1381 pcic_delay(h, timo, wmesg) 1382 struct pcic_handle *h; 1383 int timo; /* in ms. must not be zero */ 1384 const char *wmesg; 1385 { 1386 1387 #ifdef DIAGNOSTIC 1388 if (timo <= 0) { 1389 printf("called with timeout %d\n", timo); 1390 panic("pcic_delay"); 1391 } 1392 if (curproc == NULL) { 1393 printf("called in interrupt context\n"); 1394 panic("pcic_delay"); 1395 } 1396 if (h->event_thread == NULL) { 1397 printf("no event thread\n"); 1398 panic("pcic_delay"); 1399 } 1400 #endif 1401 DPRINTF(("pcic_delay: \"%s\" %p, sleep %d ms\n", 1402 wmesg, h->event_thread, timo)); 1403 tsleep(pcic_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 1404 } 1405 1406 void 1407 pcic_chip_socket_enable(pch) 1408 pcmcia_chipset_handle_t pch; 1409 { 1410 struct pcic_handle *h = (struct pcic_handle *) pch; 1411 int cardtype, win, intr, pwr; 1412 int vcc_3v, regtmp; 1413 #if defined(DIAGNOSTIC) || defined(PCICDEBUG) 1414 int reg; 1415 #endif 1416 1417 #ifdef DIAGNOSTIC 1418 if (h->flags & PCIC_FLAG_ENABLED) 1419 printf("pcic_chip_socket_enable: enabling twice\n"); 1420 #endif 1421 1422 /* disable interrupts */ 1423 intr = pcic_read(h, PCIC_INTR); 1424 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE); 1425 pcic_write(h, PCIC_INTR, intr); 1426 1427 /* power down the socket to reset it, clear the card reset pin */ 1428 pwr = 0; 1429 pcic_write(h, PCIC_PWRCTL, pwr); 1430 1431 /* 1432 * wait 300ms until power fails (Tpf). Then, wait 100ms since 1433 * we are changing Vcc (Toff). 1434 */ 1435 pcic_delay(h, 300 + 100, "pccen0"); 1436 1437 /* 1438 * power hack for RICOH RF5C[23]96 1439 */ 1440 switch( h->vendor ) { 1441 case PCIC_VENDOR_RICOH_5C296: 1442 case PCIC_VENDOR_RICOH_5C396: 1443 vcc_3v = 0; 1444 regtmp = pcic_read(h, PCIC_CARD_DETECT); 1445 if(regtmp & PCIC_CARD_DETECT_GPI_ENABLE) { 1446 DPRINTF(("\nGPI is enabled. Can't sense VS1\n")); 1447 } else { 1448 regtmp = pcic_read(h, PCIC_IF_STATUS) ; 1449 vcc_3v = (regtmp & PCIC_IF_STATUS_GPI) ? 1 : 0; 1450 DPRINTF(("\n5VDET = %s\n", 1451 vcc_3v ? "1 (3.3V)" : "0 (5V)")); 1452 } 1453 1454 regtmp = pcic_read(h, PCIC_RICOH_REG_MCR2); 1455 regtmp &= ~PCIC_RICOH_MCR2_VCC_SEL_MASK; 1456 if(vcc_3v) { 1457 regtmp |= PCIC_RICOH_MCR2_VCC_SEL_3V; 1458 } else { 1459 regtmp |= PCIC_RICOH_MCR2_VCC_SEL_5V; 1460 } 1461 pcic_write(h, PCIC_RICOH_REG_MCR2, regtmp); 1462 break; 1463 default: 1464 break; 1465 } 1466 1467 #ifdef VADEM_POWER_HACK 1468 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x0e); 1469 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x37); 1470 printf("prcr = %02x\n", pcic_read(h, 0x02)); 1471 printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1472 printf("DANGER WILL ROBINSON! Changing voltage select!\n"); 1473 pcic_write(h, 0x2f, pcic_read(h, 0x2f) & ~0x03); 1474 printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1475 #endif 1476 /* power up the socket */ 1477 pwr |= PCIC_PWRCTL_DISABLE_RESETDRV | PCIC_PWRCTL_PWR_ENABLE | PCIC_PWRCTL_VPP1_VCC; 1478 pcic_write(h, PCIC_PWRCTL, pwr); 1479 1480 /* 1481 * wait 100ms until power raise (Tpr) and 20ms to become 1482 * stable (Tsu(Vcc)). 1483 * 1484 * some machines require some more time to be settled 1485 * (300ms is added here). 1486 */ 1487 pcic_delay(h, 100 + 20 + 300, "pccen1"); 1488 pwr |= PCIC_PWRCTL_OE; 1489 pcic_write(h, PCIC_PWRCTL, pwr); 1490 1491 /* now make sure we have reset# active */ 1492 intr &= ~PCIC_INTR_RESET; 1493 pcic_write(h, PCIC_INTR, intr); 1494 1495 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV | 1496 PCIC_PWRCTL_OE | PCIC_PWRCTL_PWR_ENABLE | PCIC_PWRCTL_VPP1_VCC); 1497 /* 1498 * hold RESET at least 10us, this is a min allow for slop in 1499 * delay routine. 1500 */ 1501 delay(20); 1502 1503 /* clear the reset flag */ 1504 intr |= PCIC_INTR_RESET; 1505 pcic_write(h, PCIC_INTR, intr); 1506 1507 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1508 pcic_delay(h, 20, "pccen2"); 1509 1510 #if defined(DIAGNOSTIC) || defined(PCICDEBUG) 1511 reg = pcic_read(h, PCIC_IF_STATUS); 1512 #endif 1513 #ifdef DIAGNOSTIC 1514 if (!(reg & PCIC_IF_STATUS_POWERACTIVE)) { 1515 printf("pcic_chip_socket_enable: status %x\n", reg); 1516 } 1517 #endif 1518 /* wait for the chip to finish initializing */ 1519 pcic_wait_ready(h); 1520 1521 /* zero out the address windows */ 1522 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1523 1524 /* set the card type and enable the interrupt */ 1525 cardtype = pcmcia_card_gettype(h->pcmcia); 1526 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 1527 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 1528 pcic_write(h, PCIC_INTR, intr); 1529 1530 DPRINTF(("%s: pcic_chip_socket_enable %02x cardtype %s %02x\n", 1531 h->ph_parent->dv_xname, h->sock, 1532 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg)); 1533 1534 /* reinstall all the memory and io mappings */ 1535 for (win = 0; win < PCIC_MEM_WINS; win++) 1536 if (h->memalloc & (1 << win)) 1537 pcic_chip_do_mem_map(h, win); 1538 for (win = 0; win < PCIC_IO_WINS; win++) 1539 if (h->ioalloc & (1 << win)) 1540 pcic_chip_do_io_map(h, win); 1541 1542 h->flags |= PCIC_FLAG_ENABLED; 1543 1544 /* finally enable the interrupt */ 1545 intr |= h->ih_irq; 1546 pcic_write(h, PCIC_INTR, intr); 1547 } 1548 1549 void 1550 pcic_chip_socket_disable(pch) 1551 pcmcia_chipset_handle_t pch; 1552 { 1553 struct pcic_handle *h = (struct pcic_handle *) pch; 1554 int intr; 1555 1556 DPRINTF(("pcic_chip_socket_disable\n")); 1557 1558 /* disable interrupts */ 1559 intr = pcic_read(h, PCIC_INTR); 1560 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE); 1561 pcic_write(h, PCIC_INTR, intr); 1562 1563 /* power down the socket */ 1564 pcic_write(h, PCIC_PWRCTL, 0); 1565 1566 /* zero out the address windows */ 1567 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1568 1569 h->flags &= ~PCIC_FLAG_ENABLED; 1570 } 1571 1572 static u_int8_t 1573 st_pcic_read(h, idx) 1574 struct pcic_handle *h; 1575 int idx; 1576 { 1577 1578 if (idx != -1) 1579 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1580 h->sock + idx); 1581 return (bus_space_read_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA)); 1582 } 1583 1584 static void 1585 st_pcic_write(h, idx, data) 1586 struct pcic_handle *h; 1587 int idx; 1588 u_int8_t data; 1589 { 1590 1591 if (idx != -1) 1592 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1593 h->sock + idx); 1594 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA, data); 1595 } 1596