1 /* $NetBSD: i8253reg.h,v 1.5 1998/01/19 11:38:00 drochner Exp $ */ 2 3 /*- 4 * Copyright (c) 1993 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 /* 37 * Register definitions for the Intel 8253 Programmable Interval Timer. 38 * 39 * This chip has three independent 16-bit down counters that can be 40 * read on the fly. There are three mode registers and three countdown 41 * registers. The countdown registers are addressed directly, via the 42 * first three I/O ports. The three mode registers are accessed via 43 * the fourth I/O port, with two bits in the mode byte indicating the 44 * register. (Why are hardware interfaces always so braindead?). 45 * 46 * To write a value into the countdown register, the mode register 47 * is first programmed with a command indicating the which byte of 48 * the two byte register is to be modified. The three possibilities 49 * are load msb (TMR_MR_MSB), load lsb (TMR_MR_LSB), or load lsb then 50 * msb (TMR_MR_BOTH). 51 * 52 * To read the current value ("on the fly") from the countdown register, 53 * you write a "latch" command into the mode register, then read the stable 54 * value from the corresponding I/O port. For example, you write 55 * TMR_MR_LATCH into the corresponding mode register. Presumably, 56 * after doing this, a write operation to the I/O port would result 57 * in undefined behavior (but hopefully not fry the chip). 58 * Reading in this manner has no side effects. 59 * 60 * The outputs of the three timers are connected as follows: 61 * 62 * timer 0 -> irq 0 63 * timer 1 -> dma chan 0 (for dram refresh) 64 * timer 2 -> speaker (via keyboard controller) 65 * 66 * Timer 0 is used to call hardclock. 67 * Timer 2 is used to generate console beeps. 68 */ 69 70 /* 71 * Frequency of all three count-down timers; (TIMER_FREQ/freq) is the 72 * appropriate count to generate a frequency of freq hz. 73 */ 74 #ifndef TIMER_FREQ 75 #define TIMER_FREQ 1193182 76 #endif 77 #define TIMER_DIV(x) ((TIMER_FREQ+(x)/2)/(x)) 78 79 /* 80 * Macros for specifying values to be written into a mode register. 81 */ 82 #define TIMER_CNTR0 0 /* timer 0 counter port */ 83 #define TIMER_CNTR1 1 /* timer 1 counter port */ 84 #define TIMER_CNTR2 2 /* timer 2 counter port */ 85 #define TIMER_MODE 3 /* timer mode port */ 86 #define TIMER_SEL0 0x00 /* select counter 0 */ 87 #define TIMER_SEL1 0x40 /* select counter 1 */ 88 #define TIMER_SEL2 0x80 /* select counter 2 */ 89 #define TIMER_INTTC 0x00 /* mode 0, intr on terminal cnt */ 90 #define TIMER_ONESHOT 0x02 /* mode 1, one shot */ 91 #define TIMER_RATEGEN 0x04 /* mode 2, rate generator */ 92 #define TIMER_SQWAVE 0x06 /* mode 3, square wave */ 93 #define TIMER_SWSTROBE 0x08 /* mode 4, s/w triggered strobe */ 94 #define TIMER_HWSTROBE 0x0a /* mode 5, h/w triggered strobe */ 95 #define TIMER_LATCH 0x00 /* latch counter for reading */ 96 #define TIMER_LSB 0x10 /* r/w counter LSB */ 97 #define TIMER_MSB 0x20 /* r/w counter MSB */ 98 #define TIMER_16BIT 0x30 /* r/w counter 16 bits, LSB first */ 99 #define TIMER_BCD 0x01 /* count in BCD */ 100 101