1 /* $NetBSD: i82557.c,v 1.65 2002/05/20 15:23:01 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 68 */ 69 70 /* 71 * Device driver for the Intel i82557 fast Ethernet controller, 72 * and its successors, the i82558 and i82559. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.65 2002/05/20 15:23:01 mycroft Exp $"); 77 78 #include "bpfilter.h" 79 #include "rnd.h" 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/callout.h> 84 #include <sys/mbuf.h> 85 #include <sys/malloc.h> 86 #include <sys/kernel.h> 87 #include <sys/socket.h> 88 #include <sys/ioctl.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 92 #include <machine/endian.h> 93 94 #include <uvm/uvm_extern.h> 95 96 #if NRND > 0 97 #include <sys/rnd.h> 98 #endif 99 100 #include <net/if.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 #include <net/if_ether.h> 104 105 #if NBPFILTER > 0 106 #include <net/bpf.h> 107 #endif 108 109 #include <machine/bus.h> 110 #include <machine/intr.h> 111 112 #include <dev/mii/miivar.h> 113 114 #include <dev/ic/i82557reg.h> 115 #include <dev/ic/i82557var.h> 116 117 #include <dev/microcode/i8255x/rcvbundl.h> 118 119 /* 120 * NOTE! On the Alpha, we have an alignment constraint. The 121 * card DMAs the packet immediately following the RFA. However, 122 * the first thing in the packet is a 14-byte Ethernet header. 123 * This means that the packet is misaligned. To compensate, 124 * we actually offset the RFA 2 bytes into the cluster. This 125 * alignes the packet after the Ethernet header at a 32-bit 126 * boundary. HOWEVER! This means that the RFA is misaligned! 127 */ 128 #define RFA_ALIGNMENT_FUDGE 2 129 130 /* 131 * The configuration byte map has several undefined fields which 132 * must be one or must be zero. Set up a template for these bits 133 * only (assuming an i82557 chip), leaving the actual configuration 134 * for fxp_init(). 135 * 136 * See the definition of struct fxp_cb_config for the bit definitions. 137 */ 138 const u_int8_t fxp_cb_config_template[] = { 139 0x0, 0x0, /* cb_status */ 140 0x0, 0x0, /* cb_command */ 141 0x0, 0x0, 0x0, 0x0, /* link_addr */ 142 0x0, /* 0 */ 143 0x0, /* 1 */ 144 0x0, /* 2 */ 145 0x0, /* 3 */ 146 0x0, /* 4 */ 147 0x0, /* 5 */ 148 0x32, /* 6 */ 149 0x0, /* 7 */ 150 0x0, /* 8 */ 151 0x0, /* 9 */ 152 0x6, /* 10 */ 153 0x0, /* 11 */ 154 0x0, /* 12 */ 155 0x0, /* 13 */ 156 0xf2, /* 14 */ 157 0x48, /* 15 */ 158 0x0, /* 16 */ 159 0x40, /* 17 */ 160 0xf0, /* 18 */ 161 0x0, /* 19 */ 162 0x3f, /* 20 */ 163 0x5, /* 21 */ 164 0x0, /* 22 */ 165 0x0, /* 23 */ 166 0x0, /* 24 */ 167 0x0, /* 25 */ 168 0x0, /* 26 */ 169 0x0, /* 27 */ 170 0x0, /* 28 */ 171 0x0, /* 29 */ 172 0x0, /* 30 */ 173 0x0, /* 31 */ 174 }; 175 176 void fxp_mii_initmedia(struct fxp_softc *); 177 int fxp_mii_mediachange(struct ifnet *); 178 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 179 180 void fxp_80c24_initmedia(struct fxp_softc *); 181 int fxp_80c24_mediachange(struct ifnet *); 182 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 183 184 void fxp_start(struct ifnet *); 185 int fxp_ioctl(struct ifnet *, u_long, caddr_t); 186 void fxp_watchdog(struct ifnet *); 187 int fxp_init(struct ifnet *); 188 void fxp_stop(struct ifnet *, int); 189 190 void fxp_txintr(struct fxp_softc *); 191 void fxp_rxintr(struct fxp_softc *); 192 193 void fxp_rxdrain(struct fxp_softc *); 194 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 195 int fxp_mdi_read(struct device *, int, int); 196 void fxp_statchg(struct device *); 197 void fxp_mdi_write(struct device *, int, int, int); 198 void fxp_autosize_eeprom(struct fxp_softc*); 199 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 200 void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 201 void fxp_eeprom_update_cksum(struct fxp_softc *); 202 void fxp_get_info(struct fxp_softc *, u_int8_t *); 203 void fxp_tick(void *); 204 void fxp_mc_setup(struct fxp_softc *); 205 void fxp_load_ucode(struct fxp_softc *); 206 207 void fxp_shutdown(void *); 208 void fxp_power(int, void *); 209 210 int fxp_copy_small = 0; 211 212 /* 213 * Variables for interrupt mitigating microcode. 214 */ 215 int fxp_int_delay = 1000; /* usec */ 216 int fxp_bundle_max = 6; /* packets */ 217 218 struct fxp_phytype { 219 int fp_phy; /* type of PHY, -1 for MII at the end. */ 220 void (*fp_init)(struct fxp_softc *); 221 } fxp_phytype_table[] = { 222 { FXP_PHY_80C24, fxp_80c24_initmedia }, 223 { -1, fxp_mii_initmedia }, 224 }; 225 226 /* 227 * Set initial transmit threshold at 64 (512 bytes). This is 228 * increased by 64 (512 bytes) at a time, to maximum of 192 229 * (1536 bytes), if an underrun occurs. 230 */ 231 static int tx_threshold = 64; 232 233 /* 234 * Wait for the previous command to be accepted (but not necessarily 235 * completed). 236 */ 237 static __inline void 238 fxp_scb_wait(struct fxp_softc *sc) 239 { 240 int i = 10000; 241 242 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 243 delay(2); 244 if (i == 0) 245 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 246 } 247 248 /* 249 * Submit a command to the i82557. 250 */ 251 static __inline void 252 fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 253 { 254 255 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 256 } 257 258 /* 259 * Finish attaching an i82557 interface. Called by bus-specific front-end. 260 */ 261 void 262 fxp_attach(struct fxp_softc *sc) 263 { 264 u_int8_t enaddr[ETHER_ADDR_LEN]; 265 struct ifnet *ifp; 266 bus_dma_segment_t seg; 267 int rseg, i, error; 268 struct fxp_phytype *fp; 269 270 callout_init(&sc->sc_callout); 271 272 /* Start out using the standard RFA. */ 273 sc->sc_rfa_size = RFA_SIZE; 274 275 /* 276 * Enable some good stuff on i82558 and later. 277 */ 278 if (sc->sc_rev >= FXP_REV_82558_A4) { 279 /* Enable the extended TxCB. */ 280 sc->sc_flags |= FXPF_EXT_TXCB; 281 } 282 283 /* 284 * Allocate the control data structures, and create and load the 285 * DMA map for it. 286 */ 287 if ((error = bus_dmamem_alloc(sc->sc_dmat, 288 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 289 0)) != 0) { 290 printf("%s: unable to allocate control data, error = %d\n", 291 sc->sc_dev.dv_xname, error); 292 goto fail_0; 293 } 294 295 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 296 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 297 BUS_DMA_COHERENT)) != 0) { 298 printf("%s: unable to map control data, error = %d\n", 299 sc->sc_dev.dv_xname, error); 300 goto fail_1; 301 } 302 sc->sc_cdseg = seg; 303 sc->sc_cdnseg = rseg; 304 305 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 306 307 if ((error = bus_dmamap_create(sc->sc_dmat, 308 sizeof(struct fxp_control_data), 1, 309 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 310 printf("%s: unable to create control data DMA map, " 311 "error = %d\n", sc->sc_dev.dv_xname, error); 312 goto fail_2; 313 } 314 315 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 316 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 317 0)) != 0) { 318 printf("%s: can't load control data DMA map, error = %d\n", 319 sc->sc_dev.dv_xname, error); 320 goto fail_3; 321 } 322 323 /* 324 * Create the transmit buffer DMA maps. 325 */ 326 for (i = 0; i < FXP_NTXCB; i++) { 327 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 328 FXP_NTXSEG, MCLBYTES, 0, 0, 329 &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 330 printf("%s: unable to create tx DMA map %d, " 331 "error = %d\n", sc->sc_dev.dv_xname, i, error); 332 goto fail_4; 333 } 334 } 335 336 /* 337 * Create the receive buffer DMA maps. 338 */ 339 for (i = 0; i < FXP_NRFABUFS; i++) { 340 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 341 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 342 printf("%s: unable to create rx DMA map %d, " 343 "error = %d\n", sc->sc_dev.dv_xname, i, error); 344 goto fail_5; 345 } 346 } 347 348 /* Initialize MAC address and media structures. */ 349 fxp_get_info(sc, enaddr); 350 351 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 352 ether_sprintf(enaddr)); 353 354 ifp = &sc->sc_ethercom.ec_if; 355 356 /* 357 * Get info about our media interface, and initialize it. Note 358 * the table terminates itself with a phy of -1, indicating 359 * that we're using MII. 360 */ 361 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 362 if (fp->fp_phy == sc->phy_primary_device) 363 break; 364 (*fp->fp_init)(sc); 365 366 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 367 ifp->if_softc = sc; 368 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 369 ifp->if_ioctl = fxp_ioctl; 370 ifp->if_start = fxp_start; 371 ifp->if_watchdog = fxp_watchdog; 372 ifp->if_init = fxp_init; 373 ifp->if_stop = fxp_stop; 374 IFQ_SET_READY(&ifp->if_snd); 375 376 /* 377 * We can support 802.1Q VLAN-sized frames. 378 */ 379 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 380 381 /* 382 * Attach the interface. 383 */ 384 if_attach(ifp); 385 ether_ifattach(ifp, enaddr); 386 #if NRND > 0 387 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 388 RND_TYPE_NET, 0); 389 #endif 390 391 #ifdef FXP_EVENT_COUNTERS 392 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 393 NULL, sc->sc_dev.dv_xname, "txstall"); 394 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 395 NULL, sc->sc_dev.dv_xname, "txintr"); 396 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 397 NULL, sc->sc_dev.dv_xname, "rxintr"); 398 #endif /* FXP_EVENT_COUNTERS */ 399 400 /* 401 * Add shutdown hook so that DMA is disabled prior to reboot. Not 402 * doing do could allow DMA to corrupt kernel memory during the 403 * reboot before the driver initializes. 404 */ 405 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 406 if (sc->sc_sdhook == NULL) 407 printf("%s: WARNING: unable to establish shutdown hook\n", 408 sc->sc_dev.dv_xname); 409 /* 410 * Add suspend hook, for similar reasons.. 411 */ 412 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 413 if (sc->sc_powerhook == NULL) 414 printf("%s: WARNING: unable to establish power hook\n", 415 sc->sc_dev.dv_xname); 416 417 /* The attach is successful. */ 418 sc->sc_flags |= FXPF_ATTACHED; 419 420 return; 421 422 /* 423 * Free any resources we've allocated during the failed attach 424 * attempt. Do this in reverse order and fall though. 425 */ 426 fail_5: 427 for (i = 0; i < FXP_NRFABUFS; i++) { 428 if (sc->sc_rxmaps[i] != NULL) 429 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 430 } 431 fail_4: 432 for (i = 0; i < FXP_NTXCB; i++) { 433 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 434 bus_dmamap_destroy(sc->sc_dmat, 435 FXP_DSTX(sc, i)->txs_dmamap); 436 } 437 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 438 fail_3: 439 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 440 fail_2: 441 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 442 sizeof(struct fxp_control_data)); 443 fail_1: 444 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 445 fail_0: 446 return; 447 } 448 449 void 450 fxp_mii_initmedia(struct fxp_softc *sc) 451 { 452 int flags; 453 454 sc->sc_flags |= FXPF_MII; 455 456 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 457 sc->sc_mii.mii_readreg = fxp_mdi_read; 458 sc->sc_mii.mii_writereg = fxp_mdi_write; 459 sc->sc_mii.mii_statchg = fxp_statchg; 460 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_mii_mediachange, 461 fxp_mii_mediastatus); 462 463 flags = MIIF_NOISOLATE; 464 if (sc->sc_rev >= FXP_REV_82558_A4) 465 flags |= MIIF_DOPAUSE; 466 /* 467 * The i82557 wedges if all of its PHYs are isolated! 468 */ 469 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 470 MII_OFFSET_ANY, flags); 471 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 472 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 473 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 474 } else 475 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 476 } 477 478 void 479 fxp_80c24_initmedia(struct fxp_softc *sc) 480 { 481 482 /* 483 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 484 * doesn't have a programming interface of any sort. The 485 * media is sensed automatically based on how the link partner 486 * is configured. This is, in essence, manual configuration. 487 */ 488 printf("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 489 sc->sc_dev.dv_xname); 490 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 491 fxp_80c24_mediastatus); 492 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 493 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 494 } 495 496 /* 497 * Device shutdown routine. Called at system shutdown after sync. The 498 * main purpose of this routine is to shut off receiver DMA so that 499 * kernel memory doesn't get clobbered during warmboot. 500 */ 501 void 502 fxp_shutdown(void *arg) 503 { 504 struct fxp_softc *sc = arg; 505 506 /* 507 * Since the system's going to halt shortly, don't bother 508 * freeing mbufs. 509 */ 510 fxp_stop(&sc->sc_ethercom.ec_if, 0); 511 } 512 /* 513 * Power handler routine. Called when the system is transitioning 514 * into/out of power save modes. As with fxp_shutdown, the main 515 * purpose of this routine is to shut off receiver DMA so it doesn't 516 * clobber kernel memory at the wrong time. 517 */ 518 void 519 fxp_power(int why, void *arg) 520 { 521 struct fxp_softc *sc = arg; 522 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 523 int s; 524 525 s = splnet(); 526 switch (why) { 527 case PWR_SUSPEND: 528 case PWR_STANDBY: 529 fxp_stop(ifp, 0); 530 break; 531 case PWR_RESUME: 532 if (ifp->if_flags & IFF_UP) 533 fxp_init(ifp); 534 break; 535 case PWR_SOFTSUSPEND: 536 case PWR_SOFTSTANDBY: 537 case PWR_SOFTRESUME: 538 break; 539 } 540 splx(s); 541 } 542 543 /* 544 * Initialize the interface media. 545 */ 546 void 547 fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 548 { 549 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 550 551 /* 552 * Reset to a stable state. 553 */ 554 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 555 DELAY(10); 556 557 sc->sc_eeprom_size = 0; 558 fxp_autosize_eeprom(sc); 559 if(sc->sc_eeprom_size == 0) { 560 printf("%s: failed to detect EEPROM size\n", sc->sc_dev.dv_xname); 561 sc->sc_eeprom_size = 6; /* XXX panic here? */ 562 } 563 #ifdef DEBUG 564 printf("%s: detected %d word EEPROM\n", 565 sc->sc_dev.dv_xname, 566 1 << sc->sc_eeprom_size); 567 #endif 568 569 /* 570 * Get info about the primary PHY 571 */ 572 fxp_read_eeprom(sc, &data, 6, 1); 573 sc->phy_primary_device = 574 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 575 576 /* 577 * Read MAC address. 578 */ 579 fxp_read_eeprom(sc, myea, 0, 3); 580 enaddr[0] = myea[0] & 0xff; 581 enaddr[1] = myea[0] >> 8; 582 enaddr[2] = myea[1] & 0xff; 583 enaddr[3] = myea[1] >> 8; 584 enaddr[4] = myea[2] & 0xff; 585 enaddr[5] = myea[2] >> 8; 586 587 /* 588 * Systems based on the ICH2/ICH2-M chip from Intel, as well 589 * as some i82559 designs, have a defect where the chip can 590 * cause a PCI protocol violation if it receives a CU_RESUME 591 * command when it is entering the IDLE state. 592 * 593 * The work-around is to disable Dynamic Standby Mode, so that 594 * the chip never deasserts #CLKRUN, and always remains in the 595 * active state. 596 * 597 * Unfortunately, the only way to disable Dynamic Standby is 598 * to frob an EEPROM setting and reboot (the EEPROM setting 599 * is only consulted when the PCI bus comes out of reset). 600 * 601 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 602 */ 603 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 604 fxp_read_eeprom(sc, &data, 10, 1); 605 if (data & 0x02) { /* STB enable */ 606 printf("%s: WARNING: Disabling dynamic standby mode in EEPROM to work around a", sc->sc_dev.dv_xname); 607 printf("%s: WARNING: hardware bug. You must reset the system before using this", sc->sc_dev.dv_xname); 608 printf("%s: WARNING: interface.", sc->sc_dev.dv_xname); 609 data &= ~0x02; 610 fxp_write_eeprom(sc, &data, 10, 1); 611 printf("%s: new EEPROM ID: 0x%04x\n", 612 sc->sc_dev.dv_xname, data); 613 fxp_eeprom_update_cksum(sc); 614 } 615 } 616 } 617 618 static void 619 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 620 { 621 uint16_t reg; 622 int x; 623 624 for (x = 1 << (len - 1); x != 0; x >>= 1) { 625 if (data & x) 626 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 627 else 628 reg = FXP_EEPROM_EECS; 629 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 630 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 631 reg | FXP_EEPROM_EESK); 632 DELAY(4); 633 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 634 DELAY(4); 635 } 636 } 637 638 /* 639 * Figure out EEPROM size. 640 * 641 * 559's can have either 64-word or 256-word EEPROMs, the 558 642 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 643 * talks about the existance of 16 to 256 word EEPROMs. 644 * 645 * The only known sizes are 64 and 256, where the 256 version is used 646 * by CardBus cards to store CIS information. 647 * 648 * The address is shifted in msb-to-lsb, and after the last 649 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 650 * after which follows the actual data. We try to detect this zero, by 651 * probing the data-out bit in the EEPROM control register just after 652 * having shifted in a bit. If the bit is zero, we assume we've 653 * shifted enough address bits. The data-out should be tri-state, 654 * before this, which should translate to a logical one. 655 * 656 * Other ways to do this would be to try to read a register with known 657 * contents with a varying number of address bits, but no such 658 * register seem to be available. The high bits of register 10 are 01 659 * on the 558 and 559, but apparently not on the 557. 660 * 661 * The Linux driver computes a checksum on the EEPROM data, but the 662 * value of this checksum is not very well documented. 663 */ 664 665 void 666 fxp_autosize_eeprom(struct fxp_softc *sc) 667 { 668 int x; 669 670 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 671 672 /* Shift in read opcode. */ 673 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 674 675 /* 676 * Shift in address, wait for the dummy zero following a correct 677 * address shift. 678 */ 679 for (x = 1; x <= 8; x++) { 680 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 681 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 682 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 683 DELAY(4); 684 if((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 685 FXP_EEPROM_EEDO) == 0) 686 break; 687 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 688 DELAY(4); 689 } 690 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 691 DELAY(4); 692 if(x != 6 && x != 8) { 693 #ifdef DEBUG 694 printf("%s: strange EEPROM size (%d)\n", 695 sc->sc_dev.dv_xname, 1 << x); 696 #endif 697 } else 698 sc->sc_eeprom_size = x; 699 } 700 701 /* 702 * Read from the serial EEPROM. Basically, you manually shift in 703 * the read opcode (one bit at a time) and then shift in the address, 704 * and then you shift out the data (all of this one bit at a time). 705 * The word size is 16 bits, so you have to provide the address for 706 * every 16 bits of data. 707 */ 708 void 709 fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 710 { 711 u_int16_t reg; 712 int i, x; 713 714 for (i = 0; i < words; i++) { 715 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 716 717 /* Shift in read opcode. */ 718 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 719 720 /* Shift in address. */ 721 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 722 723 reg = FXP_EEPROM_EECS; 724 data[i] = 0; 725 726 /* Shift out data. */ 727 for (x = 16; x > 0; x--) { 728 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 729 reg | FXP_EEPROM_EESK); 730 DELAY(4); 731 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 732 FXP_EEPROM_EEDO) 733 data[i] |= (1 << (x - 1)); 734 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 735 DELAY(4); 736 } 737 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 738 DELAY(4); 739 } 740 } 741 742 /* 743 * Write data to the serial EEPROM. 744 */ 745 void 746 fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 747 { 748 int i, j; 749 750 for (i = 0; i < words; i++) { 751 /* Erase/write enable. */ 752 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 753 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 754 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 755 sc->sc_eeprom_size); 756 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 757 DELAY(4); 758 759 /* Shift in write opcode, address, data. */ 760 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 761 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 762 fxp_eeprom_shiftin(sc, offset, sc->sc_eeprom_size); 763 fxp_eeprom_shiftin(sc, data[i], 16); 764 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 765 DELAY(4); 766 767 /* Wait for the EEPROM to finish up. */ 768 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 769 DELAY(4); 770 for (j = 0; j < 1000; j++) { 771 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 772 FXP_EEPROM_EEDO) 773 break; 774 DELAY(50); 775 } 776 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 777 DELAY(4); 778 779 /* Erase/write disable. */ 780 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 781 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 782 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 783 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 784 DELAY(4); 785 } 786 } 787 788 /* 789 * Update the checksum of the EEPROM. 790 */ 791 void 792 fxp_eeprom_update_cksum(struct fxp_softc *sc) 793 { 794 int i; 795 uint16_t data, cksum; 796 797 cksum = 0; 798 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 799 fxp_read_eeprom(sc, &data, i, 1); 800 cksum += data; 801 } 802 i = (1 << sc->sc_eeprom_size) - 1; 803 cksum = 0xbaba - cksum; 804 fxp_read_eeprom(sc, &data, i, 1); 805 fxp_write_eeprom(sc, &cksum, i, 1); 806 printf("%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 807 sc->sc_dev.dv_xname, i, data, cksum); 808 } 809 810 /* 811 * Start packet transmission on the interface. 812 */ 813 void 814 fxp_start(struct ifnet *ifp) 815 { 816 struct fxp_softc *sc = ifp->if_softc; 817 struct mbuf *m0, *m; 818 struct fxp_txdesc *txd; 819 struct fxp_txsoft *txs; 820 bus_dmamap_t dmamap; 821 int error, lasttx, nexttx, opending, seg; 822 823 /* 824 * If we want a re-init, bail out now. 825 */ 826 if (sc->sc_flags & FXPF_WANTINIT) { 827 ifp->if_flags |= IFF_OACTIVE; 828 return; 829 } 830 831 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 832 return; 833 834 /* 835 * Remember the previous txpending and the current lasttx. 836 */ 837 opending = sc->sc_txpending; 838 lasttx = sc->sc_txlast; 839 840 /* 841 * Loop through the send queue, setting up transmit descriptors 842 * until we drain the queue, or use up all available transmit 843 * descriptors. 844 */ 845 for (;;) { 846 /* 847 * Grab a packet off the queue. 848 */ 849 IFQ_POLL(&ifp->if_snd, m0); 850 if (m0 == NULL) 851 break; 852 m = NULL; 853 854 if (sc->sc_txpending == FXP_NTXCB) { 855 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 856 break; 857 } 858 859 /* 860 * Get the next available transmit descriptor. 861 */ 862 nexttx = FXP_NEXTTX(sc->sc_txlast); 863 txd = FXP_CDTX(sc, nexttx); 864 txs = FXP_DSTX(sc, nexttx); 865 dmamap = txs->txs_dmamap; 866 867 /* 868 * Load the DMA map. If this fails, the packet either 869 * didn't fit in the allotted number of frags, or we were 870 * short on resources. In this case, we'll copy and try 871 * again. 872 */ 873 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 874 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 875 MGETHDR(m, M_DONTWAIT, MT_DATA); 876 if (m == NULL) { 877 printf("%s: unable to allocate Tx mbuf\n", 878 sc->sc_dev.dv_xname); 879 break; 880 } 881 if (m0->m_pkthdr.len > MHLEN) { 882 MCLGET(m, M_DONTWAIT); 883 if ((m->m_flags & M_EXT) == 0) { 884 printf("%s: unable to allocate Tx " 885 "cluster\n", sc->sc_dev.dv_xname); 886 m_freem(m); 887 break; 888 } 889 } 890 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 891 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 892 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 893 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 894 if (error) { 895 printf("%s: unable to load Tx buffer, " 896 "error = %d\n", sc->sc_dev.dv_xname, error); 897 break; 898 } 899 } 900 901 IFQ_DEQUEUE(&ifp->if_snd, m0); 902 if (m != NULL) { 903 m_freem(m0); 904 m0 = m; 905 } 906 907 /* Initialize the fraglist. */ 908 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 909 txd->txd_tbd[seg].tb_addr = 910 htole32(dmamap->dm_segs[seg].ds_addr); 911 txd->txd_tbd[seg].tb_size = 912 htole32(dmamap->dm_segs[seg].ds_len); 913 } 914 915 /* Sync the DMA map. */ 916 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 917 BUS_DMASYNC_PREWRITE); 918 919 /* 920 * Store a pointer to the packet so we can free it later. 921 */ 922 txs->txs_mbuf = m0; 923 924 /* 925 * Initialize the transmit descriptor. 926 */ 927 /* BIG_ENDIAN: no need to swap to store 0 */ 928 txd->txd_txcb.cb_status = 0; 929 txd->txd_txcb.cb_command = 930 htole16(FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF); 931 txd->txd_txcb.tx_threshold = tx_threshold; 932 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 933 934 FXP_CDTXSYNC(sc, nexttx, 935 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 936 937 /* Advance the tx pointer. */ 938 sc->sc_txpending++; 939 sc->sc_txlast = nexttx; 940 941 #if NBPFILTER > 0 942 /* 943 * Pass packet to bpf if there is a listener. 944 */ 945 if (ifp->if_bpf) 946 bpf_mtap(ifp->if_bpf, m0); 947 #endif 948 } 949 950 if (sc->sc_txpending == FXP_NTXCB) { 951 /* No more slots; notify upper layer. */ 952 ifp->if_flags |= IFF_OACTIVE; 953 } 954 955 if (sc->sc_txpending != opending) { 956 /* 957 * We enqueued packets. If the transmitter was idle, 958 * reset the txdirty pointer. 959 */ 960 if (opending == 0) 961 sc->sc_txdirty = FXP_NEXTTX(lasttx); 962 963 /* 964 * Cause the chip to interrupt and suspend command 965 * processing once the last packet we've enqueued 966 * has been transmitted. 967 */ 968 FXP_CDTX(sc, sc->sc_txlast)->txd_txcb.cb_command |= 969 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 970 FXP_CDTXSYNC(sc, sc->sc_txlast, 971 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 972 973 /* 974 * The entire packet chain is set up. Clear the suspend bit 975 * on the command prior to the first packet we set up. 976 */ 977 FXP_CDTXSYNC(sc, lasttx, 978 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 979 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 980 htole16(~FXP_CB_COMMAND_S); 981 FXP_CDTXSYNC(sc, lasttx, 982 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 983 984 /* 985 * Issue a Resume command in case the chip was suspended. 986 */ 987 fxp_scb_wait(sc); 988 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 989 990 /* Set a watchdog timer in case the chip flakes out. */ 991 ifp->if_timer = 5; 992 } 993 } 994 995 /* 996 * Process interface interrupts. 997 */ 998 int 999 fxp_intr(void *arg) 1000 { 1001 struct fxp_softc *sc = arg; 1002 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1003 bus_dmamap_t rxmap; 1004 int claimed = 0; 1005 u_int8_t statack; 1006 1007 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1008 return (0); 1009 /* 1010 * If the interface isn't running, don't try to 1011 * service the interrupt.. just ack it and bail. 1012 */ 1013 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1014 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1015 if (statack) { 1016 claimed = 1; 1017 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1018 } 1019 return (claimed); 1020 } 1021 1022 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1023 claimed = 1; 1024 1025 /* 1026 * First ACK all the interrupts in this pass. 1027 */ 1028 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1029 1030 /* 1031 * Process receiver interrupts. If a no-resource (RNR) 1032 * condition exists, get whatever packets we can and 1033 * re-start the receiver. 1034 */ 1035 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1036 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1037 fxp_rxintr(sc); 1038 } 1039 1040 if (statack & FXP_SCB_STATACK_RNR) { 1041 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1042 fxp_scb_wait(sc); 1043 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1044 rxmap->dm_segs[0].ds_addr + 1045 RFA_ALIGNMENT_FUDGE); 1046 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1047 } 1048 1049 /* 1050 * Free any finished transmit mbuf chains. 1051 */ 1052 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1053 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1054 fxp_txintr(sc); 1055 1056 /* 1057 * Try to get more packets going. 1058 */ 1059 fxp_start(ifp); 1060 1061 if (sc->sc_txpending == 0) { 1062 /* 1063 * If we want a re-init, do that now. 1064 */ 1065 if (sc->sc_flags & FXPF_WANTINIT) 1066 (void) fxp_init(ifp); 1067 } 1068 } 1069 } 1070 1071 #if NRND > 0 1072 if (claimed) 1073 rnd_add_uint32(&sc->rnd_source, statack); 1074 #endif 1075 return (claimed); 1076 } 1077 1078 /* 1079 * Handle transmit completion interrupts. 1080 */ 1081 void 1082 fxp_txintr(struct fxp_softc *sc) 1083 { 1084 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1085 struct fxp_txdesc *txd; 1086 struct fxp_txsoft *txs; 1087 int i; 1088 u_int16_t txstat; 1089 1090 ifp->if_flags &= ~IFF_OACTIVE; 1091 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1092 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1093 txd = FXP_CDTX(sc, i); 1094 txs = FXP_DSTX(sc, i); 1095 1096 FXP_CDTXSYNC(sc, i, 1097 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1098 1099 txstat = le16toh(txd->txd_txcb.cb_status); 1100 1101 if ((txstat & FXP_CB_STATUS_C) == 0) 1102 break; 1103 1104 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1105 0, txs->txs_dmamap->dm_mapsize, 1106 BUS_DMASYNC_POSTWRITE); 1107 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1108 m_freem(txs->txs_mbuf); 1109 txs->txs_mbuf = NULL; 1110 } 1111 1112 /* Update the dirty transmit buffer pointer. */ 1113 sc->sc_txdirty = i; 1114 1115 /* 1116 * Cancel the watchdog timer if there are no pending 1117 * transmissions. 1118 */ 1119 if (sc->sc_txpending == 0) 1120 ifp->if_timer = 0; 1121 } 1122 1123 /* 1124 * Handle receive interrupts. 1125 */ 1126 void 1127 fxp_rxintr(struct fxp_softc *sc) 1128 { 1129 struct ethercom *ec = &sc->sc_ethercom; 1130 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1131 struct mbuf *m, *m0; 1132 bus_dmamap_t rxmap; 1133 struct fxp_rfa *rfa; 1134 u_int16_t len, rxstat; 1135 1136 for (;;) { 1137 m = sc->sc_rxq.ifq_head; 1138 rfa = FXP_MTORFA(m); 1139 rxmap = M_GETCTX(m, bus_dmamap_t); 1140 1141 FXP_RFASYNC(sc, m, 1142 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1143 1144 rxstat = le16toh(rfa->rfa_status); 1145 1146 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1147 /* 1148 * We have processed all of the 1149 * receive buffers. 1150 */ 1151 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1152 return; 1153 } 1154 1155 IF_DEQUEUE(&sc->sc_rxq, m); 1156 1157 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1158 1159 len = le16toh(rfa->actual_size) & 1160 (m->m_ext.ext_size - 1); 1161 1162 if (len < sizeof(struct ether_header)) { 1163 /* 1164 * Runt packet; drop it now. 1165 */ 1166 FXP_INIT_RFABUF(sc, m); 1167 continue; 1168 } 1169 1170 /* 1171 * If support for 802.1Q VLAN sized frames is 1172 * enabled, we need to do some additional error 1173 * checking (as we are saving bad frames, in 1174 * order to receive the larger ones). 1175 */ 1176 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1177 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1178 FXP_RFA_STATUS_RNR| 1179 FXP_RFA_STATUS_ALIGN| 1180 FXP_RFA_STATUS_CRC)) != 0) { 1181 FXP_INIT_RFABUF(sc, m); 1182 continue; 1183 } 1184 1185 /* 1186 * If the packet is small enough to fit in a 1187 * single header mbuf, allocate one and copy 1188 * the data into it. This greatly reduces 1189 * memory consumption when we receive lots 1190 * of small packets. 1191 * 1192 * Otherwise, we add a new buffer to the receive 1193 * chain. If this fails, we drop the packet and 1194 * recycle the old buffer. 1195 */ 1196 if (fxp_copy_small != 0 && len <= MHLEN) { 1197 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1198 if (m == NULL) 1199 goto dropit; 1200 memcpy(mtod(m0, caddr_t), 1201 mtod(m, caddr_t), len); 1202 FXP_INIT_RFABUF(sc, m); 1203 m = m0; 1204 } else { 1205 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1206 dropit: 1207 ifp->if_ierrors++; 1208 FXP_INIT_RFABUF(sc, m); 1209 continue; 1210 } 1211 } 1212 1213 m->m_pkthdr.rcvif = ifp; 1214 m->m_pkthdr.len = m->m_len = len; 1215 1216 #if NBPFILTER > 0 1217 /* 1218 * Pass this up to any BPF listeners, but only 1219 * pass it up the stack it its for us. 1220 */ 1221 if (ifp->if_bpf) 1222 bpf_mtap(ifp->if_bpf, m); 1223 #endif 1224 1225 /* Pass it on. */ 1226 (*ifp->if_input)(ifp, m); 1227 } 1228 } 1229 1230 /* 1231 * Update packet in/out/collision statistics. The i82557 doesn't 1232 * allow you to access these counters without doing a fairly 1233 * expensive DMA to get _all_ of the statistics it maintains, so 1234 * we do this operation here only once per second. The statistics 1235 * counters in the kernel are updated from the previous dump-stats 1236 * DMA and then a new dump-stats DMA is started. The on-chip 1237 * counters are zeroed when the DMA completes. If we can't start 1238 * the DMA immediately, we don't wait - we just prepare to read 1239 * them again next time. 1240 */ 1241 void 1242 fxp_tick(void *arg) 1243 { 1244 struct fxp_softc *sc = arg; 1245 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1246 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1247 int s; 1248 1249 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1250 return; 1251 1252 s = splnet(); 1253 1254 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1255 1256 ifp->if_opackets += le32toh(sp->tx_good); 1257 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1258 if (sp->rx_good) { 1259 ifp->if_ipackets += le32toh(sp->rx_good); 1260 sc->sc_rxidle = 0; 1261 } else { 1262 sc->sc_rxidle++; 1263 } 1264 ifp->if_ierrors += 1265 le32toh(sp->rx_crc_errors) + 1266 le32toh(sp->rx_alignment_errors) + 1267 le32toh(sp->rx_rnr_errors) + 1268 le32toh(sp->rx_overrun_errors); 1269 /* 1270 * If any transmit underruns occurred, bump up the transmit 1271 * threshold by another 512 bytes (64 * 8). 1272 */ 1273 if (sp->tx_underruns) { 1274 ifp->if_oerrors += le32toh(sp->tx_underruns); 1275 if (tx_threshold < 192) 1276 tx_threshold += 64; 1277 } 1278 1279 /* 1280 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1281 * then assume the receiver has locked up and attempt to clear 1282 * the condition by reprogramming the multicast filter (actually, 1283 * resetting the interface). This is a work-around for a bug in 1284 * the 82557 where the receiver locks up if it gets certain types 1285 * of garbage in the syncronization bits prior to the packet header. 1286 * This bug is supposed to only occur in 10Mbps mode, but has been 1287 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1288 * speed transition). 1289 */ 1290 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1291 (void) fxp_init(ifp); 1292 splx(s); 1293 return; 1294 } 1295 /* 1296 * If there is no pending command, start another stats 1297 * dump. Otherwise punt for now. 1298 */ 1299 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1300 /* 1301 * Start another stats dump. 1302 */ 1303 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1304 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1305 } else { 1306 /* 1307 * A previous command is still waiting to be accepted. 1308 * Just zero our copy of the stats and wait for the 1309 * next timer event to update them. 1310 */ 1311 /* BIG_ENDIAN: no swap required to store 0 */ 1312 sp->tx_good = 0; 1313 sp->tx_underruns = 0; 1314 sp->tx_total_collisions = 0; 1315 1316 sp->rx_good = 0; 1317 sp->rx_crc_errors = 0; 1318 sp->rx_alignment_errors = 0; 1319 sp->rx_rnr_errors = 0; 1320 sp->rx_overrun_errors = 0; 1321 } 1322 1323 if (sc->sc_flags & FXPF_MII) { 1324 /* Tick the MII clock. */ 1325 mii_tick(&sc->sc_mii); 1326 } 1327 1328 splx(s); 1329 1330 /* 1331 * Schedule another timeout one second from now. 1332 */ 1333 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1334 } 1335 1336 /* 1337 * Drain the receive queue. 1338 */ 1339 void 1340 fxp_rxdrain(struct fxp_softc *sc) 1341 { 1342 bus_dmamap_t rxmap; 1343 struct mbuf *m; 1344 1345 for (;;) { 1346 IF_DEQUEUE(&sc->sc_rxq, m); 1347 if (m == NULL) 1348 break; 1349 rxmap = M_GETCTX(m, bus_dmamap_t); 1350 bus_dmamap_unload(sc->sc_dmat, rxmap); 1351 FXP_RXMAP_PUT(sc, rxmap); 1352 m_freem(m); 1353 } 1354 } 1355 1356 /* 1357 * Stop the interface. Cancels the statistics updater and resets 1358 * the interface. 1359 */ 1360 void 1361 fxp_stop(struct ifnet *ifp, int disable) 1362 { 1363 struct fxp_softc *sc = ifp->if_softc; 1364 struct fxp_txsoft *txs; 1365 int i; 1366 1367 /* 1368 * Turn down interface (done early to avoid bad interactions 1369 * between panics, shutdown hooks, and the watchdog timer) 1370 */ 1371 ifp->if_timer = 0; 1372 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1373 1374 /* 1375 * Cancel stats updater. 1376 */ 1377 callout_stop(&sc->sc_callout); 1378 if (sc->sc_flags & FXPF_MII) { 1379 /* Down the MII. */ 1380 mii_down(&sc->sc_mii); 1381 } 1382 1383 /* 1384 * Issue software reset. This unloads any microcode that 1385 * might already be loaded. 1386 */ 1387 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1388 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1389 DELAY(50); 1390 1391 /* 1392 * Release any xmit buffers. 1393 */ 1394 for (i = 0; i < FXP_NTXCB; i++) { 1395 txs = FXP_DSTX(sc, i); 1396 if (txs->txs_mbuf != NULL) { 1397 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1398 m_freem(txs->txs_mbuf); 1399 txs->txs_mbuf = NULL; 1400 } 1401 } 1402 sc->sc_txpending = 0; 1403 1404 if (disable) { 1405 fxp_rxdrain(sc); 1406 fxp_disable(sc); 1407 } 1408 1409 } 1410 1411 /* 1412 * Watchdog/transmission transmit timeout handler. Called when a 1413 * transmission is started on the interface, but no interrupt is 1414 * received before the timeout. This usually indicates that the 1415 * card has wedged for some reason. 1416 */ 1417 void 1418 fxp_watchdog(struct ifnet *ifp) 1419 { 1420 struct fxp_softc *sc = ifp->if_softc; 1421 1422 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1423 ifp->if_oerrors++; 1424 1425 (void) fxp_init(ifp); 1426 } 1427 1428 /* 1429 * Initialize the interface. Must be called at splnet(). 1430 */ 1431 int 1432 fxp_init(struct ifnet *ifp) 1433 { 1434 struct fxp_softc *sc = ifp->if_softc; 1435 struct fxp_cb_config *cbp; 1436 struct fxp_cb_ias *cb_ias; 1437 struct fxp_txdesc *txd; 1438 bus_dmamap_t rxmap; 1439 int i, prm, save_bf, lrxen, allm, error = 0; 1440 1441 if ((error = fxp_enable(sc)) != 0) 1442 goto out; 1443 1444 /* 1445 * Cancel any pending I/O 1446 */ 1447 fxp_stop(ifp, 0); 1448 1449 /* 1450 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1451 * flag, and this prevents the MII from detaching resulting in 1452 * a panic. The flags field should perhaps be split in runtime 1453 * flags and more static information. For now, just clear the 1454 * only other flag set. 1455 */ 1456 1457 sc->sc_flags &= ~FXPF_WANTINIT; 1458 1459 /* 1460 * Initialize base of CBL and RFA memory. Loading with zero 1461 * sets it up for regular linear addressing. 1462 */ 1463 fxp_scb_wait(sc); 1464 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1465 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1466 1467 fxp_scb_wait(sc); 1468 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1469 1470 /* 1471 * Initialize the multicast filter. Do this now, since we might 1472 * have to setup the config block differently. 1473 */ 1474 fxp_mc_setup(sc); 1475 1476 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1477 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1478 1479 /* 1480 * In order to support receiving 802.1Q VLAN frames, we have to 1481 * enable "save bad frames", since they are 4 bytes larger than 1482 * the normal Ethernet maximum frame length. On i82558 and later, 1483 * we have a better mechanism for this. 1484 */ 1485 save_bf = 0; 1486 lrxen = 0; 1487 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1488 if (sc->sc_rev < FXP_REV_82558_A4) 1489 save_bf = 1; 1490 else 1491 lrxen = 1; 1492 } 1493 1494 /* 1495 * Initialize base of dump-stats buffer. 1496 */ 1497 fxp_scb_wait(sc); 1498 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1499 sc->sc_cddma + FXP_CDSTATSOFF); 1500 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1501 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1502 1503 cbp = &sc->sc_control_data->fcd_configcb; 1504 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1505 1506 /* 1507 * Load microcode for this controller. 1508 */ 1509 fxp_load_ucode(sc); 1510 1511 /* 1512 * This copy is kind of disgusting, but there are a bunch of must be 1513 * zero and must be one bits in this structure and this is the easiest 1514 * way to initialize them all to proper values. 1515 */ 1516 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1517 1518 /* BIG_ENDIAN: no need to swap to store 0 */ 1519 cbp->cb_status = 0; 1520 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1521 FXP_CB_COMMAND_EL); 1522 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1523 cbp->link_addr = 0xffffffff; /* (no) next command */ 1524 /* bytes in config block */ 1525 cbp->byte_count = FXP_CONFIG_LEN; 1526 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1527 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1528 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1529 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1530 cbp->type_enable = 0; /* actually reserved */ 1531 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1532 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1533 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1534 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1535 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1536 cbp->late_scb = 0; /* (don't) defer SCB update */ 1537 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1538 cbp->ci_int = 1; /* interrupt on CU idle */ 1539 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1540 cbp->ext_stats_dis = 1; /* disable extended counters */ 1541 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1542 cbp->save_bf = save_bf;/* save bad frames */ 1543 cbp->disc_short_rx = !prm; /* discard short packets */ 1544 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1545 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1546 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1547 /* interface mode */ 1548 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1549 cbp->csma_dis = 0; /* (don't) disable link */ 1550 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1551 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1552 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1553 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1554 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1555 cbp->nsai = 1; /* (don't) disable source addr insert */ 1556 cbp->preamble_length = 2; /* (7 byte) preamble */ 1557 cbp->loopback = 0; /* (don't) loopback */ 1558 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1559 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1560 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1561 cbp->promiscuous = prm; /* promiscuous mode */ 1562 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1563 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1564 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1565 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1566 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1567 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1568 cbp->padding = 1; /* (do) pad short tx packets */ 1569 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1570 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1571 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1572 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1573 /* must set wake_en in PMCSR also */ 1574 cbp->force_fdx = 0; /* (don't) force full duplex */ 1575 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1576 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1577 cbp->mc_all = allm; /* accept all multicasts */ 1578 1579 if (sc->sc_rev < FXP_REV_82558_A4) { 1580 /* 1581 * The i82557 has no hardware flow control, the values 1582 * here are the defaults for the chip. 1583 */ 1584 cbp->fc_delay_lsb = 0; 1585 cbp->fc_delay_msb = 0x40; 1586 cbp->pri_fc_thresh = 3; 1587 cbp->tx_fc_dis = 0; 1588 cbp->rx_fc_restop = 0; 1589 cbp->rx_fc_restart = 0; 1590 cbp->fc_filter = 0; 1591 cbp->pri_fc_loc = 1; 1592 } else { 1593 cbp->fc_delay_lsb = 0x1f; 1594 cbp->fc_delay_msb = 0x01; 1595 cbp->pri_fc_thresh = 3; 1596 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1597 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1598 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1599 cbp->fc_filter = !prm; /* drop FC frames to host */ 1600 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1601 } 1602 1603 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1604 1605 /* 1606 * Start the config command/DMA. 1607 */ 1608 fxp_scb_wait(sc); 1609 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1610 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1611 /* ...and wait for it to complete. */ 1612 i = 1000; 1613 do { 1614 FXP_CDCONFIGSYNC(sc, 1615 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1616 DELAY(1); 1617 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1618 if (i == 0) { 1619 printf("%s at line %d: dmasync timeout\n", 1620 sc->sc_dev.dv_xname, __LINE__); 1621 return ETIMEDOUT; 1622 } 1623 1624 /* 1625 * Initialize the station address. 1626 */ 1627 cb_ias = &sc->sc_control_data->fcd_iascb; 1628 /* BIG_ENDIAN: no need to swap to store 0 */ 1629 cb_ias->cb_status = 0; 1630 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1631 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1632 cb_ias->link_addr = 0xffffffff; 1633 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1634 1635 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1636 1637 /* 1638 * Start the IAS (Individual Address Setup) command/DMA. 1639 */ 1640 fxp_scb_wait(sc); 1641 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1642 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1643 /* ...and wait for it to complete. */ 1644 i = 1000; 1645 do { 1646 FXP_CDIASSYNC(sc, 1647 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1648 DELAY(1); 1649 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1650 if (i == 0) { 1651 printf("%s at line %d: dmasync timeout\n", 1652 sc->sc_dev.dv_xname, __LINE__); 1653 return ETIMEDOUT; 1654 } 1655 1656 /* 1657 * Initialize the transmit descriptor ring. txlast is initialized 1658 * to the end of the list so that it will wrap around to the first 1659 * descriptor when the first packet is transmitted. 1660 */ 1661 for (i = 0; i < FXP_NTXCB; i++) { 1662 txd = FXP_CDTX(sc, i); 1663 memset(txd, 0, sizeof(*txd)); 1664 txd->txd_txcb.cb_command = 1665 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1666 txd->txd_txcb.link_addr = 1667 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1668 if (sc->sc_flags & FXPF_EXT_TXCB) 1669 txd->txd_txcb.tbd_array_addr = 1670 htole32(FXP_CDTBDADDR(sc, i) + 1671 (2 * sizeof(struct fxp_tbd))); 1672 else 1673 txd->txd_txcb.tbd_array_addr = 1674 htole32(FXP_CDTBDADDR(sc, i)); 1675 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1676 } 1677 sc->sc_txpending = 0; 1678 sc->sc_txdirty = 0; 1679 sc->sc_txlast = FXP_NTXCB - 1; 1680 1681 /* 1682 * Initialize the receive buffer list. 1683 */ 1684 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1685 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1686 rxmap = FXP_RXMAP_GET(sc); 1687 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1688 printf("%s: unable to allocate or map rx " 1689 "buffer %d, error = %d\n", 1690 sc->sc_dev.dv_xname, 1691 sc->sc_rxq.ifq_len, error); 1692 /* 1693 * XXX Should attempt to run with fewer receive 1694 * XXX buffers instead of just failing. 1695 */ 1696 FXP_RXMAP_PUT(sc, rxmap); 1697 fxp_rxdrain(sc); 1698 goto out; 1699 } 1700 } 1701 sc->sc_rxidle = 0; 1702 1703 /* 1704 * Give the transmit ring to the chip. We do this by pointing 1705 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1706 * issuing a start command. It will execute the NOP and then 1707 * suspend, pointing at the first descriptor. 1708 */ 1709 fxp_scb_wait(sc); 1710 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1711 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1712 1713 /* 1714 * Initialize receiver buffer area - RFA. 1715 */ 1716 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1717 fxp_scb_wait(sc); 1718 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1719 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1720 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1721 1722 if (sc->sc_flags & FXPF_MII) { 1723 /* 1724 * Set current media. 1725 */ 1726 mii_mediachg(&sc->sc_mii); 1727 } 1728 1729 /* 1730 * ...all done! 1731 */ 1732 ifp->if_flags |= IFF_RUNNING; 1733 ifp->if_flags &= ~IFF_OACTIVE; 1734 1735 /* 1736 * Start the one second timer. 1737 */ 1738 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1739 1740 /* 1741 * Attempt to start output on the interface. 1742 */ 1743 fxp_start(ifp); 1744 1745 out: 1746 if (error) { 1747 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1748 ifp->if_timer = 0; 1749 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1750 } 1751 return (error); 1752 } 1753 1754 /* 1755 * Change media according to request. 1756 */ 1757 int 1758 fxp_mii_mediachange(struct ifnet *ifp) 1759 { 1760 struct fxp_softc *sc = ifp->if_softc; 1761 1762 if (ifp->if_flags & IFF_UP) 1763 mii_mediachg(&sc->sc_mii); 1764 return (0); 1765 } 1766 1767 /* 1768 * Notify the world which media we're using. 1769 */ 1770 void 1771 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1772 { 1773 struct fxp_softc *sc = ifp->if_softc; 1774 1775 if(sc->sc_enabled == 0) { 1776 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1777 ifmr->ifm_status = 0; 1778 return; 1779 } 1780 1781 mii_pollstat(&sc->sc_mii); 1782 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1783 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1784 } 1785 1786 int 1787 fxp_80c24_mediachange(struct ifnet *ifp) 1788 { 1789 1790 /* Nothing to do here. */ 1791 return (0); 1792 } 1793 1794 void 1795 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1796 { 1797 struct fxp_softc *sc = ifp->if_softc; 1798 1799 /* 1800 * Media is currently-selected media. We cannot determine 1801 * the link status. 1802 */ 1803 ifmr->ifm_status = 0; 1804 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1805 } 1806 1807 /* 1808 * Add a buffer to the end of the RFA buffer list. 1809 * Return 0 if successful, error code on failure. 1810 * 1811 * The RFA struct is stuck at the beginning of mbuf cluster and the 1812 * data pointer is fixed up to point just past it. 1813 */ 1814 int 1815 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 1816 { 1817 struct mbuf *m; 1818 int error; 1819 1820 MGETHDR(m, M_DONTWAIT, MT_DATA); 1821 if (m == NULL) 1822 return (ENOBUFS); 1823 1824 MCLGET(m, M_DONTWAIT); 1825 if ((m->m_flags & M_EXT) == 0) { 1826 m_freem(m); 1827 return (ENOBUFS); 1828 } 1829 1830 if (unload) 1831 bus_dmamap_unload(sc->sc_dmat, rxmap); 1832 1833 M_SETCTX(m, rxmap); 1834 1835 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1836 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1837 BUS_DMA_READ|BUS_DMA_NOWAIT); 1838 if (error) { 1839 printf("%s: can't load rx DMA map %d, error = %d\n", 1840 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1841 panic("fxp_add_rfabuf"); /* XXX */ 1842 } 1843 1844 FXP_INIT_RFABUF(sc, m); 1845 1846 return (0); 1847 } 1848 1849 int 1850 fxp_mdi_read(struct device *self, int phy, int reg) 1851 { 1852 struct fxp_softc *sc = (struct fxp_softc *)self; 1853 int count = 10000; 1854 int value; 1855 1856 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1857 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1858 1859 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1860 && count--) 1861 DELAY(10); 1862 1863 if (count <= 0) 1864 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1865 1866 return (value & 0xffff); 1867 } 1868 1869 void 1870 fxp_statchg(struct device *self) 1871 { 1872 1873 /* Nothing to do. */ 1874 } 1875 1876 void 1877 fxp_mdi_write(struct device *self, int phy, int reg, int value) 1878 { 1879 struct fxp_softc *sc = (struct fxp_softc *)self; 1880 int count = 10000; 1881 1882 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1883 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1884 (value & 0xffff)); 1885 1886 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1887 count--) 1888 DELAY(10); 1889 1890 if (count <= 0) 1891 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 1892 } 1893 1894 int 1895 fxp_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1896 { 1897 struct fxp_softc *sc = ifp->if_softc; 1898 struct ifreq *ifr = (struct ifreq *)data; 1899 int s, error; 1900 1901 s = splnet(); 1902 1903 switch (cmd) { 1904 case SIOCSIFMEDIA: 1905 case SIOCGIFMEDIA: 1906 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1907 break; 1908 1909 default: 1910 error = ether_ioctl(ifp, cmd, data); 1911 if (error == ENETRESET) { 1912 if (sc->sc_enabled) { 1913 /* 1914 * Multicast list has changed; set the 1915 * hardware filter accordingly. 1916 */ 1917 if (sc->sc_txpending) { 1918 sc->sc_flags |= FXPF_WANTINIT; 1919 error = 0; 1920 } else 1921 error = fxp_init(ifp); 1922 } else 1923 error = 0; 1924 } 1925 break; 1926 } 1927 1928 /* Try to get more packets going. */ 1929 if (sc->sc_enabled) 1930 fxp_start(ifp); 1931 1932 splx(s); 1933 return (error); 1934 } 1935 1936 /* 1937 * Program the multicast filter. 1938 * 1939 * This function must be called at splnet(). 1940 */ 1941 void 1942 fxp_mc_setup(struct fxp_softc *sc) 1943 { 1944 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 1945 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1946 struct ethercom *ec = &sc->sc_ethercom; 1947 struct ether_multi *enm; 1948 struct ether_multistep step; 1949 int count, nmcasts; 1950 1951 #ifdef DIAGNOSTIC 1952 if (sc->sc_txpending) 1953 panic("fxp_mc_setup: pending transmissions"); 1954 #endif 1955 1956 ifp->if_flags &= ~IFF_ALLMULTI; 1957 1958 /* 1959 * Initialize multicast setup descriptor. 1960 */ 1961 nmcasts = 0; 1962 ETHER_FIRST_MULTI(step, ec, enm); 1963 while (enm != NULL) { 1964 /* 1965 * Check for too many multicast addresses or if we're 1966 * listening to a range. Either way, we simply have 1967 * to accept all multicasts. 1968 */ 1969 if (nmcasts >= MAXMCADDR || 1970 memcmp(enm->enm_addrlo, enm->enm_addrhi, 1971 ETHER_ADDR_LEN) != 0) { 1972 /* 1973 * Callers of this function must do the 1974 * right thing with this. If we're called 1975 * from outside fxp_init(), the caller must 1976 * detect if the state if IFF_ALLMULTI changes. 1977 * If it does, the caller must then call 1978 * fxp_init(), since allmulti is handled by 1979 * the config block. 1980 */ 1981 ifp->if_flags |= IFF_ALLMULTI; 1982 return; 1983 } 1984 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 1985 ETHER_ADDR_LEN); 1986 nmcasts++; 1987 ETHER_NEXT_MULTI(step, enm); 1988 } 1989 1990 /* BIG_ENDIAN: no need to swap to store 0 */ 1991 mcsp->cb_status = 0; 1992 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1993 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 1994 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 1995 1996 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1997 1998 /* 1999 * Wait until the command unit is not active. This should never 2000 * happen since nothing is queued, but make sure anyway. 2001 */ 2002 count = 100; 2003 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2004 FXP_SCB_CUS_ACTIVE && --count) 2005 DELAY(1); 2006 if (count == 0) { 2007 printf("%s at line %d: command queue timeout\n", 2008 sc->sc_dev.dv_xname, __LINE__); 2009 return; 2010 } 2011 2012 /* 2013 * Start the multicast setup command/DMA. 2014 */ 2015 fxp_scb_wait(sc); 2016 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2017 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2018 2019 /* ...and wait for it to complete. */ 2020 count = 1000; 2021 do { 2022 FXP_CDMCSSYNC(sc, 2023 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2024 DELAY(1); 2025 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2026 if (count == 0) { 2027 printf("%s at line %d: dmasync timeout\n", 2028 sc->sc_dev.dv_xname, __LINE__); 2029 return; 2030 } 2031 } 2032 2033 static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2034 static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2035 static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2036 static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2037 static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2038 static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2039 2040 #define UCODE(x) x, sizeof(x) 2041 2042 static const struct ucode { 2043 uint32_t revision; 2044 const uint32_t *ucode; 2045 size_t length; 2046 uint16_t int_delay_offset; 2047 uint16_t bundle_max_offset; 2048 } ucode_table[] = { 2049 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2050 D101_CPUSAVER_DWORD, 0 }, 2051 2052 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2053 D101_CPUSAVER_DWORD, 0 }, 2054 2055 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2056 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2057 2058 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2059 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2060 2061 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2062 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2063 2064 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2065 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2066 2067 { 0, NULL, 0, 0, 0 } 2068 }; 2069 2070 void 2071 fxp_load_ucode(struct fxp_softc *sc) 2072 { 2073 const struct ucode *uc; 2074 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2075 int count; 2076 2077 if (sc->sc_flags & FXPF_UCODE_LOADED) 2078 return; 2079 2080 /* 2081 * Only load the uCode if the user has requested that 2082 * we do so. 2083 */ 2084 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2085 sc->sc_int_delay = 0; 2086 sc->sc_bundle_max = 0; 2087 return; 2088 } 2089 2090 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2091 if (sc->sc_rev == uc->revision) 2092 break; 2093 } 2094 if (uc->ucode == NULL) 2095 return; 2096 2097 /* BIG ENDIAN: no need to swap to store 0 */ 2098 cbp->cb_status = 0; 2099 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2100 cbp->link_addr = 0xffffffff; /* (no) next command */ 2101 memcpy((void *) cbp->ucode, uc->ucode, uc->length); 2102 2103 if (uc->int_delay_offset) 2104 *(uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2105 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2106 2107 if (uc->bundle_max_offset) 2108 *(uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2109 htole16(fxp_bundle_max); 2110 2111 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2112 2113 /* 2114 * Download the uCode to the chip. 2115 */ 2116 fxp_scb_wait(sc); 2117 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2118 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2119 2120 /* ...and wait for it to complete. */ 2121 count = 10000; 2122 do { 2123 FXP_CDUCODESYNC(sc, 2124 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2125 DELAY(2); 2126 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2127 if (count == 0) { 2128 sc->sc_int_delay = 0; 2129 sc->sc_bundle_max = 0; 2130 printf("%s: timeout loading microcode\n", 2131 sc->sc_dev.dv_xname); 2132 return; 2133 } 2134 2135 if (sc->sc_int_delay != fxp_int_delay || 2136 sc->sc_bundle_max != fxp_bundle_max) { 2137 sc->sc_int_delay = fxp_int_delay; 2138 sc->sc_bundle_max = fxp_bundle_max; 2139 printf("%s: Microcode loaded: int delay: %d usec, " 2140 "max bundle: %d\n", sc->sc_dev.dv_xname, 2141 sc->sc_int_delay, 2142 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2143 } 2144 2145 sc->sc_flags |= FXPF_UCODE_LOADED; 2146 } 2147 2148 int 2149 fxp_enable(struct fxp_softc *sc) 2150 { 2151 2152 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2153 if ((*sc->sc_enable)(sc) != 0) { 2154 printf("%s: device enable failed\n", 2155 sc->sc_dev.dv_xname); 2156 return (EIO); 2157 } 2158 } 2159 2160 sc->sc_enabled = 1; 2161 return (0); 2162 } 2163 2164 void 2165 fxp_disable(struct fxp_softc *sc) 2166 { 2167 2168 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2169 (*sc->sc_disable)(sc); 2170 sc->sc_enabled = 0; 2171 } 2172 } 2173 2174 /* 2175 * fxp_activate: 2176 * 2177 * Handle device activation/deactivation requests. 2178 */ 2179 int 2180 fxp_activate(struct device *self, enum devact act) 2181 { 2182 struct fxp_softc *sc = (void *) self; 2183 int s, error = 0; 2184 2185 s = splnet(); 2186 switch (act) { 2187 case DVACT_ACTIVATE: 2188 error = EOPNOTSUPP; 2189 break; 2190 2191 case DVACT_DEACTIVATE: 2192 if (sc->sc_flags & FXPF_MII) 2193 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2194 MII_OFFSET_ANY); 2195 if_deactivate(&sc->sc_ethercom.ec_if); 2196 break; 2197 } 2198 splx(s); 2199 2200 return (error); 2201 } 2202 2203 /* 2204 * fxp_detach: 2205 * 2206 * Detach an i82557 interface. 2207 */ 2208 int 2209 fxp_detach(struct fxp_softc *sc) 2210 { 2211 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2212 int i; 2213 2214 /* Succeed now if there's no work to do. */ 2215 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2216 return (0); 2217 2218 /* Unhook our tick handler. */ 2219 callout_stop(&sc->sc_callout); 2220 2221 if (sc->sc_flags & FXPF_MII) { 2222 /* Detach all PHYs */ 2223 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2224 } 2225 2226 /* Delete all remaining media. */ 2227 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2228 2229 #if NRND > 0 2230 rnd_detach_source(&sc->rnd_source); 2231 #endif 2232 ether_ifdetach(ifp); 2233 if_detach(ifp); 2234 2235 for (i = 0; i < FXP_NRFABUFS; i++) { 2236 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2237 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2238 } 2239 2240 for (i = 0; i < FXP_NTXCB; i++) { 2241 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2242 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2243 } 2244 2245 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2246 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2247 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2248 sizeof(struct fxp_control_data)); 2249 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2250 2251 shutdownhook_disestablish(sc->sc_sdhook); 2252 powerhook_disestablish(sc->sc_powerhook); 2253 2254 return (0); 2255 } 2256