1 /* $NetBSD: i82557var.h,v 1.29 2002/05/20 15:23:01 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice unmodified, this list of conditions, and the following 49 * disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 55 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 * Id: if_fxpvar.h,v 1.4 1997/11/29 08:11:01 davidg Exp 67 */ 68 69 #include <sys/callout.h> 70 71 /* 72 * Misc. defintions for the Intel i82557 fast Ethernet controller 73 * driver. 74 */ 75 76 /* 77 * Transmit descriptor list size. 78 */ 79 #define FXP_NTXCB 256 80 #define FXP_NTXCB_MASK (FXP_NTXCB - 1) 81 #define FXP_NEXTTX(x) ((x + 1) & FXP_NTXCB_MASK) 82 #define FXP_NTXSEG 16 83 84 /* 85 * Number of receive frame area buffers. These are large, so 86 * choose wisely. 87 */ 88 #define FXP_NRFABUFS 128 89 90 /* 91 * Maximum number of seconds that the receiver can be idle before we 92 * assume it's dead and attempt to reset it by reprogramming the 93 * multicast filter. This is part of a work-around for a bug in the 94 * NIC. See fxp_stats_update(). 95 */ 96 #define FXP_MAX_RX_IDLE 15 97 98 /* 99 * Misc. DMA'd data structures are allocated in a single clump, that 100 * maps to a single DMA segment, to make several things easier (computing 101 * offsets, setting up DMA maps, etc.) 102 */ 103 struct fxp_control_data { 104 /* 105 * The transmit control blocks and transmit buffer descriptors. 106 * We arrange them like this so that everything is all lined 107 * up to use the extended TxCB feature. 108 */ 109 struct fxp_txdesc { 110 struct fxp_cb_tx txd_txcb; 111 struct fxp_tbd txd_tbd[FXP_NTXSEG]; 112 } fcd_txdescs[FXP_NTXCB]; 113 114 /* 115 * The configuration CB. 116 */ 117 struct fxp_cb_config fcd_configcb; 118 119 /* 120 * The Individual Address CB. 121 */ 122 struct fxp_cb_ias fcd_iascb; 123 124 /* 125 * The multicast setup CB. 126 */ 127 struct fxp_cb_mcs fcd_mcscb; 128 129 /* 130 * The microcode setup CB. 131 */ 132 struct fxp_cb_ucode fcd_ucode; 133 134 /* 135 * The NIC statistics. 136 */ 137 struct fxp_stats fcd_stats; 138 }; 139 140 #define FXP_CDOFF(x) offsetof(struct fxp_control_data, x) 141 #define FXP_CDTXOFF(x) FXP_CDOFF(fcd_txdescs[(x)].txd_txcb) 142 #define FXP_CDTBDOFF(x) FXP_CDOFF(fcd_txdescs[(x)].txd_tbd) 143 #define FXP_CDCONFIGOFF FXP_CDOFF(fcd_configcb) 144 #define FXP_CDIASOFF FXP_CDOFF(fcd_iascb) 145 #define FXP_CDMCSOFF FXP_CDOFF(fcd_mcscb) 146 #define FXP_CDUCODEOFF FXP_CDOFF(fcd_ucode) 147 #define FXP_CDSTATSOFF FXP_CDOFF(fcd_stats) 148 149 /* 150 * Software state for transmit descriptors. 151 */ 152 struct fxp_txsoft { 153 struct mbuf *txs_mbuf; /* head of mbuf chain */ 154 bus_dmamap_t txs_dmamap; /* our DMA map */ 155 }; 156 157 /* 158 * Software state per device. 159 */ 160 struct fxp_softc { 161 struct device sc_dev; /* generic device structures */ 162 bus_space_tag_t sc_st; /* bus space tag */ 163 bus_space_handle_t sc_sh; /* bus space handle */ 164 bus_dma_tag_t sc_dmat; /* bus dma tag */ 165 struct ethercom sc_ethercom; /* ethernet common part */ 166 void *sc_sdhook; /* shutdown hook */ 167 void *sc_ih; /* interrupt handler cookie */ 168 void *sc_powerhook; /* power hook */ 169 170 struct mii_data sc_mii; /* MII/media information */ 171 struct callout sc_callout; /* MII callout */ 172 173 /* 174 * We create a single DMA map that maps all data structure 175 * overhead, except for RFAs, which are mapped by the 176 * fxp_rxdesc DMA map on a per-mbuf basis. 177 */ 178 bus_dmamap_t sc_dmamap; 179 #define sc_cddma sc_dmamap->dm_segs[0].ds_addr 180 181 /* 182 * Software state for transmit descriptors. 183 */ 184 struct fxp_txsoft sc_txsoft[FXP_NTXCB]; 185 186 int sc_rfa_size; /* size of the RFA structure */ 187 struct ifqueue sc_rxq; /* receive buffer queue */ 188 bus_dmamap_t sc_rxmaps[FXP_NRFABUFS]; /* free receive buffer DMA maps */ 189 int sc_rxfree; /* free map index */ 190 int sc_rxidle; /* # of seconds RX has been idle */ 191 192 /* 193 * Control data structures. 194 */ 195 struct fxp_control_data *sc_control_data; 196 197 #ifdef FXP_EVENT_COUNTERS 198 struct evcnt sc_ev_txstall; /* Tx stalled */ 199 struct evcnt sc_ev_txintr; /* Tx interrupts */ 200 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 201 #endif /* FXP_EVENT_COUNTERS */ 202 203 bus_dma_segment_t sc_cdseg; /* control dma segment */ 204 int sc_cdnseg; 205 206 int sc_rev; /* chip revision */ 207 int sc_flags; /* misc. flags */ 208 209 #define FXPF_MII 0x0001 /* device uses MII */ 210 #define FXPF_ATTACHED 0x0002 /* attach has succeeded */ 211 #define FXPF_WANTINIT 0x0004 /* want a re-init */ 212 #define FXPF_HAS_RESUME_BUG 0x0008 /* has the resume bug */ 213 #define FXPF_MWI 0x0010 /* enable PCI MWI */ 214 #define FXPF_READ_ALIGN 0x0020 /* align read access w/ cacheline */ 215 #define FXPF_WRITE_ALIGN 0x0040 /* end write on cacheline */ 216 #define FXPF_EXT_TXCB 0x0080 /* enable extended TxCB */ 217 #define FXPF_UCODE_LOADED 0x0100 /* microcode is loaded */ 218 219 int sc_int_delay; /* interrupt delay */ 220 int sc_bundle_max; /* max packet bundle */ 221 222 int sc_txpending; /* number of TX requests pending */ 223 int sc_txdirty; /* first dirty TX descriptor */ 224 int sc_txlast; /* last used TX descriptor */ 225 226 int phy_primary_device; /* device type of primary PHY */ 227 228 int sc_enabled; /* boolean; power enabled on interface */ 229 int (*sc_enable)(struct fxp_softc *); 230 void (*sc_disable)(struct fxp_softc *); 231 232 int sc_eeprom_size; /* log2 size of EEPROM */ 233 #if NRND > 0 234 rndsource_element_t rnd_source; /* random source */ 235 #endif 236 237 }; 238 239 #ifdef FXP_EVENT_COUNTERS 240 #define FXP_EVCNT_INCR(ev) (ev)->ev_count++ 241 #else 242 #define FXP_EVCNT_INCR(ev) /* nothing */ 243 #endif 244 245 #define FXP_RXMAP_GET(sc) ((sc)->sc_rxmaps[(sc)->sc_rxfree++]) 246 #define FXP_RXMAP_PUT(sc, map) (sc)->sc_rxmaps[--(sc)->sc_rxfree] = (map) 247 248 #define FXP_CDTXADDR(sc, x) ((sc)->sc_cddma + FXP_CDTXOFF((x))) 249 #define FXP_CDTBDADDR(sc, x) ((sc)->sc_cddma + FXP_CDTBDOFF((x))) 250 251 #define FXP_CDTX(sc, x) (&(sc)->sc_control_data->fcd_txdescs[(x)]) 252 253 #define FXP_DSTX(sc, x) (&(sc)->sc_txsoft[(x)]) 254 255 #define FXP_CDTXSYNC(sc, x, ops) \ 256 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \ 257 FXP_CDTXOFF((x)), sizeof(struct fxp_txdesc), (ops)) 258 259 #define FXP_CDCONFIGSYNC(sc, ops) \ 260 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \ 261 FXP_CDCONFIGOFF, sizeof(struct fxp_cb_config), (ops)) 262 263 #define FXP_CDIASSYNC(sc, ops) \ 264 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \ 265 FXP_CDIASOFF, sizeof(struct fxp_cb_ias), (ops)) 266 267 #define FXP_CDMCSSYNC(sc, ops) \ 268 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \ 269 FXP_CDMCSOFF, sizeof(struct fxp_cb_mcs), (ops)) 270 271 #define FXP_CDUCODESYNC(sc, ops) \ 272 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \ 273 FXP_CDUCODEOFF, sizeof(struct fxp_cb_ucode), (ops)) 274 275 #define FXP_CDSTATSSYNC(sc, ops) \ 276 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \ 277 FXP_CDSTATSOFF, sizeof(struct fxp_stats), (ops)) 278 279 #define FXP_RXBUFSIZE(sc, m) ((m)->m_ext.ext_size - \ 280 (sc->sc_rfa_size + \ 281 RFA_ALIGNMENT_FUDGE)) 282 283 #define FXP_RFASYNC(sc, m, ops) \ 284 bus_dmamap_sync((sc)->sc_dmat, M_GETCTX((m), bus_dmamap_t), \ 285 RFA_ALIGNMENT_FUDGE, (sc)->sc_rfa_size, (ops)) 286 287 #define FXP_RXBUFSYNC(sc, m, ops) \ 288 bus_dmamap_sync((sc)->sc_dmat, M_GETCTX((m), bus_dmamap_t), \ 289 RFA_ALIGNMENT_FUDGE + (sc)->sc_rfa_size, \ 290 FXP_RXBUFSIZE((sc), (m)), (ops)) 291 292 #define FXP_MTORFA(m) (struct fxp_rfa *)((m)->m_ext.ext_buf + \ 293 RFA_ALIGNMENT_FUDGE) 294 295 #define FXP_INIT_RFABUF(sc, m) \ 296 do { \ 297 bus_dmamap_t __rxmap = M_GETCTX((m), bus_dmamap_t); \ 298 struct mbuf *__p_m; \ 299 struct fxp_rfa *__rfa, *__p_rfa; \ 300 u_int32_t __v; \ 301 \ 302 (m)->m_data = (m)->m_ext.ext_buf + (sc)->sc_rfa_size + \ 303 RFA_ALIGNMENT_FUDGE; \ 304 \ 305 __rfa = FXP_MTORFA((m)); \ 306 __rfa->size = htole16(FXP_RXBUFSIZE((sc), (m))); \ 307 /* BIG_ENDIAN: no need to swap to store 0 */ \ 308 __rfa->rfa_status = 0; \ 309 __rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); \ 310 /* BIG_ENDIAN: no need to swap to store 0 */ \ 311 __rfa->actual_size = 0; \ 312 \ 313 /* NOTE: the RFA is misaligned, so we must copy. */ \ 314 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ \ 315 __v = 0xffffffff; \ 316 memcpy((void *)&__rfa->link_addr, &__v, sizeof(__v)); \ 317 memcpy((void *)&__rfa->rbd_addr, &__v, sizeof(__v)); \ 318 \ 319 FXP_RFASYNC((sc), (m), \ 320 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 321 \ 322 FXP_RXBUFSYNC((sc), (m), BUS_DMASYNC_PREREAD); \ 323 \ 324 if ((__p_m = (sc)->sc_rxq.ifq_tail) != NULL) { \ 325 __p_rfa = FXP_MTORFA(__p_m); \ 326 __v = htole32(__rxmap->dm_segs[0].ds_addr + \ 327 RFA_ALIGNMENT_FUDGE); \ 328 FXP_RFASYNC((sc), __p_m, \ 329 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); \ 330 memcpy((void *)&__p_rfa->link_addr, &__v, \ 331 sizeof(__v)); \ 332 __p_rfa->rfa_control &= htole16(~FXP_RFA_CONTROL_EL); \ 333 FXP_RFASYNC((sc), __p_m, \ 334 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 335 } \ 336 IF_ENQUEUE(&(sc)->sc_rxq, (m)); \ 337 } while (0) 338 339 /* Macros to ease CSR access. */ 340 #define CSR_READ_1(sc, reg) \ 341 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 342 #define CSR_READ_2(sc, reg) \ 343 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 344 #define CSR_READ_4(sc, reg) \ 345 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 346 #define CSR_WRITE_1(sc, reg, val) \ 347 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 348 #define CSR_WRITE_2(sc, reg, val) \ 349 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 350 #define CSR_WRITE_4(sc, reg, val) \ 351 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 352 353 void fxp_attach(struct fxp_softc *); 354 int fxp_activate(struct device *, enum devact); 355 int fxp_detach(struct fxp_softc *); 356 int fxp_intr(void *); 357 358 int fxp_enable(struct fxp_softc*); 359 void fxp_disable(struct fxp_softc*); 360