1 /* $NetBSD: i8259reg.h,v 1.2 2001/06/21 18:57:04 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _DEV_IC_I8259REG_H_ 40 #define _DEV_IC_I8259REG_H_ 41 42 /* 43 * Register definitions for the Intel i8259 Programmable Interrupt 44 * Controller. 45 * 46 * XXX More bits should be filled in, here, as this was taken from 47 * XXX the Intel PIIX4 manual. Someone with a real 8259 data sheet 48 * XXX should fill them in. 49 */ 50 51 /* 52 * Note a write to ICW1 starts an initialization cycle, and must be 53 * followied by writes to ICW2, ICW3, and ICW4. 54 */ 55 #define PIC_ICW1 0x00 /* Initialization Command Word 1 (w) */ 56 #define ICW1_IC4 (1U << 0) /* ICW4 Write Required */ 57 #define ICW1_SNGL (1U << 1) /* 1 == single, 0 == cascade */ 58 #define ICW1_ADI (1U << 2) /* CALL address interval */ 59 #define ICW1_LTIM (1U << 3) /* 1 == intrs are level trigger */ 60 #define ICW1_SELECT (1U << 4) /* select ICW1 */ 61 #define ICW1_IVA(x) ((x) << 5) /* interrupt vector address (MCS-80) */ 62 63 #define PIC_ICW2 0x01 /* Initialization Command Word 2 (w) */ 64 #define ICW2_VECTOR(x) ((x) & 0xf8) /* vector base address */ 65 #define ICW2_IRL(x) ((x) << 0) /* interrupt request level */ 66 67 #define PIC_ICW3 0x01 /* Initialization Command Word 3 (w) */ 68 #define ICW3_CASCADE(x) (1U << (x)) /* cascaded mode enable */ 69 #define ICW3_SIC(x) ((x) << 0) /* slave identifcation code */ 70 71 #define PIC_ICW4 0x01 /* Initialization Command Word 4 (w) */ 72 #define ICW4_8086 (1U << 0) /* 8086 mode */ 73 #define ICW4_AEOI (1U << 1) /* automatic end-of-interrupt */ 74 #define ICW4_BUFM (1U << 2) /* buffered mode master */ 75 #define ICW4_BUF (1U << 3) /* buffered mode */ 76 #define ICW4_SFNM (1U << 4) /* special fully nested mode */ 77 78 /* 79 * After an initialization sequence, you get to access the OCWs. 80 */ 81 #define PIC_OCW1 0x01 /* Operational Control Word 1 (r/w) */ 82 #define OCW1_IRM(x) (1U << (x)) /* interrupt request mask */ 83 84 #define PIC_OCW2 0x00 /* Operational Control Word 2 (w) */ 85 #define OCW2_SELECT (0) /* select OCW2 */ 86 #define OCW3_EOI (1U << 5) /* EOI */ 87 #define OCW3_SL (1U << 6) /* specific */ 88 #define OCW3_R (1U << 7) /* rotate */ 89 #define OCW2_ILS(x) ((x) << 0) /* interrupt level select */ 90 91 #define PIC_OCW3 0x00 /* Operational Control Word 3 (r/w) */ 92 #define OCW3_SSMM (1U << 6) /* set special mask mode */ 93 #define OCW3_SMM (1U << 5) /* 1 = enable smm, 0 = disable */ 94 #define OCW3_SELECT (1U << 3) /* select OCW3 */ 95 #define OCW3_POLL (1U << 2) /* poll mode command */ 96 #define OCW3_RR (1U << 1) /* register read */ 97 #define OCW3_RIS (1U << 0) /* 1 = read IS, 0 = read IR */ 98 99 #define OCW3_POLL_IRQ(x) ((x) & 0x7f) 100 #define OCW3_POLL_PENDING (1U << 7) 101 102 #endif /* _DEV_IC_I8259REG_H_ */ 103