1 /* $NetBSD: iha.c,v 1.41 2010/11/13 13:52:01 uebayasi Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 Izumi Tsutsui 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Device driver for the INI-9XXXU/UW or INIC-940/950 PCI SCSI Controller. 29 * 30 * Written for 386bsd and FreeBSD by 31 * Winston Hung <winstonh@initio.com> 32 * 33 * Copyright (c) 1997-1999 Initio Corp. 34 * Copyright (c) 2000, 2001 Ken Westerback 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer, 42 * without modification, immediately at the beginning of the file. 43 * 2. The name of the author may not be used to endorse or promote products 44 * derived from this software without specific prior written permission. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 48 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 49 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 50 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 51 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 52 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 54 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 55 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 56 * THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 /* 60 * Ported to NetBSD by Izumi Tsutsui <tsutsui@NetBSD.org> from OpenBSD: 61 * $OpenBSD: iha.c,v 1.3 2001/02/20 00:47:33 krw Exp $ 62 */ 63 64 #include <sys/cdefs.h> 65 __KERNEL_RCSID(0, "$NetBSD: iha.c,v 1.41 2010/11/13 13:52:01 uebayasi Exp $"); 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/kernel.h> 70 #include <sys/buf.h> 71 #include <sys/device.h> 72 #include <sys/malloc.h> 73 74 #include <sys/bus.h> 75 #include <sys/intr.h> 76 77 #include <dev/scsipi/scsi_spc.h> 78 #include <dev/scsipi/scsi_all.h> 79 #include <dev/scsipi/scsipi_all.h> 80 #include <dev/scsipi/scsiconf.h> 81 #include <dev/scsipi/scsi_message.h> 82 83 #include <dev/ic/ihareg.h> 84 #include <dev/ic/ihavar.h> 85 86 /* 87 * SCSI Rate Table, indexed by FLAG_SCSI_RATE field of 88 * tcs flags. 89 */ 90 static const uint8_t iha_rate_tbl[] = { 91 /* fast 20 */ 92 /* nanosecond divide by 4 */ 93 12, /* 50ns, 20M */ 94 18, /* 75ns, 13.3M */ 95 25, /* 100ns, 10M */ 96 31, /* 125ns, 8M */ 97 37, /* 150ns, 6.6M */ 98 43, /* 175ns, 5.7M */ 99 50, /* 200ns, 5M */ 100 62 /* 250ns, 4M */ 101 }; 102 #define IHA_MAX_PERIOD 62 103 104 #ifdef notused 105 static uint16_t eeprom_default[EEPROM_SIZE] = { 106 /* -- Header ------------------------------------ */ 107 /* signature */ 108 EEP_SIGNATURE, 109 /* size, revision */ 110 EEP_WORD(EEPROM_SIZE * 2, 0x01), 111 /* -- Host Adapter Structure -------------------- */ 112 /* model */ 113 0x0095, 114 /* model info, number of channel */ 115 EEP_WORD(0x00, 1), 116 /* BIOS config */ 117 EEP_BIOSCFG_DEFAULT, 118 /* host adapter config */ 119 0, 120 121 /* -- eeprom_adapter[0] ------------------------------- */ 122 /* ID, adapter config 1 */ 123 EEP_WORD(7, CFG_DEFAULT), 124 /* adapter config 2, number of targets */ 125 EEP_WORD(0x00, 8), 126 /* target flags */ 127 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 128 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 129 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 130 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 131 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 132 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 133 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 134 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 135 136 /* -- eeprom_adapter[1] ------------------------------- */ 137 /* ID, adapter config 1 */ 138 EEP_WORD(7, CFG_DEFAULT), 139 /* adapter config 2, number of targets */ 140 EEP_WORD(0x00, 8), 141 /* target flags */ 142 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 143 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 144 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 145 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 146 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 147 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 148 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 149 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 150 /* reserved[5] */ 151 0, 0, 0, 0, 0, 152 /* checksum */ 153 0 154 }; 155 #endif 156 157 static void iha_append_free_scb(struct iha_softc *, struct iha_scb *); 158 static void iha_append_done_scb(struct iha_softc *, struct iha_scb *, uint8_t); 159 static inline struct iha_scb *iha_pop_done_scb(struct iha_softc *); 160 161 static struct iha_scb *iha_find_pend_scb(struct iha_softc *); 162 static inline void iha_append_pend_scb(struct iha_softc *, struct iha_scb *); 163 static inline void iha_push_pend_scb(struct iha_softc *, struct iha_scb *); 164 static inline void iha_del_pend_scb(struct iha_softc *, struct iha_scb *); 165 static inline void iha_mark_busy_scb(struct iha_scb *); 166 167 static inline void iha_set_ssig(struct iha_softc *, uint8_t, uint8_t); 168 169 static int iha_alloc_sglist(struct iha_softc *); 170 171 static void iha_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, 172 void *); 173 static void iha_update_xfer_mode(struct iha_softc *, int); 174 175 static void iha_reset_scsi_bus(struct iha_softc *); 176 static void iha_reset_chip(struct iha_softc *); 177 static void iha_reset_dma(struct iha_softc *); 178 static void iha_reset_tcs(struct tcs *, uint8_t); 179 180 static void iha_main(struct iha_softc *); 181 static void iha_scsi(struct iha_softc *); 182 static void iha_select(struct iha_softc *, struct iha_scb *, uint8_t); 183 static int iha_wait(struct iha_softc *, uint8_t); 184 185 static void iha_exec_scb(struct iha_softc *, struct iha_scb *); 186 static void iha_done_scb(struct iha_softc *, struct iha_scb *); 187 static int iha_push_sense_request(struct iha_softc *, struct iha_scb *); 188 189 static void iha_timeout(void *); 190 static void iha_abort_xs(struct iha_softc *, struct scsipi_xfer *, uint8_t); 191 static uint8_t iha_data_over_run(struct iha_scb *); 192 193 static int iha_next_state(struct iha_softc *); 194 static int iha_state_1(struct iha_softc *); 195 static int iha_state_2(struct iha_softc *); 196 static int iha_state_3(struct iha_softc *); 197 static int iha_state_4(struct iha_softc *); 198 static int iha_state_5(struct iha_softc *); 199 static int iha_state_6(struct iha_softc *); 200 static int iha_state_8(struct iha_softc *); 201 202 static int iha_xfer_data(struct iha_softc *, struct iha_scb *, int); 203 static int iha_xpad_in(struct iha_softc *); 204 static int iha_xpad_out(struct iha_softc *); 205 206 static int iha_status_msg(struct iha_softc *); 207 static void iha_busfree(struct iha_softc *); 208 static int iha_resel(struct iha_softc *); 209 210 static int iha_msgin(struct iha_softc *); 211 static int iha_msgin_extended(struct iha_softc *); 212 static int iha_msgin_sdtr(struct iha_softc *); 213 static int iha_msgin_ignore_wid_resid(struct iha_softc *); 214 215 static int iha_msgout(struct iha_softc *, uint8_t); 216 static void iha_msgout_abort(struct iha_softc *, uint8_t); 217 static int iha_msgout_reject(struct iha_softc *); 218 static int iha_msgout_extended(struct iha_softc *); 219 static int iha_msgout_wdtr(struct iha_softc *); 220 static int iha_msgout_sdtr(struct iha_softc *); 221 222 static void iha_wide_done(struct iha_softc *); 223 static void iha_sync_done(struct iha_softc *); 224 225 static void iha_bad_seq(struct iha_softc *); 226 227 static void iha_read_eeprom(struct iha_softc *, struct iha_eeprom *); 228 static int iha_se2_rd_all(struct iha_softc *, uint16_t *); 229 static void iha_se2_instr(struct iha_softc *, int); 230 static uint16_t iha_se2_rd(struct iha_softc *, int); 231 #ifdef notused 232 static void iha_se2_update_all(struct iha_softc *); 233 static void iha_se2_wr(struct iha_softc *, int, uint16_t); 234 #endif 235 236 /* 237 * iha_append_free_scb - append the supplied SCB to the tail of the 238 * sc_freescb queue after clearing and resetting 239 * everything possible. 240 */ 241 static void 242 iha_append_free_scb(struct iha_softc *sc, struct iha_scb *scb) 243 { 244 int s; 245 246 s = splbio(); 247 248 if (scb == sc->sc_actscb) 249 sc->sc_actscb = NULL; 250 251 scb->status = STATUS_QUEUED; 252 scb->ha_stat = HOST_OK; 253 scb->ta_stat = SCSI_OK; 254 255 scb->nextstat = 0; 256 scb->scb_tagmsg = 0; 257 258 scb->xs = NULL; 259 scb->tcs = NULL; 260 261 /* 262 * scb_tagid, sg_addr, sglist 263 * SCB_SensePtr are set at initialization 264 * and never change 265 */ 266 267 TAILQ_INSERT_TAIL(&sc->sc_freescb, scb, chain); 268 269 splx(s); 270 } 271 272 static void 273 iha_append_done_scb(struct iha_softc *sc, struct iha_scb *scb, uint8_t hastat) 274 { 275 struct tcs *tcs; 276 int s; 277 278 s = splbio(); 279 280 if (scb->xs != NULL) 281 callout_stop(&scb->xs->xs_callout); 282 283 if (scb == sc->sc_actscb) 284 sc->sc_actscb = NULL; 285 286 tcs = scb->tcs; 287 288 if (scb->scb_tagmsg != 0) { 289 if (tcs->tagcnt) 290 tcs->tagcnt--; 291 } else if (tcs->ntagscb == scb) 292 tcs->ntagscb = NULL; 293 294 scb->status = STATUS_QUEUED; 295 scb->ha_stat = hastat; 296 297 TAILQ_INSERT_TAIL(&sc->sc_donescb, scb, chain); 298 299 splx(s); 300 } 301 302 static inline struct iha_scb * 303 iha_pop_done_scb(struct iha_softc *sc) 304 { 305 struct iha_scb *scb; 306 int s; 307 308 s = splbio(); 309 310 scb = TAILQ_FIRST(&sc->sc_donescb); 311 312 if (scb != NULL) { 313 scb->status = STATUS_RENT; 314 TAILQ_REMOVE(&sc->sc_donescb, scb, chain); 315 } 316 317 splx(s); 318 319 return (scb); 320 } 321 322 /* 323 * iha_find_pend_scb - scan the pending queue for a SCB that can be 324 * processed immediately. Return NULL if none found 325 * and a pointer to the SCB if one is found. If there 326 * is an active SCB, return NULL! 327 */ 328 static struct iha_scb * 329 iha_find_pend_scb(struct iha_softc *sc) 330 { 331 struct iha_scb *scb; 332 struct tcs *tcs; 333 int s; 334 335 s = splbio(); 336 337 if (sc->sc_actscb != NULL) 338 scb = NULL; 339 340 else 341 TAILQ_FOREACH(scb, &sc->sc_pendscb, chain) { 342 if ((scb->xs->xs_control & XS_CTL_RESET) != 0) 343 /* ALWAYS willing to reset a device */ 344 break; 345 346 tcs = scb->tcs; 347 348 if ((scb->scb_tagmsg) != 0) { 349 /* 350 * A Tagged I/O. OK to start If no 351 * non-tagged I/O is active on the same 352 * target 353 */ 354 if (tcs->ntagscb == NULL) 355 break; 356 357 } else if (scb->cmd[0] == SCSI_REQUEST_SENSE) { 358 /* 359 * OK to do a non-tagged request sense 360 * even if a non-tagged I/O has been 361 * started, 'cuz we don't allow any 362 * disconnect during a request sense op 363 */ 364 break; 365 366 } else if (tcs->tagcnt == 0) { 367 /* 368 * No tagged I/O active on this target, 369 * ok to start a non-tagged one if one 370 * is not already active 371 */ 372 if (tcs->ntagscb == NULL) 373 break; 374 } 375 } 376 377 splx(s); 378 379 return (scb); 380 } 381 382 static inline void 383 iha_append_pend_scb(struct iha_softc *sc, struct iha_scb *scb) 384 { 385 /* ASSUMPTION: only called within a splbio()/splx() pair */ 386 387 if (scb == sc->sc_actscb) 388 sc->sc_actscb = NULL; 389 390 scb->status = STATUS_QUEUED; 391 392 TAILQ_INSERT_TAIL(&sc->sc_pendscb, scb, chain); 393 } 394 395 static inline void 396 iha_push_pend_scb(struct iha_softc *sc, struct iha_scb *scb) 397 { 398 int s; 399 400 s = splbio(); 401 402 if (scb == sc->sc_actscb) 403 sc->sc_actscb = NULL; 404 405 scb->status = STATUS_QUEUED; 406 407 TAILQ_INSERT_HEAD(&sc->sc_pendscb, scb, chain); 408 409 splx(s); 410 } 411 412 /* 413 * iha_del_pend_scb - remove scb from sc_pendscb 414 */ 415 static inline void 416 iha_del_pend_scb(struct iha_softc *sc, struct iha_scb *scb) 417 { 418 int s; 419 420 s = splbio(); 421 422 TAILQ_REMOVE(&sc->sc_pendscb, scb, chain); 423 424 splx(s); 425 } 426 427 static inline void 428 iha_mark_busy_scb(struct iha_scb *scb) 429 { 430 int s; 431 432 s = splbio(); 433 434 scb->status = STATUS_BUSY; 435 436 if (scb->scb_tagmsg == 0) 437 scb->tcs->ntagscb = scb; 438 else 439 scb->tcs->tagcnt++; 440 441 splx(s); 442 } 443 444 /* 445 * iha_set_ssig - read the current scsi signal mask, then write a new 446 * one which turns off/on the specified signals. 447 */ 448 static inline void 449 iha_set_ssig(struct iha_softc *sc, uint8_t offsigs, uint8_t onsigs) 450 { 451 bus_space_tag_t iot = sc->sc_iot; 452 bus_space_handle_t ioh = sc->sc_ioh; 453 uint8_t currsigs; 454 455 currsigs = bus_space_read_1(iot, ioh, TUL_SSIGI); 456 bus_space_write_1(iot, ioh, TUL_SSIGO, (currsigs & ~offsigs) | onsigs); 457 } 458 459 /* 460 * iha_intr - the interrupt service routine for the iha driver 461 */ 462 int 463 iha_intr(void *arg) 464 { 465 bus_space_tag_t iot; 466 bus_space_handle_t ioh; 467 struct iha_softc *sc; 468 int s; 469 470 sc = (struct iha_softc *)arg; 471 iot = sc->sc_iot; 472 ioh = sc->sc_ioh; 473 474 if ((bus_space_read_1(iot, ioh, TUL_STAT0) & INTPD) == 0) 475 return (0); 476 477 s = splbio(); /* XXX - Or are interrupts off when ISR's are called? */ 478 479 if (sc->sc_semaph != SEMAPH_IN_MAIN) { 480 /* XXX - need these inside a splbio()/splx()? */ 481 bus_space_write_1(iot, ioh, TUL_IMSK, MASK_ALL); 482 sc->sc_semaph = SEMAPH_IN_MAIN; 483 484 iha_main(sc); 485 486 sc->sc_semaph = ~SEMAPH_IN_MAIN; 487 bus_space_write_1(iot, ioh, TUL_IMSK, (MASK_ALL & ~MSCMP)); 488 } 489 490 splx(s); 491 492 return (1); 493 } 494 495 void 496 iha_attach(struct iha_softc *sc) 497 { 498 bus_space_tag_t iot = sc->sc_iot; 499 bus_space_handle_t ioh = sc->sc_ioh; 500 struct iha_scb *scb; 501 struct iha_eeprom eeprom; 502 struct eeprom_adapter *conf; 503 int i, error, reg; 504 505 iha_read_eeprom(sc, &eeprom); 506 507 conf = &eeprom.adapter[0]; 508 509 /* 510 * fill in the rest of the iha_softc fields 511 */ 512 sc->sc_id = CFG_ID(conf->config1); 513 sc->sc_semaph = ~SEMAPH_IN_MAIN; 514 sc->sc_status0 = 0; 515 sc->sc_actscb = NULL; 516 517 TAILQ_INIT(&sc->sc_freescb); 518 TAILQ_INIT(&sc->sc_pendscb); 519 TAILQ_INIT(&sc->sc_donescb); 520 error = iha_alloc_sglist(sc); 521 if (error != 0) { 522 aprint_error_dev(sc->sc_dev, "cannot allocate sglist\n"); 523 return; 524 } 525 526 sc->sc_scb = malloc(sizeof(struct iha_scb) * IHA_MAX_SCB, 527 M_DEVBUF, M_NOWAIT|M_ZERO); 528 if (sc->sc_scb == NULL) { 529 aprint_error_dev(sc->sc_dev, "cannot allocate SCB\n"); 530 return; 531 } 532 533 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) { 534 scb->scb_tagid = i; 535 scb->sgoffset = IHA_SG_SIZE * i; 536 scb->sglist = sc->sc_sglist + IHA_MAX_SG_ENTRIES * i; 537 scb->sg_addr = 538 sc->sc_dmamap->dm_segs[0].ds_addr + scb->sgoffset; 539 540 error = bus_dmamap_create(sc->sc_dmat, 541 MAXPHYS, IHA_MAX_SG_ENTRIES, MAXPHYS, 0, 542 BUS_DMA_NOWAIT, &scb->dmap); 543 544 if (error != 0) { 545 aprint_error_dev(sc->sc_dev, 546 "couldn't create SCB DMA map, error = %d\n", 547 error); 548 return; 549 } 550 TAILQ_INSERT_TAIL(&sc->sc_freescb, scb, chain); 551 } 552 553 /* Mask all the interrupts */ 554 bus_space_write_1(iot, ioh, TUL_IMSK, MASK_ALL); 555 556 /* Stop any I/O and reset the scsi module */ 557 iha_reset_dma(sc); 558 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSMOD); 559 560 /* Program HBA's SCSI ID */ 561 bus_space_write_1(iot, ioh, TUL_SID, sc->sc_id << 4); 562 563 /* 564 * Configure the channel as requested by the NVRAM settings read 565 * by iha_read_eeprom() above. 566 */ 567 568 sc->sc_sconf1 = SCONFIG0DEFAULT; 569 if ((conf->config1 & CFG_EN_PAR) != 0) 570 sc->sc_sconf1 |= SPCHK; 571 bus_space_write_1(iot, ioh, TUL_SCONFIG0, sc->sc_sconf1); 572 573 /* set selection time out 250 ms */ 574 bus_space_write_1(iot, ioh, TUL_STIMO, STIMO_250MS); 575 576 /* Enable desired SCSI termination configuration read from eeprom */ 577 reg = 0; 578 if (conf->config1 & CFG_ACT_TERM1) 579 reg |= ENTMW; 580 if (conf->config1 & CFG_ACT_TERM2) 581 reg |= ENTM; 582 bus_space_write_1(iot, ioh, TUL_DCTRL0, reg); 583 584 reg = bus_space_read_1(iot, ioh, TUL_GCTRL1) & ~ATDEN; 585 if (conf->config1 & CFG_AUTO_TERM) 586 reg |= ATDEN; 587 bus_space_write_1(iot, ioh, TUL_GCTRL1, reg); 588 589 for (i = 0; i < IHA_MAX_TARGETS / 2; i++) { 590 sc->sc_tcs[i * 2 ].flags = EEP_LBYTE(conf->tflags[i]); 591 sc->sc_tcs[i * 2 + 1].flags = EEP_HBYTE(conf->tflags[i]); 592 iha_reset_tcs(&sc->sc_tcs[i * 2 ], sc->sc_sconf1); 593 iha_reset_tcs(&sc->sc_tcs[i * 2 + 1], sc->sc_sconf1); 594 } 595 596 iha_reset_chip(sc); 597 bus_space_write_1(iot, ioh, TUL_SIEN, ALL_INTERRUPTS); 598 599 /* 600 * fill in the adapter. 601 */ 602 sc->sc_adapter.adapt_dev = sc->sc_dev; 603 sc->sc_adapter.adapt_nchannels = 1; 604 sc->sc_adapter.adapt_openings = IHA_MAX_SCB; 605 sc->sc_adapter.adapt_max_periph = IHA_MAX_SCB; 606 sc->sc_adapter.adapt_ioctl = NULL; 607 sc->sc_adapter.adapt_minphys = minphys; 608 sc->sc_adapter.adapt_request = iha_scsipi_request; 609 610 /* 611 * fill in the channel. 612 */ 613 sc->sc_channel.chan_adapter = &sc->sc_adapter; 614 sc->sc_channel.chan_bustype = &scsi_bustype; 615 sc->sc_channel.chan_channel = 0; 616 sc->sc_channel.chan_ntargets = CFG_TARGET(conf->config2); 617 sc->sc_channel.chan_nluns = 8; 618 sc->sc_channel.chan_id = sc->sc_id; 619 620 /* 621 * Now try to attach all the sub devices. 622 */ 623 config_found(sc->sc_dev, &sc->sc_channel, scsiprint); 624 } 625 626 /* 627 * iha_alloc_sglist - allocate and map sglist for SCB's 628 */ 629 static int 630 iha_alloc_sglist(struct iha_softc *sc) 631 { 632 bus_dma_segment_t seg; 633 int error, rseg; 634 635 /* 636 * Allocate DMA-safe memory for the SCB's sglist 637 */ 638 if ((error = bus_dmamem_alloc(sc->sc_dmat, 639 IHA_SG_SIZE * IHA_MAX_SCB, 640 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 641 printf(": unable to allocate sglist, error = %d\n", error); 642 return (error); 643 } 644 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 645 IHA_SG_SIZE * IHA_MAX_SCB, (void **)&sc->sc_sglist, 646 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 647 printf(": unable to map sglist, error = %d\n", error); 648 return (error); 649 } 650 651 /* 652 * Create and load the DMA map used for the SCBs 653 */ 654 if ((error = bus_dmamap_create(sc->sc_dmat, 655 IHA_SG_SIZE * IHA_MAX_SCB, 1, IHA_SG_SIZE * IHA_MAX_SCB, 656 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 657 printf(": unable to create control DMA map, error = %d\n", 658 error); 659 return (error); 660 } 661 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 662 sc->sc_sglist, IHA_SG_SIZE * IHA_MAX_SCB, 663 NULL, BUS_DMA_NOWAIT)) != 0) { 664 printf(": unable to load control DMA map, error = %d\n", error); 665 return (error); 666 } 667 668 memset(sc->sc_sglist, 0, IHA_SG_SIZE * IHA_MAX_SCB); 669 670 return (0); 671 } 672 673 void 674 iha_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 675 void *arg) 676 { 677 struct scsipi_xfer *xs; 678 struct scsipi_periph *periph; 679 struct iha_scb *scb; 680 struct iha_softc *sc; 681 int error, s; 682 683 sc = device_private(chan->chan_adapter->adapt_dev); 684 685 switch (req) { 686 case ADAPTER_REQ_RUN_XFER: 687 xs = arg; 688 periph = xs->xs_periph; 689 690 /* XXX This size isn't actually a hardware restriction. */ 691 if (xs->cmdlen > sizeof(scb->cmd) || 692 periph->periph_target >= IHA_MAX_TARGETS) { 693 xs->error = XS_DRIVER_STUFFUP; 694 scsipi_done(xs); 695 return; 696 } 697 698 s = splbio(); 699 scb = TAILQ_FIRST(&sc->sc_freescb); 700 if (scb != NULL) { 701 scb->status = STATUS_RENT; 702 TAILQ_REMOVE(&sc->sc_freescb, scb, chain); 703 } 704 else { 705 printf("unable to allocate scb\n"); 706 #ifdef DIAGNOSTIC 707 scsipi_printaddr(periph); 708 panic("iha_scsipi_request"); 709 #else 710 splx(s); 711 return; 712 #endif 713 } 714 splx(s); 715 716 scb->target = periph->periph_target; 717 scb->lun = periph->periph_lun; 718 scb->tcs = &sc->sc_tcs[scb->target]; 719 scb->scb_id = MSG_IDENTIFY(periph->periph_lun, 720 (xs->xs_control & XS_CTL_REQSENSE) == 0); 721 722 scb->xs = xs; 723 scb->cmdlen = xs->cmdlen; 724 memcpy(&scb->cmd, xs->cmd, xs->cmdlen); 725 scb->buflen = xs->datalen; 726 scb->flags = 0; 727 if (xs->xs_control & XS_CTL_DATA_OUT) 728 scb->flags |= FLAG_DATAOUT; 729 if (xs->xs_control & XS_CTL_DATA_IN) 730 scb->flags |= FLAG_DATAIN; 731 732 if (scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) { 733 error = bus_dmamap_load(sc->sc_dmat, scb->dmap, 734 xs->data, scb->buflen, NULL, 735 ((xs->xs_control & XS_CTL_NOSLEEP) ? 736 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 737 BUS_DMA_STREAMING | 738 ((scb->flags & FLAG_DATAIN) ? 739 BUS_DMA_READ : BUS_DMA_WRITE)); 740 741 if (error) { 742 printf("%s: error %d loading DMA map\n", 743 device_xname(sc->sc_dev), error); 744 iha_append_free_scb(sc, scb); 745 xs->error = XS_DRIVER_STUFFUP; 746 scsipi_done(xs); 747 return; 748 } 749 bus_dmamap_sync(sc->sc_dmat, scb->dmap, 750 0, scb->dmap->dm_mapsize, 751 (scb->flags & FLAG_DATAIN) ? 752 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 753 } 754 755 iha_exec_scb(sc, scb); 756 return; 757 758 case ADAPTER_REQ_GROW_RESOURCES: 759 return; /* XXX */ 760 761 case ADAPTER_REQ_SET_XFER_MODE: 762 { 763 struct tcs *tcs; 764 struct scsipi_xfer_mode *xm = arg; 765 766 tcs = &sc->sc_tcs[xm->xm_target]; 767 768 if ((xm->xm_mode & PERIPH_CAP_WIDE16) != 0 && 769 (tcs->flags & FLAG_NO_WIDE) == 0) 770 tcs->flags &= ~(FLAG_WIDE_DONE|FLAG_SYNC_DONE); 771 772 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0 && 773 (tcs->flags & FLAG_NO_SYNC) == 0) 774 tcs->flags &= ~FLAG_SYNC_DONE; 775 776 /* 777 * If we're not going to negotiate, send the 778 * notification now, since it won't happen later. 779 */ 780 if ((tcs->flags & (FLAG_WIDE_DONE|FLAG_SYNC_DONE)) == 781 (FLAG_WIDE_DONE|FLAG_SYNC_DONE)) 782 iha_update_xfer_mode(sc, xm->xm_target); 783 784 return; 785 } 786 } 787 } 788 789 void 790 iha_update_xfer_mode(struct iha_softc *sc, int target) 791 { 792 struct tcs *tcs = &sc->sc_tcs[target]; 793 struct scsipi_xfer_mode xm; 794 795 xm.xm_target = target; 796 xm.xm_mode = 0; 797 xm.xm_period = 0; 798 xm.xm_offset = 0; 799 800 if (tcs->syncm & PERIOD_WIDE_SCSI) 801 xm.xm_mode |= PERIPH_CAP_WIDE16; 802 803 if (tcs->period) { 804 xm.xm_mode |= PERIPH_CAP_SYNC; 805 xm.xm_period = tcs->period; 806 xm.xm_offset = tcs->offset; 807 } 808 809 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 810 } 811 812 static void 813 iha_reset_scsi_bus(struct iha_softc *sc) 814 { 815 struct iha_scb *scb; 816 struct tcs *tcs; 817 int i, s; 818 819 s = splbio(); 820 821 iha_reset_dma(sc); 822 823 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) 824 switch (scb->status) { 825 case STATUS_BUSY: 826 iha_append_done_scb(sc, scb, HOST_SCSI_RST); 827 break; 828 829 case STATUS_SELECT: 830 iha_push_pend_scb(sc, scb); 831 break; 832 833 default: 834 break; 835 } 836 837 for (i = 0, tcs = sc->sc_tcs; i < IHA_MAX_TARGETS; i++, tcs++) 838 iha_reset_tcs(tcs, sc->sc_sconf1); 839 840 splx(s); 841 } 842 843 void 844 iha_reset_chip(struct iha_softc *sc) 845 { 846 bus_space_tag_t iot = sc->sc_iot; 847 bus_space_handle_t ioh = sc->sc_ioh; 848 849 /* reset tulip chip */ 850 851 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSCSI); 852 853 do { 854 sc->sc_sistat = bus_space_read_1(iot, ioh, TUL_SISTAT); 855 } while ((sc->sc_sistat & SRSTD) == 0); 856 857 iha_set_ssig(sc, 0, 0); 858 859 /* Clear any active interrupt*/ 860 (void)bus_space_read_1(iot, ioh, TUL_SISTAT); 861 } 862 863 /* 864 * iha_reset_dma - abort any active DMA xfer, reset tulip FIFO. 865 */ 866 static void 867 iha_reset_dma(struct iha_softc *sc) 868 { 869 bus_space_tag_t iot = sc->sc_iot; 870 bus_space_handle_t ioh = sc->sc_ioh; 871 872 if ((bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) != 0) { 873 /* if DMA xfer is pending, abort DMA xfer */ 874 bus_space_write_1(iot, ioh, TUL_DCMD, ABTXFR); 875 /* wait Abort DMA xfer done */ 876 while ((bus_space_read_1(iot, ioh, TUL_ISTUS0) & DABT) == 0) 877 ; 878 } 879 880 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 881 } 882 883 /* 884 * iha_reset_tcs - reset the target control structure pointed 885 * to by tcs to default values. tcs flags 886 * only has the negotiation done bits reset as 887 * the other bits are fixed at initialization. 888 */ 889 static void 890 iha_reset_tcs(struct tcs *tcs, uint8_t config0) 891 { 892 893 tcs->flags &= ~(FLAG_SYNC_DONE | FLAG_WIDE_DONE); 894 tcs->period = 0; 895 tcs->offset = 0; 896 tcs->tagcnt = 0; 897 tcs->ntagscb = NULL; 898 tcs->syncm = 0; 899 tcs->sconfig0 = config0; 900 } 901 902 /* 903 * iha_main - process the active SCB, taking one off pending and making it 904 * active if necessary, and any done SCB's created as 905 * a result until there are no interrupts pending and no pending 906 * SCB's that can be started. 907 */ 908 static void 909 iha_main(struct iha_softc *sc) 910 { 911 bus_space_tag_t iot = sc->sc_iot; 912 bus_space_handle_t ioh =sc->sc_ioh; 913 struct iha_scb *scb; 914 915 for (;;) { 916 iha_scsi(sc); 917 918 while ((scb = iha_pop_done_scb(sc)) != NULL) 919 iha_done_scb(sc, scb); 920 921 /* 922 * If there are no interrupts pending, or we can't start 923 * a pending sc, break out of the for(;;). Otherwise 924 * continue the good work with another call to 925 * iha_scsi(). 926 */ 927 if (((bus_space_read_1(iot, ioh, TUL_STAT0) & INTPD) == 0) 928 && (iha_find_pend_scb(sc) == NULL)) 929 break; 930 } 931 } 932 933 /* 934 * iha_scsi - service any outstanding interrupts. If there are none, try to 935 * start another SCB currently in the pending queue. 936 */ 937 static void 938 iha_scsi(struct iha_softc *sc) 939 { 940 bus_space_tag_t iot = sc->sc_iot; 941 bus_space_handle_t ioh = sc->sc_ioh; 942 struct iha_scb *scb; 943 struct tcs *tcs; 944 uint8_t stat; 945 946 /* service pending interrupts asap */ 947 948 stat = bus_space_read_1(iot, ioh, TUL_STAT0); 949 if ((stat & INTPD) != 0) { 950 sc->sc_status0 = stat; 951 sc->sc_status1 = bus_space_read_1(iot, ioh, TUL_STAT1); 952 sc->sc_sistat = bus_space_read_1(iot, ioh, TUL_SISTAT); 953 954 sc->sc_phase = sc->sc_status0 & PH_MASK; 955 956 if ((sc->sc_sistat & SRSTD) != 0) { 957 iha_reset_scsi_bus(sc); 958 return; 959 } 960 961 if ((sc->sc_sistat & RSELED) != 0) { 962 iha_resel(sc); 963 return; 964 } 965 966 if ((sc->sc_sistat & (STIMEO | DISCD)) != 0) { 967 iha_busfree(sc); 968 return; 969 } 970 971 if ((sc->sc_sistat & (SCMDN | SBSRV)) != 0) { 972 iha_next_state(sc); 973 return; 974 } 975 976 if ((sc->sc_sistat & SELED) != 0) 977 iha_set_ssig(sc, 0, 0); 978 } 979 980 /* 981 * There were no interrupts pending which required action elsewhere, so 982 * see if it is possible to start the selection phase on a pending SCB 983 */ 984 if ((scb = iha_find_pend_scb(sc)) == NULL) 985 return; 986 987 tcs = scb->tcs; 988 989 /* program HBA's SCSI ID & target SCSI ID */ 990 bus_space_write_1(iot, ioh, TUL_SID, (sc->sc_id << 4) | scb->target); 991 992 if ((scb->xs->xs_control & XS_CTL_RESET) == 0) { 993 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 994 995 if ((tcs->flags & FLAG_NO_NEG_SYNC) == 0 || 996 (tcs->flags & FLAG_NO_NEG_WIDE) == 0) 997 iha_select(sc, scb, SELATNSTOP); 998 999 else if (scb->scb_tagmsg != 0) 1000 iha_select(sc, scb, SEL_ATN3); 1001 1002 else 1003 iha_select(sc, scb, SEL_ATN); 1004 1005 } else { 1006 iha_select(sc, scb, SELATNSTOP); 1007 scb->nextstat = 8; 1008 } 1009 1010 if ((scb->xs->xs_control & XS_CTL_POLL) != 0) { 1011 int timeout; 1012 for (timeout = scb->xs->timeout; timeout > 0; timeout--) { 1013 if (iha_wait(sc, NO_OP) == -1) 1014 break; 1015 if (iha_next_state(sc) == -1) 1016 break; 1017 delay(1000); /* Only happens in boot, so it's ok */ 1018 } 1019 1020 /* 1021 * Since done queue processing not done until AFTER this 1022 * function returns, scb is on the done queue, not 1023 * the free queue at this point and still has valid data 1024 * 1025 * Conversely, xs->error has not been set yet 1026 */ 1027 if (timeout == 0) 1028 iha_timeout(scb); 1029 } 1030 } 1031 1032 static void 1033 iha_select(struct iha_softc *sc, struct iha_scb *scb, uint8_t select_type) 1034 { 1035 bus_space_tag_t iot = sc->sc_iot; 1036 bus_space_handle_t ioh = sc->sc_ioh; 1037 1038 switch (select_type) { 1039 case SEL_ATN: 1040 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_id); 1041 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, 1042 scb->cmd, scb->cmdlen); 1043 1044 scb->nextstat = 2; 1045 break; 1046 1047 case SELATNSTOP: 1048 scb->nextstat = 1; 1049 break; 1050 1051 case SEL_ATN3: 1052 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_id); 1053 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_tagmsg); 1054 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_tagid); 1055 1056 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, scb->cmd, 1057 scb->cmdlen); 1058 1059 scb->nextstat = 2; 1060 break; 1061 1062 default: 1063 printf("[debug] iha_select() - unknown select type = 0x%02x\n", 1064 select_type); 1065 return; 1066 } 1067 1068 iha_del_pend_scb(sc, scb); 1069 scb->status = STATUS_SELECT; 1070 1071 sc->sc_actscb = scb; 1072 1073 bus_space_write_1(iot, ioh, TUL_SCMD, select_type); 1074 } 1075 1076 /* 1077 * iha_wait - wait for an interrupt to service or a SCSI bus phase change 1078 * after writing the supplied command to the tulip chip. If 1079 * the command is NO_OP, skip the command writing. 1080 */ 1081 static int 1082 iha_wait(struct iha_softc *sc, uint8_t cmd) 1083 { 1084 bus_space_tag_t iot = sc->sc_iot; 1085 bus_space_handle_t ioh = sc->sc_ioh; 1086 1087 if (cmd != NO_OP) 1088 bus_space_write_1(iot, ioh, TUL_SCMD, cmd); 1089 1090 /* 1091 * Have to do this here, in addition to in iha_isr, because 1092 * interrupts might be turned off when we get here. 1093 */ 1094 do { 1095 sc->sc_status0 = bus_space_read_1(iot, ioh, TUL_STAT0); 1096 } while ((sc->sc_status0 & INTPD) == 0); 1097 1098 sc->sc_status1 = bus_space_read_1(iot, ioh, TUL_STAT1); 1099 sc->sc_sistat = bus_space_read_1(iot, ioh, TUL_SISTAT); 1100 1101 sc->sc_phase = sc->sc_status0 & PH_MASK; 1102 1103 if ((sc->sc_sistat & SRSTD) != 0) { 1104 /* SCSI bus reset interrupt */ 1105 iha_reset_scsi_bus(sc); 1106 return (-1); 1107 } 1108 1109 if ((sc->sc_sistat & RSELED) != 0) 1110 /* Reselection interrupt */ 1111 return (iha_resel(sc)); 1112 1113 if ((sc->sc_sistat & STIMEO) != 0) { 1114 /* selected/reselected timeout interrupt */ 1115 iha_busfree(sc); 1116 return (-1); 1117 } 1118 1119 if ((sc->sc_sistat & DISCD) != 0) { 1120 /* BUS disconnection interrupt */ 1121 if ((sc->sc_flags & FLAG_EXPECT_DONE_DISC) != 0) { 1122 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1123 bus_space_write_1(iot, ioh, TUL_SCONFIG0, 1124 SCONFIG0DEFAULT); 1125 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 1126 iha_append_done_scb(sc, sc->sc_actscb, HOST_OK); 1127 sc->sc_flags &= ~FLAG_EXPECT_DONE_DISC; 1128 1129 } else if ((sc->sc_flags & FLAG_EXPECT_DISC) != 0) { 1130 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1131 bus_space_write_1(iot, ioh, TUL_SCONFIG0, 1132 SCONFIG0DEFAULT); 1133 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 1134 sc->sc_actscb = NULL; 1135 sc->sc_flags &= ~FLAG_EXPECT_DISC; 1136 1137 } else 1138 iha_busfree(sc); 1139 1140 return (-1); 1141 } 1142 1143 return (sc->sc_phase); 1144 } 1145 1146 static void 1147 iha_exec_scb(struct iha_softc *sc, struct iha_scb *scb) 1148 { 1149 bus_space_tag_t iot; 1150 bus_space_handle_t ioh; 1151 bus_dmamap_t dm; 1152 struct scsipi_xfer *xs = scb->xs; 1153 int nseg, s; 1154 1155 dm = scb->dmap; 1156 nseg = dm->dm_nsegs; 1157 1158 if (nseg > 1) { 1159 struct iha_sg_element *sg = scb->sglist; 1160 int i; 1161 1162 for (i = 0; i < nseg; i++) { 1163 sg[i].sg_len = htole32(dm->dm_segs[i].ds_len); 1164 sg[i].sg_addr = htole32(dm->dm_segs[i].ds_addr); 1165 } 1166 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1167 scb->sgoffset, IHA_SG_SIZE, 1168 BUS_DMASYNC_PREWRITE); 1169 1170 scb->flags |= FLAG_SG; 1171 scb->sg_size = scb->sg_max = nseg; 1172 scb->sg_index = 0; 1173 1174 scb->bufaddr = scb->sg_addr; 1175 } else 1176 scb->bufaddr = dm->dm_segs[0].ds_addr; 1177 1178 if ((xs->xs_control & XS_CTL_POLL) == 0) { 1179 int timeout = mstohz(xs->timeout); 1180 if (timeout == 0) 1181 timeout = 1; 1182 callout_reset(&xs->xs_callout, timeout, iha_timeout, scb); 1183 } 1184 1185 s = splbio(); 1186 1187 if (((scb->xs->xs_control & XS_RESET) != 0) || 1188 (scb->cmd[0] == SCSI_REQUEST_SENSE)) 1189 iha_push_pend_scb(sc, scb); /* Insert SCB at head of Pend */ 1190 else 1191 iha_append_pend_scb(sc, scb); /* Append SCB to tail of Pend */ 1192 1193 /* 1194 * Run through iha_main() to ensure something is active, if 1195 * only this new SCB. 1196 */ 1197 if (sc->sc_semaph != SEMAPH_IN_MAIN) { 1198 iot = sc->sc_iot; 1199 ioh = sc->sc_ioh; 1200 1201 bus_space_write_1(iot, ioh, TUL_IMSK, MASK_ALL); 1202 sc->sc_semaph = SEMAPH_IN_MAIN; 1203 1204 splx(s); 1205 iha_main(sc); 1206 s = splbio(); 1207 1208 sc->sc_semaph = ~SEMAPH_IN_MAIN; 1209 bus_space_write_1(iot, ioh, TUL_IMSK, (MASK_ALL & ~MSCMP)); 1210 } 1211 1212 splx(s); 1213 } 1214 1215 /* 1216 * iha_done_scb - We have a scb which has been processed by the 1217 * adaptor, now we look to see how the operation went. 1218 */ 1219 static void 1220 iha_done_scb(struct iha_softc *sc, struct iha_scb *scb) 1221 { 1222 struct scsipi_xfer *xs = scb->xs; 1223 1224 if (xs != NULL) { 1225 /* Cancel the timeout. */ 1226 callout_stop(&xs->xs_callout); 1227 1228 if (scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) { 1229 bus_dmamap_sync(sc->sc_dmat, scb->dmap, 1230 0, scb->dmap->dm_mapsize, 1231 (scb->flags & FLAG_DATAIN) ? 1232 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1233 bus_dmamap_unload(sc->sc_dmat, scb->dmap); 1234 } 1235 1236 xs->status = scb->ta_stat; 1237 1238 switch (scb->ha_stat) { 1239 case HOST_OK: 1240 switch (scb->ta_stat) { 1241 case SCSI_OK: 1242 case SCSI_CONDITION_MET: 1243 case SCSI_INTERM: 1244 case SCSI_INTERM_COND_MET: 1245 xs->resid = scb->buflen; 1246 xs->error = XS_NOERROR; 1247 if ((scb->flags & FLAG_RSENS) != 0) 1248 xs->error = XS_SENSE; 1249 break; 1250 1251 case SCSI_RESV_CONFLICT: 1252 case SCSI_BUSY: 1253 case SCSI_QUEUE_FULL: 1254 xs->error = XS_BUSY; 1255 break; 1256 1257 case SCSI_TERMINATED: 1258 case SCSI_ACA_ACTIVE: 1259 case SCSI_CHECK: 1260 scb->tcs->flags &= 1261 ~(FLAG_SYNC_DONE | FLAG_WIDE_DONE); 1262 1263 if ((scb->flags & FLAG_RSENS) != 0 || 1264 iha_push_sense_request(sc, scb) != 0) { 1265 scb->flags &= ~FLAG_RSENS; 1266 printf("%s: request sense failed\n", 1267 device_xname(sc->sc_dev)); 1268 xs->error = XS_DRIVER_STUFFUP; 1269 break; 1270 } 1271 1272 xs->error = XS_SENSE; 1273 return; 1274 1275 default: 1276 xs->error = XS_DRIVER_STUFFUP; 1277 break; 1278 } 1279 break; 1280 1281 case HOST_SEL_TOUT: 1282 xs->error = XS_SELTIMEOUT; 1283 break; 1284 1285 case HOST_SCSI_RST: 1286 case HOST_DEV_RST: 1287 xs->error = XS_RESET; 1288 break; 1289 1290 case HOST_SPERR: 1291 printf("%s: SCSI Parity error detected\n", 1292 device_xname(sc->sc_dev)); 1293 xs->error = XS_DRIVER_STUFFUP; 1294 break; 1295 1296 case HOST_TIMED_OUT: 1297 xs->error = XS_TIMEOUT; 1298 break; 1299 1300 case HOST_DO_DU: 1301 case HOST_BAD_PHAS: 1302 default: 1303 xs->error = XS_DRIVER_STUFFUP; 1304 break; 1305 } 1306 1307 scsipi_done(xs); 1308 } 1309 1310 iha_append_free_scb(sc, scb); 1311 } 1312 1313 /* 1314 * iha_push_sense_request - obtain auto sense data by pushing the 1315 * SCB needing it back onto the pending 1316 * queue with a REQUEST_SENSE CDB. 1317 */ 1318 static int 1319 iha_push_sense_request(struct iha_softc *sc, struct iha_scb *scb) 1320 { 1321 struct scsipi_xfer *xs = scb->xs; 1322 struct scsipi_periph *periph = xs->xs_periph; 1323 struct scsi_request_sense *ss = (struct scsi_request_sense *)scb->cmd; 1324 int lun = periph->periph_lun; 1325 int err; 1326 1327 memset(ss, 0, sizeof(*ss)); 1328 ss->opcode = SCSI_REQUEST_SENSE; 1329 ss->byte2 = lun << SCSI_CMD_LUN_SHIFT; 1330 ss->length = sizeof(struct scsi_sense_data); 1331 1332 scb->flags = FLAG_RSENS | FLAG_DATAIN; 1333 1334 scb->scb_id &= ~MSG_IDENTIFY_DISCFLAG; 1335 1336 scb->scb_tagmsg = 0; 1337 scb->ta_stat = SCSI_OK; 1338 1339 scb->cmdlen = sizeof(struct scsi_request_sense); 1340 scb->buflen = ss->length; 1341 1342 err = bus_dmamap_load(sc->sc_dmat, scb->dmap, 1343 &xs->sense.scsi_sense, scb->buflen, NULL, 1344 BUS_DMA_READ|BUS_DMA_NOWAIT); 1345 if (err != 0) { 1346 printf("iha_push_sense_request: cannot bus_dmamap_load()\n"); 1347 xs->error = XS_DRIVER_STUFFUP; 1348 return 1; 1349 } 1350 bus_dmamap_sync(sc->sc_dmat, scb->dmap, 1351 0, scb->buflen, BUS_DMASYNC_PREREAD); 1352 1353 /* XXX What about queued command? */ 1354 iha_exec_scb(sc, scb); 1355 1356 return 0; 1357 } 1358 1359 static void 1360 iha_timeout(void *arg) 1361 { 1362 struct iha_scb *scb = (struct iha_scb *)arg; 1363 struct scsipi_xfer *xs = scb->xs; 1364 struct scsipi_periph *periph; 1365 struct iha_softc *sc; 1366 1367 if (xs == NULL) { 1368 printf("[debug] iha_timeout called with xs == NULL\n"); 1369 return; 1370 } 1371 1372 periph = xs->xs_periph; 1373 1374 sc = device_private(periph->periph_channel->chan_adapter->adapt_dev); 1375 1376 scsipi_printaddr(periph); 1377 printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 1378 iha_abort_xs(sc, xs, HOST_TIMED_OUT); 1379 } 1380 1381 /* 1382 * iha_abort_xs - find the SCB associated with the supplied xs and 1383 * stop all processing on it, moving it to the done 1384 * queue with the supplied host status value. 1385 */ 1386 static void 1387 iha_abort_xs(struct iha_softc *sc, struct scsipi_xfer *xs, uint8_t hastat) 1388 { 1389 struct iha_scb *scb; 1390 int i, s; 1391 1392 s = splbio(); 1393 1394 /* Check the pending queue for the SCB pointing to xs */ 1395 1396 TAILQ_FOREACH(scb, &sc->sc_pendscb, chain) 1397 if (scb->xs == xs) { 1398 iha_del_pend_scb(sc, scb); 1399 iha_append_done_scb(sc, scb, hastat); 1400 splx(s); 1401 return; 1402 } 1403 1404 /* 1405 * If that didn't work, check all BUSY/SELECTING SCB's for one 1406 * pointing to xs 1407 */ 1408 1409 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) 1410 switch (scb->status) { 1411 case STATUS_BUSY: 1412 case STATUS_SELECT: 1413 if (scb->xs == xs) { 1414 iha_append_done_scb(sc, scb, hastat); 1415 splx(s); 1416 return; 1417 } 1418 break; 1419 default: 1420 break; 1421 } 1422 1423 splx(s); 1424 } 1425 1426 /* 1427 * iha_data_over_run - return HOST_OK for all SCSI opcodes where BufLen 1428 * is an 'Allocation Length'. All other SCSI opcodes 1429 * get HOST_DO_DU as they SHOULD have xferred all the 1430 * data requested. 1431 * 1432 * The list of opcodes using 'Allocation Length' was 1433 * found by scanning all the SCSI-3 T10 drafts. See 1434 * www.t10.org for the curious with a .pdf reader. 1435 */ 1436 static uint8_t 1437 iha_data_over_run(struct iha_scb *scb) 1438 { 1439 switch (scb->cmd[0]) { 1440 case 0x03: /* Request Sense SPC-2 */ 1441 case 0x12: /* Inquiry SPC-2 */ 1442 case 0x1a: /* Mode Sense (6 byte version) SPC-2 */ 1443 case 0x1c: /* Receive Diagnostic Results SPC-2 */ 1444 case 0x23: /* Read Format Capacities MMC-2 */ 1445 case 0x29: /* Read Generation SBC */ 1446 case 0x34: /* Read Position SSC-2 */ 1447 case 0x37: /* Read Defect Data SBC */ 1448 case 0x3c: /* Read Buffer SPC-2 */ 1449 case 0x42: /* Read Sub Channel MMC-2 */ 1450 case 0x43: /* Read TOC/PMA/ATIP MMC */ 1451 1452 /* XXX - 2 with same opcode of 0x44? */ 1453 case 0x44: /* Read Header/Read Density Suprt MMC/SSC*/ 1454 1455 case 0x46: /* Get Configuration MMC-2 */ 1456 case 0x4a: /* Get Event/Status Notification MMC-2 */ 1457 case 0x4d: /* Log Sense SPC-2 */ 1458 case 0x51: /* Read Disc Information MMC */ 1459 case 0x52: /* Read Track Information MMC */ 1460 case 0x59: /* Read Master CUE MMC */ 1461 case 0x5a: /* Mode Sense (10 byte version) SPC-2 */ 1462 case 0x5c: /* Read Buffer Capacity MMC */ 1463 case 0x5e: /* Persistent Reserve In SPC-2 */ 1464 case 0x84: /* Receive Copy Results SPC-2 */ 1465 case 0xa0: /* Report LUNs SPC-2 */ 1466 case 0xa3: /* Various Report requests SBC-2/SCC-2*/ 1467 case 0xa4: /* Report Key MMC-2 */ 1468 case 0xad: /* Read DVD Structure MMC-2 */ 1469 case 0xb4: /* Read Element Status (Attached) SMC */ 1470 case 0xb5: /* Request Volume Element Address SMC */ 1471 case 0xb7: /* Read Defect Data (12 byte ver.) SBC */ 1472 case 0xb8: /* Read Element Status (Independ.) SMC */ 1473 case 0xba: /* Report Redundancy SCC-2 */ 1474 case 0xbd: /* Mechanism Status MMC */ 1475 case 0xbe: /* Report Basic Redundancy SCC-2 */ 1476 1477 return (HOST_OK); 1478 1479 default: 1480 return (HOST_DO_DU); 1481 } 1482 } 1483 1484 /* 1485 * iha_next_state - process the current SCB as requested in its 1486 * nextstat member. 1487 */ 1488 static int 1489 iha_next_state(struct iha_softc *sc) 1490 { 1491 1492 if (sc->sc_actscb == NULL) 1493 return (-1); 1494 1495 switch (sc->sc_actscb->nextstat) { 1496 case 1: 1497 if (iha_state_1(sc) == 3) 1498 goto state_3; 1499 break; 1500 1501 case 2: 1502 switch (iha_state_2(sc)) { 1503 case 3: 1504 goto state_3; 1505 case 4: 1506 goto state_4; 1507 default: 1508 break; 1509 } 1510 break; 1511 1512 case 3: 1513 state_3: 1514 if (iha_state_3(sc) == 4) 1515 goto state_4; 1516 break; 1517 1518 case 4: 1519 state_4: 1520 switch (iha_state_4(sc)) { 1521 case 0: 1522 return (0); 1523 case 6: 1524 goto state_6; 1525 default: 1526 break; 1527 } 1528 break; 1529 1530 case 5: 1531 switch (iha_state_5(sc)) { 1532 case 4: 1533 goto state_4; 1534 case 6: 1535 goto state_6; 1536 default: 1537 break; 1538 } 1539 break; 1540 1541 case 6: 1542 state_6: 1543 iha_state_6(sc); 1544 break; 1545 1546 case 8: 1547 iha_state_8(sc); 1548 break; 1549 1550 default: 1551 #ifdef IHA_DEBUG_STATE 1552 printf("[debug] -unknown state: %i-\n", 1553 sc->sc_actscb->nextstat); 1554 #endif 1555 iha_bad_seq(sc); 1556 break; 1557 } 1558 1559 return (-1); 1560 } 1561 1562 /* 1563 * iha_state_1 - selection is complete after a SELATNSTOP. If the target 1564 * has put the bus into MSG_OUT phase start wide/sync 1565 * negotiation. Otherwise clear the FIFO and go to state 3, 1566 * which will send the SCSI CDB to the target. 1567 */ 1568 static int 1569 iha_state_1(struct iha_softc *sc) 1570 { 1571 bus_space_tag_t iot = sc->sc_iot; 1572 bus_space_handle_t ioh = sc->sc_ioh; 1573 struct iha_scb *scb = sc->sc_actscb; 1574 struct tcs *tcs; 1575 int flags; 1576 1577 iha_mark_busy_scb(scb); 1578 1579 tcs = scb->tcs; 1580 1581 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 1582 1583 /* 1584 * If we are in PHASE_MSG_OUT, send 1585 * a) IDENT message (with tags if appropriate) 1586 * b) WDTR if the target is configured to negotiate wide xfers 1587 * ** OR ** 1588 * c) SDTR if the target is configured to negotiate sync xfers 1589 * but not wide ones 1590 * 1591 * If we are NOT, then the target is not asking for anything but 1592 * the data/command, so go straight to state 3. 1593 */ 1594 if (sc->sc_phase == PHASE_MSG_OUT) { 1595 bus_space_write_1(iot, ioh, TUL_SCTRL1, (ESBUSIN | EHRSL)); 1596 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_id); 1597 1598 if (scb->scb_tagmsg != 0) { 1599 bus_space_write_1(iot, ioh, TUL_SFIFO, 1600 scb->scb_tagmsg); 1601 bus_space_write_1(iot, ioh, TUL_SFIFO, 1602 scb->scb_tagid); 1603 } 1604 1605 flags = tcs->flags; 1606 if ((flags & FLAG_NO_NEG_WIDE) == 0) { 1607 if (iha_msgout_wdtr(sc) == -1) 1608 return (-1); 1609 } else if ((flags & FLAG_NO_NEG_SYNC) == 0) { 1610 if (iha_msgout_sdtr(sc) == -1) 1611 return (-1); 1612 } 1613 1614 } else { 1615 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1616 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 1617 } 1618 1619 return (3); 1620 } 1621 1622 /* 1623 * iha_state_2 - selection is complete after a SEL_ATN or SEL_ATN3. If the SCSI 1624 * CDB has already been send, go to state 4 to start the data 1625 * xfer. Otherwise reset the FIFO and go to state 3, sending 1626 * the SCSI CDB. 1627 */ 1628 static int 1629 iha_state_2(struct iha_softc *sc) 1630 { 1631 bus_space_tag_t iot = sc->sc_iot; 1632 bus_space_handle_t ioh = sc->sc_ioh; 1633 struct iha_scb *scb = sc->sc_actscb; 1634 1635 iha_mark_busy_scb(scb); 1636 1637 bus_space_write_1(iot, ioh, TUL_SCONFIG0, scb->tcs->sconfig0); 1638 1639 if ((sc->sc_status1 & CPDNE) != 0) 1640 return (4); 1641 1642 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1643 1644 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 1645 1646 return (3); 1647 } 1648 1649 /* 1650 * iha_state_3 - send the SCSI CDB to the target, processing any status 1651 * or other messages received until that is done or 1652 * abandoned. 1653 */ 1654 static int 1655 iha_state_3(struct iha_softc *sc) 1656 { 1657 bus_space_tag_t iot = sc->sc_iot; 1658 bus_space_handle_t ioh = sc->sc_ioh; 1659 struct iha_scb *scb = sc->sc_actscb; 1660 int flags; 1661 1662 for (;;) { 1663 switch (sc->sc_phase) { 1664 case PHASE_CMD_OUT: 1665 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, 1666 scb->cmd, scb->cmdlen); 1667 if (iha_wait(sc, XF_FIFO_OUT) == -1) 1668 return (-1); 1669 else if (sc->sc_phase == PHASE_CMD_OUT) { 1670 iha_bad_seq(sc); 1671 return (-1); 1672 } else 1673 return (4); 1674 1675 case PHASE_MSG_IN: 1676 scb->nextstat = 3; 1677 if (iha_msgin(sc) == -1) 1678 return (-1); 1679 break; 1680 1681 case PHASE_STATUS_IN: 1682 if (iha_status_msg(sc) == -1) 1683 return (-1); 1684 break; 1685 1686 case PHASE_MSG_OUT: 1687 flags = scb->tcs->flags; 1688 if ((flags & FLAG_NO_NEG_SYNC) != 0) { 1689 if (iha_msgout(sc, MSG_NOOP) == -1) 1690 return (-1); 1691 } else if (iha_msgout_sdtr(sc) == -1) 1692 return (-1); 1693 break; 1694 1695 default: 1696 printf("[debug] -s3- bad phase = %d\n", sc->sc_phase); 1697 iha_bad_seq(sc); 1698 return (-1); 1699 } 1700 } 1701 } 1702 1703 /* 1704 * iha_state_4 - start a data xfer. Handle any bus state 1705 * transitions until PHASE_DATA_IN/_OUT 1706 * or the attempt is abandoned. If there is 1707 * no data to xfer, go to state 6 and finish 1708 * processing the current SCB. 1709 */ 1710 static int 1711 iha_state_4(struct iha_softc *sc) 1712 { 1713 struct iha_scb *scb = sc->sc_actscb; 1714 1715 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) == 1716 (FLAG_DATAIN | FLAG_DATAOUT)) 1717 return (6); /* Both dir flags set => NO xfer was requested */ 1718 1719 for (;;) { 1720 if (scb->buflen == 0) 1721 return (6); 1722 1723 switch (sc->sc_phase) { 1724 case PHASE_STATUS_IN: 1725 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != 0) 1726 scb->ha_stat = iha_data_over_run(scb); 1727 if ((iha_status_msg(sc)) == -1) 1728 return (-1); 1729 break; 1730 1731 case PHASE_MSG_IN: 1732 scb->nextstat = 4; 1733 if (iha_msgin(sc) == -1) 1734 return (-1); 1735 break; 1736 1737 case PHASE_MSG_OUT: 1738 if ((sc->sc_status0 & SPERR) != 0) { 1739 scb->buflen = 0; 1740 scb->ha_stat = HOST_SPERR; 1741 if (iha_msgout(sc, MSG_INITIATOR_DET_ERR) == -1) 1742 return (-1); 1743 else 1744 return (6); 1745 } else { 1746 if (iha_msgout(sc, MSG_NOOP) == -1) 1747 return (-1); 1748 } 1749 break; 1750 1751 case PHASE_DATA_IN: 1752 return (iha_xfer_data(sc, scb, FLAG_DATAIN)); 1753 1754 case PHASE_DATA_OUT: 1755 return (iha_xfer_data(sc, scb, FLAG_DATAOUT)); 1756 1757 default: 1758 iha_bad_seq(sc); 1759 return (-1); 1760 } 1761 } 1762 } 1763 1764 /* 1765 * iha_state_5 - handle the partial or final completion of the current 1766 * data xfer. If DMA is still active stop it. If there is 1767 * more data to xfer, go to state 4 and start the xfer. 1768 * If not go to state 6 and finish the SCB. 1769 */ 1770 static int 1771 iha_state_5(struct iha_softc *sc) 1772 { 1773 bus_space_tag_t iot = sc->sc_iot; 1774 bus_space_handle_t ioh = sc->sc_ioh; 1775 struct iha_scb *scb = sc->sc_actscb; 1776 struct iha_sg_element *sg; 1777 uint32_t cnt; 1778 uint8_t period, stat; 1779 long xcnt; /* cannot use unsigned!! see code: if (xcnt < 0) */ 1780 int i; 1781 1782 cnt = bus_space_read_4(iot, ioh, TUL_STCNT0) & TCNT; 1783 1784 /* 1785 * Stop any pending DMA activity and check for parity error. 1786 */ 1787 1788 if ((bus_space_read_1(iot, ioh, TUL_DCMD) & XDIR) != 0) { 1789 /* Input Operation */ 1790 if ((sc->sc_status0 & SPERR) != 0) 1791 scb->ha_stat = HOST_SPERR; 1792 1793 if ((bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) != 0) { 1794 bus_space_write_1(iot, ioh, TUL_DCTRL0, 1795 bus_space_read_1(iot, ioh, TUL_DCTRL0) | SXSTP); 1796 while (bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) 1797 ; 1798 } 1799 1800 } else { 1801 /* Output Operation */ 1802 if ((sc->sc_status1 & SXCMP) == 0) { 1803 period = scb->tcs->syncm; 1804 if ((period & PERIOD_WIDE_SCSI) != 0) 1805 cnt += (bus_space_read_1(iot, ioh, 1806 TUL_SFIFOCNT) & FIFOC) * 2; 1807 else 1808 cnt += bus_space_read_1(iot, ioh, 1809 TUL_SFIFOCNT) & FIFOC; 1810 } 1811 1812 if ((bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) != 0) { 1813 bus_space_write_1(iot, ioh, TUL_DCMD, ABTXFR); 1814 do 1815 stat = bus_space_read_1(iot, ioh, TUL_ISTUS0); 1816 while ((stat & DABT) == 0); 1817 } 1818 1819 if ((cnt == 1) && (sc->sc_phase == PHASE_DATA_OUT)) { 1820 if (iha_wait(sc, XF_FIFO_OUT) == -1) 1821 return (-1); 1822 cnt = 0; 1823 1824 } else if ((sc->sc_status1 & SXCMP) == 0) 1825 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1826 } 1827 1828 if (cnt == 0) { 1829 scb->buflen = 0; 1830 return (6); 1831 } 1832 1833 /* Update active data pointer and restart the I/O at the new point */ 1834 1835 xcnt = scb->buflen - cnt; /* xcnt == bytes xferred */ 1836 scb->buflen = cnt; /* cnt == bytes left */ 1837 1838 if ((scb->flags & FLAG_SG) != 0) { 1839 sg = &scb->sglist[scb->sg_index]; 1840 for (i = scb->sg_index; i < scb->sg_max; sg++, i++) { 1841 xcnt -= le32toh(sg->sg_len); 1842 if (xcnt < 0) { 1843 xcnt += le32toh(sg->sg_len); 1844 1845 sg->sg_addr = 1846 htole32(le32toh(sg->sg_addr) + xcnt); 1847 sg->sg_len = 1848 htole32(le32toh(sg->sg_len) - xcnt); 1849 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1850 scb->sgoffset, IHA_SG_SIZE, 1851 BUS_DMASYNC_PREWRITE); 1852 1853 scb->bufaddr += (i - scb->sg_index) * 1854 sizeof(struct iha_sg_element); 1855 scb->sg_size = scb->sg_max - i; 1856 scb->sg_index = i; 1857 1858 return (4); 1859 } 1860 } 1861 return (6); 1862 1863 } else 1864 scb->bufaddr += xcnt; 1865 1866 return (4); 1867 } 1868 1869 /* 1870 * iha_state_6 - finish off the active scb (may require several 1871 * iterations if PHASE_MSG_IN) and return -1 to indicate 1872 * the bus is free. 1873 */ 1874 static int 1875 iha_state_6(struct iha_softc *sc) 1876 { 1877 1878 for (;;) { 1879 switch (sc->sc_phase) { 1880 case PHASE_STATUS_IN: 1881 if (iha_status_msg(sc) == -1) 1882 return (-1); 1883 break; 1884 1885 case PHASE_MSG_IN: 1886 sc->sc_actscb->nextstat = 6; 1887 if ((iha_msgin(sc)) == -1) 1888 return (-1); 1889 break; 1890 1891 case PHASE_MSG_OUT: 1892 if ((iha_msgout(sc, MSG_NOOP)) == -1) 1893 return (-1); 1894 break; 1895 1896 case PHASE_DATA_IN: 1897 if (iha_xpad_in(sc) == -1) 1898 return (-1); 1899 break; 1900 1901 case PHASE_DATA_OUT: 1902 if (iha_xpad_out(sc) == -1) 1903 return (-1); 1904 break; 1905 1906 default: 1907 iha_bad_seq(sc); 1908 return (-1); 1909 } 1910 } 1911 } 1912 1913 /* 1914 * iha_state_8 - reset the active device and all busy SCBs using it 1915 */ 1916 static int 1917 iha_state_8(struct iha_softc *sc) 1918 { 1919 bus_space_tag_t iot = sc->sc_iot; 1920 bus_space_handle_t ioh = sc->sc_ioh; 1921 struct iha_scb *scb; 1922 int i; 1923 uint8_t tar; 1924 1925 if (sc->sc_phase == PHASE_MSG_OUT) { 1926 bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_BUS_DEV_RESET); 1927 1928 scb = sc->sc_actscb; 1929 1930 /* This SCB finished correctly -- resetting the device */ 1931 iha_append_done_scb(sc, scb, HOST_OK); 1932 1933 iha_reset_tcs(scb->tcs, sc->sc_sconf1); 1934 1935 tar = scb->target; 1936 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) 1937 if (scb->target == tar) 1938 switch (scb->status) { 1939 case STATUS_BUSY: 1940 iha_append_done_scb(sc, 1941 scb, HOST_DEV_RST); 1942 break; 1943 1944 case STATUS_SELECT: 1945 iha_push_pend_scb(sc, scb); 1946 break; 1947 1948 default: 1949 break; 1950 } 1951 1952 sc->sc_flags |= FLAG_EXPECT_DISC; 1953 1954 if (iha_wait(sc, XF_FIFO_OUT) == -1) 1955 return (-1); 1956 } 1957 1958 iha_bad_seq(sc); 1959 return (-1); 1960 } 1961 1962 /* 1963 * iha_xfer_data - initiate the DMA xfer of the data 1964 */ 1965 static int 1966 iha_xfer_data(struct iha_softc *sc, struct iha_scb *scb, int direction) 1967 { 1968 bus_space_tag_t iot = sc->sc_iot; 1969 bus_space_handle_t ioh = sc->sc_ioh; 1970 uint32_t xferlen; 1971 uint8_t xfercmd; 1972 1973 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != direction) 1974 return (6); /* wrong direction, abandon I/O */ 1975 1976 bus_space_write_4(iot, ioh, TUL_STCNT0, scb->buflen); 1977 1978 xfercmd = STRXFR; 1979 if (direction == FLAG_DATAIN) 1980 xfercmd |= XDIR; 1981 1982 if (scb->flags & FLAG_SG) { 1983 xferlen = scb->sg_size * sizeof(struct iha_sg_element); 1984 xfercmd |= SGXFR; 1985 } else 1986 xferlen = scb->buflen; 1987 1988 bus_space_write_4(iot, ioh, TUL_DXC, xferlen); 1989 bus_space_write_4(iot, ioh, TUL_DXPA, scb->bufaddr); 1990 bus_space_write_1(iot, ioh, TUL_DCMD, xfercmd); 1991 1992 bus_space_write_1(iot, ioh, TUL_SCMD, 1993 (direction == FLAG_DATAIN) ? XF_DMA_IN : XF_DMA_OUT); 1994 1995 scb->nextstat = 5; 1996 1997 return (0); 1998 } 1999 2000 static int 2001 iha_xpad_in(struct iha_softc *sc) 2002 { 2003 bus_space_tag_t iot = sc->sc_iot; 2004 bus_space_handle_t ioh = sc->sc_ioh; 2005 struct iha_scb *scb = sc->sc_actscb; 2006 2007 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != 0) 2008 scb->ha_stat = HOST_DO_DU; 2009 2010 for (;;) { 2011 if ((scb->tcs->syncm & PERIOD_WIDE_SCSI) != 0) 2012 bus_space_write_4(iot, ioh, TUL_STCNT0, 2); 2013 else 2014 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2015 2016 switch (iha_wait(sc, XF_FIFO_IN)) { 2017 case -1: 2018 return (-1); 2019 2020 case PHASE_DATA_IN: 2021 (void)bus_space_read_1(iot, ioh, TUL_SFIFO); 2022 break; 2023 2024 default: 2025 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2026 return (6); 2027 } 2028 } 2029 } 2030 2031 static int 2032 iha_xpad_out(struct iha_softc *sc) 2033 { 2034 bus_space_tag_t iot = sc->sc_iot; 2035 bus_space_handle_t ioh = sc->sc_ioh; 2036 struct iha_scb *scb = sc->sc_actscb; 2037 2038 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != 0) 2039 scb->ha_stat = HOST_DO_DU; 2040 2041 for (;;) { 2042 if ((scb->tcs->syncm & PERIOD_WIDE_SCSI) != 0) 2043 bus_space_write_4(iot, ioh, TUL_STCNT0, 2); 2044 else 2045 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2046 2047 bus_space_write_1(iot, ioh, TUL_SFIFO, 0); 2048 2049 switch (iha_wait(sc, XF_FIFO_OUT)) { 2050 case -1: 2051 return (-1); 2052 2053 case PHASE_DATA_OUT: 2054 break; 2055 2056 default: 2057 /* Disable wide CPU to allow read 16 bits */ 2058 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 2059 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2060 return (6); 2061 } 2062 } 2063 } 2064 2065 static int 2066 iha_status_msg(struct iha_softc *sc) 2067 { 2068 bus_space_tag_t iot = sc->sc_iot; 2069 bus_space_handle_t ioh = sc->sc_ioh; 2070 struct iha_scb *scb; 2071 uint8_t msg; 2072 int phase; 2073 2074 if ((phase = iha_wait(sc, CMD_COMP)) == -1) 2075 return (-1); 2076 2077 scb = sc->sc_actscb; 2078 2079 scb->ta_stat = bus_space_read_1(iot, ioh, TUL_SFIFO); 2080 2081 if (phase == PHASE_MSG_OUT) { 2082 if ((sc->sc_status0 & SPERR) == 0) 2083 bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_NOOP); 2084 else 2085 bus_space_write_1(iot, ioh, TUL_SFIFO, 2086 MSG_PARITY_ERROR); 2087 2088 return (iha_wait(sc, XF_FIFO_OUT)); 2089 2090 } else if (phase == PHASE_MSG_IN) { 2091 msg = bus_space_read_1(iot, ioh, TUL_SFIFO); 2092 2093 if ((sc->sc_status0 & SPERR) != 0) 2094 switch (iha_wait(sc, MSG_ACCEPT)) { 2095 case -1: 2096 return (-1); 2097 case PHASE_MSG_OUT: 2098 bus_space_write_1(iot, ioh, TUL_SFIFO, 2099 MSG_PARITY_ERROR); 2100 return (iha_wait(sc, XF_FIFO_OUT)); 2101 default: 2102 iha_bad_seq(sc); 2103 return (-1); 2104 } 2105 2106 if (msg == MSG_CMDCOMPLETE) { 2107 if ((scb->ta_stat & 2108 (SCSI_INTERM | SCSI_BUSY)) == SCSI_INTERM) { 2109 iha_bad_seq(sc); 2110 return (-1); 2111 } 2112 sc->sc_flags |= FLAG_EXPECT_DONE_DISC; 2113 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2114 return (iha_wait(sc, MSG_ACCEPT)); 2115 } 2116 2117 if ((msg == MSG_LINK_CMD_COMPLETE) 2118 || (msg == MSG_LINK_CMD_COMPLETEF)) { 2119 if ((scb->ta_stat & 2120 (SCSI_INTERM | SCSI_BUSY)) == SCSI_INTERM) 2121 return (iha_wait(sc, MSG_ACCEPT)); 2122 } 2123 } 2124 2125 iha_bad_seq(sc); 2126 return (-1); 2127 } 2128 2129 /* 2130 * iha_busfree - SCSI bus free detected as a result of a TIMEOUT or 2131 * DISCONNECT interrupt. Reset the tulip FIFO and 2132 * SCONFIG0 and enable hardware reselect. Move any active 2133 * SCB to sc_donescb list. Return an appropriate host status 2134 * if an I/O was active. 2135 */ 2136 static void 2137 iha_busfree(struct iha_softc *sc) 2138 { 2139 bus_space_tag_t iot = sc->sc_iot; 2140 bus_space_handle_t ioh = sc->sc_ioh; 2141 struct iha_scb *scb; 2142 2143 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2144 bus_space_write_1(iot, ioh, TUL_SCONFIG0, SCONFIG0DEFAULT); 2145 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 2146 2147 scb = sc->sc_actscb; 2148 2149 if (scb != NULL) { 2150 if (scb->status == STATUS_SELECT) 2151 /* selection timeout */ 2152 iha_append_done_scb(sc, scb, HOST_SEL_TOUT); 2153 else 2154 /* Unexpected bus free */ 2155 iha_append_done_scb(sc, scb, HOST_BAD_PHAS); 2156 } 2157 } 2158 2159 /* 2160 * iha_resel - handle a detected SCSI bus reselection request. 2161 */ 2162 static int 2163 iha_resel(struct iha_softc *sc) 2164 { 2165 bus_space_tag_t iot = sc->sc_iot; 2166 bus_space_handle_t ioh = sc->sc_ioh; 2167 struct iha_scb *scb; 2168 struct tcs *tcs; 2169 uint8_t tag, target, lun, msg, abortmsg; 2170 2171 if (sc->sc_actscb != NULL) { 2172 if ((sc->sc_actscb->status == STATUS_SELECT)) 2173 iha_push_pend_scb(sc, sc->sc_actscb); 2174 sc->sc_actscb = NULL; 2175 } 2176 2177 target = bus_space_read_1(iot, ioh, TUL_SBID); 2178 lun = bus_space_read_1(iot, ioh, TUL_SALVC) & IHA_MSG_IDENTIFY_LUNMASK; 2179 2180 tcs = &sc->sc_tcs[target]; 2181 2182 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 2183 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 2184 2185 abortmsg = MSG_ABORT; /* until a valid tag has been obtained */ 2186 2187 if (tcs->ntagscb != NULL) 2188 /* There is a non-tagged I/O active on the target */ 2189 scb = tcs->ntagscb; 2190 2191 else { 2192 /* 2193 * Since there is no active non-tagged operation 2194 * read the tag type, the tag itself, and find 2195 * the appropriate scb by indexing sc_scb with 2196 * the tag. 2197 */ 2198 2199 switch (iha_wait(sc, MSG_ACCEPT)) { 2200 case -1: 2201 return (-1); 2202 case PHASE_MSG_IN: 2203 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2204 if ((iha_wait(sc, XF_FIFO_IN)) == -1) 2205 return (-1); 2206 break; 2207 default: 2208 goto abort; 2209 } 2210 2211 msg = bus_space_read_1(iot, ioh, TUL_SFIFO); /* Read Tag Msg */ 2212 2213 if ((msg < MSG_SIMPLE_Q_TAG) || (msg > MSG_ORDERED_Q_TAG)) 2214 goto abort; 2215 2216 switch (iha_wait(sc, MSG_ACCEPT)) { 2217 case -1: 2218 return (-1); 2219 case PHASE_MSG_IN: 2220 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2221 if ((iha_wait(sc, XF_FIFO_IN)) == -1) 2222 return (-1); 2223 break; 2224 default: 2225 goto abort; 2226 } 2227 2228 tag = bus_space_read_1(iot, ioh, TUL_SFIFO); /* Read Tag ID */ 2229 scb = &sc->sc_scb[tag]; 2230 2231 abortmsg = MSG_ABORT_TAG; /* Now that we have valdid tag! */ 2232 } 2233 2234 if ((scb->target != target) 2235 || (scb->lun != lun) 2236 || (scb->status != STATUS_BUSY)) { 2237 abort: 2238 iha_msgout_abort(sc, abortmsg); 2239 return (-1); 2240 } 2241 2242 sc->sc_actscb = scb; 2243 2244 if (iha_wait(sc, MSG_ACCEPT) == -1) 2245 return (-1); 2246 2247 return (iha_next_state(sc)); 2248 } 2249 2250 static int 2251 iha_msgin(struct iha_softc *sc) 2252 { 2253 bus_space_tag_t iot = sc->sc_iot; 2254 bus_space_handle_t ioh = sc->sc_ioh; 2255 int flags; 2256 int phase; 2257 uint8_t msg; 2258 2259 for (;;) { 2260 if ((bus_space_read_1(iot, ioh, TUL_SFIFOCNT) & FIFOC) > 0) 2261 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2262 2263 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2264 2265 phase = iha_wait(sc, XF_FIFO_IN); 2266 msg = bus_space_read_1(iot, ioh, TUL_SFIFO); 2267 2268 switch (msg) { 2269 case MSG_DISCONNECT: 2270 sc->sc_flags |= FLAG_EXPECT_DISC; 2271 if (iha_wait(sc, MSG_ACCEPT) != -1) 2272 iha_bad_seq(sc); 2273 phase = -1; 2274 break; 2275 case MSG_SAVEDATAPOINTER: 2276 case MSG_RESTOREPOINTERS: 2277 case MSG_NOOP: 2278 phase = iha_wait(sc, MSG_ACCEPT); 2279 break; 2280 case MSG_MESSAGE_REJECT: 2281 /* XXX - need to clear FIFO like other 'Clear ATN'?*/ 2282 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 2283 flags = sc->sc_actscb->tcs->flags; 2284 if ((flags & FLAG_NO_NEG_SYNC) == 0) 2285 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2286 phase = iha_wait(sc, MSG_ACCEPT); 2287 break; 2288 case MSG_EXTENDED: 2289 phase = iha_msgin_extended(sc); 2290 break; 2291 case MSG_IGN_WIDE_RESIDUE: 2292 phase = iha_msgin_ignore_wid_resid(sc); 2293 break; 2294 case MSG_CMDCOMPLETE: 2295 sc->sc_flags |= FLAG_EXPECT_DONE_DISC; 2296 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2297 phase = iha_wait(sc, MSG_ACCEPT); 2298 if (phase != -1) { 2299 iha_bad_seq(sc); 2300 return (-1); 2301 } 2302 break; 2303 default: 2304 printf("[debug] iha_msgin: bad msg type: %d\n", msg); 2305 phase = iha_msgout_reject(sc); 2306 break; 2307 } 2308 2309 if (phase != PHASE_MSG_IN) 2310 return (phase); 2311 } 2312 /* NOTREACHED */ 2313 } 2314 2315 static int 2316 iha_msgin_extended(struct iha_softc *sc) 2317 { 2318 bus_space_tag_t iot = sc->sc_iot; 2319 bus_space_handle_t ioh = sc->sc_ioh; 2320 int flags, i, phase, msglen, msgcode; 2321 2322 /* 2323 * XXX - can we just stop reading and reject, or do we have to 2324 * read all input, discarding the excess, and then reject 2325 */ 2326 for (i = 0; i < IHA_MAX_EXTENDED_MSG; i++) { 2327 phase = iha_wait(sc, MSG_ACCEPT); 2328 2329 if (phase != PHASE_MSG_IN) 2330 return (phase); 2331 2332 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2333 2334 if (iha_wait(sc, XF_FIFO_IN) == -1) 2335 return (-1); 2336 2337 sc->sc_msg[i] = bus_space_read_1(iot, ioh, TUL_SFIFO); 2338 2339 if (sc->sc_msg[0] == i) 2340 break; 2341 } 2342 2343 msglen = sc->sc_msg[0]; 2344 msgcode = sc->sc_msg[1]; 2345 2346 if ((msglen == MSG_EXT_SDTR_LEN) && (msgcode == MSG_EXT_SDTR)) { 2347 if (iha_msgin_sdtr(sc) == 0) { 2348 iha_sync_done(sc); 2349 return (iha_wait(sc, MSG_ACCEPT)); 2350 } 2351 2352 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2353 2354 phase = iha_wait(sc, MSG_ACCEPT); 2355 if (phase != PHASE_MSG_OUT) 2356 return (phase); 2357 2358 /* Clear FIFO for important message - final SYNC offer */ 2359 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2360 2361 iha_sync_done(sc); /* This is our final offer */ 2362 2363 } else if ((msglen == MSG_EXT_WDTR_LEN) && (msgcode == MSG_EXT_WDTR)) { 2364 2365 flags = sc->sc_actscb->tcs->flags; 2366 2367 if ((flags & FLAG_NO_WIDE) != 0) 2368 /* Offer 8bit xfers only */ 2369 sc->sc_msg[2] = MSG_EXT_WDTR_BUS_8_BIT; 2370 2371 else if (sc->sc_msg[2] > MSG_EXT_WDTR_BUS_32_BIT) 2372 /* BAD MSG */ 2373 return (iha_msgout_reject(sc)); 2374 2375 else if (sc->sc_msg[2] == MSG_EXT_WDTR_BUS_32_BIT) 2376 /* Offer 16bit instead */ 2377 sc->sc_msg[2] = MSG_EXT_WDTR_BUS_16_BIT; 2378 2379 else { 2380 iha_wide_done(sc); 2381 if ((flags & FLAG_NO_NEG_SYNC) == 0) 2382 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2383 return (iha_wait(sc, MSG_ACCEPT)); 2384 } 2385 2386 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2387 2388 phase = iha_wait(sc, MSG_ACCEPT); 2389 if (phase != PHASE_MSG_OUT) 2390 return (phase); 2391 } else 2392 return (iha_msgout_reject(sc)); 2393 2394 return (iha_msgout_extended(sc)); 2395 } 2396 2397 /* 2398 * iha_msgin_sdtr - check SDTR msg in sc_msg. If the offer is 2399 * acceptable leave sc_msg as is and return 0. 2400 * If the negotiation must continue, modify sc_msg 2401 * as needed and return 1. Else return 0. 2402 */ 2403 static int 2404 iha_msgin_sdtr(struct iha_softc *sc) 2405 { 2406 int flags; 2407 int newoffer; 2408 uint8_t default_period; 2409 2410 flags = sc->sc_actscb->tcs->flags; 2411 2412 default_period = iha_rate_tbl[flags & FLAG_SCSI_RATE]; 2413 2414 if (sc->sc_msg[3] == 0) 2415 /* target offered async only. Accept it. */ 2416 return (0); 2417 2418 newoffer = 0; 2419 2420 if ((flags & FLAG_NO_SYNC) != 0) { 2421 sc->sc_msg[3] = 0; 2422 newoffer = 1; 2423 } 2424 2425 if (sc->sc_msg[3] > IHA_MAX_OFFSET) { 2426 sc->sc_msg[3] = IHA_MAX_OFFSET; 2427 newoffer = 1; 2428 } 2429 2430 if (sc->sc_msg[2] < default_period) { 2431 sc->sc_msg[2] = default_period; 2432 newoffer = 1; 2433 } 2434 2435 if (sc->sc_msg[2] > IHA_MAX_PERIOD) { 2436 /* Use async */ 2437 sc->sc_msg[3] = 0; 2438 newoffer = 1; 2439 } 2440 2441 return (newoffer); 2442 } 2443 2444 static int 2445 iha_msgin_ignore_wid_resid(struct iha_softc *sc) 2446 { 2447 bus_space_tag_t iot = sc->sc_iot; 2448 bus_space_handle_t ioh = sc->sc_ioh; 2449 int phase; 2450 2451 phase = iha_wait(sc, MSG_ACCEPT); 2452 2453 if (phase == PHASE_MSG_IN) { 2454 phase = iha_wait(sc, XF_FIFO_IN); 2455 2456 if (phase != -1) { 2457 bus_space_write_1(iot, ioh, TUL_SFIFO, 0); 2458 (void)bus_space_read_1(iot, ioh, TUL_SFIFO); 2459 (void)bus_space_read_1(iot, ioh, TUL_SFIFO); 2460 2461 phase = iha_wait(sc, MSG_ACCEPT); 2462 } 2463 } 2464 2465 return (phase); 2466 } 2467 2468 static int 2469 iha_msgout(struct iha_softc *sc, uint8_t msg) 2470 { 2471 2472 bus_space_write_1(sc->sc_iot, sc->sc_ioh, TUL_SFIFO, msg); 2473 2474 return (iha_wait(sc, XF_FIFO_OUT)); 2475 } 2476 2477 static void 2478 iha_msgout_abort(struct iha_softc *sc, uint8_t aborttype) 2479 { 2480 2481 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2482 2483 switch (iha_wait(sc, MSG_ACCEPT)) { 2484 case -1: 2485 break; 2486 2487 case PHASE_MSG_OUT: 2488 sc->sc_flags |= FLAG_EXPECT_DISC; 2489 if (iha_msgout(sc, aborttype) != -1) 2490 iha_bad_seq(sc); 2491 break; 2492 2493 default: 2494 iha_bad_seq(sc); 2495 break; 2496 } 2497 } 2498 2499 static int 2500 iha_msgout_reject(struct iha_softc *sc) 2501 { 2502 2503 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2504 2505 if (iha_wait(sc, MSG_ACCEPT) == PHASE_MSG_OUT) 2506 return (iha_msgout(sc, MSG_MESSAGE_REJECT)); 2507 2508 return (-1); 2509 } 2510 2511 static int 2512 iha_msgout_extended(struct iha_softc *sc) 2513 { 2514 bus_space_tag_t iot = sc->sc_iot; 2515 bus_space_handle_t ioh = sc->sc_ioh; 2516 int phase; 2517 2518 bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_EXTENDED); 2519 2520 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, 2521 sc->sc_msg, sc->sc_msg[0] + 1); 2522 2523 phase = iha_wait(sc, XF_FIFO_OUT); 2524 2525 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2526 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 2527 2528 return (phase); 2529 } 2530 2531 static int 2532 iha_msgout_wdtr(struct iha_softc *sc) 2533 { 2534 2535 sc->sc_actscb->tcs->flags |= FLAG_WIDE_DONE; 2536 2537 sc->sc_msg[0] = MSG_EXT_WDTR_LEN; 2538 sc->sc_msg[1] = MSG_EXT_WDTR; 2539 sc->sc_msg[2] = MSG_EXT_WDTR_BUS_16_BIT; 2540 2541 return (iha_msgout_extended(sc)); 2542 } 2543 2544 static int 2545 iha_msgout_sdtr(struct iha_softc *sc) 2546 { 2547 struct tcs *tcs = sc->sc_actscb->tcs; 2548 2549 tcs->flags |= FLAG_SYNC_DONE; 2550 2551 sc->sc_msg[0] = MSG_EXT_SDTR_LEN; 2552 sc->sc_msg[1] = MSG_EXT_SDTR; 2553 sc->sc_msg[2] = iha_rate_tbl[tcs->flags & FLAG_SCSI_RATE]; 2554 sc->sc_msg[3] = IHA_MAX_OFFSET; /* REQ/ACK */ 2555 2556 return (iha_msgout_extended(sc)); 2557 } 2558 2559 static void 2560 iha_wide_done(struct iha_softc *sc) 2561 { 2562 bus_space_tag_t iot = sc->sc_iot; 2563 bus_space_handle_t ioh = sc->sc_ioh; 2564 struct tcs *tcs = sc->sc_actscb->tcs; 2565 2566 tcs->syncm = 0; 2567 tcs->period = 0; 2568 tcs->offset = 0; 2569 2570 if (sc->sc_msg[2] != 0) 2571 tcs->syncm |= PERIOD_WIDE_SCSI; 2572 2573 tcs->sconfig0 &= ~ALTPD; 2574 tcs->flags &= ~FLAG_SYNC_DONE; 2575 tcs->flags |= FLAG_WIDE_DONE; 2576 2577 iha_update_xfer_mode(sc, sc->sc_actscb->target); 2578 2579 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 2580 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 2581 } 2582 2583 static void 2584 iha_sync_done(struct iha_softc *sc) 2585 { 2586 bus_space_tag_t iot = sc->sc_iot; 2587 bus_space_handle_t ioh = sc->sc_ioh; 2588 struct tcs *tcs = sc->sc_actscb->tcs; 2589 int i; 2590 2591 tcs->period = sc->sc_msg[2]; 2592 tcs->offset = sc->sc_msg[3]; 2593 if (tcs->offset != 0) { 2594 tcs->syncm |= tcs->offset; 2595 2596 /* pick the highest possible rate */ 2597 for (i = 0; i < sizeof(iha_rate_tbl); i++) 2598 if (iha_rate_tbl[i] >= tcs->period) 2599 break; 2600 2601 tcs->syncm |= (i << 4); 2602 tcs->sconfig0 |= ALTPD; 2603 } 2604 2605 tcs->flags |= FLAG_SYNC_DONE; 2606 2607 iha_update_xfer_mode(sc, sc->sc_actscb->target); 2608 2609 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 2610 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 2611 } 2612 2613 /* 2614 * iha_bad_seq - a SCSI bus phase was encountered out of the 2615 * correct/expected sequence. Reset the SCSI bus. 2616 */ 2617 static void 2618 iha_bad_seq(struct iha_softc *sc) 2619 { 2620 struct iha_scb *scb = sc->sc_actscb; 2621 2622 if (scb != NULL) 2623 iha_append_done_scb(sc, scb, HOST_BAD_PHAS); 2624 2625 iha_reset_scsi_bus(sc); 2626 iha_reset_chip(sc); 2627 } 2628 2629 /* 2630 * iha_read_eeprom - read Serial EEPROM value & set to defaults 2631 * if required. XXX - Writing does NOT work! 2632 */ 2633 static void 2634 iha_read_eeprom(struct iha_softc *sc, struct iha_eeprom *eeprom) 2635 { 2636 bus_space_tag_t iot = sc->sc_iot; 2637 bus_space_handle_t ioh = sc->sc_ioh; 2638 uint16_t *tbuf = (uint16_t *)eeprom; 2639 uint8_t gctrl; 2640 2641 /* Enable EEProm programming */ 2642 gctrl = bus_space_read_1(iot, ioh, TUL_GCTRL0) | EEPRG; 2643 bus_space_write_1(iot, ioh, TUL_GCTRL0, gctrl); 2644 2645 /* Read EEProm */ 2646 if (iha_se2_rd_all(sc, tbuf) == 0) 2647 panic("%s: cannot read EEPROM", device_xname(sc->sc_dev)); 2648 2649 /* Disable EEProm programming */ 2650 gctrl = bus_space_read_1(iot, ioh, TUL_GCTRL0) & ~EEPRG; 2651 bus_space_write_1(iot, ioh, TUL_GCTRL0, gctrl); 2652 } 2653 2654 #ifdef notused 2655 /* 2656 * iha_se2_update_all - Update SCSI H/A configuration parameters from 2657 * serial EEPROM Setup default pattern. Only 2658 * change those values different from the values 2659 * in iha_eeprom. 2660 */ 2661 static void 2662 iha_se2_update_all(struct iha_softc *sc) 2663 { 2664 bus_space_tag_t iot = sc->sc_iot; 2665 bus_space_handle_t ioh = sc->sc_ioh; 2666 uint16_t *np; 2667 uint32_t chksum; 2668 int i; 2669 2670 /* Enable erase/write state of EEPROM */ 2671 iha_se2_instr(sc, ENABLE_ERASE); 2672 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2673 EEP_WAIT(); 2674 2675 np = (uint16_t *)&eeprom_default; 2676 2677 for (i = 0, chksum = 0; i < EEPROM_SIZE - 1; i++) { 2678 iha_se2_wr(sc, i, *np); 2679 chksum += *np++; 2680 } 2681 2682 chksum &= 0x0000ffff; 2683 iha_se2_wr(sc, 31, chksum); 2684 2685 /* Disable erase/write state of EEPROM */ 2686 iha_se2_instr(sc, 0); 2687 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2688 EEP_WAIT(); 2689 } 2690 2691 /* 2692 * iha_se2_wr - write the given 16 bit value into the Serial EEPROM 2693 * at the specified offset 2694 */ 2695 static void 2696 iha_se2_wr(struct iha_softc *sc, int addr, uint16_t writeword) 2697 { 2698 bus_space_tag_t iot = sc->sc_iot; 2699 bus_space_handle_t ioh = sc->sc_ioh; 2700 int i, bit; 2701 2702 /* send 'WRITE' Instruction == address | WRITE bit */ 2703 iha_se2_instr(sc, addr | WRITE); 2704 2705 for (i = 16; i > 0; i--) { 2706 if (writeword & (1 << (i - 1))) 2707 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRDO); 2708 else 2709 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2710 EEP_WAIT(); 2711 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRCK); 2712 EEP_WAIT(); 2713 } 2714 2715 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2716 EEP_WAIT(); 2717 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2718 EEP_WAIT(); 2719 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2720 EEP_WAIT(); 2721 2722 for (;;) { 2723 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRCK); 2724 EEP_WAIT(); 2725 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2726 EEP_WAIT(); 2727 bit = bus_space_read_1(iot, ioh, TUL_NVRAM) & NVRDI; 2728 EEP_WAIT(); 2729 if (bit != 0) 2730 break; /* write complete */ 2731 } 2732 2733 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2734 } 2735 #endif 2736 2737 /* 2738 * iha_se2_rd - read & return the 16 bit value at the specified 2739 * offset in the Serial E2PROM 2740 * 2741 */ 2742 static uint16_t 2743 iha_se2_rd(struct iha_softc *sc, int addr) 2744 { 2745 bus_space_tag_t iot = sc->sc_iot; 2746 bus_space_handle_t ioh = sc->sc_ioh; 2747 int i, bit; 2748 uint16_t readword; 2749 2750 /* Send 'READ' instruction == address | READ bit */ 2751 iha_se2_instr(sc, addr | READ); 2752 2753 readword = 0; 2754 for (i = 16; i > 0; i--) { 2755 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRCK); 2756 EEP_WAIT(); 2757 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2758 EEP_WAIT(); 2759 /* sample data after the following edge of clock */ 2760 bit = bus_space_read_1(iot, ioh, TUL_NVRAM) & NVRDI ? 1 : 0; 2761 EEP_WAIT(); 2762 2763 readword |= bit << (i - 1); 2764 } 2765 2766 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2767 2768 return (readword); 2769 } 2770 2771 /* 2772 * iha_se2_rd_all - Read SCSI H/A config parameters from serial EEPROM 2773 */ 2774 static int 2775 iha_se2_rd_all(struct iha_softc *sc, uint16_t *tbuf) 2776 { 2777 struct iha_eeprom *eeprom = (struct iha_eeprom *)tbuf; 2778 uint32_t chksum; 2779 int i; 2780 2781 for (i = 0, chksum = 0; i < EEPROM_SIZE - 1; i++) { 2782 *tbuf = iha_se2_rd(sc, i); 2783 chksum += *tbuf++; 2784 } 2785 *tbuf = iha_se2_rd(sc, 31); /* read checksum from EEPROM */ 2786 2787 chksum &= 0x0000ffff; /* lower 16 bits */ 2788 2789 return (eeprom->signature == EEP_SIGNATURE) && 2790 (eeprom->checksum == chksum); 2791 } 2792 2793 /* 2794 * iha_se2_instr - write an octet to serial E2PROM one bit at a time 2795 */ 2796 static void 2797 iha_se2_instr(struct iha_softc *sc, int instr) 2798 { 2799 bus_space_tag_t iot = sc->sc_iot; 2800 bus_space_handle_t ioh = sc->sc_ioh; 2801 int b, i; 2802 2803 b = NVRCS | NVRDO; /* Write the start bit (== 1) */ 2804 2805 bus_space_write_1(iot, ioh, TUL_NVRAM, b); 2806 EEP_WAIT(); 2807 bus_space_write_1(iot, ioh, TUL_NVRAM, b | NVRCK); 2808 EEP_WAIT(); 2809 2810 for (i = 8; i > 0; i--) { 2811 if (instr & (1 << (i - 1))) 2812 b = NVRCS | NVRDO; /* Write a 1 bit */ 2813 else 2814 b = NVRCS; /* Write a 0 bit */ 2815 2816 bus_space_write_1(iot, ioh, TUL_NVRAM, b); 2817 EEP_WAIT(); 2818 bus_space_write_1(iot, ioh, TUL_NVRAM, b | NVRCK); 2819 EEP_WAIT(); 2820 } 2821 2822 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2823 } 2824