1 /* $NetBSD: ihareg.h,v 1.3 2001/11/17 21:26:12 tsutsui Exp $ */ 2 /* 3 * Initio INI-9xxxU/UW SCSI Device Driver 4 * 5 * Copyright (c) 2000 Ken Westerback 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer, 13 * without modification, immediately at the beginning of the file. 14 * 2. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 21 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 22 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 23 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 25 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 26 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 *------------------------------------------------------------------------- 30 * 31 * Ported from i91uscsi.h, provided by Initio Corporation, which probably 32 * came from the same people who provided i91u.c: 33 * 34 * Device driver for the INI-9XXXU/UW or INIC-940/950 PCI SCSI Controller. 35 * 36 * FreeBSD 37 * 38 * Written for 386bsd and FreeBSD by 39 * Winston Hung <winstonh@initio.com> 40 * 41 * Copyright (c) 1997-99 Initio Corp. All rights reserved. 42 * 43 *------------------------------------------------------------------------- 44 */ 45 46 /* 47 * Ported to NetBSD by Izumi Tsutsui <tsutsui@ceres.dti.ne.jp> from OpenBSD: 48 * $OpenBSD: iha.h,v 1.2 2001/02/08 17:35:05 krw Exp $ 49 */ 50 51 /* 52 * Tulip (aka inic-940/950) PCI Configuration Space Initio Specific Registers 53 * 54 * Offsets 0x00 through 0x3f are the standard PCI Configuration Header 55 * registers. 56 * 57 * Offsets 0x40 through 0x4f, 0x51, 0x53, 0x57, 0x5b, 0x5e and 0x5f are 58 * reserved registers. 59 * 60 * Registers 0x50 and 0x52 always read as 0. 61 * 62 * The register offset names and associated bit field names are taken 63 * from the Inic-950 Data Sheet, Version 2.1, March 1997 64 */ 65 #define TUL_GCTRL0 0x54 /* R/W Global Control 0 */ 66 #define EEPRG 0x04 /* Enable EEPROM Programming */ 67 #define TUL_GCTRL1 0x55 /* R/W Global Control 1 */ 68 #define ATDEN 0x01 /* Auto Termination Detect Enable */ 69 #define TUL_GSTAT 0x56 /* R/W Global Status - connector type */ 70 #define TUL_EPAD0 0x58 /* R/W External EEPROM Addr (lo byte) */ 71 #define TUL_EPAD1 0x59 /* R/W External EEPROM Addr (hi byte) */ 72 #define TUL_PNVPG 0x5A /* R/W Data port to external BIOS */ 73 #define TUL_EPDATA 0x5C /* R/W EEPROM Data port */ 74 #define TUL_NVRAM 0x5D /* R/W Non-volatile RAM port */ 75 #define READ 0x80 /* Read from given NVRAM addr */ 76 #define WRITE 0x40 /* Write to given NVRAM addr */ 77 #define ENABLE_ERASE 0x30 /* Enable NVRAM Erase/Write */ 78 #define NVRCS 0x08 /* Select external NVRAM */ 79 #define NVRCK 0x04 /* NVRAM Clock */ 80 #define NVRDO 0x02 /* NVRAM Write Data */ 81 #define NVRDI 0x01 /* NVRAM Read Data */ 82 83 /* 84 * Tulip (aka inic-940/950) SCSI Registers 85 */ 86 #define TUL_STCNT0 0x80 /* R/W 24 bit SCSI Xfer Count */ 87 #define TCNT 0x00ffffff /* SCSI Xfer Transfer Count */ 88 #define TUL_SFIFOCNT 0x83 /* R/W 5 bit FIFO counter */ 89 #define FIFOC 0x1f /* SCSI Offset Fifo Count */ 90 #define TUL_SISTAT 0x84 /* R Interrupt Register */ 91 #define RSELED 0x80 /* Reselected */ 92 #define STIMEO 0x40 /* Selected/Reselected Timeout */ 93 #define SBSRV 0x20 /* SCSI Bus Service */ 94 #define SRSTD 0x10 /* SCSI Reset Detected */ 95 #define DISCD 0x08 /* Disconnected Status */ 96 #define SELED 0x04 /* Select Interrupt */ 97 #define SCAMSCT 0x02 /* SCAM selected */ 98 #define SCMDN 0x01 /* Command Complete */ 99 #define TUL_SIEN 0x84 /* W Interrupt enable */ 100 #define ALL_INTERRUPTS 0xff 101 #define TUL_STAT0 0x85 /* R Status 0 */ 102 #define INTPD 0x80 /* Interrupt pending */ 103 #define SQACT 0x40 /* Sequencer active */ 104 #define XFCZ 0x20 /* Xfer counter zero */ 105 #define SFEMP 0x10 /* FIFO empty */ 106 #define SPERR 0x08 /* SCSI parity error */ 107 #define PH_MASK 0x07 /* SCSI phase mask */ 108 #define TUL_SCTRL0 0x85 /* W Control 0 */ 109 #define RSSQC 0x20 /* Reset sequence counter */ 110 #define RSFIFO 0x10 /* Flush FIFO */ 111 #define CMDAB 0x04 /* Abort command (sequence) */ 112 #define RSMOD 0x02 /* Reset SCSI Chip */ 113 #define RSCSI 0x01 /* Reset SCSI Bus */ 114 #define TUL_STAT1 0x86 /* R Status 1 */ 115 #define STRCV 0x80 /* Status received */ 116 #define MSGST 0x40 /* Message sent */ 117 #define CPDNE 0x20 /* Data phase done */ 118 #define DPHDN 0x10 /* Data phase done */ 119 #define STSNT 0x08 /* Status sent */ 120 #define SXCMP 0x04 /* Xfer completed */ 121 #define SLCMP 0x02 /* Selection completed */ 122 #define ARBCMP 0x01 /* Arbitration completed */ 123 #define TUL_SCTRL1 0x86 /* W Control 1 */ 124 #define ENSCAM 0x80 /* Enable SCAM */ 125 #define NIDARB 0x40 /* No ID for Arbitration */ 126 #define ENLRS 0x20 /* Low Level Reselect */ 127 #define PWDN 0x10 /* Power down mode */ 128 #define WCPU 0x08 /* Wide CPU */ 129 #define EHRSL 0x04 /* Enable HW reselect */ 130 #define ESBUSOUT 0x02 /* Enable SCSI data bus out latch */ 131 #define ESBUSIN 0x01 /* Enable SCSI data bus in latch */ 132 #define TUL_SSTATUS2 0x87 /* R Status 2 */ 133 #define SABRT 0x80 /* Command aborted */ 134 #define OSCZ 0x40 /* Offset counter zero */ 135 #define SFFUL 0x20 /* FIFO full */ 136 #define TMCZ 0x10 /* Timeout counter zero */ 137 #define BSYGN 0x08 /* Busy release */ 138 #define PHMIS 0x04 /* Phase mismatch */ 139 #define SBEN 0x02 /* SCSI data bus enable */ 140 #define SRST 0x01 /* SCSI bus reset in progress */ 141 #define TUL_SCONFIG0 0x87 /* W Configuration */ 142 #define PHLAT 0x80 /* Enable phase latch */ 143 #define ITMOD 0x40 /* Initiator mode */ 144 #define SPCHK 0x20 /* Enable SCSI parity */ 145 #define ADMA8 0x10 /* Alternate dma 8-bits mode */ 146 #define ADMAW 0x08 /* Alternate dma 16-bits mode */ 147 #define EDACK 0x04 /* Enable DACK in wide SCSI xfer */ 148 #define ALTPD 0x02 /* Alternate sync period mode */ 149 #define DSRST 0x01 /* Disable SCSI Reset signal */ 150 #define SCONFIG0DEFAULT (PHLAT | ITMOD | ALTPD | DSRST) 151 #define TUL_SOFSC 0x88 /* R Offset */ 152 #define PERIOD_WIDE_SCSI 0x80 /* Enable Wide SCSI */ 153 #define PERIOD_SYXPD 0x70 /* Synch. SCSI Xfer rate */ 154 #define PERIOD_SYOFS 0x0f /* Synch. SCSI Offset */ 155 #define TUL_SYNCM 0x88 /* W Sync. Xfer Period & Offset */ 156 #define TUL_SBID 0x89 /* R SCSI BUS ID */ 157 #define TUL_SID 0x89 /* W SCSI ID */ 158 #define TUL_SALVC 0x8A /* R FIFO Avail Cnt/Identify Msg */ 159 #define MSG_IDENTIFY_LUNMASK 0x07 160 #define TUL_STIMO 0x8A /* W Sel/Resel Time Out Register */ 161 #define STIMO_250MS 153 /* in units of 1.6385us */ 162 #define TUL_SDATI 0x8B /* R SCSI Bus contents */ 163 #define TUL_SDAT0 0x8B /* W SCSI Data Out */ 164 #define TUL_SFIFO 0x8C /* R/W FIFO */ 165 #define TUL_SSIGI 0x90 /* R SCSI signal in */ 166 #define REQ 0x80 /* REQ signal */ 167 #define ACK 0x40 /* ACK signal */ 168 #define BSY 0x20 /* BSY signal */ 169 #define SEL 0x10 /* SEL signal */ 170 #define ATN 0x08 /* ATN signal */ 171 #define MSG 0x04 /* MSG signal */ 172 #define CD 0x02 /* C/D signal */ 173 #define IO 0x01 /* I/O signal */ 174 #define TUL_SSIGO 0x90 /* W SCSI signal out */ 175 #define TUL_SCMD 0x91 /* R/W SCSI Command */ 176 #define NO_OP 0x00 /* Place Holder for tulip_wait() */ 177 #define SEL_NOATN 0x01 /* Select w/o ATN Sequence */ 178 #define XF_FIFO_OUT 0x03 /* FIFO Xfer Infomation out */ 179 #define MSG_ACCEPT 0x0F /* Message Accept */ 180 #define SEL_ATN 0x11 /* Select w ATN Sequence */ 181 #define SEL_ATNSTOP 0x12 /* Select w ATN & Stop Sequence */ 182 #define SELATNSTOP 0x1E /* Select w ATN & Stop Sequence */ 183 #define SEL_ATN3 0x31 /* Select w ATN3 Sequence */ 184 #define XF_DMA_OUT 0x43 /* DMA Xfer Infomation out */ 185 #define EN_RESEL 0x80 /* Enable Reselection */ 186 #define XF_FIFO_IN 0x83 /* FIFO Xfer Infomation in */ 187 #define CMD_COMP 0x84 /* Command Complete Sequence */ 188 #define XF_DMA_IN 0xC3 /* DMA Xfer Infomation in */ 189 #define TUL_STEST0 0x92 /* R/W Test0 */ 190 #define TUL_STEST1 0x93 /* R/W Test1 */ 191 192 /* 193 * Tulip (aka inic-940/950) DMA Registers 194 */ 195 #define TUL_DXPA 0xC0 /* R/W DMA Xfer Physcl Addr 0-31*/ 196 #define TUL_DXPAE 0xC4 /* R/W DMA Xfer Physcl Addr 32-63*/ 197 #define TUL_DCXA 0xC8 /* R DMA Curr Xfer Physcl Addr 0-31*/ 198 #define TUL_DCXAE 0xCC /* R DMA Curr Xfer Physcl Addr 32-63*/ 199 #define TUL_DXC 0xD0 /* R/W DMA Xfer Counter */ 200 #define TUL_DCXC 0xD4 /* R DMA Current Xfer Counter */ 201 #define TUL_DCMD 0xD8 /* R/W DMA Command Register */ 202 #define SGXFR 0x80 /* Scatter/Gather Xfer */ 203 #define RSVD 0x40 /* Reserved - always reads as 0 */ 204 #define XDIR 0x20 /* Xfer Direction 0/1 = out/in */ 205 #define BMTST 0x10 /* Bus Master Test */ 206 #define CLFIFO 0x08 /* Clear FIFO */ 207 #define ABTXFR 0x04 /* Abort Xfer */ 208 #define FRXFR 0x02 /* Force Xfer */ 209 #define STRXFR 0x01 /* Start Xfer */ 210 #define TUL_ISTUS0 0xDC /* R/W Interrupt Status Register */ 211 #define DGINT 0x80 /* DMA Global Interrupt */ 212 #define RSVRD0 0x40 /* Reserved */ 213 #define RSVRD1 0x20 /* Reserved */ 214 #define SCMP 0x10 /* SCSI Complete */ 215 #define PXERR 0x08 /* PCI Xfer Error */ 216 #define DABT 0x04 /* DMA Xfer Aborted */ 217 #define FXCMP 0x02 /* Forced Xfer Complete */ 218 #define XCMP 0x01 /* Bus Master Xfer Complete */ 219 #define TUL_ISTUS1 0xDD /* R DMA status Register */ 220 #define SCBSY 0x08 /* SCSI Busy */ 221 #define FFULL 0x04 /* FIFO Full */ 222 #define FEMPT 0x02 /* FIFO Empty */ 223 #define XPEND 0x01 /* Xfer pending */ 224 #define TUL_IMSK 0xE0 /* R/W Interrupt Mask Register */ 225 #define MSCMP 0x10 /* Mask SCSI Complete */ 226 #define MPXFER 0x08 /* Mask PCI Xfer Error */ 227 #define MDABT 0x04 /* Mask Bus Master Abort */ 228 #define MFCMP 0x02 /* Mask Force Xfer Complete */ 229 #define MXCMP 0x01 /* Mask Bus Master Xfer Complete */ 230 #define MASK_ALL (MXCMP | MFCMP | MDABT | MPXFER | MSCMP) 231 #define TUL_DCTRL0 0xE4 /* R/W DMA Control Register */ 232 #define SXSTP 0x80 /* SCSI Xfer Stop */ 233 #define RPMOD 0x40 /* Reset PCI Module */ 234 #define RSVRD2 0x20 /* SCSI Xfer Stop */ 235 #define PWDWN 0x10 /* Power Down */ 236 #define ENTM 0x08 /* Enable SCSI Terminator Low */ 237 #define ENTMW 0x04 /* Enable SCSI Terminator High */ 238 #define DISAFC 0x02 /* Disable Auto Clear */ 239 #define LEDCTL 0x01 /* LED Control */ 240 #define TUL_DCTRL1 0xE5 /* R/W DMA Control Register 1 */ 241 #define SDWS 0x01 /* SCSI DMA Wait State */ 242 #define TUL_DFIFO 0xE8 /* R/W DMA FIFO */ 243 244 #define TUL_WCTRL 0xF7 /* ?/? Bus master wait state control */ 245 #define TUL_DCTRL 0xFB /* ?/? DMA delay control */ 246