xref: /netbsd/sys/dev/ic/intersil7170.c (revision ce099b40)
1*ce099b40Smartin /*	$NetBSD: intersil7170.c,v 1.12 2008/04/28 20:23:50 martin Exp $ */
24ba0c6b5Spk /*-
34ba0c6b5Spk  * Copyright (c) 2000 The NetBSD Foundation, Inc.
44ba0c6b5Spk  * All rights reserved.
54ba0c6b5Spk  *
64ba0c6b5Spk  * This code is derived from software contributed to The NetBSD Foundation
74ba0c6b5Spk  * by Paul Kranenburg.
84ba0c6b5Spk  *
94ba0c6b5Spk  * Redistribution and use in source and binary forms, with or without
104ba0c6b5Spk  * modification, are permitted provided that the following conditions
114ba0c6b5Spk  * are met:
124ba0c6b5Spk  * 1. Redistributions of source code must retain the above copyright
134ba0c6b5Spk  *    notice, this list of conditions and the following disclaimer.
144ba0c6b5Spk  * 2. Redistributions in binary form must reproduce the above copyright
154ba0c6b5Spk  *    notice, this list of conditions and the following disclaimer in the
164ba0c6b5Spk  *    documentation and/or other materials provided with the distribution.
174ba0c6b5Spk  *
184ba0c6b5Spk  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
194ba0c6b5Spk  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
204ba0c6b5Spk  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
214ba0c6b5Spk  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
224ba0c6b5Spk  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
234ba0c6b5Spk  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
244ba0c6b5Spk  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
254ba0c6b5Spk  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
264ba0c6b5Spk  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
274ba0c6b5Spk  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
284ba0c6b5Spk  * POSSIBILITY OF SUCH DAMAGE.
294ba0c6b5Spk  */
304ba0c6b5Spk 
314ba0c6b5Spk /*
324ba0c6b5Spk  * Intersil 7170 time-of-day chip subroutines.
334ba0c6b5Spk  */
344ba0c6b5Spk 
35a4bae8b0Slukem #include <sys/cdefs.h>
36*ce099b40Smartin __KERNEL_RCSID(0, "$NetBSD: intersil7170.c,v 1.12 2008/04/28 20:23:50 martin Exp $");
37a4bae8b0Slukem 
384ba0c6b5Spk #include <sys/param.h>
394ba0c6b5Spk #include <sys/malloc.h>
404ba0c6b5Spk #include <sys/systm.h>
412f49bc32Stsutsui #include <sys/device.h>
424ba0c6b5Spk #include <sys/errno.h>
434ba0c6b5Spk 
44a2a38285Sad #include <sys/bus.h>
454ba0c6b5Spk #include <dev/clock_subr.h>
462f49bc32Stsutsui #include <dev/ic/intersil7170reg.h>
472f49bc32Stsutsui #include <dev/ic/intersil7170var.h>
484ba0c6b5Spk 
491a001de3Sgdamore int intersil7170_gettime_ymdhms(todr_chip_handle_t, struct clock_ymdhms *);
501a001de3Sgdamore int intersil7170_settime_ymdhms(todr_chip_handle_t, struct clock_ymdhms *);
514ba0c6b5Spk 
522f49bc32Stsutsui void
intersil7170_attach(struct intersil7170_softc * sc)532f49bc32Stsutsui intersil7170_attach(struct intersil7170_softc *sc)
544ba0c6b5Spk {
554ba0c6b5Spk 	todr_chip_handle_t handle;
564ba0c6b5Spk 
5757e50507Stsutsui 	aprint_normal(": intersil7170");
584ba0c6b5Spk 
592f49bc32Stsutsui 	handle = &sc->sc_handle;
602f49bc32Stsutsui 
612f49bc32Stsutsui 	handle->cookie = sc;
621a001de3Sgdamore 	handle->todr_gettime = NULL;
631a001de3Sgdamore 	handle->todr_settime = NULL;
641a001de3Sgdamore 	handle->todr_gettime_ymdhms = intersil7170_gettime_ymdhms;
651a001de3Sgdamore 	handle->todr_settime_ymdhms = intersil7170_settime_ymdhms;
662f49bc32Stsutsui 	handle->todr_setwen = NULL;
67fba7c262Stsutsui 
68fba7c262Stsutsui 	todr_attach(handle);
694ba0c6b5Spk }
704ba0c6b5Spk 
714ba0c6b5Spk /*
724ba0c6b5Spk  * Set up the system's time, given a `reasonable' time value.
734ba0c6b5Spk  */
744ba0c6b5Spk int
intersil7170_gettime_ymdhms(todr_chip_handle_t handle,struct clock_ymdhms * dt)751a001de3Sgdamore intersil7170_gettime_ymdhms(todr_chip_handle_t handle, struct clock_ymdhms *dt)
764ba0c6b5Spk {
772f49bc32Stsutsui 	struct intersil7170_softc *sc = handle->cookie;
782f49bc32Stsutsui 	bus_space_tag_t bt = sc->sc_bst;
792f49bc32Stsutsui 	bus_space_handle_t bh = sc->sc_bsh;
802f49bc32Stsutsui 	uint8_t cmd;
814ba0c6b5Spk 	int year;
824ba0c6b5Spk 	int s;
834ba0c6b5Spk 
844ba0c6b5Spk 	/* No interrupts while we're fiddling with the chip */
854ba0c6b5Spk 	s = splhigh();
864ba0c6b5Spk 
874ba0c6b5Spk 	/* Enable read (stop time) */
882f49bc32Stsutsui 	cmd = INTERSIL_COMMAND(INTERSIL_CMD_STOP, INTERSIL_CMD_IENABLE);
894ba0c6b5Spk 	bus_space_write_1(bt, bh, INTERSIL_ICMD, cmd);
904ba0c6b5Spk 
914ba0c6b5Spk 	/* The order of reading out the clock elements is important */
922f49bc32Stsutsui 	(void)bus_space_read_1(bt, bh, INTERSIL_ICSEC);	/* not used */
931a001de3Sgdamore 	dt->dt_hour = bus_space_read_1(bt, bh, INTERSIL_IHOUR);
941a001de3Sgdamore 	dt->dt_min = bus_space_read_1(bt, bh, INTERSIL_IMIN);
951a001de3Sgdamore 	dt->dt_sec = bus_space_read_1(bt, bh, INTERSIL_ISEC);
961a001de3Sgdamore 	dt->dt_mon = bus_space_read_1(bt, bh, INTERSIL_IMON);
971a001de3Sgdamore 	dt->dt_day = bus_space_read_1(bt, bh, INTERSIL_IDAY);
984ba0c6b5Spk 	year = bus_space_read_1(bt, bh, INTERSIL_IYEAR);
991a001de3Sgdamore 	dt->dt_wday = bus_space_read_1(bt, bh, INTERSIL_IDOW);
1004ba0c6b5Spk 
1014ba0c6b5Spk 	/* Done writing (time wears on) */
1022f49bc32Stsutsui 	cmd = INTERSIL_COMMAND(INTERSIL_CMD_RUN, INTERSIL_CMD_IENABLE);
1034ba0c6b5Spk 	bus_space_write_1(bt, bh, INTERSIL_ICMD, cmd);
1044ba0c6b5Spk 	splx(s);
1054ba0c6b5Spk 
1062f49bc32Stsutsui 	year += sc->sc_year0;
1072f49bc32Stsutsui 	if (year < POSIX_BASE_YEAR &&
1082f49bc32Stsutsui 	    (sc->sc_flag & INTERSIL7170_NO_CENT_ADJUST) == 0)
1094ba0c6b5Spk 		year += 100;
1104ba0c6b5Spk 
1111a001de3Sgdamore 	dt->dt_year = year;
1124ba0c6b5Spk 
1132f49bc32Stsutsui 	return 0;
1144ba0c6b5Spk }
1154ba0c6b5Spk 
1164ba0c6b5Spk /*
1174ba0c6b5Spk  * Reset the clock based on the current time.
1184ba0c6b5Spk  */
1194ba0c6b5Spk int
intersil7170_settime_ymdhms(todr_chip_handle_t handle,struct clock_ymdhms * dt)1201a001de3Sgdamore intersil7170_settime_ymdhms(todr_chip_handle_t handle, struct clock_ymdhms *dt)
1214ba0c6b5Spk {
1222f49bc32Stsutsui 	struct intersil7170_softc *sc = handle->cookie;
1232f49bc32Stsutsui 	bus_space_tag_t bt = sc->sc_bst;
1242f49bc32Stsutsui 	bus_space_handle_t bh = sc->sc_bsh;
1252f49bc32Stsutsui 	uint8_t cmd;
1264ba0c6b5Spk 	int year;
1274ba0c6b5Spk 	int s;
1284ba0c6b5Spk 
1292f49bc32Stsutsui 	year = dt->dt_year - sc->sc_year0;
1302f49bc32Stsutsui 	if (year > 99 && (sc->sc_flag & INTERSIL7170_NO_CENT_ADJUST) == 0)
1314ba0c6b5Spk 		year -= 100;
1324ba0c6b5Spk 
1334ba0c6b5Spk 	/* No interrupts while we're fiddling with the chip */
1344ba0c6b5Spk 	s = splhigh();
1354ba0c6b5Spk 
1364ba0c6b5Spk 	/* Enable write (stop time) */
1372f49bc32Stsutsui 	cmd = INTERSIL_COMMAND(INTERSIL_CMD_STOP, INTERSIL_CMD_IENABLE);
1384ba0c6b5Spk 	bus_space_write_1(bt, bh, INTERSIL_ICMD, cmd);
1394ba0c6b5Spk 
1404ba0c6b5Spk 	/* The order of reading writing the clock elements is important */
1414ba0c6b5Spk 	bus_space_write_1(bt, bh, INTERSIL_ICSEC, 0);
1421a001de3Sgdamore 	bus_space_write_1(bt, bh, INTERSIL_IHOUR, dt->dt_hour);
1431a001de3Sgdamore 	bus_space_write_1(bt, bh, INTERSIL_IMIN, dt->dt_min);
1441a001de3Sgdamore 	bus_space_write_1(bt, bh, INTERSIL_ISEC, dt->dt_sec);
1451a001de3Sgdamore 	bus_space_write_1(bt, bh, INTERSIL_IMON, dt->dt_mon);
1461a001de3Sgdamore 	bus_space_write_1(bt, bh, INTERSIL_IDAY, dt->dt_day);
1474ba0c6b5Spk 	bus_space_write_1(bt, bh, INTERSIL_IYEAR, year);
1481a001de3Sgdamore 	bus_space_write_1(bt, bh, INTERSIL_IDOW, dt->dt_wday);
1494ba0c6b5Spk 
1504ba0c6b5Spk 	/* Done writing (time wears on) */
1512f49bc32Stsutsui 	cmd = INTERSIL_COMMAND(INTERSIL_CMD_RUN, INTERSIL_CMD_IENABLE);
1524ba0c6b5Spk 	bus_space_write_1(bt, bh, INTERSIL_ICMD, cmd);
1534ba0c6b5Spk 	splx(s);
1544ba0c6b5Spk 
1552f49bc32Stsutsui 	return 0;
1564ba0c6b5Spk }
157