1 /* $NetBSD: mb86960reg.h,v 1.4 2001/12/23 09:21:00 ichiro Exp $ */ 2 3 /* 4 * All Rights Reserved, Copyright (C) Fujitsu Limited 1995 5 * 6 * This software may be used, modified, copied, distributed, and sold, in 7 * both source and binary form provided that the above copyright, these 8 * terms and the following disclaimer are retained. The name of the author 9 * and/or the contributor may not be used to endorse or promote products 10 * derived from this software without specific prior written permission. 11 * 12 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND THE CONTRIBUTOR ``AS IS'' AND 13 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR THE CONTRIBUTOR BE LIABLE 16 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22 * SUCH DAMAGE. 23 */ 24 25 #define FE_MB86960_H_VERSION "mb86960.h ver. 0.8" 26 27 /* 28 * Registers of Fujitsu MB86960A/MB86965A Ethernet controller. 29 * Written and contributed by M.S. <seki@sysrap.cs.fujitsu.co.jp> 30 */ 31 32 /* 33 * Notes on register naming: 34 * 35 * Fujitsu documents for MB86960A/MB86965A uses no mnemorable names 36 * for their registers. They defined only three names for 32 37 * registers and appended numbers to distinguish registers of 38 * same name. Surprisingly, the numbers represent I/O address 39 * offsets of the registers from the base addresses, and their 40 * names correspond to the "bank" the registers are allocated. 41 * All this means that, for example, to say "read DLCR8" has no more 42 * than to say "read a register at offset 8 on bank DLCR." 43 * 44 * The following definitions may look silly, but that's what Fujitsu 45 * did, and it is necessary to know these names to read Fujitsu 46 * documents.. 47 */ 48 49 /* Data Link Control Registrs, on invaliant port addresses. */ 50 #define FE_DLCR0 0 51 #define FE_DLCR1 1 52 #define FE_DLCR2 2 53 #define FE_DLCR3 3 54 #define FE_DLCR4 4 55 #define FE_DLCR5 5 56 #define FE_DLCR6 6 57 #define FE_DLCR7 7 58 59 /* More DLCRs, on register bank #0. */ 60 #define FE_DLCR8 8 61 #define FE_DLCR9 9 62 #define FE_DLCR10 10 63 #define FE_DLCR11 11 64 #define FE_DLCR12 12 65 #define FE_DLCR13 13 66 #define FE_DLCR14 14 67 #define FE_DLCR15 15 68 69 /* Malticast Address Registers. On register bank #1. */ 70 #define FE_MAR8 8 71 #define FE_MAR9 9 72 #define FE_MAR10 10 73 #define FE_MAR11 11 74 #define FE_MAR12 12 75 #define FE_MAR13 13 76 #define FE_MAR14 14 77 #define FE_MAR15 15 78 79 /* Buffer Memory Port Registers. On register bank #2. */ 80 #define FE_BMPR8 8 81 #define FE_BMPR9 9 82 #define FE_BMPR10 10 83 #define FE_BMPR11 11 84 #define FE_BMPR12 12 85 #define FE_BMPR13 13 86 #define FE_BMPR14 14 87 #define FE_BMPR15 15 88 89 /* More BMPRs, only on MB86965A, accessible only when JLI mode. */ 90 #define FE_BMPR16 16 91 #define FE_BMPR17 17 92 #define FE_BMPR18 18 93 #define FE_BMPR19 19 94 95 #define FE_RESET 31 96 97 /* 98 * Definitions of registers. 99 * I don't have Fujitsu documents of MB86960A/MB86965A, so I don't 100 * know the official names for each flags and fields. The following 101 * names are assigned by me (the author of this file,) since I cannot 102 * mnemorize hexadecimal constants for all of these functions. 103 * Comments? FIXME. 104 */ 105 106 /* DLCR0 -- transmitter status */ 107 #define FE_D0_BUSERR 0x01 /* Bus write error */ 108 #define FE_D0_COLL16 0x02 /* Collision limit (16) encountered */ 109 #define FE_D0_COLLID 0x04 /* Collision on last transmission */ 110 #define FE_D0_JABBER 0x08 /* Jabber */ 111 #define FE_D0_CRLOST 0x10 /* Carrier lost on last transmission */ 112 #define FE_D0_PKTRCD 0x20 /* No corrision on last transmission */ 113 #define FE_D0_NETBSY 0x40 /* Network Busy (Carrier Detected) */ 114 #define FE_D0_TXDONE 0x80 /* Transmission complete */ 115 116 /* DLCR1 -- receiver status */ 117 #define FE_D1_OVRFLO 0x01 /* Receiver buffer overflow */ 118 #define FE_D1_CRCERR 0x02 /* CRC error on last packet */ 119 #define FE_D1_ALGERR 0x04 /* Alignment error on last packet */ 120 #define FE_D1_SRTPKT 0x08 /* Short (RUNT) packet is received */ 121 #define FE_D1_RMTRST 0x10 /* Remote reset packet (type = 0x0900) */ 122 #define FE_D1_DMAEOP 0x20 /* Host asserted End of DMA OPeration */ 123 #define FE_D1_BUSERR 0x40 /* Bus read error */ 124 #define FE_D1_PKTRDY 0x80 /* Packet(s) ready on receive buffer */ 125 126 #define FE_D1_ERRBITS "\20\4SRTPKT\3ALGERR\2CRCERR\1OVRFLO" 127 128 /* DLCR2 -- transmitter interrupt control; same layout as DLCR0 */ 129 #define FE_D2_BUSERR FE_D0_BUSERR 130 #define FE_D2_COLL16 FE_D0_COLL16 131 #define FE_D2_COLLID FE_D0_COLLID 132 #define FE_D2_JABBER FE_D0_JABBER 133 #define FE_D2_TXDONE FE_D0_TXDONE 134 135 #define FE_D2_RESERVED 0x70 136 137 /* DLCR3 -- receiver interrupt control; same layout as DLCR1 */ 138 #define FE_D3_OVRFLO FE_D1_OVRFLO 139 #define FE_D3_CRCERR FE_D1_CRCERR 140 #define FE_D3_ALGERR FE_D1_ALGERR 141 #define FE_D3_SRTPKT FE_D1_SRTPKT 142 #define FE_D3_RMTRST FE_D1_RMTRST 143 #define FE_D3_DMAEOP FE_D1_DMAEOP 144 #define FE_D3_BUSERR FE_D1_BUSERR 145 #define FE_D3_PKTRDY FE_D1_PKTRDY 146 147 /* DLCR4 -- transmitter operation mode */ 148 #define FE_D4_DSC 0x01 /* Disable carrier sense on trans. */ 149 #define FE_D4_LBC 0x02 /* Loop back test control */ 150 #define FE_D4_CNTRL 0x04 /* - ??? */ 151 #define FE_D4_TEST1 0x08 /* Test output #1 */ 152 #define FE_D4_COL 0xF0 /* Collision counter */ 153 154 #define FE_D4_LBC_ENABLE 0x00 /* Perform loop back test */ 155 #define FE_D4_LBC_DISABLE 0x02 /* Normal operation */ 156 157 #define FE_D4_COL_SHIFT 4 158 159 /* DLCR5 -- receiver operation mode */ 160 #define FE_D5_AFM0 0x01 /* Receive packets for other stations */ 161 #define FE_D5_AFM1 0x02 /* Receive packets for this station */ 162 #define FE_D5_RMTRST 0x04 /* Enable remote reset operation */ 163 #define FE_D5_SRTPKT 0x08 /* Accept short (RUNT) packets */ 164 #define FE_D5_SRTADR 0x10 /* Short (16 bits?) MAC address */ 165 #define FE_D5_BADPKT 0x20 /* Accept packets with error */ 166 #define FE_D5_BUFEMP 0x40 /* Receive buffer is empty */ 167 #define FE_D5_TEST2 0x80 /* Test output #2 */ 168 169 /* DLCR6 -- hardware configuration #0 */ 170 #define FE_D6_BUFSIZ 0x03 /* Size of NIC buffer SRAM */ 171 #define FE_D6_TXBSIZ 0x0C /* Size (and config)of trans. buffer */ 172 #define FE_D6_BBW 0x10 /* Buffer SRAM bus width */ 173 #define FE_D6_SBW 0x20 /* System bus width */ 174 #define FE_D6_SRAM 0x40 /* Buffer SRAM access time */ 175 #define FE_D6_DLC 0x80 /* Disable DLC (recever/transmitter) */ 176 177 #define FE_D6_BUFSIZ_8KB 0x00 /* The board has 8KB SRAM */ 178 #define FE_D6_BUFSIZ_16KB 0x01 /* The board has 16KB SRAM */ 179 #define FE_D6_BUFSIZ_32KB 0x02 /* The board has 32KB SRAM */ 180 #define FE_D6_BUFSIZ_64KB 0x03 /* The board has 64KB SRAM */ 181 182 #define FE_D6_TXBSIZ_1x2KB 0x00 /* Single 2KB buffer for trans. */ 183 #define FE_D6_TXBSIZ_2x2KB 0x04 /* Double 2KB buffers */ 184 #define FE_D6_TXBSIZ_2x4KB 0x08 /* Double 4KB buffers */ 185 #define FE_D6_TXBSIZ_2x8KB 0x0C /* Double 8KB buffers */ 186 187 #define FE_D6_BBW_WORD 0x00 /* SRAM has 16 bit data line */ 188 #define FE_D6_BBW_BYTE 0x10 /* SRAM has 8 bit data line */ 189 190 #define FE_D6_SBW_WORD 0x00 /* Access with 16 bit (AT) bus */ 191 #define FE_D6_SBW_BYTE 0x20 /* Access with 8 bit (XT) bus */ 192 193 #define FE_D6_SRAM_150ns 0x00 /* The board has slow SRAM */ 194 #define FE_D6_SRAM_100ns 0x40 /* The board has fast SRAM */ 195 196 #define FE_D6_DLC_ENABLE 0x00 /* Normal operation */ 197 #define FE_D6_DLC_DISABLE 0x80 /* Stop sending/receiving */ 198 199 /* DLC7 -- hardware configuration #1 */ 200 #define FE_D7_BYTSWP 0x01 /* Host byte order control */ 201 #define FE_D7_EOPPOL 0x02 /* Polarity of DMA EOP signal */ 202 #define FE_D7_RBS 0x0C /* Register bank select */ 203 #define FE_D7_RDYPNS 0x10 /* Senses RDYPNSEL input signal */ 204 #define FE_D7_POWER 0x20 /* Stand-by (power down) mode control */ 205 #define FE_D7_IDENT 0xC0 /* Chip identification */ 206 207 #define FE_D7_BYTSWP_LH 0x00 /* DEC/Intel byte order */ 208 #define FE_D7_BYTSWP_HL 0x01 /* IBM/Motorolla byte order */ 209 210 #define FE_D7_RBS_DLCR 0x00 /* Select DLCR8-15 */ 211 #define FE_D7_RBS_MAR 0x04 /* Select MAR8-15 */ 212 #define FE_D7_RBS_BMPR 0x08 /* Select BMPR8-15 */ 213 214 #define FE_D7_POWER_DOWN 0x00 /* Power down (stand-by) mode */ 215 #define FE_D7_POWER_UP 0x20 /* Normal operation */ 216 217 #define FE_D7_IDENT_NICE 0x80 218 #define FE_D7_IDENT_EC 0xC0 219 220 /* DLCR8 thru DLCR13 are for Ethernet station address. */ 221 222 /* DLCR14 and DLCR15 are for TDR. (BTW, what is TDR? FIXME.) */ 223 224 /* MAR8 thru MAR15 are for Multicast address filter. */ 225 226 /* BMPR8 and BMPR9 are for packet data. */ 227 228 /* BMPR10 -- transmitter start trigger */ 229 #define FE_B10_START 0x80 /* Start transmitter */ 230 #define FE_B10_COUNT 0x7F /* Packet count */ 231 232 /* BMPR11 -- 16 collisions control */ 233 #define FE_B11_CTRL 0x01 /* Skip or resend errored packets */ 234 #define FE_B11_MODE1 0x02 /* Restart transmitter after COLL16 */ 235 #define FE_B11_MODE2 0x04 /* Automatic restart enable */ 236 237 #define FE_B11_CTRL_RESEND 0x00 /* Re-send the collided packet */ 238 #define FE_B11_CTRL_SKIP 0x01 /* Skip the collided packet */ 239 240 /* BMPR12 -- DMA enable */ 241 #define FE_B12_TXDMA 0x01 /* Enable transmitter DMA */ 242 #define FE_B12_RXDMA 0x02 /* Enable receiver DMA */ 243 244 /* BMPR13 -- DMA control */ 245 #define FE_B13_BSTCTL 0x03 /* DMA burst mode control */ 246 #define FE_B13_TPTYPE 0x04 /* Twisted pair cable impedance */ 247 #define FE_B13_PORT 0x18 /* Port (TP/AUI) selection */ 248 #define FE_B13_LNKTST 0x20 /* Link test enable */ 249 #define FE_B13_SQTHLD 0x40 /* Lower squelch threshold */ 250 #define FE_B13_IOUNLK 0x80 /* Change I/O base address */ 251 252 #define FE_B13_BSTCTL_1 0x00 253 #define FE_B13_BSTCTL_4 0x01 254 #define FE_B13_BSTCTL_8 0x02 255 #define FE_B13_BSTCLT_12 0x03 256 257 #define FE_B13_TPTYPE_UTP 0x00 /* Unshielded (standard) cable */ 258 #define FE_B13_TPTYPE_STP 0x04 /* Shielded (IBM) cable */ 259 260 #define FE_B13_PORT_AUTO 0x00 /* Auto detected */ 261 #define FE_B13_PORT_TP 0x08 /* Force TP */ 262 #define FE_B13_PORT_AUI 0x18 /* Force AUI */ 263 264 /* BMPR14 -- More receiver control and more transmission interrupts */ 265 #define FE_B14_FILTER 0x01 /* Filter out self-originated packets */ 266 #define FE_B14_SQE 0x02 /* SQE interrupt enable */ 267 #define FE_B14_SKIP 0x04 /* Skip a received packet */ 268 #define FE_B14_RJAB 0x20 /* RJAB interrupt enable */ 269 #define FE_B14_LLD 0x40 /* Local-link-down interrupt enable */ 270 #define FE_B14_RLD 0x80 /* Remote-link-down interrupt enable */ 271 272 /* BMPR15 -- More transmitter status; basically same layout as BMPR14 */ 273 #define FE_B15_SQE FE_B14_SQE 274 #define FE_B15_RCVPOL 0x08 /* Reversed receive line polarity */ 275 #define FE_B15_RMTPRT 0x10 /* ??? */ 276 #define FE_B15_RAJB FE_B14_RJAB 277 #define FE_B15_LLD FE_B14_LLD 278 #define FE_B15_RLD FE_B14_RLD 279 280 /* BMPR16 -- EEPROM control */ 281 #define FE_B16_DOUT 0x04 /* EEPROM Data in (CPU to EEPROM) */ 282 #define FE_B16_SELECT 0x20 /* EEPROM chip select */ 283 #define FE_B16_CLOCK 0x40 /* EEPROM shift clock */ 284 #define FE_B16_DIN 0x80 /* EEPROM data out (EEPROM to CPU) */ 285 286 /* BMPR17 -- EEPROM data */ 287 #define FE_B17_DATA 0x80 /* EEPROM data bit */ 288 289 /* BMPR18 ??? */ 290 291 /* BMPR19 -- ISA interface configuration */ 292 #define FE_B19_IRQ 0xC0 293 #define FE_B19_IRQ_SHIFT 6 294 295 #define FE_B19_ROM 0x38 296 #define FE_B19_ROM_SHIFT 3 297 298 #define FE_B19_ADDR 0x07 299 #define FE_B19_ADDR_SHIFT 0 300 301 /* 302 * EEPROM specification (of JLI mode). 303 */ 304 305 /* Number of bytes in an EEPROM accessible through 86965. */ 306 #define FE_EEPROM_SIZE 32 307 308 /* Offset for JLI config; automatically copied into BMPR19 at startup. */ 309 #define FE_EEPROM_CONF 0 310 311 /* 312 * Some 86960 specific constants. 313 */ 314 315 /* Length (in bytes) of a Multicast Address Filter. */ 316 #define FE_FILTER_LEN 8 317 318 /* How many packets we can put in the transmission buffer on NIC memory. */ 319 #define FE_QUEUEING_MAX 127 320 321 /* Length (in bytes) of a "packet length" word in transmission buffer. */ 322 #define FE_DATA_LEN_LEN 2 323 324 /* 325 * FUJITSU MBH10302 specific Registers. 326 */ 327 328 #define FE_MBH0 0x10 /* Master interrupt register */ 329 #define FE_MBH_ENADDR 0x1A /* Mac address */ 330 #define FE_MBH0_MASK 0x0D 331 #define FE_MBH0_INTR_ENABLE 0x10 /* Enable interrupts */ 332