1 /* $NetBSD: mc146818reg.h,v 1.2 1997/03/12 06:53:42 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Permission to use, copy, modify and distribute this software and 8 * its documentation is hereby granted, provided that both the copyright 9 * notice and this permission notice appear in all copies of the 10 * software, derivative works or modified versions, and any portions 11 * thereof, and that both notices appear in supporting documentation. 12 * 13 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 14 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 15 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 16 * 17 * Carnegie Mellon requests users of this software to return to 18 * 19 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 20 * School of Computer Science 21 * Carnegie Mellon University 22 * Pittsburgh PA 15213-3890 23 * 24 * any improvements or extensions that they make and grant Carnegie the 25 * rights to redistribute these changes. 26 */ 27 28 /* 29 * Definitions for the Motorola MC146818A Real Time Clock. 30 * They also apply for the (compatible) Dallas Semicontuctor DS1287A RTC. 31 * 32 * Though there are undoubtedly other (better) sources, this material was 33 * culled from the DEC "KN121 System Module Programmer's Reference 34 * Information." 35 * 36 * The MC146818A has 16 registers. The first 10 contain time-of-year 37 * and alarm data. The rest contain various control and status bits. 38 * 39 * To read or write the registers, one writes the register number to 40 * the RTC's control port, then either reads from or writes the new 41 * data to the RTC's data port. Since the locations of these ports 42 * and the method used to access them can be machine-dependent, the 43 * low-level details of reading and writing the RTC's registers are 44 * handled by machine-specific functions. 45 * 46 * The time-of-year and alarm data can be expressed in either binary 47 * or BCD, and they are selected by a bit in register B. 48 * 49 * The "hour" time-of-year and alarm fields can either be expressed in 50 * AM/PM format, or in 24-hour format. If AM/PM format is chosen, the 51 * hour fields can have the values: 1-12 and 81-92 (the latter being 52 * PM). If the 24-hour format is chosen, they can have the values 53 * 0-24. The hour format is selectable by a bit in register B. 54 * (XXX IS AM/PM MODE DESCRIPTION CORRECT?) 55 * 56 * It is assumed the if systems are going to use BCD (rather than 57 * binary) mode, or AM/PM hour format, they'll do the appropriate 58 * conversions in machine-dependent code. Also, if the clock is 59 * switched between BCD and binary mode, or between AM/PM mode and 60 * 24-hour mode, the time-of-day and alarm registers are NOT 61 * automatically reset; they must be reprogrammed with correct values. 62 */ 63 64 /* 65 * The registers, and the bits within each register. 66 */ 67 68 #define MC_SEC 0x0 /* Time of year: seconds (0-59) */ 69 #define MC_ASEC 0x1 /* Alarm: seconds */ 70 #define MC_MIN 0x2 /* Time of year: minutes (0-59) */ 71 #define MC_AMIN 0x3 /* Alarm: minutes */ 72 #define MC_HOUR 0x4 /* Time of year: hour (see above) */ 73 #define MC_AHOUR 0x5 /* Alarm: hour */ 74 #define MC_DOW 0x6 /* Time of year: day of week (1-7) */ 75 #define MC_DOM 0x7 /* Time of year: day of month (1-31) */ 76 #define MC_MONTH 0x8 /* Time of year: month (1-12) */ 77 #define MC_YEAR 0x9 /* Time of year: year in century (0-99) */ 78 79 #define MC_REGA 0xa /* Control register A */ 80 81 #define MC_REGA_RSMASK 0x0f /* Interrupt rate select mask (see below) */ 82 #define MC_REGA_DVMASK 0x70 /* Divisor select mask (see below) */ 83 #define MC_REGA_UIP 0x80 /* Update in progress; read only. */ 84 85 #define MC_REGB 0xb /* Control register B */ 86 87 #define MC_REGB_DSE 0x01 /* Daylight Savings Enable */ 88 #define MC_REGB_24HR 0x02 /* 24-hour mode (AM/PM mode when clear) */ 89 #define MC_REGB_BINARY 0x04 /* Binary mode (BCD mode when clear) */ 90 #define MC_REGB_SQWE 0x08 /* Square Wave Enable */ 91 #define MC_REGB_UIE 0x10 /* Update End interrupt enable */ 92 #define MC_REGB_AIE 0x20 /* Alarm interrupt enable */ 93 #define MC_REGB_PIE 0x40 /* Periodic interrupt enable */ 94 #define MC_REGB_SET 0x80 /* Allow time to be set; stops updates */ 95 96 #define MC_REGC 0xc /* Control register C */ 97 98 /* MC_REGC_UNUSED 0x0f UNUSED */ 99 #define MC_REGC_UF 0x10 /* Update End interrupt flag */ 100 #define MC_REGC_AF 0x20 /* Alarm interrupt flag */ 101 #define MC_REGC_PF 0x40 /* Periodic interrupt flag */ 102 #define MC_REGC_IRQF 0x80 /* Interrupt request pending flag */ 103 104 #define MC_REGD 0xd /* Control register D */ 105 106 /* MC_REGD_UNUSED 0x7f UNUSED */ 107 #define MC_REGD_VRT 0x80 /* Valid RAM and Time bit */ 108 109 110 #define MC_NREGS 0xe /* 14 registers; CMOS follows */ 111 #define MC_NTODREGS 0xa /* 10 of those regs are for TOD and alarm */ 112 113 #define MC_NVRAM_START 0xe /* start of NVRAM: offset 14 */ 114 #define MC_NVRAM_SIZE 50 /* 50 bytes of NVRAM */ 115 116 /* 117 * Periodic Interrupt Rate Select constants (Control register A) 118 */ 119 #define MC_RATE_NONE 0x0 /* No periodic interrupt */ 120 #define MC_RATE_1 0x1 /* 256 Hz if MC_BASE_32_KHz, else 32768 Hz */ 121 #define MC_RATE_2 0x2 /* 128 Hz if MC_BASE_32_KHz, else 16384 Hz */ 122 #define MC_RATE_8192_Hz 0x3 /* 122.070 us period */ 123 #define MC_RATE_4096_Hz 0x4 /* 244.141 us period */ 124 #define MC_RATE_2048_Hz 0x5 /* 488.281 us period */ 125 #define MC_RATE_1024_Hz 0x6 /* 976.562 us period */ 126 #define MC_RATE_512_Hz 0x7 /* 1.953125 ms period */ 127 #define MC_RATE_256_Hz 0x8 /* 3.90625 ms period */ 128 #define MC_RATE_128_Hz 0x9 /* 7.8125 ms period */ 129 #define MC_RATE_64_Hz 0xa /* 15.625 ms period */ 130 #define MC_RATE_32_Hz 0xb /* 31.25 ms period */ 131 #define MC_RATE_16_Hz 0xc /* 62.5 ms period */ 132 #define MC_RATE_8_Hz 0xd /* 125 ms period */ 133 #define MC_RATE_4_Hz 0xe /* 250 ms period */ 134 #define MC_RATE_2_Hz 0xf /* 500 ms period */ 135 136 /* 137 * Time base (divisor select) constants (Control register A) 138 */ 139 #define MC_BASE_4_MHz 0x00 /* 4MHz crystal */ 140 #define MC_BASE_1_MHz 0x10 /* 1MHz crystal */ 141 #define MC_BASE_32_KHz 0x20 /* 32KHz crystal */ 142 #define MC_BASE_NONE 0x60 /* actually, both of these reset */ 143 #define MC_BASE_RESET 0x70 144 145 146 /* 147 * RTC register/NVRAM read and write functions -- machine-dependent. 148 * Appropriately manipulate RTC registers to get/put data values. 149 */ 150 u_int mc146818_read __P((void *sc, u_int reg)); 151 void mc146818_write __P((void *sc, u_int reg, u_int datum)); 152 153 /* 154 * A collection of TOD/Alarm registers. 155 */ 156 typedef u_int mc_todregs[MC_NTODREGS]; 157 158 /* 159 * Get all of the TOD/Alarm registers 160 * Must be called at splhigh(), and with the RTC properly set up. 161 */ 162 #define MC146818_GETTOD(sc, regs) \ 163 do { \ 164 int i; \ 165 \ 166 /* update in progress; spin loop */ \ 167 while (mc146818_read(sc, MC_REGA) & MC_REGA_UIP) \ 168 ; \ 169 \ 170 /* read all of the tod/alarm regs */ \ 171 for (i = 0; i < MC_NTODREGS; i++) \ 172 (*regs)[i] = mc146818_read(sc, i); \ 173 } while (0); 174 175 /* 176 * Set all of the TOD/Alarm registers 177 * Must be called at splhigh(), and with the RTC properly set up. 178 */ 179 #define MC146818_PUTTOD(sc, regs) \ 180 do { \ 181 int i; \ 182 \ 183 /* stop updates while setting */ \ 184 mc146818_write(sc, MC_REGB, \ 185 mc146818_read(sc, MC_REGB) | MC_REGB_SET); \ 186 \ 187 /* write all of the tod/alarm regs */ \ 188 for (i = 0; i < MC_NTODREGS; i++) \ 189 mc146818_write(sc, i, (*regs)[i]); \ 190 \ 191 /* reenable updates */ \ 192 mc146818_write(sc, MC_REGB, \ 193 mc146818_read(sc, MC_REGB) & ~MC_REGB_SET); \ 194 } while (0); 195