1 /* $NetBSD: ncr53c400reg.h,v 1.2 2008/04/28 20:23:50 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by John M. Ruschmeyer. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Definitions for 53C400 SCSI-controller chip. 34 * 35 * Derived from Linux NCR-5380 generic driver sources (by Drew Eckhardt). 36 * 37 * Copyright (C) 1994 Serge Vakulenko (vak@cronyx.ru) 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE DEVELOPERS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE DEVELOPERS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 */ 60 61 /* 62 * NCR5380 registers 63 */ 64 #define C80_CSDR 0 /* ro - Current SCSI Data Reg. */ 65 #define C80_ODR 0 /* wo - Output Data Reg. */ 66 #define C80_ICR 1 /* rw - Initiator Command Reg. */ 67 #define C80_MR 2 /* rw - Mode Reg. */ 68 #define C80_TCR 3 /* rw - Target Command Reg. */ 69 #define C80_CSBR 4 /* ro - Current SCSI Bus Status Reg. */ 70 #define C80_SER 4 /* wo - Select Enable Reg. */ 71 #define C80_BSR 5 /* ro - Bus and Status Reg. */ 72 #define C80_SDSR 5 /* wo - Start DMA Send Reg. */ 73 #define C80_IDR 6 /* ro - Input Data Reg. */ 74 #define C80_SDTR 6 /* wo - Start DMA Target Receive Reg. */ 75 #define C80_RPIR 7 /* ro - Reset Parity/Interrupt Reg. */ 76 #define C80_SDIR 7 /* wo - Start DMA Initiator Receive Reg. */ 77 78 79 #define C400_CSR 0 /* rw - Control and Status Reg. */ 80 # define C400_CSR_5380_ENABLE 0x80 81 # define C400_CSR_TRANSFER_DIRECTION 0x40 82 # define C400_CSR_TRANSFER_READY_INTR 0x20 83 # define C400_CSR_5380_INTR 0x10 84 # define C400_CSR_SHARED_INTR 0x08 85 # define C400_CSR_HOST_BUF_NOT_READY 0x04 /* read only */ 86 # define C400_CSR_SCSI_BUF_READY 0x02 /* read only */ 87 # define C400_CSR_5380_GATED_IRQ 0x01 /* read only */ 88 # define C400_CSR_BITS "\20\1irq\2sbrdy\3hbrdy\4shintr\5intr\6tintr\7tdir\10enable" 89 90 #define C400_CCR 1 /* rw - Clock Counter Reg. */ 91 92 #define C400_HBR 4 /* rw - Host Buffer Reg. */ 93 94 #define C400_5380_REG_OFFSET 8 /* Offset of 5380 registers. */ 95