1 /* $NetBSD: osiopreg.h,v 1.1 2001/04/30 04:47:51 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Van Jacobson of Lawrence Berkeley Laboratory. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)siopreg.h 7.3 (Berkeley) 2/5/91 39 */ 40 41 /* 42 * NCR 53C710 SCSI interface hardware description. 43 * 44 * From the Mach scsi driver for the 53C710 and amiga siop driver 45 */ 46 47 /* byte lane definitions */ 48 #if BYTE_ORDER == LITTLE_ENDIAN 49 #define BL0 0 50 #define BL1 1 51 #define BL2 2 52 #define BL3 3 53 #else 54 #define BL0 3 55 #define BL1 2 56 #define BL2 1 57 #define BL3 0 58 #endif 59 60 #define OSIOP_SCNTL0 (0x00+BL0) /* rw: SCSI control reg 0 */ 61 #define OSIOP_SCNTL1 (0x00+BL1) /* rw: SCSI control reg 1 */ 62 #define OSIOP_SDID (0x00+BL2) /* rw: SCSI destination ID */ 63 #define OSIOP_SIEN (0x00+BL3) /* rw: SCSI interrupt enable */ 64 65 #define OSIOP_SCID (0x04+BL0) /* rw: SCSI Chip ID reg */ 66 #define OSIOP_SXFER (0x04+BL1) /* rw: SCSI Transfer reg */ 67 #define OSIOP_SODL (0x04+BL2) /* rw: SCSI Output Data Latch */ 68 #define OSIOP_SOCL (0x04+BL3) /* rw: SCSI Output Control Latch */ 69 70 #define OSIOP_SFBR (0x08+BL0) /* ro: SCSI First Byte Received */ 71 #define OSIOP_SIDL (0x08+BL1) /* ro: SCSI Input Data Latch */ 72 #define OSIOP_SBDL (0x08+BL2) /* ro: SCSI Bus Data Lines */ 73 #define OSIOP_SBCL (0x08+BL3) /* rw: SCSI Bus Control Lines */ 74 75 #define OSIOP_DSTAT (0x0c+BL0) /* ro: DMA status */ 76 #define OSIOP_SSTAT0 (0x0c+BL1) /* ro: SCSI status reg 0 */ 77 #define OSIOP_SSTAT1 (0x0c+BL2) /* ro: SCSI status reg 1 */ 78 #define OSIOP_SSTAT2 (0x0c+BL3) /* ro: SCSI status reg 2 */ 79 80 #define OSIOP_DSA 0x10 /* rw: Data Structure Address */ 81 82 #define OSIOP_CTEST0 (0x14+BL0) /* ro: Chip test register 0 */ 83 #define OSIOP_CTEST1 (0x14+BL1) /* ro: Chip test register 1 */ 84 #define OSIOP_CTEST2 (0x14+BL2) /* ro: Chip test register 2 */ 85 #define OSIOP_CTEST3 (0x14+BL3) /* ro: Chip test register 3 */ 86 87 #define OSIOP_CTEST4 (0x18+BL0) /* rw: Chip test register 4 */ 88 #define OSIOP_CTEST5 (0x18+BL1) /* rw: Chip test register 5 */ 89 #define OSIOP_CTEST6 (0x18+BL2) /* rw: Chip test register 6 */ 90 #define OSIOP_CTEST7 (0x18+BL3) /* rw: Chip test register 7 */ 91 92 #define OSIOP_TEMP 0x1c /* rw: Temporary Stack reg */ 93 94 #define OSIOP_DFIFO (0x20+BL0) /* rw: DMA FIFO */ 95 #define OSIOP_ISTAT (0x20+BL1) /* rw: Interrupt Status reg */ 96 #define OSIOP_CTEST8 (0x20+BL2) /* rw: Chip test register 8 */ 97 #define OSIOP_LCRC (0x20+BL3) /* rw: LCRC value */ 98 99 #define OSIOP_DBC 0x24 /* rw: DMA Counter reg (longword) */ 100 #define OSIOP_DBC0 (0x24+BL0) /* rw: DMA Byte Counter reg 0 */ 101 #define OSIOP_DBC1 (0x24+BL1) /* rw: DMA Byte Counter reg 1 */ 102 #define OSIOP_DBC2 (0x24+BL2) /* rw: DMA Byte Counter reg 2 */ 103 #define OSIOP_DCMD (0x24+BL3) /* rw: DMA Command Register */ 104 105 #define OSIOP_DNAD 0x28 /* rw: DMA Next Data Address */ 106 107 #define OSIOP_DSP 0x2c /* rw: DMA SCRIPTS Pointer reg */ 108 109 #define OSIOP_DSPS 0x30 /* rw: DMA SCRIPTS Pointer Save reg */ 110 111 #define OSIOP_SCRATCH 0x34 /* rw: Scratch register */ 112 113 #define OSIOP_DMODE (0x38+BL0) /* rw: DMA Mode reg */ 114 #define OSIOP_DIEN (0x38+BL1) /* rw: DMA Interrupt Enable */ 115 #define OSIOP_DWT (0x38+BL2) /* rw: DMA Watchdog Timer */ 116 #define OSIOP_DCNTL (0x38+BL3) /* rw: DMA Control reg */ 117 118 #define OSIOP_ADDER 0x3c /* ro: Adder Sum Output */ 119 120 #define OSIOP_NREGS 0x40 121 122 123 /* 124 * Register defines 125 */ 126 127 /* Scsi control register 0 (scntl0) */ 128 129 #define OSIOP_SCNTL0_ARB 0xc0 /* Arbitration mode */ 130 #define OSIOP_ARB_SIMPLE 0x00 131 #define OSIOP_ARB_FULL 0xc0 132 #define OSIOP_SCNTL0_START 0x20 /* Start Sequence */ 133 #define OSIOP_SCNTL0_WATN 0x10 /* (Select) With ATN */ 134 #define OSIOP_SCNTL0_EPC 0x08 /* Enable Parity Checking */ 135 #define OSIOP_SCNTL0_EPG 0x04 /* Enable Parity Generation */ 136 #define OSIOP_SCNTL0_AAP 0x02 /* Assert ATN on Parity Error */ 137 #define OSIOP_SCNTL0_TRG 0x01 /* Target Mode */ 138 139 /* Scsi control register 1 (scntl1) */ 140 141 #define OSIOP_SCNTL1_EXC 0x80 /* Extra Clock Cycle of data setup */ 142 #define OSIOP_SCNTL1_ADB 0x40 /* Assert Data Bus */ 143 #define OSIOP_SCNTL1_ESR 0x20 /* Enable Selection/Reselection */ 144 #define OSIOP_SCNTL1_CON 0x10 /* Connected */ 145 #define OSIOP_SCNTL1_RST 0x08 /* Assert RST */ 146 #define OSIOP_SCNTL1_AESP 0x04 /* Assert even SCSI parity */ 147 #define OSIOP_SCNTL1_PAR 0x04 /* Force bad Parity */ 148 #define OSIOP_SCNTL1_RES0 0x02 /* Reserved */ 149 #define OSIOP_SCNTL1_RES1 0x01 /* Reserved */ 150 151 /* Scsi interrupt enable register (sien) */ 152 153 #define OSIOP_SIEN_M_A 0x80 /* Phase Mismatch or ATN active */ 154 #define OSIOP_SIEN_FCMP 0x40 /* Function Complete */ 155 #define OSIOP_SIEN_STO 0x20 /* (Re)Selection timeout */ 156 #define OSIOP_SIEN_SEL 0x10 /* (Re)Selected */ 157 #define OSIOP_SIEN_SGE 0x08 /* SCSI Gross Error */ 158 #define OSIOP_SIEN_UDC 0x04 /* Unexpected Disconnect */ 159 #define OSIOP_SIEN_RST 0x02 /* RST asserted */ 160 #define OSIOP_SIEN_PAR 0x01 /* Parity Error */ 161 162 /* Scsi chip ID (scid) */ 163 164 #define OSIOP_SCID_VALUE(i) (1 << (i)) 165 166 /* Scsi transfer register (sxfer) */ 167 168 #define OSIOP_SXFER_DHP 0x80 /* Disable Halt on Parity error/ 169 ATN asserted */ 170 #define OSIOP_SXFER_TP 0x70 /* Synch Transfer Period */ 171 /* see specs for formulas: 172 Period = TCP * (4 + XFERP ) 173 TCP = 1 + CLK + 1..2; 174 */ 175 #define OSIOP_SXFER_MO 0x0f /* Synch Max Offset */ 176 #define OSIOP_MAX_OFFSET 8 177 178 /* Scsi output data latch register (sodl) */ 179 180 /* Scsi output control latch register (socl) */ 181 182 #define OSIOP_REQ 0x80 /* SCSI signal <x> asserted */ 183 #define OSIOP_ACK 0x40 184 #define OSIOP_BSY 0x20 185 #define OSIOP_SEL 0x10 186 #define OSIOP_ATN 0x08 187 #define OSIOP_MSG 0x04 188 #define OSIOP_CD 0x02 189 #define OSIOP_IO 0x01 190 191 #define OSIOP_PHASE(x) ((x) & (OSIOP_MSG|OSIOP_CD|OSIOP_IO)) 192 #define DATA_OUT_PHASE 0x00 193 #define DATA_IN_PHASE OSIOP_IO 194 #define COMMAND_PHASE OSIOP_CD 195 #define STATUS_PHASE (OSIOP_CD|OSIOP_IO) 196 #define MSG_OUT_PHASE (OSIOP_MSG|OSIOP_CD) 197 #define MSG_IN_PHASE (OSIOP_MSG|OSIOP_CD|OSIOP_IO) 198 199 /* Scsi first byte received register (sfbr) */ 200 201 /* Scsi input data latch register (sidl) */ 202 203 /* Scsi bus data lines register (sbdl) */ 204 205 /* Scsi bus control lines register (sbcl). Same as socl */ 206 207 #define OSIOP_SBCL_SSCF1 0x02 /* wo */ 208 #define OSIOP_SBCL_SSCF0 0x01 /* wo */ 209 210 /* DMA status register (dstat) */ 211 212 #define OSIOP_DSTAT_DFE 0x80 /* DMA FIFO empty */ 213 #define OSIOP_DSTAT_RES 0x40 214 #define OSIOP_DSTAT_BF 0x20 /* Bus fault */ 215 #define OSIOP_DSTAT_ABRT 0x10 /* Aborted */ 216 #define OSIOP_DSTAT_SSI 0x08 /* SCRIPT Single Step */ 217 #define OSIOP_DSTAT_SIR 0x04 /* SCRIPT Interrupt Instruction */ 218 #define OSIOP_DSTAT_WTD 0x02 /* Watchdog Timeout Detected */ 219 #define OSIOP_DSTAT_IID 0x01 /* Invalid Instruction Detected */ 220 221 /* Scsi status register 0 (sstat0) */ 222 223 #define OSIOP_SSTAT0_M_A 0x80 /* Phase Mismatch or ATN active */ 224 #define OSIOP_SSTAT0_FCMP 0x40 /* Function Complete */ 225 #define OSIOP_SSTAT0_STO 0x20 /* (Re)Selection timeout */ 226 #define OSIOP_SSTAT0_SEL 0x10 /* (Re)Selected */ 227 #define OSIOP_SSTAT0_SGE 0x08 /* SCSI Gross Error */ 228 #define OSIOP_SSTAT0_UDC 0x04 /* Unexpected Disconnect */ 229 #define OSIOP_SSTAT0_RST 0x02 /* RST asserted */ 230 #define OSIOP_SSTAT0_PAR 0x01 /* Parity Error */ 231 232 /* Scsi status register 1 (sstat1) */ 233 234 #define OSIOP_SSTAT1_ILF 0x80 /* Input latch (sidl) full */ 235 #define OSIOP_SSTAT1_ORF 0x40 /* output reg (sodr) full */ 236 #define OSIOP_SSTAT1_OLF 0x20 /* output latch (sodl) full */ 237 #define OSIOP_SSTAT1_AIP 0x10 /* Arbitration in progress */ 238 #define OSIOP_SSTAT1_LOA 0x08 /* Lost arbitration */ 239 #define OSIOP_SSTAT1_WOA 0x04 /* Won arbitration */ 240 #define OSIOP_SSTAT1_RST 0x02 /* SCSI RST current value */ 241 #define OSIOP_SSTAT1_SDP 0x01 /* SCSI SDP current value */ 242 243 /* Scsi status register 2 (sstat2) */ 244 245 #define OSIOP_SSTAT2_FF 0xf0 /* SCSI FIFO flags (bytecount) */ 246 #define OSIOP_SCSI_FIFO_DEEP 8 247 #define OSIOP_SSTAT2_SDP 0x08 /* Latched (on REQ) SCSI SDP */ 248 #define OSIOP_SSTAT2_MSG 0x04 /* Latched SCSI phase */ 249 #define OSIOP_SSTAT2_CD 0x02 250 #define OSIOP_SSTAT2_IO 0x01 251 252 /* Chip test register 0 (ctest0) */ 253 254 #define OSIOP_CTEST0_RES0 0x80 255 #define OSIOP_CTEST0_BTD 0x40 /* Byte-to-byte Timer Disable */ 256 #define OSIOP_CTEST0_GRP 0x20 /* Generate Receive Parity */ 257 #define OSIOP_CTEST0_EAN 0x10 /* Enable Active Negation */ 258 #define OSIOP_CTEST0_HSC 0x08 /* Halt SCSI clock */ 259 #define OSIOP_CTEST0_ERF 0x04 /* Extend REQ/ACK Filtering */ 260 #define OSIOP_CTEST0_RES1 0x02 261 #define OSIOP_CTEST0_DDIR 0x01 /* Xfer direction (1-> from SCSI bus) */ 262 263 264 /* Chip test register 1 (ctest1) */ 265 266 #define OSIOP_CTEST1_FMT 0xf0 /* Byte empty in DMA FIFO bottom 267 (high->byte3) */ 268 #define OSIOP_CTEST1_FFL 0x0f /* Byte full in DMA FIFO top, same */ 269 270 /* Chip test register 2 (ctest2) */ 271 272 #define OSIOP_CTEST2_RES 0x80 273 #define OSIOP_CTEST2_SIGP 0x40 /* Signal process */ 274 #define OSIOP_CTEST2_SOFF 0x20 /* Synch Offset compare 275 (1-> zero Init, max Tgt */ 276 #define OSIOP_CTEST2_SFP 0x10 /* SCSI FIFO Parity */ 277 #define OSIOP_CTEST2_DFP 0x08 /* DMA FIFO Parity */ 278 #define OSIOP_CTEST2_TEOP 0x04 /* True EOP (a-la 5380) */ 279 #define OSIOP_CTEST2_DREQ 0x02 /* DREQ status */ 280 #define OSIOP_CTEST2_DACK 0x01 /* DACK status */ 281 282 /* Chip test register 3 (ctest3) read-only, top of SCSI FIFO */ 283 284 /* Chip test register 4 (ctest4) */ 285 286 #define OSIOP_CTEST4_MUX 0x80 /* Host bus multiplex mode */ 287 #define OSIOP_CTEST4_ZMOD 0x40 /* High-impedance outputs */ 288 #define OSIOP_CTEST4_SZM 0x20 /* ditto, SCSI "outputs" */ 289 #define OSIOP_CTEST4_SLBE 0x10 /* SCSI loobpack enable */ 290 #define OSIOP_CTEST4_SFWR 0x08 /* SCSI FIFO write enable (from sodl) */ 291 #define OSIOP_CTEST4_FBL 0x07 /* DMA FIFO Byte Lane select 292 (from ctest6) 4->0, .. 7->3 */ 293 294 /* Chip test register 5 (ctest5) */ 295 296 #define OSIOP_CTEST5_ADCK 0x80 /* Clock Address Incrementor */ 297 #define OSIOP_CTEST5_BBCK 0x40 /* Clock Byte counter */ 298 #define OSIOP_CTEST5_ROFF 0x20 /* Reset SCSI offset */ 299 #define OSIOP_CTEST5_MASR 0x10 /* Master set/reset pulses 300 (of bits 3-0) */ 301 #define OSIOP_CTEST5_DDIR 0x08 /* (re)set internal DMA direction */ 302 #define OSIOP_CTEST5_EOP 0x04 /* (re)set internal EOP */ 303 #define OSIOP_CTEST5_DREQ 0x02 /* (re)set internal REQ */ 304 #define OSIOP_CTEST5_DACK 0x01 /* (re)set internal ACK */ 305 306 /* Chip test register 6 (ctest6) DMA FIFO access */ 307 308 /* Chip test register 7 (ctest7) */ 309 310 #define OSIOP_CTEST7_CDIS 0x80 /* Cache burst disable */ 311 #define OSIOP_CTEST7_SC1 0x40 /* Snoop control 1 */ 312 #define OSIOP_CTEST7_SC0 0x20 /* Snoop contorl 0 */ 313 #define OSIOP_CTEST7_STD 0x10 /* Selection timeout disable */ 314 #define OSIOP_CTEST7_DFP 0x08 /* DMA FIFO parity bit */ 315 #define OSIOP_CTEST7_EVP 0x04 /* Even parity (to host bus) */ 316 #define OSIOP_CTEST7_TT1 0x02 /* Transfer type bit */ 317 #define OSIOP_CTEST7_DIFF 0x01 /* Differential mode */ 318 319 /* DMA FIFO register (dfifo) */ 320 321 #define OSIOP_DFIFO_FLF 0x80 /* Flush (spill) DMA FIFO */ 322 #define OSIOP_DFIFO_BO 0x7f /* FIFO byte offset counter */ 323 324 /* Interrupt status register (istat) */ 325 326 #define OSIOP_ISTAT_ABRT 0x80 /* Abort operation */ 327 #define OSIOP_ISTAT_RST 0x40 /* Software reset */ 328 #define OSIOP_ISTAT_SIGP 0x20 /* Signal process */ 329 #define OSIOP_ISTAT_RES 0x10 330 #define OSIOP_ISTAT_CON 0x08 /* Connected */ 331 #define OSIOP_ISTAT_RES1 0x04 332 #define OSIOP_ISTAT_SIP 0x02 /* SCSI Interrupt pending */ 333 #define OSIOP_ISTAT_DIP 0x01 /* DMA Interrupt pending */ 334 335 /* Chip test register 8 (ctest8) */ 336 337 #define OSIOP_CTEST8_V 0xf0 /* Chip revision level */ 338 #define OSIOP_CTEST8_FLF 0x08 /* Flush DMA FIFO */ 339 #define OSIOP_CTEST8_CLF 0x04 /* Clear DMA and SCSI FIFOs */ 340 #define OSIOP_CTEST8_FM 0x02 /* Fetch pin mode */ 341 #define OSIOP_CTEST8_SM 0x01 /* Snoop pins mode */ 342 343 /* DMA Mode register (dmode) */ 344 345 #define OSIOP_DMODE_BL_MASK 0xc0 /* DMA burst length */ 346 #define OSIOP_DMODE_BL8 0xc0 /* 8 bytes */ 347 #define OSIOP_DMODE_BL4 0x80 /* 4 bytes */ 348 #define OSIOP_DMODE_BL2 0x40 /* 2 bytes */ 349 #define OSIOP_DMODE_BL1 0x00 /* 1 byte */ 350 #define OSIOP_DMODE_FC 0x30 /* Function code */ 351 #define OSIOP_DMODE_PD 0x08 /* Program/data */ 352 #define OSIOP_DMODE_FAM 0x04 /* fixed address mode */ 353 #define OSIOP_DMODE_U0 0x02 /* User programmable transfer type */ 354 #define OSIOP_DMODE_MAN 0x01 /* SCRIPTS in Manual start mode */ 355 356 /* DMA interrupt enable register (dien) */ 357 358 #define OSIOP_DIEN_RES 0xc0 359 #define OSIOP_DIEN_BF 0x20 /* On Bus Fault */ 360 #define OSIOP_DIEN_ABRT 0x10 /* On Abort */ 361 #define OSIOP_DIEN_SSI 0x08 /* On SCRIPTS sstep */ 362 #define OSIOP_DIEN_SIR 0x04 /* On SCRIPTS intr instruction */ 363 #define OSIOP_DIEN_WTD 0x02 /* On watchdog timeout */ 364 #define OSIOP_DIEN_IID 0x01 /* On illegal instruction detected */ 365 366 /* DMA control register (dcntl) */ 367 368 #define OSIOP_DCNTL_CF_MASK 0xc0 /* Clock frequency dividers: */ 369 #define OSIOP_DCNTL_CF_2 0x00 /* 0 --> 37.51..50.00 Mhz, div=2 */ 370 #define OSIOP_DCNTL_CF_1_5 0x40 /* 1 --> 25.01..37.50 Mhz, div=1.5 */ 371 #define OSIOP_DCNTL_CF_1 0x80 /* 2 --> 16.67..25.00 Mhz, div=1 */ 372 #define OSIOP_DCNTL_CF_3 0xc0 /* 3 --> 50.01..66.67 Mhz, div=3 */ 373 #define OSIOP_DCNTL_EA 0x20 /* Enable ACK */ 374 #define OSIOP_DCNTL_SSM 0x10 /* Single step mode */ 375 #define OSIOP_DCNTL_LLM 0x08 /* Enable SCSI Low-level mode */ 376 #define OSIOP_DCNTL_STD 0x04 /* Start DMA operation */ 377 #define OSIOP_DCNTL_FA 0x02 /* Fast arbitration */ 378 #define OSIOP_DCNTL_COM 0x01 /* 53C700 Compatibility */ 379