1 /* $NetBSD: rtl81x9.c,v 1.92 2010/11/13 13:52:02 uebayasi Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_rl.c,v 1.17 1999/06/19 20:17:37 wpaul Exp 35 */ 36 37 /* 38 * RealTek 8129/8139 PCI NIC driver 39 * 40 * Supports several extremely cheap PCI 10/100 adapters based on 41 * the RealTek chipset. Datasheets can be obtained from 42 * www.realtek.com.tw. 43 * 44 * Written by Bill Paul <wpaul@ctr.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48 49 /* 50 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 51 * probably the worst PCI ethernet controller ever made, with the possible 52 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 53 * DMA, but it has a terrible interface that nullifies any performance 54 * gains that bus-master DMA usually offers. 55 * 56 * For transmission, the chip offers a series of four TX descriptor 57 * registers. Each transmit frame must be in a contiguous buffer, aligned 58 * on a longword (32-bit) boundary. This means we almost always have to 59 * do mbuf copies in order to transmit a frame, except in the unlikely 60 * case where a) the packet fits into a single mbuf, and b) the packet 61 * is 32-bit aligned within the mbuf's data area. The presence of only 62 * four descriptor registers means that we can never have more than four 63 * packets queued for transmission at any one time. 64 * 65 * Reception is not much better. The driver has to allocate a single large 66 * buffer area (up to 64K in size) into which the chip will DMA received 67 * frames. Because we don't know where within this region received packets 68 * will begin or end, we have no choice but to copy data from the buffer 69 * area into mbufs in order to pass the packets up to the higher protocol 70 * levels. 71 * 72 * It's impossible given this rotten design to really achieve decent 73 * performance at 100Mbps, unless you happen to have a 400MHz PII or 74 * some equally overmuscled CPU to drive it. 75 * 76 * On the bright side, the 8139 does have a built-in PHY, although 77 * rather than using an MDIO serial interface like most other NICs, the 78 * PHY registers are directly accessible through the 8139's register 79 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 80 * filter. 81 * 82 * The 8129 chip is an older version of the 8139 that uses an external PHY 83 * chip. The 8129 has a serial MDIO interface for accessing the MII where 84 * the 8139 lets you directly access the on-board PHY registers. We need 85 * to select which interface to use depending on the chip type. 86 */ 87 88 #include <sys/cdefs.h> 89 __KERNEL_RCSID(0, "$NetBSD: rtl81x9.c,v 1.92 2010/11/13 13:52:02 uebayasi Exp $"); 90 91 #include "rnd.h" 92 93 #include <sys/param.h> 94 #include <sys/systm.h> 95 #include <sys/callout.h> 96 #include <sys/device.h> 97 #include <sys/sockio.h> 98 #include <sys/mbuf.h> 99 #include <sys/malloc.h> 100 #include <sys/kernel.h> 101 #include <sys/socket.h> 102 103 #include <net/if.h> 104 #include <net/if_arp.h> 105 #include <net/if_ether.h> 106 #include <net/if_dl.h> 107 #include <net/if_media.h> 108 109 #include <net/bpf.h> 110 #if NRND > 0 111 #include <sys/rnd.h> 112 #endif 113 114 #include <sys/bus.h> 115 #include <machine/endian.h> 116 117 #include <dev/mii/mii.h> 118 #include <dev/mii/miivar.h> 119 120 #include <dev/ic/rtl81x9reg.h> 121 #include <dev/ic/rtl81x9var.h> 122 123 static void rtk_reset(struct rtk_softc *); 124 static void rtk_rxeof(struct rtk_softc *); 125 static void rtk_txeof(struct rtk_softc *); 126 static void rtk_start(struct ifnet *); 127 static int rtk_ioctl(struct ifnet *, u_long, void *); 128 static int rtk_init(struct ifnet *); 129 static void rtk_stop(struct ifnet *, int); 130 131 static void rtk_watchdog(struct ifnet *); 132 133 static void rtk_eeprom_putbyte(struct rtk_softc *, int, int); 134 static void rtk_mii_sync(struct rtk_softc *); 135 static void rtk_mii_send(struct rtk_softc *, uint32_t, int); 136 static int rtk_mii_readreg(struct rtk_softc *, struct rtk_mii_frame *); 137 static int rtk_mii_writereg(struct rtk_softc *, struct rtk_mii_frame *); 138 139 static int rtk_phy_readreg(device_t, int, int); 140 static void rtk_phy_writereg(device_t, int, int, int); 141 static void rtk_phy_statchg(device_t); 142 static void rtk_tick(void *); 143 144 static int rtk_enable(struct rtk_softc *); 145 static void rtk_disable(struct rtk_softc *); 146 147 static void rtk_list_tx_init(struct rtk_softc *); 148 149 #define EE_SET(x) \ 150 CSR_WRITE_1(sc, RTK_EECMD, \ 151 CSR_READ_1(sc, RTK_EECMD) | (x)) 152 153 #define EE_CLR(x) \ 154 CSR_WRITE_1(sc, RTK_EECMD, \ 155 CSR_READ_1(sc, RTK_EECMD) & ~(x)) 156 157 #define EE_DELAY() DELAY(100) 158 159 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 160 161 /* 162 * Send a read command and address to the EEPROM, check for ACK. 163 */ 164 static void 165 rtk_eeprom_putbyte(struct rtk_softc *sc, int addr, int addr_len) 166 { 167 int d, i; 168 169 d = (RTK_EECMD_READ << addr_len) | addr; 170 171 /* 172 * Feed in each bit and stobe the clock. 173 */ 174 for (i = RTK_EECMD_LEN + addr_len; i > 0; i--) { 175 if (d & (1 << (i - 1))) { 176 EE_SET(RTK_EE_DATAIN); 177 } else { 178 EE_CLR(RTK_EE_DATAIN); 179 } 180 EE_DELAY(); 181 EE_SET(RTK_EE_CLK); 182 EE_DELAY(); 183 EE_CLR(RTK_EE_CLK); 184 EE_DELAY(); 185 } 186 } 187 188 /* 189 * Read a word of data stored in the EEPROM at address 'addr.' 190 */ 191 uint16_t 192 rtk_read_eeprom(struct rtk_softc *sc, int addr, int addr_len) 193 { 194 uint16_t word; 195 int i; 196 197 /* Enter EEPROM access mode. */ 198 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_PROGRAM); 199 EE_DELAY(); 200 EE_SET(RTK_EE_SEL); 201 202 /* 203 * Send address of word we want to read. 204 */ 205 rtk_eeprom_putbyte(sc, addr, addr_len); 206 207 /* 208 * Start reading bits from EEPROM. 209 */ 210 word = 0; 211 for (i = 16; i > 0; i--) { 212 EE_SET(RTK_EE_CLK); 213 EE_DELAY(); 214 if (CSR_READ_1(sc, RTK_EECMD) & RTK_EE_DATAOUT) 215 word |= 1 << (i - 1); 216 EE_CLR(RTK_EE_CLK); 217 EE_DELAY(); 218 } 219 220 /* Turn off EEPROM access mode. */ 221 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 222 223 return word; 224 } 225 226 /* 227 * MII access routines are provided for the 8129, which 228 * doesn't have a built-in PHY. For the 8139, we fake things 229 * up by diverting rtk_phy_readreg()/rtk_phy_writereg() to the 230 * direct access PHY registers. 231 */ 232 #define MII_SET(x) \ 233 CSR_WRITE_1(sc, RTK_MII, \ 234 CSR_READ_1(sc, RTK_MII) | (x)) 235 236 #define MII_CLR(x) \ 237 CSR_WRITE_1(sc, RTK_MII, \ 238 CSR_READ_1(sc, RTK_MII) & ~(x)) 239 240 /* 241 * Sync the PHYs by setting data bit and strobing the clock 32 times. 242 */ 243 static void 244 rtk_mii_sync(struct rtk_softc *sc) 245 { 246 int i; 247 248 MII_SET(RTK_MII_DIR|RTK_MII_DATAOUT); 249 250 for (i = 0; i < 32; i++) { 251 MII_SET(RTK_MII_CLK); 252 DELAY(1); 253 MII_CLR(RTK_MII_CLK); 254 DELAY(1); 255 } 256 } 257 258 /* 259 * Clock a series of bits through the MII. 260 */ 261 static void 262 rtk_mii_send(struct rtk_softc *sc, uint32_t bits, int cnt) 263 { 264 int i; 265 266 MII_CLR(RTK_MII_CLK); 267 268 for (i = cnt; i > 0; i--) { 269 if (bits & (1 << (i - 1))) { 270 MII_SET(RTK_MII_DATAOUT); 271 } else { 272 MII_CLR(RTK_MII_DATAOUT); 273 } 274 DELAY(1); 275 MII_CLR(RTK_MII_CLK); 276 DELAY(1); 277 MII_SET(RTK_MII_CLK); 278 } 279 } 280 281 /* 282 * Read an PHY register through the MII. 283 */ 284 static int 285 rtk_mii_readreg(struct rtk_softc *sc, struct rtk_mii_frame *frame) 286 { 287 int i, ack, s; 288 289 s = splnet(); 290 291 /* 292 * Set up frame for RX. 293 */ 294 frame->mii_stdelim = RTK_MII_STARTDELIM; 295 frame->mii_opcode = RTK_MII_READOP; 296 frame->mii_turnaround = 0; 297 frame->mii_data = 0; 298 299 CSR_WRITE_2(sc, RTK_MII, 0); 300 301 /* 302 * Turn on data xmit. 303 */ 304 MII_SET(RTK_MII_DIR); 305 306 rtk_mii_sync(sc); 307 308 /* 309 * Send command/address info. 310 */ 311 rtk_mii_send(sc, frame->mii_stdelim, 2); 312 rtk_mii_send(sc, frame->mii_opcode, 2); 313 rtk_mii_send(sc, frame->mii_phyaddr, 5); 314 rtk_mii_send(sc, frame->mii_regaddr, 5); 315 316 /* Idle bit */ 317 MII_CLR((RTK_MII_CLK|RTK_MII_DATAOUT)); 318 DELAY(1); 319 MII_SET(RTK_MII_CLK); 320 DELAY(1); 321 322 /* Turn off xmit. */ 323 MII_CLR(RTK_MII_DIR); 324 325 /* Check for ack */ 326 MII_CLR(RTK_MII_CLK); 327 DELAY(1); 328 ack = CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN; 329 MII_SET(RTK_MII_CLK); 330 DELAY(1); 331 332 /* 333 * Now try reading data bits. If the ack failed, we still 334 * need to clock through 16 cycles to keep the PHY(s) in sync. 335 */ 336 if (ack) { 337 for (i = 0; i < 16; i++) { 338 MII_CLR(RTK_MII_CLK); 339 DELAY(1); 340 MII_SET(RTK_MII_CLK); 341 DELAY(1); 342 } 343 goto fail; 344 } 345 346 for (i = 16; i > 0; i--) { 347 MII_CLR(RTK_MII_CLK); 348 DELAY(1); 349 if (!ack) { 350 if (CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN) 351 frame->mii_data |= 1 << (i - 1); 352 DELAY(1); 353 } 354 MII_SET(RTK_MII_CLK); 355 DELAY(1); 356 } 357 358 fail: 359 MII_CLR(RTK_MII_CLK); 360 DELAY(1); 361 MII_SET(RTK_MII_CLK); 362 DELAY(1); 363 364 splx(s); 365 366 if (ack) 367 return 1; 368 return 0; 369 } 370 371 /* 372 * Write to a PHY register through the MII. 373 */ 374 static int 375 rtk_mii_writereg(struct rtk_softc *sc, struct rtk_mii_frame *frame) 376 { 377 int s; 378 379 s = splnet(); 380 /* 381 * Set up frame for TX. 382 */ 383 frame->mii_stdelim = RTK_MII_STARTDELIM; 384 frame->mii_opcode = RTK_MII_WRITEOP; 385 frame->mii_turnaround = RTK_MII_TURNAROUND; 386 387 /* 388 * Turn on data output. 389 */ 390 MII_SET(RTK_MII_DIR); 391 392 rtk_mii_sync(sc); 393 394 rtk_mii_send(sc, frame->mii_stdelim, 2); 395 rtk_mii_send(sc, frame->mii_opcode, 2); 396 rtk_mii_send(sc, frame->mii_phyaddr, 5); 397 rtk_mii_send(sc, frame->mii_regaddr, 5); 398 rtk_mii_send(sc, frame->mii_turnaround, 2); 399 rtk_mii_send(sc, frame->mii_data, 16); 400 401 /* Idle bit. */ 402 MII_SET(RTK_MII_CLK); 403 DELAY(1); 404 MII_CLR(RTK_MII_CLK); 405 DELAY(1); 406 407 /* 408 * Turn off xmit. 409 */ 410 MII_CLR(RTK_MII_DIR); 411 412 splx(s); 413 414 return 0; 415 } 416 417 static int 418 rtk_phy_readreg(device_t self, int phy, int reg) 419 { 420 struct rtk_softc *sc = device_private(self); 421 struct rtk_mii_frame frame; 422 int rval; 423 int rtk8139_reg; 424 425 if ((sc->sc_quirk & RTKQ_8129) == 0) { 426 if (phy != 7) 427 return 0; 428 429 switch (reg) { 430 case MII_BMCR: 431 rtk8139_reg = RTK_BMCR; 432 break; 433 case MII_BMSR: 434 rtk8139_reg = RTK_BMSR; 435 break; 436 case MII_ANAR: 437 rtk8139_reg = RTK_ANAR; 438 break; 439 case MII_ANER: 440 rtk8139_reg = RTK_ANER; 441 break; 442 case MII_ANLPAR: 443 rtk8139_reg = RTK_LPAR; 444 break; 445 default: 446 #if 0 447 printf("%s: bad phy register\n", device_xname(self)); 448 #endif 449 return 0; 450 } 451 rval = CSR_READ_2(sc, rtk8139_reg); 452 return rval; 453 } 454 455 memset(&frame, 0, sizeof(frame)); 456 457 frame.mii_phyaddr = phy; 458 frame.mii_regaddr = reg; 459 rtk_mii_readreg(sc, &frame); 460 461 return frame.mii_data; 462 } 463 464 static void 465 rtk_phy_writereg(device_t self, int phy, int reg, int data) 466 { 467 struct rtk_softc *sc = device_private(self); 468 struct rtk_mii_frame frame; 469 int rtk8139_reg; 470 471 if ((sc->sc_quirk & RTKQ_8129) == 0) { 472 if (phy != 7) 473 return; 474 475 switch (reg) { 476 case MII_BMCR: 477 rtk8139_reg = RTK_BMCR; 478 break; 479 case MII_BMSR: 480 rtk8139_reg = RTK_BMSR; 481 break; 482 case MII_ANAR: 483 rtk8139_reg = RTK_ANAR; 484 break; 485 case MII_ANER: 486 rtk8139_reg = RTK_ANER; 487 break; 488 case MII_ANLPAR: 489 rtk8139_reg = RTK_LPAR; 490 break; 491 default: 492 #if 0 493 printf("%s: bad phy register\n", device_xname(self)); 494 #endif 495 return; 496 } 497 CSR_WRITE_2(sc, rtk8139_reg, data); 498 return; 499 } 500 501 memset(&frame, 0, sizeof(frame)); 502 503 frame.mii_phyaddr = phy; 504 frame.mii_regaddr = reg; 505 frame.mii_data = data; 506 507 rtk_mii_writereg(sc, &frame); 508 } 509 510 static void 511 rtk_phy_statchg(device_t v) 512 { 513 514 /* Nothing to do. */ 515 } 516 517 #define rtk_calchash(addr) \ 518 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 519 520 /* 521 * Program the 64-bit multicast hash filter. 522 */ 523 void 524 rtk_setmulti(struct rtk_softc *sc) 525 { 526 struct ifnet *ifp; 527 uint32_t hashes[2] = { 0, 0 }; 528 uint32_t rxfilt; 529 struct ether_multi *enm; 530 struct ether_multistep step; 531 int h, mcnt; 532 533 ifp = &sc->ethercom.ec_if; 534 535 rxfilt = CSR_READ_4(sc, RTK_RXCFG); 536 537 if (ifp->if_flags & IFF_PROMISC) { 538 allmulti: 539 ifp->if_flags |= IFF_ALLMULTI; 540 rxfilt |= RTK_RXCFG_RX_MULTI; 541 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); 542 CSR_WRITE_4(sc, RTK_MAR0, 0xFFFFFFFF); 543 CSR_WRITE_4(sc, RTK_MAR4, 0xFFFFFFFF); 544 return; 545 } 546 547 /* first, zot all the existing hash bits */ 548 CSR_WRITE_4(sc, RTK_MAR0, 0); 549 CSR_WRITE_4(sc, RTK_MAR4, 0); 550 551 /* now program new ones */ 552 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 553 mcnt = 0; 554 while (enm != NULL) { 555 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 556 ETHER_ADDR_LEN) != 0) 557 goto allmulti; 558 559 h = rtk_calchash(enm->enm_addrlo); 560 if (h < 32) 561 hashes[0] |= (1 << h); 562 else 563 hashes[1] |= (1 << (h - 32)); 564 mcnt++; 565 ETHER_NEXT_MULTI(step, enm); 566 } 567 568 ifp->if_flags &= ~IFF_ALLMULTI; 569 570 if (mcnt) 571 rxfilt |= RTK_RXCFG_RX_MULTI; 572 else 573 rxfilt &= ~RTK_RXCFG_RX_MULTI; 574 575 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); 576 577 /* 578 * For some unfathomable reason, RealTek decided to reverse 579 * the order of the multicast hash registers in the PCI Express 580 * parts. This means we have to write the hash pattern in reverse 581 * order for those devices. 582 */ 583 if ((sc->sc_quirk & RTKQ_PCIE) != 0) { 584 CSR_WRITE_4(sc, RTK_MAR0, bswap32(hashes[1])); 585 CSR_WRITE_4(sc, RTK_MAR4, bswap32(hashes[0])); 586 } else { 587 CSR_WRITE_4(sc, RTK_MAR0, hashes[0]); 588 CSR_WRITE_4(sc, RTK_MAR4, hashes[1]); 589 } 590 } 591 592 void 593 rtk_reset(struct rtk_softc *sc) 594 { 595 int i; 596 597 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 598 599 for (i = 0; i < RTK_TIMEOUT; i++) { 600 DELAY(10); 601 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0) 602 break; 603 } 604 if (i == RTK_TIMEOUT) 605 printf("%s: reset never completed!\n", 606 device_xname(sc->sc_dev)); 607 } 608 609 /* 610 * Attach the interface. Allocate softc structures, do ifmedia 611 * setup and ethernet/BPF attach. 612 */ 613 void 614 rtk_attach(struct rtk_softc *sc) 615 { 616 device_t self = sc->sc_dev; 617 struct ifnet *ifp; 618 struct rtk_tx_desc *txd; 619 uint16_t val; 620 uint8_t eaddr[ETHER_ADDR_LEN]; 621 int error; 622 int i, addr_len; 623 624 callout_init(&sc->rtk_tick_ch, 0); 625 626 /* 627 * Check EEPROM type 9346 or 9356. 628 */ 629 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 630 addr_len = RTK_EEADDR_LEN1; 631 else 632 addr_len = RTK_EEADDR_LEN0; 633 634 /* 635 * Get station address. 636 */ 637 val = rtk_read_eeprom(sc, RTK_EE_EADDR0, addr_len); 638 eaddr[0] = val & 0xff; 639 eaddr[1] = val >> 8; 640 val = rtk_read_eeprom(sc, RTK_EE_EADDR1, addr_len); 641 eaddr[2] = val & 0xff; 642 eaddr[3] = val >> 8; 643 val = rtk_read_eeprom(sc, RTK_EE_EADDR2, addr_len); 644 eaddr[4] = val & 0xff; 645 eaddr[5] = val >> 8; 646 647 if ((error = bus_dmamem_alloc(sc->sc_dmat, 648 RTK_RXBUFLEN + 16, PAGE_SIZE, 0, &sc->sc_dmaseg, 1, &sc->sc_dmanseg, 649 BUS_DMA_NOWAIT)) != 0) { 650 aprint_error_dev(self, 651 "can't allocate recv buffer, error = %d\n", error); 652 goto fail_0; 653 } 654 655 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg, 656 RTK_RXBUFLEN + 16, (void **)&sc->rtk_rx_buf, 657 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 658 aprint_error_dev(self, 659 "can't map recv buffer, error = %d\n", error); 660 goto fail_1; 661 } 662 663 if ((error = bus_dmamap_create(sc->sc_dmat, 664 RTK_RXBUFLEN + 16, 1, RTK_RXBUFLEN + 16, 0, BUS_DMA_NOWAIT, 665 &sc->recv_dmamap)) != 0) { 666 aprint_error_dev(self, 667 "can't create recv buffer DMA map, error = %d\n", error); 668 goto fail_2; 669 } 670 671 if ((error = bus_dmamap_load(sc->sc_dmat, sc->recv_dmamap, 672 sc->rtk_rx_buf, RTK_RXBUFLEN + 16, 673 NULL, BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 674 aprint_error_dev(self, 675 "can't load recv buffer DMA map, error = %d\n", error); 676 goto fail_3; 677 } 678 679 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 680 txd = &sc->rtk_tx_descs[i]; 681 if ((error = bus_dmamap_create(sc->sc_dmat, 682 MCLBYTES, 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 683 &txd->txd_dmamap)) != 0) { 684 aprint_error_dev(self, 685 "can't create snd buffer DMA map, error = %d\n", 686 error); 687 goto fail_4; 688 } 689 txd->txd_txaddr = RTK_TXADDR0 + (i * 4); 690 txd->txd_txstat = RTK_TXSTAT0 + (i * 4); 691 } 692 SIMPLEQ_INIT(&sc->rtk_tx_free); 693 SIMPLEQ_INIT(&sc->rtk_tx_dirty); 694 695 /* 696 * From this point forward, the attachment cannot fail. A failure 697 * before this releases all resources thar may have been 698 * allocated. 699 */ 700 sc->sc_flags |= RTK_ATTACHED; 701 702 /* Reset the adapter. */ 703 rtk_reset(sc); 704 705 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(eaddr)); 706 707 ifp = &sc->ethercom.ec_if; 708 ifp->if_softc = sc; 709 strcpy(ifp->if_xname, device_xname(self)); 710 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 711 ifp->if_ioctl = rtk_ioctl; 712 ifp->if_start = rtk_start; 713 ifp->if_watchdog = rtk_watchdog; 714 ifp->if_init = rtk_init; 715 ifp->if_stop = rtk_stop; 716 IFQ_SET_READY(&ifp->if_snd); 717 718 /* 719 * Do ifmedia setup. 720 */ 721 sc->mii.mii_ifp = ifp; 722 sc->mii.mii_readreg = rtk_phy_readreg; 723 sc->mii.mii_writereg = rtk_phy_writereg; 724 sc->mii.mii_statchg = rtk_phy_statchg; 725 sc->ethercom.ec_mii = &sc->mii; 726 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, ether_mediachange, 727 ether_mediastatus); 728 mii_attach(self, &sc->mii, 0xffffffff, 729 MII_PHY_ANY, MII_OFFSET_ANY, 0); 730 731 /* Choose a default media. */ 732 if (LIST_FIRST(&sc->mii.mii_phys) == NULL) { 733 ifmedia_add(&sc->mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 734 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_NONE); 735 } else { 736 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_AUTO); 737 } 738 739 /* 740 * Call MI attach routines. 741 */ 742 if_attach(ifp); 743 ether_ifattach(ifp, eaddr); 744 745 #if NRND > 0 746 rnd_attach_source(&sc->rnd_source, device_xname(self), 747 RND_TYPE_NET, 0); 748 #endif 749 750 return; 751 fail_4: 752 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 753 txd = &sc->rtk_tx_descs[i]; 754 if (txd->txd_dmamap != NULL) 755 bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap); 756 } 757 fail_3: 758 bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap); 759 fail_2: 760 bus_dmamem_unmap(sc->sc_dmat, sc->rtk_rx_buf, 761 RTK_RXBUFLEN + 16); 762 fail_1: 763 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg); 764 fail_0: 765 return; 766 } 767 768 /* 769 * Initialize the transmit descriptors. 770 */ 771 static void 772 rtk_list_tx_init(struct rtk_softc *sc) 773 { 774 struct rtk_tx_desc *txd; 775 int i; 776 777 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) 778 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q); 779 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL) 780 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_free, txd_q); 781 782 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 783 txd = &sc->rtk_tx_descs[i]; 784 CSR_WRITE_4(sc, txd->txd_txaddr, 0); 785 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q); 786 } 787 } 788 789 /* 790 * rtk_activate: 791 * Handle device activation/deactivation requests. 792 */ 793 int 794 rtk_activate(device_t self, enum devact act) 795 { 796 struct rtk_softc *sc = device_private(self); 797 798 switch (act) { 799 case DVACT_DEACTIVATE: 800 if_deactivate(&sc->ethercom.ec_if); 801 return 0; 802 default: 803 return EOPNOTSUPP; 804 } 805 } 806 807 /* 808 * rtk_detach: 809 * Detach a rtk interface. 810 */ 811 int 812 rtk_detach(struct rtk_softc *sc) 813 { 814 struct ifnet *ifp = &sc->ethercom.ec_if; 815 struct rtk_tx_desc *txd; 816 int i; 817 818 /* 819 * Succeed now if there isn't any work to do. 820 */ 821 if ((sc->sc_flags & RTK_ATTACHED) == 0) 822 return 0; 823 824 /* Unhook our tick handler. */ 825 callout_stop(&sc->rtk_tick_ch); 826 827 /* Detach all PHYs. */ 828 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 829 830 /* Delete all remaining media. */ 831 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 832 833 #if NRND > 0 834 rnd_detach_source(&sc->rnd_source); 835 #endif 836 837 ether_ifdetach(ifp); 838 if_detach(ifp); 839 840 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 841 txd = &sc->rtk_tx_descs[i]; 842 if (txd->txd_dmamap != NULL) 843 bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap); 844 } 845 bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap); 846 bus_dmamem_unmap(sc->sc_dmat, sc->rtk_rx_buf, 847 RTK_RXBUFLEN + 16); 848 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg); 849 850 /* we don't want to run again */ 851 sc->sc_flags &= ~RTK_ATTACHED; 852 853 return 0; 854 } 855 856 /* 857 * rtk_enable: 858 * Enable the RTL81X9 chip. 859 */ 860 int 861 rtk_enable(struct rtk_softc *sc) 862 { 863 864 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 865 if ((*sc->sc_enable)(sc) != 0) { 866 printf("%s: device enable failed\n", 867 device_xname(sc->sc_dev)); 868 return EIO; 869 } 870 sc->sc_flags |= RTK_ENABLED; 871 } 872 return 0; 873 } 874 875 /* 876 * rtk_disable: 877 * Disable the RTL81X9 chip. 878 */ 879 void 880 rtk_disable(struct rtk_softc *sc) 881 { 882 883 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 884 (*sc->sc_disable)(sc); 885 sc->sc_flags &= ~RTK_ENABLED; 886 } 887 } 888 889 /* 890 * A frame has been uploaded: pass the resulting mbuf chain up to 891 * the higher level protocols. 892 * 893 * You know there's something wrong with a PCI bus-master chip design. 894 * 895 * The receive operation is badly documented in the datasheet, so I'll 896 * attempt to document it here. The driver provides a buffer area and 897 * places its base address in the RX buffer start address register. 898 * The chip then begins copying frames into the RX buffer. Each frame 899 * is preceded by a 32-bit RX status word which specifies the length 900 * of the frame and certain other status bits. Each frame (starting with 901 * the status word) is also 32-bit aligned. The frame length is in the 902 * first 16 bits of the status word; the lower 15 bits correspond with 903 * the 'rx status register' mentioned in the datasheet. 904 * 905 * Note: to make the Alpha happy, the frame payload needs to be aligned 906 * on a 32-bit boundary. To achieve this, we copy the data to mbuf 907 * shifted forward 2 bytes. 908 */ 909 static void 910 rtk_rxeof(struct rtk_softc *sc) 911 { 912 struct mbuf *m; 913 struct ifnet *ifp; 914 uint8_t *rxbufpos, *dst; 915 u_int total_len, wrap; 916 uint32_t rxstat; 917 uint16_t cur_rx, new_rx; 918 uint16_t limit; 919 uint16_t rx_bytes, max_bytes; 920 921 ifp = &sc->ethercom.ec_if; 922 923 cur_rx = (CSR_READ_2(sc, RTK_CURRXADDR) + 16) % RTK_RXBUFLEN; 924 925 /* Do not try to read past this point. */ 926 limit = CSR_READ_2(sc, RTK_CURRXBUF) % RTK_RXBUFLEN; 927 928 if (limit < cur_rx) 929 max_bytes = (RTK_RXBUFLEN - cur_rx) + limit; 930 else 931 max_bytes = limit - cur_rx; 932 rx_bytes = 0; 933 934 while ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_EMPTY_RXBUF) == 0) { 935 rxbufpos = sc->rtk_rx_buf + cur_rx; 936 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 937 RTK_RXSTAT_LEN, BUS_DMASYNC_POSTREAD); 938 rxstat = le32toh(*(uint32_t *)rxbufpos); 939 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 940 RTK_RXSTAT_LEN, BUS_DMASYNC_PREREAD); 941 942 /* 943 * Here's a totally undocumented fact for you. When the 944 * RealTek chip is in the process of copying a packet into 945 * RAM for you, the length will be 0xfff0. If you spot a 946 * packet header with this value, you need to stop. The 947 * datasheet makes absolutely no mention of this and 948 * RealTek should be shot for this. 949 */ 950 total_len = rxstat >> 16; 951 if (total_len == RTK_RXSTAT_UNFINISHED) 952 break; 953 954 if ((rxstat & RTK_RXSTAT_RXOK) == 0 || 955 total_len < ETHER_MIN_LEN || 956 total_len > (MCLBYTES - RTK_ETHER_ALIGN)) { 957 ifp->if_ierrors++; 958 959 /* 960 * submitted by:[netbsd-pcmcia:00484] 961 * Takahiro Kambe <taca@sky.yamashina.kyoto.jp> 962 * obtain from: 963 * FreeBSD if_rl.c rev 1.24->1.25 964 * 965 */ 966 #if 0 967 if (rxstat & (RTK_RXSTAT_BADSYM|RTK_RXSTAT_RUNT| 968 RTK_RXSTAT_GIANT|RTK_RXSTAT_CRCERR| 969 RTK_RXSTAT_ALIGNERR)) { 970 CSR_WRITE_2(sc, RTK_COMMAND, RTK_CMD_TX_ENB); 971 CSR_WRITE_2(sc, RTK_COMMAND, 972 RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 973 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 974 CSR_WRITE_4(sc, RTK_RXADDR, 975 sc->recv_dmamap->dm_segs[0].ds_addr); 976 cur_rx = 0; 977 } 978 break; 979 #else 980 rtk_init(ifp); 981 return; 982 #endif 983 } 984 985 /* No errors; receive the packet. */ 986 rx_bytes += total_len + RTK_RXSTAT_LEN; 987 988 /* 989 * Avoid trying to read more bytes than we know 990 * the chip has prepared for us. 991 */ 992 if (rx_bytes > max_bytes) 993 break; 994 995 /* 996 * Skip the status word, wrapping around to the beginning 997 * of the Rx area, if necessary. 998 */ 999 cur_rx = (cur_rx + RTK_RXSTAT_LEN) % RTK_RXBUFLEN; 1000 rxbufpos = sc->rtk_rx_buf + cur_rx; 1001 1002 /* 1003 * Compute the number of bytes at which the packet 1004 * will wrap to the beginning of the ring buffer. 1005 */ 1006 wrap = RTK_RXBUFLEN - cur_rx; 1007 1008 /* 1009 * Compute where the next pending packet is. 1010 */ 1011 if (total_len > wrap) 1012 new_rx = total_len - wrap; 1013 else 1014 new_rx = cur_rx + total_len; 1015 /* Round up to 32-bit boundary. */ 1016 new_rx = roundup2(new_rx, sizeof(uint32_t)) % RTK_RXBUFLEN; 1017 1018 /* 1019 * The RealTek chip includes the CRC with every 1020 * incoming packet; trim it off here. 1021 */ 1022 total_len -= ETHER_CRC_LEN; 1023 1024 /* 1025 * Now allocate an mbuf (and possibly a cluster) to hold 1026 * the packet. Note we offset the packet 2 bytes so that 1027 * data after the Ethernet header will be 4-byte aligned. 1028 */ 1029 MGETHDR(m, M_DONTWAIT, MT_DATA); 1030 if (m == NULL) { 1031 printf("%s: unable to allocate Rx mbuf\n", 1032 device_xname(sc->sc_dev)); 1033 ifp->if_ierrors++; 1034 goto next_packet; 1035 } 1036 if (total_len > (MHLEN - RTK_ETHER_ALIGN)) { 1037 MCLGET(m, M_DONTWAIT); 1038 if ((m->m_flags & M_EXT) == 0) { 1039 printf("%s: unable to allocate Rx cluster\n", 1040 device_xname(sc->sc_dev)); 1041 ifp->if_ierrors++; 1042 m_freem(m); 1043 m = NULL; 1044 goto next_packet; 1045 } 1046 } 1047 m->m_data += RTK_ETHER_ALIGN; /* for alignment */ 1048 m->m_pkthdr.rcvif = ifp; 1049 m->m_pkthdr.len = m->m_len = total_len; 1050 dst = mtod(m, void *); 1051 1052 /* 1053 * If the packet wraps, copy up to the wrapping point. 1054 */ 1055 if (total_len > wrap) { 1056 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1057 cur_rx, wrap, BUS_DMASYNC_POSTREAD); 1058 memcpy(dst, rxbufpos, wrap); 1059 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1060 cur_rx, wrap, BUS_DMASYNC_PREREAD); 1061 cur_rx = 0; 1062 rxbufpos = sc->rtk_rx_buf; 1063 total_len -= wrap; 1064 dst += wrap; 1065 } 1066 1067 /* 1068 * ...and now the rest. 1069 */ 1070 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1071 cur_rx, total_len, BUS_DMASYNC_POSTREAD); 1072 memcpy(dst, rxbufpos, total_len); 1073 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1074 cur_rx, total_len, BUS_DMASYNC_PREREAD); 1075 1076 next_packet: 1077 CSR_WRITE_2(sc, RTK_CURRXADDR, (new_rx - 16) % RTK_RXBUFLEN); 1078 cur_rx = new_rx; 1079 1080 if (m == NULL) 1081 continue; 1082 1083 ifp->if_ipackets++; 1084 1085 bpf_mtap(ifp, m); 1086 /* pass it on. */ 1087 (*ifp->if_input)(ifp, m); 1088 } 1089 } 1090 1091 /* 1092 * A frame was downloaded to the chip. It's safe for us to clean up 1093 * the list buffers. 1094 */ 1095 static void 1096 rtk_txeof(struct rtk_softc *sc) 1097 { 1098 struct ifnet *ifp; 1099 struct rtk_tx_desc *txd; 1100 uint32_t txstat; 1101 1102 ifp = &sc->ethercom.ec_if; 1103 1104 /* 1105 * Go through our tx list and free mbufs for those 1106 * frames that have been uploaded. 1107 */ 1108 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) { 1109 txstat = CSR_READ_4(sc, txd->txd_txstat); 1110 if ((txstat & (RTK_TXSTAT_TX_OK| 1111 RTK_TXSTAT_TX_UNDERRUN|RTK_TXSTAT_TXABRT)) == 0) 1112 break; 1113 1114 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q); 1115 1116 bus_dmamap_sync(sc->sc_dmat, txd->txd_dmamap, 0, 1117 txd->txd_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1118 bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap); 1119 m_freem(txd->txd_mbuf); 1120 txd->txd_mbuf = NULL; 1121 1122 ifp->if_collisions += (txstat & RTK_TXSTAT_COLLCNT) >> 24; 1123 1124 if (txstat & RTK_TXSTAT_TX_OK) 1125 ifp->if_opackets++; 1126 else { 1127 ifp->if_oerrors++; 1128 1129 /* 1130 * Increase Early TX threshold if underrun occurred. 1131 * Increase step 64 bytes. 1132 */ 1133 if (txstat & RTK_TXSTAT_TX_UNDERRUN) { 1134 #ifdef DEBUG 1135 printf("%s: transmit underrun;", 1136 device_xname(sc->sc_dev)); 1137 #endif 1138 if (sc->sc_txthresh < RTK_TXTH_MAX) { 1139 sc->sc_txthresh += 2; 1140 #ifdef DEBUG 1141 printf(" new threshold: %d bytes", 1142 sc->sc_txthresh * 32); 1143 #endif 1144 } 1145 #ifdef DEBUG 1146 printf("\n"); 1147 #endif 1148 } 1149 if (txstat & (RTK_TXSTAT_TXABRT|RTK_TXSTAT_OUTOFWIN)) 1150 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1151 } 1152 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q); 1153 ifp->if_flags &= ~IFF_OACTIVE; 1154 } 1155 1156 /* Clear the timeout timer if there is no pending packet. */ 1157 if (SIMPLEQ_EMPTY(&sc->rtk_tx_dirty)) 1158 ifp->if_timer = 0; 1159 1160 } 1161 1162 int 1163 rtk_intr(void *arg) 1164 { 1165 struct rtk_softc *sc; 1166 struct ifnet *ifp; 1167 uint16_t status; 1168 int handled; 1169 1170 sc = arg; 1171 ifp = &sc->ethercom.ec_if; 1172 1173 if (!device_has_power(sc->sc_dev)) 1174 return 0; 1175 1176 /* Disable interrupts. */ 1177 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1178 1179 handled = 0; 1180 for (;;) { 1181 1182 status = CSR_READ_2(sc, RTK_ISR); 1183 1184 if (status == 0xffff) 1185 break; /* Card is gone... */ 1186 1187 if (status) 1188 CSR_WRITE_2(sc, RTK_ISR, status); 1189 1190 if ((status & RTK_INTRS) == 0) 1191 break; 1192 1193 handled = 1; 1194 1195 if (status & RTK_ISR_RX_OK) 1196 rtk_rxeof(sc); 1197 1198 if (status & RTK_ISR_RX_ERR) 1199 rtk_rxeof(sc); 1200 1201 if (status & (RTK_ISR_TX_OK|RTK_ISR_TX_ERR)) 1202 rtk_txeof(sc); 1203 1204 if (status & RTK_ISR_SYSTEM_ERR) { 1205 rtk_reset(sc); 1206 rtk_init(ifp); 1207 } 1208 } 1209 1210 /* Re-enable interrupts. */ 1211 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS); 1212 1213 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 1214 rtk_start(ifp); 1215 1216 #if NRND > 0 1217 if (RND_ENABLED(&sc->rnd_source)) 1218 rnd_add_uint32(&sc->rnd_source, status); 1219 #endif 1220 1221 return handled; 1222 } 1223 1224 /* 1225 * Main transmit routine. 1226 */ 1227 1228 static void 1229 rtk_start(struct ifnet *ifp) 1230 { 1231 struct rtk_softc *sc; 1232 struct rtk_tx_desc *txd; 1233 struct mbuf *m_head, *m_new; 1234 int error, len; 1235 1236 sc = ifp->if_softc; 1237 1238 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL) { 1239 IFQ_POLL(&ifp->if_snd, m_head); 1240 if (m_head == NULL) 1241 break; 1242 m_new = NULL; 1243 1244 /* 1245 * Load the DMA map. If this fails, the packet didn't 1246 * fit in one DMA segment, and we need to copy. Note, 1247 * the packet must also be aligned. 1248 * if the packet is too small, copy it too, so we're sure 1249 * so have enough room for the pad buffer. 1250 */ 1251 if ((mtod(m_head, uintptr_t) & 3) != 0 || 1252 m_head->m_pkthdr.len < ETHER_PAD_LEN || 1253 bus_dmamap_load_mbuf(sc->sc_dmat, txd->txd_dmamap, 1254 m_head, BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1255 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1256 if (m_new == NULL) { 1257 printf("%s: unable to allocate Tx mbuf\n", 1258 device_xname(sc->sc_dev)); 1259 break; 1260 } 1261 if (m_head->m_pkthdr.len > MHLEN) { 1262 MCLGET(m_new, M_DONTWAIT); 1263 if ((m_new->m_flags & M_EXT) == 0) { 1264 printf("%s: unable to allocate Tx " 1265 "cluster\n", 1266 device_xname(sc->sc_dev)); 1267 m_freem(m_new); 1268 break; 1269 } 1270 } 1271 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1272 mtod(m_new, void *)); 1273 m_new->m_pkthdr.len = m_new->m_len = 1274 m_head->m_pkthdr.len; 1275 if (m_head->m_pkthdr.len < ETHER_PAD_LEN) { 1276 memset( 1277 mtod(m_new, char *) + m_head->m_pkthdr.len, 1278 0, ETHER_PAD_LEN - m_head->m_pkthdr.len); 1279 m_new->m_pkthdr.len = m_new->m_len = 1280 ETHER_PAD_LEN; 1281 } 1282 error = bus_dmamap_load_mbuf(sc->sc_dmat, 1283 txd->txd_dmamap, m_new, 1284 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1285 if (error) { 1286 printf("%s: unable to load Tx buffer, " 1287 "error = %d\n", 1288 device_xname(sc->sc_dev), error); 1289 break; 1290 } 1291 } 1292 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1293 /* 1294 * If there's a BPF listener, bounce a copy of this frame 1295 * to him. 1296 */ 1297 bpf_mtap(ifp, m_head); 1298 if (m_new != NULL) { 1299 m_freem(m_head); 1300 m_head = m_new; 1301 } 1302 txd->txd_mbuf = m_head; 1303 1304 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_free, txd_q); 1305 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_dirty, txd, txd_q); 1306 1307 /* 1308 * Transmit the frame. 1309 */ 1310 bus_dmamap_sync(sc->sc_dmat, 1311 txd->txd_dmamap, 0, txd->txd_dmamap->dm_mapsize, 1312 BUS_DMASYNC_PREWRITE); 1313 1314 len = txd->txd_dmamap->dm_segs[0].ds_len; 1315 1316 CSR_WRITE_4(sc, txd->txd_txaddr, 1317 txd->txd_dmamap->dm_segs[0].ds_addr); 1318 CSR_WRITE_4(sc, txd->txd_txstat, 1319 RTK_TXSTAT_THRESH(sc->sc_txthresh) | len); 1320 1321 /* 1322 * Set a timeout in case the chip goes out to lunch. 1323 */ 1324 ifp->if_timer = 5; 1325 } 1326 1327 /* 1328 * We broke out of the loop because all our TX slots are 1329 * full. Mark the NIC as busy until it drains some of the 1330 * packets from the queue. 1331 */ 1332 if (SIMPLEQ_EMPTY(&sc->rtk_tx_free)) 1333 ifp->if_flags |= IFF_OACTIVE; 1334 } 1335 1336 static int 1337 rtk_init(struct ifnet *ifp) 1338 { 1339 struct rtk_softc *sc = ifp->if_softc; 1340 int error, i; 1341 uint32_t rxcfg; 1342 1343 if ((error = rtk_enable(sc)) != 0) 1344 goto out; 1345 1346 /* 1347 * Cancel pending I/O. 1348 */ 1349 rtk_stop(ifp, 0); 1350 1351 /* Init our MAC address */ 1352 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1353 CSR_WRITE_1(sc, RTK_IDR0 + i, CLLADDR(ifp->if_sadl)[i]); 1354 } 1355 1356 /* Init the RX buffer pointer register. */ 1357 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 0, 1358 sc->recv_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1359 CSR_WRITE_4(sc, RTK_RXADDR, sc->recv_dmamap->dm_segs[0].ds_addr); 1360 1361 /* Init TX descriptors. */ 1362 rtk_list_tx_init(sc); 1363 1364 /* Init Early TX threshold. */ 1365 sc->sc_txthresh = RTK_TXTH_256; 1366 /* 1367 * Enable transmit and receive. 1368 */ 1369 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1370 1371 /* 1372 * Set the initial TX and RX configuration. 1373 */ 1374 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1375 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1376 1377 /* Set the individual bit to receive frames for this host only. */ 1378 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1379 rxcfg |= RTK_RXCFG_RX_INDIV; 1380 1381 /* If we want promiscuous mode, set the allframes bit. */ 1382 if (ifp->if_flags & IFF_PROMISC) { 1383 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1384 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1385 } else { 1386 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1387 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1388 } 1389 1390 /* 1391 * Set capture broadcast bit to capture broadcast frames. 1392 */ 1393 if (ifp->if_flags & IFF_BROADCAST) { 1394 rxcfg |= RTK_RXCFG_RX_BROAD; 1395 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1396 } else { 1397 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1398 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1399 } 1400 1401 /* 1402 * Program the multicast filter, if necessary. 1403 */ 1404 rtk_setmulti(sc); 1405 1406 /* 1407 * Enable interrupts. 1408 */ 1409 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS); 1410 1411 /* Start RX/TX process. */ 1412 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1413 1414 /* Enable receiver and transmitter. */ 1415 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1416 1417 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD|RTK_CFG1_FULLDUPLEX); 1418 1419 /* 1420 * Set current media. 1421 */ 1422 if ((error = ether_mediachange(ifp)) != 0) 1423 goto out; 1424 1425 ifp->if_flags |= IFF_RUNNING; 1426 ifp->if_flags &= ~IFF_OACTIVE; 1427 1428 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc); 1429 1430 out: 1431 if (error) { 1432 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1433 ifp->if_timer = 0; 1434 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1435 } 1436 return error; 1437 } 1438 1439 static int 1440 rtk_ioctl(struct ifnet *ifp, u_long command, void *data) 1441 { 1442 struct rtk_softc *sc = ifp->if_softc; 1443 int s, error; 1444 1445 s = splnet(); 1446 error = ether_ioctl(ifp, command, data); 1447 if (error == ENETRESET) { 1448 if (ifp->if_flags & IFF_RUNNING) { 1449 /* 1450 * Multicast list has changed. Set the 1451 * hardware filter accordingly. 1452 */ 1453 rtk_setmulti(sc); 1454 } 1455 error = 0; 1456 } 1457 splx(s); 1458 1459 return error; 1460 } 1461 1462 static void 1463 rtk_watchdog(struct ifnet *ifp) 1464 { 1465 struct rtk_softc *sc; 1466 1467 sc = ifp->if_softc; 1468 1469 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1470 ifp->if_oerrors++; 1471 rtk_txeof(sc); 1472 rtk_rxeof(sc); 1473 rtk_init(ifp); 1474 } 1475 1476 /* 1477 * Stop the adapter and free any mbufs allocated to the 1478 * RX and TX lists. 1479 */ 1480 static void 1481 rtk_stop(struct ifnet *ifp, int disable) 1482 { 1483 struct rtk_softc *sc = ifp->if_softc; 1484 struct rtk_tx_desc *txd; 1485 1486 callout_stop(&sc->rtk_tick_ch); 1487 1488 mii_down(&sc->mii); 1489 1490 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 1491 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1492 1493 /* 1494 * Free the TX list buffers. 1495 */ 1496 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) { 1497 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q); 1498 bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap); 1499 m_freem(txd->txd_mbuf); 1500 txd->txd_mbuf = NULL; 1501 CSR_WRITE_4(sc, txd->txd_txaddr, 0); 1502 } 1503 1504 if (disable) 1505 rtk_disable(sc); 1506 1507 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1508 ifp->if_timer = 0; 1509 } 1510 1511 static void 1512 rtk_tick(void *arg) 1513 { 1514 struct rtk_softc *sc = arg; 1515 int s; 1516 1517 s = splnet(); 1518 mii_tick(&sc->mii); 1519 splx(s); 1520 1521 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc); 1522 } 1523