1 /* $NetBSD: rtl81x9reg.h,v 1.6 2001/01/31 07:44:51 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_rlreg.h,v 1.9 1999/06/20 18:56:09 wpaul Exp 35 */ 36 37 /* 38 * RealTek 8129/8139 register offsets 39 */ 40 #define RTK_IDR0 0x0000 /* ID register 0 (station addr) */ 41 #define RTK_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 42 #define RTK_IDR2 0x0002 43 #define RTK_IDR3 0x0003 44 #define RTK_IDR4 0x0004 45 #define RTK_IDR5 0x0005 46 /* 0006-0007 reserved */ 47 #define RTK_MAR0 0x0008 /* Multicast hash table */ 48 #define RTK_MAR1 0x0009 49 #define RTK_MAR2 0x000A 50 #define RTK_MAR3 0x000B 51 #define RTK_MAR4 0x000C 52 #define RTK_MAR5 0x000D 53 #define RTK_MAR6 0x000E 54 #define RTK_MAR7 0x000F 55 56 #define RTK_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 57 #define RTK_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 58 #define RTK_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 59 #define RTK_TXSTAT3 0x001C /* status of TX descriptor 3 */ 60 61 #define RTK_TXADDR0 0x0020 /* address of TX descriptor 0 */ 62 #define RTK_TXADDR1 0x0024 /* address of TX descriptor 1 */ 63 #define RTK_TXADDR2 0x0028 /* address of TX descriptor 2 */ 64 #define RTK_TXADDR3 0x002C /* address of TX descriptor 3 */ 65 66 #define RTK_RXADDR 0x0030 /* RX ring start address */ 67 #define RTK_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 68 #define RTK_RX_EARLY_STAT 0x0036 /* RX early status */ 69 #define RTK_COMMAND 0x0037 /* command register */ 70 #define RTK_CURRXADDR 0x0038 /* current address of packet read */ 71 #define RTK_CURRXBUF 0x003A /* current RX buffer address */ 72 #define RTK_IMR 0x003C /* interrupt mask register */ 73 #define RTK_ISR 0x003E /* interrupt status register */ 74 #define RTK_TXCFG 0x0040 /* transmit config */ 75 #define RTK_RXCFG 0x0044 /* receive config */ 76 #define RTK_TIMERCNT 0x0048 /* timer count register */ 77 #define RTK_MISSEDPKT 0x004C /* missed packet counter */ 78 #define RTK_EECMD 0x0050 /* EEPROM command register */ 79 #define RTK_CFG0 0x0051 /* config register #0 */ 80 #define RTK_CFG1 0x0052 /* config register #1 */ 81 /* 0053-0057 reserved */ 82 #define RTK_MEDIASTAT 0x0058 /* media status register (8139) */ 83 /* 0059-005A reserved */ 84 #define RTK_MII 0x005A /* 8129 chip only */ 85 #define RTK_HALTCLK 0x005B 86 #define RTK_MULTIINTR 0x005C /* multiple interrupt */ 87 #define RTK_PCIREV 0x005E /* PCI revision value */ 88 /* 005F reserved */ 89 #define RTK_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 90 91 /* Direct PHY access registers only available on 8139 */ 92 #define RTK_BMCR 0x0062 /* PHY basic mode control */ 93 #define RTK_BMSR 0x0064 /* PHY basic mode status */ 94 #define RTK_ANAR 0x0066 /* PHY autoneg advert */ 95 #define RTK_LPAR 0x0068 /* PHY link partner ability */ 96 #define RTK_ANER 0x006A /* PHY autoneg expansion */ 97 98 #define RTK_DISCCNT 0x006C /* disconnect counter */ 99 #define RTK_FALSECAR 0x006E /* false carrier counter */ 100 #define RTK_NWAYTST 0x0070 /* NWAY test register */ 101 #define RTK_RX_ER 0x0072 /* RX_ER counter */ 102 #define RTK_CSCFG 0x0074 /* CS configuration register */ 103 104 105 /* 106 * TX config register bits 107 */ 108 #define RTK_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 109 #define RTK_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 110 #define RTK_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 111 #define RTK_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 112 #define RTK_TXCFG_IFG 0x03000000 /* interframe gap */ 113 114 #define RTK_TXDMA_16BYTES 0x00000000 115 #define RTK_TXDMA_32BYTES 0x00000100 116 #define RTK_TXDMA_64BYTES 0x00000200 117 #define RTK_TXDMA_128BYTES 0x00000300 118 #define RTK_TXDMA_256BYTES 0x00000400 119 #define RTK_TXDMA_512BYTES 0x00000500 120 #define RTK_TXDMA_1024BYTES 0x00000600 121 #define RTK_TXDMA_2048BYTES 0x00000700 122 123 /* 124 * Transmit descriptor status register bits. 125 */ 126 #define RTK_TXSTAT_LENMASK 0x00001FFF 127 #define RTK_TXSTAT_OWN 0x00002000 128 #define RTK_TXSTAT_TX_UNDERRUN 0x00004000 129 #define RTK_TXSTAT_TX_OK 0x00008000 130 #define RTK_TXSTAT_EARLY_THRESH 0x003F0000 131 #define RTK_TXSTAT_COLLCNT 0x0F000000 132 #define RTK_TXSTAT_CARR_HBEAT 0x10000000 133 #define RTK_TXSTAT_OUTOFWIN 0x20000000 134 #define RTK_TXSTAT_TXABRT 0x40000000 135 #define RTK_TXSTAT_CARRLOSS 0x80000000 136 137 /* 138 * Interrupt status register bits. 139 */ 140 #define RTK_ISR_RX_OK 0x0001 141 #define RTK_ISR_RX_ERR 0x0002 142 #define RTK_ISR_TX_OK 0x0004 143 #define RTK_ISR_TX_ERR 0x0008 144 #define RTK_ISR_RX_OVERRUN 0x0010 145 #define RTK_ISR_PKT_UNDERRUN 0x0020 146 #define RTK_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 147 #define RTK_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 148 #define RTK_ISR_SYSTEM_ERR 0x8000 149 150 #define RTK_INTRS \ 151 (RTK_ISR_TX_OK|RTK_ISR_RX_OK|RTK_ISR_RX_ERR|RTK_ISR_TX_ERR| \ 152 RTK_ISR_RX_OVERRUN|RTK_ISR_PKT_UNDERRUN|RTK_ISR_FIFO_OFLOW| \ 153 RTK_ISR_PCS_TIMEOUT|RTK_ISR_SYSTEM_ERR) 154 155 /* 156 * Media status register. (8139 only) 157 */ 158 #define RTK_MEDIASTAT_RXPAUSE 0x01 159 #define RTK_MEDIASTAT_TXPAUSE 0x02 160 #define RTK_MEDIASTAT_LINK 0x04 161 #define RTK_MEDIASTAT_SPEED10 0x08 162 #define RTK_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 163 #define RTK_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 164 165 /* 166 * Receive config register. 167 */ 168 #define RTK_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 169 #define RTK_RXCFG_RX_INDIV 0x00000002 /* match filter */ 170 #define RTK_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 171 #define RTK_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 172 #define RTK_RXCFG_RX_RUNT 0x00000010 173 #define RTK_RXCFG_RX_ERRPKT 0x00000020 174 #define RTK_RXCFG_WRAP 0x00000080 175 #define RTK_RXCFG_MAXDMA 0x00000700 176 #define RTK_RXCFG_BUFSZ 0x00001800 177 #define RTK_RXCFG_FIFOTHRESH 0x0000E000 178 #define RTK_RXCFG_EARLYTHRESH 0x07000000 179 180 #define RTK_RXDMA_16BYTES 0x00000000 181 #define RTK_RXDMA_32BYTES 0x00000100 182 #define RTK_RXDMA_64BYTES 0x00000200 183 #define RTK_RXDMA_128BYTES 0x00000300 184 #define RTK_RXDMA_256BYTES 0x00000400 185 #define RTK_RXDMA_512BYTES 0x00000500 186 #define RTK_RXDMA_1024BYTES 0x00000600 187 #define RTK_RXDMA_UNLIMITED 0x00000700 188 189 #define RTK_RXBUF_8 0x00000000 190 #define RTK_RXBUF_16 0x00000800 191 #define RTK_RXBUF_32 0x00001000 192 #define RTK_RXBUF_64 0x00001800 193 194 #define RTK_RXFIFO_16BYTES 0x00000000 195 #define RTK_RXFIFO_32BYTES 0x00002000 196 #define RTK_RXFIFO_64BYTES 0x00004000 197 #define RTK_RXFIFO_128BYTES 0x00006000 198 #define RTK_RXFIFO_256BYTES 0x00008000 199 #define RTK_RXFIFO_512BYTES 0x0000A000 200 #define RTK_RXFIFO_1024BYTES 0x0000C000 201 #define RTK_RXFIFO_NOTHRESH 0x0000E000 202 203 /* 204 * Bits in RX status header (included with RX'ed packet 205 * in ring buffer). 206 */ 207 #define RTK_RXSTAT_RXOK 0x00000001 208 #define RTK_RXSTAT_ALIGNERR 0x00000002 209 #define RTK_RXSTAT_CRCERR 0x00000004 210 #define RTK_RXSTAT_GIANT 0x00000008 211 #define RTK_RXSTAT_RUNT 0x00000010 212 #define RTK_RXSTAT_BADSYM 0x00000020 213 #define RTK_RXSTAT_BROAD 0x00002000 214 #define RTK_RXSTAT_INDIV 0x00004000 215 #define RTK_RXSTAT_MULTI 0x00008000 216 #define RTK_RXSTAT_LENMASK 0xFFFF0000 217 218 #define RTK_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 219 /* 220 * Command register. 221 */ 222 #define RTK_CMD_EMPTY_RXBUF 0x0001 223 #define RTK_CMD_TX_ENB 0x0004 224 #define RTK_CMD_RX_ENB 0x0008 225 #define RTK_CMD_RESET 0x0010 226 227 /* 228 * EEPROM control register 229 */ 230 #define RTK_EE_DATAOUT 0x01 /* Data out */ 231 #define RTK_EE_DATAIN 0x02 /* Data in */ 232 #define RTK_EE_CLK 0x04 /* clock */ 233 #define RTK_EE_SEL 0x08 /* chip select */ 234 #define RTK_EE_MODE (0x40|0x80) 235 236 #define RTK_EEMODE_OFF 0x00 237 #define RTK_EEMODE_AUTOLOAD 0x40 238 #define RTK_EEMODE_PROGRAM 0x80 239 #define RTK_EEMODE_WRITECFG (0x80|0x40) 240 241 /* 9346/9356 EEPROM commands */ 242 #define RTK_EEADDR_LEN0 6 /* 9346 */ 243 #define RTK_EEADDR_LEN1 8 /* 9356 */ 244 #define RTK_EECMD_LEN 4 245 246 #define RTK_EECMD_WRITE 0x5 /* 0101b */ 247 #define RTK_EECMD_READ 0x6 /* 0110b */ 248 #define RTK_EECMD_ERASE 0x7 /* 0111b */ 249 250 #define RTK_EE_ID 0x00 251 #define RTK_EE_PCI_VID 0x01 252 #define RTK_EE_PCI_DID 0x02 253 /* Location of station address inside EEPROM */ 254 #define RTK_EE_EADDR0 0x07 255 #define RTK_EE_EADDR1 0x08 256 #define RTK_EE_EADDR2 0x09 257 258 /* 259 * MII register (8129 only) 260 */ 261 #define RTK_MII_CLK 0x01 262 #define RTK_MII_DATAIN 0x02 263 #define RTK_MII_DATAOUT 0x04 264 #define RTK_MII_DIR 0x80 /* 0 == input, 1 == output */ 265 266 /* 267 * Config 0 register 268 */ 269 #define RTK_CFG0_ROM0 0x01 270 #define RTK_CFG0_ROM1 0x02 271 #define RTK_CFG0_ROM2 0x04 272 #define RTK_CFG0_PL0 0x08 273 #define RTK_CFG0_PL1 0x10 274 #define RTK_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 275 #define RTK_CFG0_PCS 0x40 276 #define RTK_CFG0_SCR 0x80 277 278 /* 279 * Config 1 register 280 */ 281 #define RTK_CFG1_PWRDWN 0x01 282 #define RTK_CFG1_SLEEP 0x02 283 #define RTK_CFG1_IOMAP 0x04 284 #define RTK_CFG1_MEMMAP 0x08 285 #define RTK_CFG1_RSVD 0x10 286 #define RTK_CFG1_DRVLOAD 0x20 287 #define RTK_CFG1_LED0 0x40 288 #define RTK_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 289 #define RTK_CFG1_LED1 0x80 290 291 /* 292 * The RealTek doesn't use a fragment-based descriptor mechanism. 293 * Instead, there are only four register sets, each or which represents 294 * one 'descriptor.' Basically, each TX descriptor is just a contiguous 295 * packet buffer (32-bit aligned!) and we place the buffer addresses in 296 * the registers so the chip knows where they are. 297 * 298 * We can sort of kludge together the same kind of buffer management 299 * used in previous drivers, but we have to do buffer copies almost all 300 * the time, so it doesn't really buy us much. 301 * 302 * For reception, there's just one large buffer where the chip stores 303 * all received packets. 304 */ 305 306 #ifdef dreamcast 307 #define RTK_RX_BUF_SZ RTK_RXBUF_16 308 #else 309 #define RTK_RX_BUF_SZ RTK_RXBUF_64 310 #endif 311 #define RTK_RXBUFLEN (1 << ((RTK_RX_BUF_SZ >> 11) + 13)) 312 #define RTK_TX_LIST_CNT 4 313 #define RTK_TX_EARLYTHRESH ((256 / 32) << 16) 314 #define RTK_RX_FIFOTHRESH RTK_RXFIFO_256BYTES 315 #define RTK_RX_MAXDMA RTK_RXDMA_256BYTES 316 #define RTK_TX_MAXDMA RTK_TXDMA_256BYTES 317 318 #define RTK_RXCFG_CONFIG (RTK_RX_FIFOTHRESH|RTK_RX_MAXDMA|RTK_RX_BUF_SZ) 319 #define RTK_TXCFG_CONFIG (RTK_TXCFG_IFG|RTK_TX_MAXDMA) 320