1 /* $NetBSD: sm502reg.h,v 1.1 2009/08/12 19:28:00 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2009 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* Silicon Motion SM502 / Voyager GX register definitions */ 29 30 #ifndef SM502REG_H 31 #define SM502REG_H 32 33 /* System Control Registers */ 34 #define SM502_SYSTEM_CTRL 0x00000000 35 #define SM502_SYSCTL_PANEL_3STATE 0x00000001 36 #define SM502_SYSCTL_MEM_3STATE 0x00000002 37 #define SM502_SYSCTL_CRT_3STATE 0x00000004 38 #define SM502_SYSCTL_BURST_32 0x00000000 39 #define SM502_SYSCTL_BURST_64 0x00000010 40 #define SM502_SYSCTL_BURST_128 0x00000020 41 #define SM502_SYSCTL_BURST_256 0x00000030 42 #define SM502_SYSCTL_PCI_CLOCK_RUN_E 0x00000040 43 #define SM502_SYSCTL_PCI_RETRY_E 0x00000080 44 #define SM502_SYSCTL_PCI_LOCK 0x00000800 45 /* stop drawing engine */ 46 #define SM502_SYSCTL_ENGINE_ABORT 0x00003000 47 #define SM502_SYSCTL_BURST_READ_E 0x00008000 48 #define SM502_SYSCTL_ZV_VSYNC_DET 0x00010000 49 #define SM502_SYSCTL_CRT_FLIP_PENDING 0x00020000 50 #define SM502_SYSCTL_ENGINE_BUSY 0x00080000 51 #define SM502_SYSCTL_FIFO_EMPTY 0x00100000 52 #define SM502_SYSCTL_VIDEO_FLIP_PENDING 0x00400000 53 #define SM502_SYSCTL_PANEL_FLIP_PENDING 0x00800000 54 #define SM502_SYSCTL_PCI_LT_E 0x01000000 55 #define SM502_SYSCTL_PCI_BM_E 0x02000000 56 #define SM502_SYSCTL_CSC_BUSY 0x10000000 57 #define SM502_SYSCTL_PCI_BURST_E 0x20000000 58 #define SM502_SYSCTL_DISABLE_HSYNC 0x40000000 59 #define SM502_SYSCTL_DISABLE_VSYNC 0x80000000 60 61 62 /* Video Controller Registers */ 63 #define SM502_PANEL_DISP_CRTL 0x080000 64 #define SM502_PDC_8BIT 0x00000000 65 #define SM502_PDC_16BIT 0x00000001 66 #define SM502_PDC_32BIT 0x00000002 67 #define SM502_PDC_DEPTH_MASK 0x00000003 68 #define SM502_PDC_PANEL_ENABLE 0x00000004 69 #define SM502_PDC_GAMMA_ENABLE 0x00000008 70 #define SM502_PDC_HPAN_AUTO 0x00000010 71 #define SM502_PDC_HPAN_DIR_LEFT 0x00000000 72 #define SM502_PDC_HPAN_DIR_RIGHT 0x00000020 73 #define SM502_PDC_VPAN_AUTO 0x00000040 74 #define SM502_PDC_VPAN_DIR_UP 0x00000080 75 #define SM502_PDC_VPAN_DIR_DOWN 0x00000000 76 #define SM502_PDC_TIMING_ENABLE 0x00000100 77 #define SM502_PDC_COLORKEY_ENABLE 0x00000200 78 #define SM502_PDC_CAPTURE_ZV_0 0x00000400 79 #define SM502_PDC_HSYNC_PHASE_LOW 0x00001000 80 #define SM502_PDC_HSYNC_PHASE_HIGH 0x00000000 81 #define SM502_PDC_VSYNC_PHASE_LOW 0x00002000 82 #define SM502_PDC_VSYNC_PHASE_HIGH 0x00000000 83 #define SM502_PDC_CLOCK_ACT_LOW 0x00004000 84 #define SM502_PDC_CLOCK_ACTIVE_HIGH 0x00000000 85 #define SM502_PDC_8BIT_TV_ENABLE 0x00008000 86 #define SM502_PDC_FIFO_HWATER_1 0x00000000 87 #define SM502_PDC_FIFO_HWATER_3 0x00010000 88 #define SM502_PDC_FIFO_HWATER_7 0x00020000 89 #define SM502_PDC_FIFO_HWATER_11 0x00030000 90 #define SM502_PDC_FIFO_HWATE_MASK 0x00030000 91 #define SM502_PDC_TYPE_TFT 0x00000000 92 #define SM502_PDC_TYPE_8BIT_STN 0x00040000 93 #define SM502_PDC_TYPE_12BIT_STN 0x00080000 94 #define SM502_PDC_TYPE_MASK 0x000c0000 95 #define SM502_PDC_DITHERING_ENABLE 0x00100000 96 #define SM502_PDC_TFT_RGB888 0x00000000 97 #define SM502_PDC_TFT_RGB333 0x00200000 98 #define SM502_PDC_TFT_RGB444 0x00400000 99 #define SM502_PDC_TFT_RGB_MASK 0x00600000 100 #define SM502_PDC_DITHER_8_GREY 0x00800000 101 #define SM502_PDC_FPVDDEN_HIGH 0x01000000 102 #define SM502_PDC_FPVDDEN_LOW 0x00000000 103 #define SM502_PDC_PANEL_SIGNALS_ENABLE 0x02000000 104 #define SM502_PDC_VBIASEN_HIGH 0x04000000 105 #define SM502_PDC_VBIASEN_LOW 0x00000000 106 #define SM502_PDC_GPEN_ENABLE 0x08000000 107 108 #define SM502_PANEL_PAN_CTRL 0x080004 109 #define SM502_PANEL_COLOR_KEY 0x080008 110 #define SM502_PANEL_FB_ADDRESS 0x08000C 111 #define SM502_FBA_MASK 0x03fffff0 /* 128bit align */ 112 #define SM502_FBA_CS1 0x04000000 113 #define SM502_FBA_CS0 0x00000000 114 #define SM502_FBA_SYSTEM_MEM 0x08000000 115 #define SM502_FBA_LOCAL_MEM 0x00000000 116 #define SM502_FBA_FLIP_PENDING 0x80000000 117 118 #define SM502_PANEL_FB_OFFSET 0x080010 119 #define SM502_FBO_FB_STRIDE_MASK 0x00003ff0 /* 128bit align */ 120 #define SM502_FBA_WIN_STRIDE_MASK 0x3ff00000 /* 128bit align */ 121 122 #define SM502_PANEL_FB_WIDTH 0x080014 123 #define SM502_FBW_WIN_X_MASK 0x00003fff 124 #define SM502_FBW_WIN_WIDTH_MASK 0x3fff0000 125 126 #define SM502_PANEL_FB_HEIGHT 0x080018 127 #define SM502_FBH_WIN_Y_MASK 0x00003fff 128 #define SM502_FBH_WIN_HEIGHT_MASK 0x3fff0000 129 #define SM502_PANEL_TL 0x08001C 130 #define SM502_TL_LEFT_MASK 0x000007ff 131 #define SM502_TL_TOP_MASK 0x07ff0000 132 133 #define SM502_PANEL_BR 0x080020 134 #define SM502_BR_RIGHT_MASK 0x000007ff 135 #define SM502_BR_BOTTOM_MASK 0x07ff0000 136 137 #define SM502_PANEL_HTOTAL 0x080024 138 #define SM502_HT_HDISPE_MASK 0x00000fff 139 #define SM502_HT_HTOTAL_MASK 0x0fff0000 140 #define SM502_PANEL_HSYNC 0x080028 141 #define SM502_PANEL_VTOTAL 0x08002C 142 #define SM502_VT_VDISPE_MASK 0x00000fff 143 #define SM502_VT_VTOTAL_MASK 0x0fff0000 144 #define SM502_PANEL_VSYNC 0x080030 145 146 #define SM502_PALETTE_PANEL 0x080400 147 #define SM502_PALETTE_VIDEO 0x080800 148 #define SM502_PALETTE_CRT 0x080c00 149 150 /* drawing engine */ 151 #define SM502_SRC 0x100000 152 #define SM502_SRC_WRAP_ENABLE 0x80000000 153 #define SM502_SRC_X_MASK 0x3fff0000 154 #define SM502_SRC_Y_MASK 0x0000ffff 155 156 #define SM502_DST 0x100004 157 #define SM502_DST_WRAP_ENABLE 0x80000000 158 #define SM502_DST_X_MASK 0x3fff0000 159 #define SM502_DST_Y_MASK 0x0000ffff 160 161 #define SM502_DIMENSION 0x100008 162 #define SM502_DIM_X_MASK 0x3fff0000 163 #define SM502_DIM_Y_MASK 0x0000ffff 164 165 #define SM502_CONTROL 0x10000c 166 #define ROP_COPY 0x0c 167 #define ROP_INVERT 0x03 168 #define SM502_CTRL_ROP_MASK 0x000000ff 169 #define SM502_CTRL_TRANSP_EN 0x00000100 170 #define SM502_CTRL_TRANSP_DST 0x00000200 171 #define SM502_CTRL_TRANSP_SRC 0x00000000 172 #define SM502_CTRL_TRANSP_MATCH 0x00000400 173 #define SM502_CTRL_OPAQUE_MATCH 0x00000000 174 #define SM502_CTRL_REPEAT_ROT 0x00000800 175 #define SM502_CTRL_MONO_PACK_MASK 0x00003000 176 #define SM502_CTRL_MONO_PACK_8BIT 0x00001000 177 #define SM502_CTRL_MONO_PACK_16BIT 0x00002000 178 #define SM502_CTRL_MONO_PACK_32BIT 0x00003000 179 #define SM502_CTRL_ROP2_SRC_PAT 0x00004000 /* otherwise src is bmp */ 180 #define SM502_CTRL_USE_ROP2 0x00008000 /* X-style ROPs vs. Win */ 181 #define SM502_CTRL_COMMAND_MASK 0x001f0000 182 #define SM502_CTRL_CMD_BITBLT 0x00000000 183 #define SM502_CTRL_CMD_RECTFILL 0x00010000 184 #define SM502_CTRL_CMD_DETILE 0x00020000 185 #define SM502_CTRL_CMD_TRAPFILL 0x00030000 186 #define SM502_CTRL_CMD_ALPHA 0x00040000 187 #define SM502_CTRL_CMD_RLESTRIP 0x00050000 188 #define SM502_CTRL_CMD_SHRTSTRK 0x00060000 189 #define SM502_CTRL_CMD_LINE 0x00070000 190 #define SM502_CTRL_CMD_HOSTWRT 0x00080000 191 #define SM502_CTRL_CMD_HOSTREAD 0x00090000 192 #define SM502_CTRL_CMD_WRT_BT 0x000a0000 193 #define SM502_CTRL_CMD_ROTATE 0x000b0000 194 #define SM502_CTRL_CMD_FONT 0x000c0000 195 #define SM502_CTRL_CMD_TEXLOAD 0x000f0000 196 #define SM502_CTRL_DRAWLAST 0x00200000 /* last pixel in line */ 197 #define SM502_CTRL_HOSTBLT_MONO 0x00400000 /* colour otherwise */ 198 #define SM502_CTRL_YSTRETCH_E 0x00800000 199 #define SM502_CTRL_Y_STEP_NEG 0x01000000 /* line, otherwise pos */ 200 #define SM502_CTRL_X_STEP_NEG 0x02000000 /* line, otherwise pos */ 201 #define SM502_CTRL_LINE_AX_Y 0x04000000 /* otherwise X */ 202 #define SM502_CTRL_R_TO_L 0x08000000 /* otherwise L to R */ 203 /* run command when writing SM502_DIMENSION */ 204 #define SM502_CTRL_QUICKSTART_E 0x10000000 205 #define SM502_CTRL_UPD_DESTX 0x20000000 206 #define SM502_CTRL_PAT_COLOR 0x40000000 /* otherwise mono */ 207 #define SM502_CTRL_ENGINE_START 0x80000000 208 209 #define SM502_PITCH 0x100010 210 #define SM502_PITCH_SRC_MASK 0x00003fff 211 #define SM502_PITCH_DST_MASK 0x3fff0000 212 213 #define SM502_FOREGROUND 0x100014 214 #define SM502_BACKGROUND 0x100018 215 #define SM502_STRETCH 0x10001c 216 #define SM502_STRETCH_HEIGHT_MASK 0x00000fff /* source */ 217 #define SM502_STRETCH_ADDR_LINEAR 0x000f0000 /* XY otherwise */ 218 #define SM502_STRETCH_PIXEL_FORMAT_MASK 0x00300000 219 #define SM502_STRETCH_8BIT 0x00000000 220 #define SM502_STRETCH_16BIT 0x00100000 221 #define SM502_STRETCH_32BIT 0x00200000 222 #define SM502_STRETCH_PAT_X_ORIGIN_MASK 0x03800000 223 #define SM502_STRETCH_PAT_Y_ORIGIN_MASK 0x38000000 224 #define SM502_STRETCH_PAT_XY_ENABLE 0x40000000 225 226 #define SM502_COLOR_COMPARE 0x100020 227 #define SM502_COLOR_COMP_MASK 0x100024 228 #define SM502_PLANEMASK 0x100028 229 #define SM502_CLIP_TOP_LEFT 0x10002c 230 #define SM501_CLIP_TOP_MASK 0xffff0000 231 #define SM501_CLIP_LEFT_MASK 0x00000fff 232 #define SM501_CLIP_BLOCK_INSIDE 0x00001000 /* otherwise block outside */ 233 #define SM501_CLIP_ENABLE 0x00002000 234 235 #define SM502_CLIP_BOTTOM_RIGHT 0x100030 236 #define SM501_CLIP_BOTTOM_MASK 0xffff0000 237 #define SM501_CLIP_RIGHT_MASK 0x00001fff 238 239 #define SM502_MONO_PATTERN_0 0x100034 240 #define SM502_MONO_PATTERN_1 0x100038 241 #define SM502_WINDOW_WIDTH 0x10003c 242 #define SM502_WIN_SRC_MASK 0x00001fff 243 #define SM502_WIN_DST_MASK 0x1fff0000 244 245 #define SM502_SRC_BASE 0x100040 246 #define SM502_SRC_BASE_ADDR_MASK 0x03fffff0 /* 128bit align */ 247 #define SM502_SRC_BASE_SYSMEM_CS1 0x04000000 /* SC0 otherw. */ 248 #define SM502_SRC_BASE_SYSMEM 0x08000000 /* local otherw. */ 249 250 #define SM502_DST_BASE 0x100044 251 #define SM502_DST_BASE_ADDR_MASK 0x03fffff0 /* 128bit align */ 252 #define SM502_DST_BASE_SYSMEM_CS1 0x04000000 /* SC0 otherw. */ 253 #define SM502_DST_BASE_SYSMEM 0x08000000 /* local otherw. */ 254 255 #define SM502_ALPHA 0x100048 256 #define SM502_WRAP 0x10004c 257 #define SM502_WRAP_HEIGHT_MASK 0x0000ffff 258 #define SM502_WRAP_WIDTH_MASK 0xffff0000 259 260 #define SM502_STATUS 0x100050 261 #define SM502_CMD_DONE 0x00000001 262 #define SM502_CSC_DONE 0x00000002 263 264 #define SM502_DATAPORT 0x110000 265 266 #endif /* SM502REG_H */ 267