1 /* $NetBSD: upcreg.h,v 1.3 2003/03/02 00:21:47 bjh21 Exp $ */ 2 3 /* 4 * Ben Harris, 2000, 2003 5 * 6 * This file is in the public domain. 7 */ 8 9 /* 10 * upcreg.h - CHIPS and Technologies Universal Peripheral Controllers 11 */ 12 13 /* 14 * This file contains register details for: 15 * CHIPS 82C710 Universal Peripheral Controller 16 * CHIPS 82C711 Universal Peripheral Controller II 17 * CHIPS 82C721 Universal Peripheral Controller III 18 */ 19 20 #define UPC_BUS_SIZE 0x400 /* Approximate */ 21 22 /* Fixed port addresses */ 23 24 #define UPC_PORT_IDECMDBASE 0x1f0 /* IDE primary base */ 25 #define UPC_PORT_IDECTLBASE 0x3f6 /* IDE secondary base */ 26 #define UPC_PORT_FDCBASE 0x3f4 /* FDC base address (82C721 only) */ 27 #define UPC_PORT_GAME 0x201 /* -GAMECS active */ 28 29 /* 82C710 Configuration magic sequences */ 30 31 #define UPC1_PORT_CFG1 0x2fa /* First magic config register */ 32 #define UPC1_PORT_CFG2 0x3fa /* Second magic config register */ 33 #define UPC1_CFGMAGIC_1 0x55 /* First magic number */ 34 #define UPC1_CFGMAGIC_2 0xaa /* Second magic number */ 35 #define UPC1_CFGMAGIC_3 0x36 /* Third magic number */ 36 37 /* 82C710 configuration registers */ 38 #define UPC1_CFGADDR_CR0 0x00 39 #define UPC1_CFGADDR_CR1 0x01 40 #define UPC1_CFGADDR_CR2 0x02 41 #define UPC1_CFGADDR_UARTBASE 0x04 42 #define UPC1_CFGADDR_PARBASE 0x06 43 #define UPC1_CFGADDR_GPCSBASE 0x09 44 #define UPC1_CFGADDR_CRA 0x0a 45 #define UPC1_CFGADDR_CRB 0x0b 46 #define UPC1_CFGADDR_CRC 0x0c 47 #define UPC1_CFGADDR_MOUSEBASE 0x0d 48 #define UPC1_CFGADDR_CRE 0x0e 49 #define UPC1_CFGADDR_CONFBASE 0x0f 50 #define UPC1_CFGADDR_EXIT 0x0f 51 52 /* 82C710 configuration register 0x00 */ 53 #define UPC1_CR0_VALID 0x80 /* Device has been configured */ 54 #define UPC1_CR0_OSC_MASK 0x60 /* Oscillator control */ 55 #define UPC1_CR0_OSC_ON 0x00 /* Oscillator always on */ 56 #define UPC1_CR0_OSC_PWRGD 0x20 /* Oscillator on when PWRGD */ 57 #define UPC1_CR0_OSC_OFF 0x60 /* Oscillator always off */ 58 #define UPC1_CR0_PEN 0x08 /* Enable parallel port */ 59 #define UPC1_CR0_SEN 0x04 /* Enable UART */ 60 61 /* 82C710 configuration register 0x01 */ 62 #define UPC1_CR1_RESET 0x80 /* Reset ignores serial port */ 63 #define UPC1_CR1_PRBI 0x40 /* Bi-directional printer support */ 64 #define UPC1_CR1_FCTS 0x20 /* Force UART CTS* active */ 65 #define UPC1_CR1_FDSR 0x10 /* Force UART DSR* active */ 66 #define UPC1_CR1_FDCD 0x08 /* Force UART DCD* active */ 67 68 /* 82C710 configuration register 0x02 */ 69 #define UPC1_CR2_SCLK 0x40 /* Divide UART clock by 4 rather than 2 */ 70 #define UPC1_CR2_RXSRC 0x20 /* Use divider output for Rx clock */ 71 #define UPC1_CR2_TXSRC 0x10 /* Use divider output for Tx clock */ 72 73 /* 82C710 configuration register 0x04 */ 74 #define UPC1_UARTBASE_SHIFT 2 75 76 /* 82C710 configuration register 0x06 */ 77 #define UPC1_PARBASE_SHIFT 2 78 79 /* 82C710 configuration register 0x09 */ 80 #define UPC1_GPCSBASE_SHIFT 2 81 82 /* 82C710 configuration register 0x0a */ 83 #define UPC1_CRA_GPCSMASK_MASK 0xe0 /* how many GPCSBASE bits matter */ 84 #define UPC1_CRA_GPCSMASK_SHIFT 1 85 #define UPC1_CRA_GPCSA1 0x08 /* Extra bit at the bottom of GPCSBASE */ 86 #define UPC1_CRA_IDEBEN 0x04 /* IDEENLO* buffer enable */ 87 #define UPC1_CRA_GPCSEN 0x02 /* GPCS enable */ 88 #define UPC1_CRA_GPCSBEN 0x01 /* GPCS buffer enable */ 89 90 /* 82C710 configuration register 0x0b */ 91 #define UPC1_CRB_MINTRP 0x80 /* Mouse interrupt polarity: 1->low */ 92 #define UPC1_CRB_FINTRP 0x40 /* Floppy interrupt polarity */ 93 #define UPC1_CRB_SINTRP 0x20 /* Serial interrupt polarity */ 94 #define UPC1_CRB_PINTRP 0x10 /* Parallel interrupt polarity */ 95 #define UPC1_CRB_SPDWN 0x08 /* Serial port power down */ 96 #define UPC1_CRB_PPWDN 0x02 /* Parallel port power down */ 97 #define UPC1_CRB_GPCSOUT 0x01 /* GPCS*/OUT1 pin function select */ 98 99 /* 82C710 configuration register 0x0c */ 100 #define UPC1_CRC_IDEEN 0x80 /* IDE enable */ 101 #define UPC1_CRC_IDEATXT 0x40 /* IDE AT/XT select */ 102 #define UPC1_CRC_FDCEN 0x20 /* FDC enable */ 103 #define UPC1_CRC_FPWDN 0x10 /* FDC power down */ 104 #define UPC1_CRC_RTCCSEN 0x08 /* RTCCS* enable */ 105 #define UPC1_CRC_RTCBEN 0x04 /* RTCCS* buffer enable */ 106 #define UPC1_CRC_MDDWN 0x01 /* Mouse port power down */ 107 108 /* 82C710 configuration register 0x0d */ 109 #define UPC1_MOUSEBASE_SHIFT 2 110 111 /* 82C710 configuration register 0x0e */ 112 #define UPC1_CRE_STEN 0x40 /* Serial port test enabled */ 113 #define UPC1_CRE_FTEN1 0x10 /* Floppy test bit 1 */ 114 #define UPC1_CRE_FTEN2 0x80 /* Floppy test bit 2 */ 115 #define UPC1_CRE_DSTEN 0x40 116 117 /* 82C710 configuration register 0x0f */ 118 #define UPC1_CONFBASE_SHIFT 2 119 120 /* 82C711/721 Configuration magic sequences */ 121 122 #define UPC2_PORT_CFGADDR 0x3f0 /* Configuration register address */ 123 #define UPC2_PORT_CFGDATA 0x3f1 /* Configuration register value */ 124 #define UPC2_CFGMAGIC_ENTER 0x55 /* Write twice to enter config mode. */ 125 #define UPC2_CFGMAGIC_EXIT 0xaa /* Write once to exit config mode. */ 126 127 /* Configuration registers */ 128 #define UPC2_CFGADDR_CR0 0x00 /* Configuration Register 0 */ 129 #define UPC2_CFGADDR_CR1 0x01 /* Configuration Register 1 */ 130 #define UPC2_CFGADDR_CR2 0x02 /* Configuration Register 2 */ 131 #define UPC2_CFGADDR_CR3 0x03 /* Configuration Register 3 */ 132 #define UPC2_CFGADDR_CR4 0x04 /* Configuration Register 4 */ 133 134 /* Configuration register 0 */ 135 #define UPC2_CR0_VALID 0x80 /* Device has been configured */ 136 #define UPC2_CR0_OSC_MASK 0x60 /* Oscillator control */ 137 #define UPC2_CR0_OSC_ON 0x00 /* Oscillator always on */ 138 #define UPC2_CR0_OSC_PWRGD 0x20 /* Oscillator on when PWRGD */ 139 #define UPC2_CR0_OSC_OFF 0x60 /* Oscillator always off */ 140 #define UPC2_CR0_FDC_ENABLE 0x10 /* FDC enabled */ 141 #define UPC2_CR0_FDC_ON 0x08 /* FDC powered */ 142 #define UPC2_CR0_IDE_AT 0x02 /* IDE controller is AT type */ 143 #define UPC2_CR0_IDE_ENABLE 0x01 /* IDE controller enabled */ 144 145 /* Configuration register 1 */ 146 #define UPC2_CR1_READ_ENABLE 0x80 /* Enable reading of config regs */ 147 #define UPC2_CR1_COM34_MASK 0x60 /* COM3/COM4 addresses */ 148 #define UPC2_CR1_COM34_338_238 0x00 /* COM3 = 0x338; COM4 = 0x238 */ 149 #define UPC2_CR1_COM34_3E8_2E8 0x20 /* COM3 = 0x3E8; COM4 = 0x2E8 */ 150 #define UPC2_CR1_COM34_2E8_2E0 0x40 /* COM3 = 0x2E8; COM4 = 0x2E0 */ 151 #define UPC2_CR1_COM34_220_228 0x60 /* COM3 = 0x220; COM4 = 0x228 */ 152 #define UPC2_CR1_IRQ_ACTHIGH 0x10 /* IRQ is active-high */ 153 #define UPC2_CR1_LPT_BORING 0x08 /* Parallel port is not EPP */ 154 #define UPC2_CR1_LPT_ON 0x04 /* Parallel port is powered */ 155 #define UPC2_CR1_LPT_MASK 0x03 /* Parallel port address */ 156 #define UPC2_CR1_LPT_DISABLE 0x00 /* Parallel port disabled */ 157 #define UPC2_CR1_LPT_3BC 0x01 /* Parallel port at 0x3BC */ 158 #define UPC2_CR1_LPT_378 0x02 /* Parallel port at 0x378 */ 159 #define UPC2_CR1_LPT_278 0x03 /* Parallel port at 0x278 */ 160 161 /* Configuration register 2 */ 162 #define UPC2_CR2_UART2_ON 0x80 /* 2ndary serial powered */ 163 #define UPC2_CR2_UART2_ENABLE 0x40 /* 2ndary serial enabled */ 164 #define UPC2_CR2_UART2_MASK 0x30 /* 2ndary serial address */ 165 #define UPC2_CR2_UART2_3F8 0x00 /* 2ndary serial at 0x3F8 */ 166 #define UPC2_CR2_UART2_2F8 0x10 /* 2ndary serial at 0x2F8 */ 167 #define UPC2_CR2_UART2_COM3 0x20 /* 2ndary serial at COM3 (see CR1) */ 168 #define UPC2_CR2_UART2_COM4 0x30 /* 2ndary serial at COM4 (see CR1) */ 169 #define UPC2_CR2_UART1_ON 0x08 /* primary serial powered */ 170 #define UPC2_CR2_UART1_ENABLE 0x04 /* primary serial enabled */ 171 #define UPC2_CR2_UART1_MASK 0x03 /* primary serial address */ 172 #define UPC2_CR2_UART1_3F8 0x00 /* primary serial at 0x3F8 */ 173 #define UPC2_CR2_UART1_2F8 0x01 /* primary serial at 0x2F8 */ 174 #define UPC2_CR2_UART1_COM3 0x02 /* primary serial at COM3 (see CR1) */ 175 #define UPC2_CR2_UART1_COM4 0x03 /* primary serial at COM4 (see CR1) */ 176 177 /* Configuration register 3 */ 178 #define UPC2_CR3_UART2_TEST 0x80 /* 2ndary serial test mode */ 179 #define UPC2_CR3_UART1_TEST 0x40 /* primary serial test mode */ 180 #define UPC2_CR3_FDC_TEST_MASK 0x30 /* FDC test modes */ 181 #define UPC2_CR3_FDC_TEST_NORMAL 0x00 /* FDC normal mode */ 182 183 /* Configuration register 4 (82C721 only) */ 184 #define UPC2_CR4_UART2_DIV13 0x01 /* Use normal (cf MIDI) clock for UART2 */ 185