1 /* $NetBSD: upcreg.h,v 1.2 2000/08/16 23:56:12 bjh21 Exp $ */ 2 3 /* 4 * Ben Harris, 2000 5 * 6 * This file is in the public domain. 7 */ 8 9 /* 10 * upcreg.h - CHIPS and Technologies Universal Peripheral Controllers 11 */ 12 13 /* 14 * This file contains register details for: 15 * CHIPS 82C710 Universal Peripheral Controller 16 * CHIPS 82C711 Universal Peripheral Controller II 17 * CHIPS 82C721 Universal Peripheral Controller III 18 */ 19 20 #define UPC_BUS_SIZE 0x400 /* Approximate */ 21 22 /* Fixed port addresses */ 23 24 #define UPC_PORT_CFGADDR 0x3f0 /* Configuration register address */ 25 #define UPC_PORT_CFGDATA 0x3f1 /* Configuration register value */ 26 #define UPC_PORT_IDECMDBASE 0x1f0 /* IDE primary base */ 27 #define UPC_PORT_IDECTLBASE 0x3f6 /* IDE secondary base */ 28 #define UPC_PORT_FDCBASE 0x3f4 /* FDC base address (82C721 only) */ 29 #define UPC_PORT_GAME 0x201 /* -GAMECS active */ 30 31 /* Configuration magic sequences */ 32 33 #define UPC_CFGMAGIC_ENTER 0x55 /* Write twice to enter config mode. */ 34 #define UPC_CFGMAGIC_EXIT 0xaa /* Write once to exit config mode. */ 35 36 /* Configuration registers */ 37 #define UPC_CFGADDR_CR0 0x00 /* Configuration Register 0 */ 38 #define UPC_CFGADDR_CR1 0x01 /* Configuration Register 1 */ 39 #define UPC_CFGADDR_CR2 0x02 /* Configuration Register 2 */ 40 #define UPC_CFGADDR_CR3 0x03 /* Configuration Register 3 */ 41 #define UPC_CFGADDR_CR4 0x04 /* Configuration Register 4 */ 42 43 /* Configuration register 0 */ 44 #define UPC_CR0_VALID 0x80 /* Device has been configured */ 45 #define UPC_CR0_OSC_MASK 0x60 /* Oscillator control */ 46 #define UPC_CR0_OSC_ON 0x00 /* Oscillator always on */ 47 #define UPC_CR0_OSC_PWRGD 0x20 /* Oscillator on when PWRGD */ 48 #define UPC_CR0_OSC_OFF 0x60 /* Oscillator always off */ 49 #define UPC_CR0_FDC_ENABLE 0x10 /* FDC enabled */ 50 #define UPC_CR0_FDC_ON 0x08 /* FDC powered */ 51 #define UPC_CR0_IDE_AT 0x02 /* IDE controller is AT type */ 52 #define UPC_CR0_IDE_ENABLE 0x01 /* IDE controller enabled */ 53 54 /* Configuration register 1 */ 55 #define UPC_CR1_READ_ENABLE 0x80 /* Enable reading of config regs */ 56 #define UPC_CR1_COM34_MASK 0x60 /* COM3/COM4 addresses */ 57 #define UPC_CR1_COM34_338_238 0x00 /* COM3 = 0x338; COM4 = 0x238 */ 58 #define UPC_CR1_COM34_3E8_2E8 0x20 /* COM3 = 0x3E8; COM4 = 0x2E8 */ 59 #define UPC_CR1_COM34_2E8_2E0 0x40 /* COM3 = 0x2E8; COM4 = 0x2E0 */ 60 #define UPC_CR1_COM34_220_228 0x60 /* COM3 = 0x220; COM4 = 0x228 */ 61 #define UPC_CR1_IRQ_ACTHIGH 0x10 /* IRQ is active-high */ 62 #define UPC_CR1_LPT_BORING 0x08 /* Parallel port is not EPP */ 63 #define UPC_CR1_LPT_ON 0x04 /* Parallel port is powered */ 64 #define UPC_CR1_LPT_MASK 0x03 /* Parallel port address */ 65 #define UPC_CR1_LPT_DISABLE 0x00 /* Parallel port disabled */ 66 #define UPC_CR1_LPT_3BC 0x01 /* Parallel port at 0x3BC */ 67 #define UPC_CR1_LPT_378 0x02 /* Parallel port at 0x378 */ 68 #define UPC_CR1_LPT_278 0x03 /* Parallel port at 0x278 */ 69 70 /* Configuration register 2 */ 71 /* I believe 2ndary serial is absent on 82C710 */ 72 #define UPC_CR2_UART2_ON 0x80 /* 2ndary serial powered */ 73 #define UPC_CR2_UART2_ENABLE 0x40 /* 2ndary serial enabled */ 74 #define UPC_CR2_UART2_MASK 0x30 /* 2ndary serial address */ 75 #define UPC_CR2_UART2_3F8 0x00 /* 2ndary serial at 0x3F8 */ 76 #define UPC_CR2_UART2_2F8 0x10 /* 2ndary serial at 0x2F8 */ 77 #define UPC_CR2_UART2_COM3 0x20 /* 2ndary serial at COM3 (see CR1) */ 78 #define UPC_CR2_UART2_COM4 0x30 /* 2ndary serial at COM4 (see CR1) */ 79 #define UPC_CR2_UART1_ON 0x08 /* primary serial powered */ 80 #define UPC_CR2_UART1_ENABLE 0x04 /* primary serial enabled */ 81 #define UPC_CR2_UART1_MASK 0x03 /* primary serial address */ 82 #define UPC_CR2_UART1_3F8 0x00 /* primary serial at 0x3F8 */ 83 #define UPC_CR2_UART1_2F8 0x01 /* primary serial at 0x2F8 */ 84 #define UPC_CR2_UART1_COM3 0x02 /* primary serial at COM3 (see CR1) */ 85 #define UPC_CR2_UART1_COM4 0x03 /* primary serial at COM4 (see CR1) */ 86 87 /* Configuration register 3 */ 88 #define UPC_CR3_UART2_TEST 0x80 /* 2ndary serial test mode */ 89 #define UPC_CR3_UART1_TEST 0x40 /* primary serial test mode */ 90 #define UPC_CR3_FDC_TEST_MASK 0x30 /* FDC test modes */ 91 #define UPC_CR3_FDC_TEST_NORMAL 0x00 /* FDC normal mode */ 92 93 /* Configuration register 4 (82C721 only) */ 94 #define UPC_CR4_UART2_DIV13 0x01 /* Use normal (cf MIDI) clock for UART2 */ 95