1 /* $NetBSD: wdcreg.h,v 1.25 2002/03/31 19:47:39 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 1991 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)wdreg.h 7.1 (Berkeley) 5/9/91 39 */ 40 41 /* 42 * Disk Controller register definitions. 43 */ 44 45 /* offsets of registers in the 'regular' register region */ 46 #define wd_data 0 /* data register (R/W - 16 bits) */ 47 #define wd_error 1 /* error register (R) */ 48 #define wd_precomp 1 /* write precompensation (W) */ 49 #define wd_features 1 /* features (W), same as wd_precomp */ 50 #define wd_seccnt 2 /* sector count (R/W) */ 51 #define wd_ireason 2 /* interrupt reason (R/W) (for atapi) */ 52 #define wd_sector 3 /* first sector number (R/W) */ 53 #define wd_cyl_lo 4 /* cylinder address, low byte (R/W) */ 54 #define wd_cyl_hi 5 /* cylinder address, high byte (R/W) */ 55 #define wd_sdh 6 /* sector size/drive/head (R/W) */ 56 #define wd_command 7 /* command register (W) */ 57 #define wd_status 7 /* immediate status (R) */ 58 #define wd_lba_lo 3 /* lba address, low byte (RW) */ 59 #define wd_lba_mi 4 /* lba address, middle byte (RW) */ 60 #define wd_lba_hi 5 /* lba address, high byte (RW) */ 61 62 /* offsets of registers in the auxiliary register region */ 63 #define wd_aux_altsts 0 /* alternate fixed disk status (R) */ 64 #define wd_aux_ctlr 0 /* fixed disk controller control (W) */ 65 #define WDCTL_4BIT 0x08 /* use four head bits (wd1003) */ 66 #define WDCTL_RST 0x04 /* reset the controller */ 67 #define WDCTL_IDS 0x02 /* disable controller interrupts */ 68 #if 0 /* NOT MAPPED; fd uses this register on PCs */ 69 #define wd_digin 1 /* disk controller input (R) */ 70 #endif 71 72 /* 73 * Status bits. 74 */ 75 #define WDCS_BSY 0x80 /* busy */ 76 #define WDCS_DRDY 0x40 /* drive ready */ 77 #define WDCS_DWF 0x20 /* drive write fault */ 78 #define WDCS_DSC 0x10 /* drive seek complete */ 79 #define WDCS_DRQ 0x08 /* data request */ 80 #define WDCS_CORR 0x04 /* corrected data */ 81 #define WDCS_IDX 0x02 /* index */ 82 #define WDCS_ERR 0x01 /* error */ 83 #define WDCS_BITS \ 84 "\020\010bsy\007drdy\006dwf\005dsc\004drq\003corr\002idx\001err" 85 86 /* 87 * Error bits. 88 */ 89 #define WDCE_BBK 0x80 /* bad block detected */ 90 #define WDCE_CRC 0x80 /* CRC error (Ultra-DMA only) */ 91 #define WDCE_UNC 0x40 /* uncorrectable data error */ 92 #define WDCE_MC 0x20 /* media changed */ 93 #define WDCE_IDNF 0x10 /* id not found */ 94 #define WDCE_MCR 0x08 /* media change requested */ 95 #define WDCE_ABRT 0x04 /* aborted command */ 96 #define WDCE_TK0NF 0x02 /* track 0 not found */ 97 #define WDCE_AMNF 0x01 /* address mark not found */ 98 99 /* 100 * Commands for Disk Controller. 101 */ 102 #define WDCC_NOP 0x00 /* Always fail with "aborted command" */ 103 #define WDCC_RECAL 0x10 /* disk restore code -- resets cntlr */ 104 105 #define WDCC_READ 0x20 /* disk read code */ 106 #define WDCC_WRITE 0x30 /* disk write code */ 107 #define WDCC__LONG 0x02 /* modifier -- access ecc bytes */ 108 #define WDCC__NORETRY 0x01 /* modifier -- no retrys */ 109 110 #define WDCC_FORMAT 0x50 /* disk format code */ 111 #define WDCC_DIAGNOSE 0x90 /* controller diagnostic */ 112 #define WDCC_IDP 0x91 /* initialize drive parameters */ 113 114 #define WDCC_SMART 0xb0 /* Self Mon, Analysis, Reporting Tech */ 115 116 #define WDCC_READMULTI 0xc4 /* read multiple */ 117 #define WDCC_WRITEMULTI 0xc5 /* write multiple */ 118 #define WDCC_SETMULTI 0xc6 /* set multiple mode */ 119 120 #define WDCC_READDMA 0xc8 /* read with DMA */ 121 #define WDCC_WRITEDMA 0xca /* write with DMA */ 122 123 #define WDCC_ACKMC 0xdb /* acknowledge media change */ 124 #define WDCC_LOCK 0xde /* lock drawer */ 125 #define WDCC_UNLOCK 0xdf /* unlock drawer */ 126 127 #define WDCC_FLUSHCACHE 0xe7 /* Flush cache */ 128 #define WDCC_IDENTIFY 0xec /* read parameters from controller */ 129 #define SET_FEATURES 0xef /* set features */ 130 131 #define WDCC_IDLE 0xe3 /* set idle timer & enter idle mode */ 132 #define WDCC_IDLE_IMMED 0xe1 /* enter idle mode */ 133 #define WDCC_SLEEP 0xe6 /* enter sleep mode */ 134 #define WDCC_STANDBY 0xe2 /* set standby timer & enter standby */ 135 #define WDCC_STANDBY_IMMED 0xe0 /* enter standby mode */ 136 #define WDCC_CHECK_PWR 0xe5 /* check power mode */ 137 138 /* 139 * Big Drive support 140 */ 141 #define WDCC_READ_EXT 0x24 /* read 48-bit addressing */ 142 #define WDCC_WRITE_EXT 0x34 /* write 48-bit addressing */ 143 144 #define WDCC_READMULTI_EXT 0x29 /* read multiple 48-bit addressing */ 145 #define WDCC_WRITEMULTI_EXT 0x39 /* write multiple 48-bit addressing */ 146 147 #define WDCC_READDMA_EXT 0x25 /* read 48-bit addressing with DMA */ 148 #define WDCC_WRITEDMA_EXT 0x35 /* write 48-bit addressing with DMA */ 149 150 /* Subcommands for SET_FEATURES (features register) */ 151 #define WDSF_EN_WR_CACHE 0x02 152 #define WDSF_SET_MODE 0x03 153 #define WDSF_REASSIGN_EN 0x04 154 #define WDSF_RETRY_DS 0x33 155 #define WDSF_SET_CACHE_SGMT 0x54 156 #define WDSF_READAHEAD_DS 0x55 157 #define WDSF_POD_DS 0x66 158 #define WDSF_ECC_DS 0x77 159 #define WDSF_WRITE_CACHE_DS 0x82 160 #define WDSF_REASSIGN_DS 0x84 161 #define WDSF_ECC_EN 0x88 162 #define WDSF_RETRY_EN 0x99 163 #define WDSF_SET_CURRENT 0x9a 164 #define WDSF_READAHEAD_EN 0xaa 165 #define WDSF_PREFETCH_SET 0xab 166 #define WDSF_POD_EN 0xcc 167 168 /* Subcommands for SMART (features register) */ 169 #define WDSM_RD_DATA 0xd0 170 #define WDSM_ATTR_AUTOSAVE_EN 0xd2 171 #define WDSM_SAVE_ATTR 0xd3 172 #define WDSM_EXEC_OFFL_IMM 0xd4 173 #define WDSM_ENABLE_OPS 0xd8 174 #define WDSM_DISABLE_OPS 0xd9 175 #define WDSM_STATUS 0xda 176 177 #define WDSMART_CYL_LO 0x4f 178 #define WDSMART_CYL_HI 0xc2 179 180 181 /* parameters uploaded to device/heads register */ 182 #define WDSD_IBM 0xa0 /* forced to 512 byte sector, ecc */ 183 #define WDSD_CHS 0x00 /* cylinder/head/sector addressing */ 184 #define WDSD_LBA 0x40 /* logical block addressing */ 185 186 /* Commands for ATAPI devices */ 187 #define ATAPI_CHECK_POWER_MODE 0xe5 188 #define ATAPI_EXEC_DRIVE_DIAGS 0x90 189 #define ATAPI_IDLE_IMMEDIATE 0xe1 190 #define ATAPI_NOP 0x00 191 #define ATAPI_PKT_CMD 0xa0 192 #define ATAPI_IDENTIFY_DEVICE 0xa1 193 #define ATAPI_SOFT_RESET 0x08 194 #define ATAPI_SLEEP 0xe6 195 #define ATAPI_STANDBY_IMMEDIATE 0xe0 196 197 /* Bytes used by ATAPI_PACKET_COMMAND ( feature register) */ 198 #define ATAPI_PKT_CMD_FTRE_DMA 0x01 199 #define ATAPI_PKT_CMD_FTRE_OVL 0x02 200 201 /* ireason */ 202 #define WDCI_CMD 0x01 /* command(1) or data(0) */ 203 #define WDCI_IN 0x02 /* transfer to(1) or from(0) the host */ 204 #define WDCI_RELEASE 0x04 /* bus released until completion */ 205 206 #define PHASE_CMDOUT (WDCS_DRQ | WDCI_CMD) 207 #define PHASE_DATAIN (WDCS_DRQ | WDCI_IN) 208 #define PHASE_DATAOUT (WDCS_DRQ) 209 #define PHASE_COMPLETED (WDCI_IN | WDCI_CMD) 210 #define PHASE_ABORTED (0) 211