1 /* $NetBSD: z8530sc.c,v 1.16 2001/11/13 13:14:46 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Gordon W. Ross 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This software was developed by the Computer Systems Engineering group 9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 10 * contributed to Berkeley. 11 * 12 * All advertising materials mentioning features or use of this software 13 * must display the following acknowledgement: 14 * This product includes software developed by the University of 15 * California, Lawrence Berkeley Laboratory. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions 19 * are met: 20 * 1. Redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer. 22 * 2. Redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution. 25 * 3. All advertising materials mentioning features or use of this software 26 * must display the following acknowledgement: 27 * This product includes software developed by the University of 28 * California, Berkeley and its contributors. 29 * 4. Neither the name of the University nor the names of its contributors 30 * may be used to endorse or promote products derived from this software 31 * without specific prior written permission. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 43 * SUCH DAMAGE. 44 * 45 * @(#)zs.c 8.1 (Berkeley) 7/19/93 46 */ 47 48 /* 49 * Zilog Z8530 Dual UART driver (common part) 50 * 51 * This file contains the machine-independent parts of the 52 * driver common to tty and keyboard/mouse sub-drivers. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: z8530sc.c,v 1.16 2001/11/13 13:14:46 lukem Exp $"); 57 58 #include <sys/param.h> 59 #include <sys/systm.h> 60 #include <sys/proc.h> 61 #include <sys/device.h> 62 #include <sys/conf.h> 63 #include <sys/file.h> 64 #include <sys/ioctl.h> 65 #include <sys/tty.h> 66 #include <sys/time.h> 67 #include <sys/kernel.h> 68 #include <sys/syslog.h> 69 70 #include <dev/ic/z8530reg.h> 71 #include <machine/z8530var.h> 72 73 void 74 zs_break(cs, set) 75 struct zs_chanstate *cs; 76 int set; 77 { 78 79 if (set) { 80 cs->cs_preg[5] |= ZSWR5_BREAK; 81 cs->cs_creg[5] |= ZSWR5_BREAK; 82 } else { 83 cs->cs_preg[5] &= ~ZSWR5_BREAK; 84 cs->cs_creg[5] &= ~ZSWR5_BREAK; 85 } 86 zs_write_reg(cs, 5, cs->cs_creg[5]); 87 } 88 89 90 /* 91 * drain on-chip fifo 92 */ 93 void 94 zs_iflush(cs) 95 struct zs_chanstate *cs; 96 { 97 u_char c, rr0, rr1; 98 int i; 99 100 /* 101 * Count how many times we loop. Some systems, such as some 102 * Apple PowerBooks, claim to have SCC's which they really don't. 103 */ 104 for (i = 0; i < 32; i++) { 105 /* Is there input available? */ 106 rr0 = zs_read_csr(cs); 107 if ((rr0 & ZSRR0_RX_READY) == 0) 108 break; 109 110 /* 111 * First read the status, because reading the data 112 * destroys the status of this char. 113 */ 114 rr1 = zs_read_reg(cs, 1); 115 c = zs_read_data(cs); 116 117 if (rr1 & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE)) { 118 /* Clear the receive error. */ 119 zs_write_csr(cs, ZSWR0_RESET_ERRORS); 120 } 121 } 122 } 123 124 125 /* 126 * Write the given register set to the given zs channel in the proper order. 127 * The channel must not be transmitting at the time. The receiver will 128 * be disabled for the time it takes to write all the registers. 129 * Call this with interrupts disabled. 130 */ 131 void 132 zs_loadchannelregs(cs) 133 struct zs_chanstate *cs; 134 { 135 u_char *reg; 136 137 zs_write_csr(cs, ZSM_RESET_ERR); /* XXX: reset error condition */ 138 139 #if 1 140 /* 141 * XXX: Is this really a good idea? 142 * XXX: Should go elsewhere! -gwr 143 */ 144 zs_iflush(cs); /* XXX */ 145 #endif 146 147 if (memcmp((caddr_t)cs->cs_preg, (caddr_t)cs->cs_creg, 16) == 0) 148 return; /* only change if values are different */ 149 150 /* Copy "pending" regs to "current" */ 151 memcpy((caddr_t)cs->cs_creg, (caddr_t)cs->cs_preg, 16); 152 reg = cs->cs_creg; /* current regs */ 153 154 /* disable interrupts */ 155 zs_write_reg(cs, 1, reg[1] & ~ZSWR1_IMASK); 156 157 /* baud clock divisor, stop bits, parity */ 158 zs_write_reg(cs, 4, reg[4]); 159 160 /* misc. TX/RX control bits */ 161 zs_write_reg(cs, 10, reg[10]); 162 163 /* char size, enable (RX/TX) */ 164 zs_write_reg(cs, 3, reg[3] & ~ZSWR3_RX_ENABLE); 165 zs_write_reg(cs, 5, reg[5] & ~ZSWR5_TX_ENABLE); 166 167 /* synchronous mode stuff */ 168 zs_write_reg(cs, 6, reg[6]); 169 zs_write_reg(cs, 7, reg[7]); 170 171 #if 0 172 /* 173 * Registers 2 and 9 are special because they are 174 * actually common to both channels, but must be 175 * programmed through channel A. The "zsc" attach 176 * function takes care of setting these registers 177 * and they should not be touched thereafter. 178 */ 179 /* interrupt vector */ 180 zs_write_reg(cs, 2, reg[2]); 181 /* master interrupt control */ 182 zs_write_reg(cs, 9, reg[9]); 183 #endif 184 185 /* Shut down the BRG */ 186 zs_write_reg(cs, 14, reg[14] & ~ZSWR14_BAUD_ENA); 187 188 #ifdef ZS_MD_SETCLK 189 /* Let the MD code setup any external clock. */ 190 ZS_MD_SETCLK(cs); 191 #endif /* ZS_MD_SETCLK */ 192 193 /* clock mode control */ 194 zs_write_reg(cs, 11, reg[11]); 195 196 /* baud rate (lo/hi) */ 197 zs_write_reg(cs, 12, reg[12]); 198 zs_write_reg(cs, 13, reg[13]); 199 200 /* Misc. control bits */ 201 zs_write_reg(cs, 14, reg[14]); 202 203 /* which lines cause status interrupts */ 204 zs_write_reg(cs, 15, reg[15]); 205 206 /* 207 * Zilog docs recommend resetting external status twice at this 208 * point. Mainly as the status bits are latched, and the first 209 * interrupt clear might unlatch them to new values, generating 210 * a second interrupt request. 211 */ 212 zs_write_csr(cs, ZSM_RESET_STINT); 213 zs_write_csr(cs, ZSM_RESET_STINT); 214 215 /* char size, enable (RX/TX)*/ 216 zs_write_reg(cs, 3, reg[3]); 217 zs_write_reg(cs, 5, reg[5]); 218 219 /* interrupt enables: RX, TX, STATUS */ 220 zs_write_reg(cs, 1, reg[1]); 221 } 222 223 224 /* 225 * ZS hardware interrupt. Scan all ZS channels. NB: we know here that 226 * channels are kept in (A,B) pairs. 227 * 228 * Do just a little, then get out; set a software interrupt if more 229 * work is needed. 230 * 231 * We deliberately ignore the vectoring Zilog gives us, and match up 232 * only the number of `reset interrupt under service' operations, not 233 * the order. 234 */ 235 int 236 zsc_intr_hard(arg) 237 void *arg; 238 { 239 struct zsc_softc *zsc = arg; 240 struct zs_chanstate *cs; 241 u_char rr3; 242 243 /* First look at channel A. */ 244 cs = zsc->zsc_cs[0]; 245 /* Note: only channel A has an RR3 */ 246 rr3 = zs_read_reg(cs, 3); 247 248 /* 249 * Clear interrupt first to avoid a race condition. 250 * If a new interrupt condition happens while we are 251 * servicing this one, we will get another interrupt 252 * shortly. We can NOT just sit here in a loop, or 253 * we will cause horrible latency for other devices 254 * on this interrupt level (i.e. sun3x floppy disk). 255 */ 256 if (rr3 & (ZSRR3_IP_A_RX | ZSRR3_IP_A_TX | ZSRR3_IP_A_STAT)) { 257 zs_write_csr(cs, ZSWR0_CLR_INTR); 258 if (rr3 & ZSRR3_IP_A_RX) 259 (*cs->cs_ops->zsop_rxint)(cs); 260 if (rr3 & ZSRR3_IP_A_STAT) 261 (*cs->cs_ops->zsop_stint)(cs, 0); 262 if (rr3 & ZSRR3_IP_A_TX) 263 (*cs->cs_ops->zsop_txint)(cs); 264 } 265 266 /* Now look at channel B. */ 267 cs = zsc->zsc_cs[1]; 268 if (rr3 & (ZSRR3_IP_B_RX | ZSRR3_IP_B_TX | ZSRR3_IP_B_STAT)) { 269 zs_write_csr(cs, ZSWR0_CLR_INTR); 270 if (rr3 & ZSRR3_IP_B_RX) 271 (*cs->cs_ops->zsop_rxint)(cs); 272 if (rr3 & ZSRR3_IP_B_STAT) 273 (*cs->cs_ops->zsop_stint)(cs, 0); 274 if (rr3 & ZSRR3_IP_B_TX) 275 (*cs->cs_ops->zsop_txint)(cs); 276 } 277 278 /* Note: caller will check cs_x->cs_softreq and DTRT. */ 279 return (rr3); 280 } 281 282 283 /* 284 * ZS software interrupt. Scan all channels for deferred interrupts. 285 */ 286 int 287 zsc_intr_soft(arg) 288 void *arg; 289 { 290 struct zsc_softc *zsc = arg; 291 struct zs_chanstate *cs; 292 int rval, chan; 293 294 rval = 0; 295 for (chan = 0; chan < 2; chan++) { 296 cs = zsc->zsc_cs[chan]; 297 298 /* 299 * The softint flag can be safely cleared once 300 * we have decided to call the softint routine. 301 * (No need to do splzs() first.) 302 */ 303 if (cs->cs_softreq) { 304 cs->cs_softreq = 0; 305 (*cs->cs_ops->zsop_softint)(cs); 306 rval++; 307 } 308 } 309 return (rval); 310 } 311 312 /* 313 * Provide a null zs "ops" vector. 314 */ 315 316 static void zsnull_rxint __P((struct zs_chanstate *)); 317 static void zsnull_stint __P((struct zs_chanstate *, int)); 318 static void zsnull_txint __P((struct zs_chanstate *)); 319 static void zsnull_softint __P((struct zs_chanstate *)); 320 321 static void 322 zsnull_rxint(cs) 323 struct zs_chanstate *cs; 324 { 325 /* Ask for softint() call. */ 326 cs->cs_softreq = 1; 327 } 328 329 static void 330 zsnull_stint(cs, force) 331 struct zs_chanstate *cs; 332 int force; 333 { 334 /* Ask for softint() call. */ 335 cs->cs_softreq = 1; 336 } 337 338 static void 339 zsnull_txint(cs) 340 struct zs_chanstate *cs; 341 { 342 /* Ask for softint() call. */ 343 cs->cs_softreq = 1; 344 } 345 346 static void 347 zsnull_softint(cs) 348 struct zs_chanstate *cs; 349 { 350 zs_write_reg(cs, 1, 0); 351 zs_write_reg(cs, 15, 0); 352 } 353 354 struct zsops zsops_null = { 355 zsnull_rxint, /* receive char available */ 356 zsnull_stint, /* external/status */ 357 zsnull_txint, /* xmit buffer empty */ 358 zsnull_softint, /* process software interrupt */ 359 }; 360