1 /* $NetBSD: ad1848_isa.c,v 1.21 2002/03/06 07:12:04 itohy Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Ken Hornstein and John Kohl. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 /* 39 * Copyright (c) 1994 John Brezak 40 * Copyright (c) 1991-1993 Regents of the University of California. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by the Computer Systems 54 * Engineering Group at Lawrence Berkeley Laboratory. 55 * 4. Neither the name of the University nor of the Laboratory may be used 56 * to endorse or promote products derived from this software without 57 * specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 */ 72 73 /* 74 * Copyright by Hannu Savolainen 1994 75 * 76 * Redistribution and use in source and binary forms, with or without 77 * modification, are permitted provided that the following conditions are 78 * met: 1. Redistributions of source code must retain the above copyright 79 * notice, this list of conditions and the following disclaimer. 2. 80 * Redistributions in binary form must reproduce the above copyright notice, 81 * this list of conditions and the following disclaimer in the documentation 82 * and/or other materials provided with the distribution. 83 * 84 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 85 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 86 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 87 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 88 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 90 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 91 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 92 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 93 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 94 * SUCH DAMAGE. 95 * 96 */ 97 /* 98 * Portions of this code are from the VOXware support for the ad1848 99 * by Hannu Savolainen <hannu@voxware.pp.fi> 100 * 101 * Portions also supplied from the SoundBlaster driver for NetBSD. 102 */ 103 104 #include <sys/cdefs.h> 105 __KERNEL_RCSID(0, "$NetBSD: ad1848_isa.c,v 1.21 2002/03/06 07:12:04 itohy Exp $"); 106 107 #include <sys/param.h> 108 #include <sys/systm.h> 109 #include <sys/errno.h> 110 #include <sys/ioctl.h> 111 #include <sys/syslog.h> 112 #include <sys/device.h> 113 #include <sys/proc.h> 114 #include <sys/buf.h> 115 116 #include <machine/cpu.h> 117 #include <machine/bus.h> 118 119 #include <sys/audioio.h> 120 121 #include <dev/audio_if.h> 122 #include <dev/auconv.h> 123 124 #include <dev/isa/isavar.h> 125 #include <dev/isa/isadmavar.h> 126 127 #include <dev/ic/ad1848reg.h> 128 #include <dev/ic/cs4231reg.h> 129 #include <dev/ic/cs4237reg.h> 130 #include <dev/isa/ad1848var.h> 131 #include <dev/isa/cs4231var.h> 132 133 #ifdef AUDIO_DEBUG 134 #define DPRINTF(x) if (ad1848debug) printf x 135 extern int ad1848debug; 136 #else 137 #define DPRINTF(x) 138 #endif 139 140 static int ad1848_isa_read __P(( struct ad1848_softc *, int)); 141 static void ad1848_isa_write __P(( struct ad1848_softc *, int, int)); 142 143 int 144 ad1848_isa_read(sc, index) 145 struct ad1848_softc *sc; 146 int index; 147 { 148 return (bus_space_read_1(sc->sc_iot, sc->sc_ioh, index)); 149 } 150 151 void 152 ad1848_isa_write(sc, index, value) 153 struct ad1848_softc *sc; 154 int index; 155 int value; 156 { 157 bus_space_write_1(sc->sc_iot, sc->sc_ioh, index, value); 158 } 159 160 /* 161 * Map and probe for the ad1848 chip 162 */ 163 int 164 ad1848_isa_mapprobe(isc, iobase) 165 struct ad1848_isa_softc *isc; 166 int iobase; 167 { 168 struct ad1848_softc *sc = &isc->sc_ad1848; 169 170 if (!AD1848_BASE_VALID(iobase)) { 171 #ifdef AUDIO_DEBUG 172 printf("ad1848: configured iobase %04x invalid\n", iobase); 173 #endif 174 return 0; 175 } 176 177 /* Map the AD1848 ports */ 178 if (bus_space_map(sc->sc_iot, iobase, AD1848_NPORT, 0, &sc->sc_ioh)) 179 return 0; 180 181 if (!ad1848_isa_probe(isc)) { 182 bus_space_unmap(sc->sc_iot, sc->sc_ioh, AD1848_NPORT); 183 return 0; 184 } else 185 return 1; 186 } 187 188 /* 189 * Probe for the ad1848 chip 190 */ 191 int 192 ad1848_isa_probe(isc) 193 struct ad1848_isa_softc *isc; 194 { 195 struct ad1848_softc *sc = &isc->sc_ad1848; 196 u_char tmp, tmp1 = 0xff, tmp2 = 0xff; 197 int i, t; 198 199 sc->sc_readreg = ad1848_isa_read; 200 sc->sc_writereg = ad1848_isa_write; 201 202 /* Is there an ad1848 chip ? */ 203 sc->MCE_bit = MODE_CHANGE_ENABLE; 204 sc->mode = 1; /* MODE 1 = original ad1848/ad1846/cs4248 */ 205 206 /* 207 * Check that the I/O address is in use. 208 * 209 * The SP_IN_INIT bit of the base I/O port is known to be 0 after the 210 * chip has performed its power-on initialization. Just assume 211 * this has happened before the OS is starting. 212 * 213 * If the I/O address is unused, inb() typically returns 0xff. 214 */ 215 tmp = ADREAD(sc, AD1848_IADDR); 216 if (tmp & SP_IN_INIT) { /* Not a AD1848 */ 217 DPRINTF(("ad_detect_A %x\n", tmp)); 218 goto bad; 219 } 220 221 /* 222 * Test if it's possible to change contents of the indirect registers. 223 * Registers 0 and 1 are ADC volume registers. The bit 0x10 is read 224 * only so try to avoid using it. The bit 0x20 is the mic preamp 225 * enable; on some chips it is always the same in both registers, so 226 * we avoid tests where they are different. 227 */ 228 ad_write(sc, 0, 0x8a); 229 ad_write(sc, 1, 0x45); /* 0x55 with bit 0x10 clear */ 230 tmp1 = ad_read(sc, 0); 231 tmp2 = ad_read(sc, 1); 232 233 if (tmp1 != 0x8a || tmp2 != 0x45) { 234 DPRINTF(("ad_detect_B (%x/%x)\n", tmp1, tmp2)); 235 goto bad; 236 } 237 238 ad_write(sc, 0, 0x65); 239 ad_write(sc, 1, 0xaa); 240 tmp1 = ad_read(sc, 0); 241 tmp2 = ad_read(sc, 1); 242 243 if (tmp1 != 0x65 || tmp2 != 0xaa) { 244 DPRINTF(("ad_detect_C (%x/%x)\n", tmp1, tmp2)); 245 goto bad; 246 } 247 248 /* 249 * The indirect register I12 has some read only bits. Lets 250 * try to change them. 251 */ 252 tmp = ad_read(sc, SP_MISC_INFO); 253 ad_write(sc, SP_MISC_INFO, (~tmp) & 0x0f); 254 255 /* Here, AD1845 may sometimes be busy. Wait til it becomes ready. */ 256 for (t = 0; t < 100000 && ADREAD(sc, AD1848_IADDR) & SP_IN_INIT; t++) 257 ; 258 #ifdef AUDIO_DEBUG 259 if (t) 260 DPRINTF(("ad1848_isa_probe: t %d\n", t)); 261 #endif 262 263 if ((tmp & 0x0f) != ((tmp1 = ad_read(sc, SP_MISC_INFO)) & 0x0f)) { 264 DPRINTF(("ad_detect_D (%x)\n", tmp1)); 265 goto bad; 266 } 267 268 /* 269 * MSB and 4 LSBs of the reg I12 tell the chip revision. 270 * 271 * A preliminary version of the AD1846 data sheet stated that it 272 * used an ID field of 0x0B. The current version, however, 273 * states that the AD1846 uses ID 0x0A, just like the AD1848K. 274 * 275 * this switch statement will need updating as newer clones arrive.... 276 */ 277 switch (tmp1 & 0x8f) { 278 case 0x09: 279 sc->chip_name = "AD1848J"; 280 break; 281 case 0x0A: 282 sc->chip_name = "AD1848K"; 283 break; 284 #if 0 /* See above */ 285 case 0x0B: 286 sc->chip_name = "AD1846"; 287 break; 288 #endif 289 case 0x81: 290 sc->chip_name = "CS4248revB"; /* or CS4231 rev B; see below */ 291 break; 292 case 0x89: 293 sc->chip_name = "CS4248"; 294 break; 295 case 0x8A: 296 sc->chip_name = "broken"; /* CS4231/AD1845; see below */ 297 break; 298 default: 299 sc->chip_name = "unknown"; 300 DPRINTF(("ad1848: unknown codec version 0x%02x\n", 301 tmp1 & 0x8f)); 302 break; 303 } 304 305 /* 306 * The original AD1848/CS4248 has just 16 indirect registers. This 307 * means that I0 and I16 should return the same value (etc.). 308 * Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test 309 * fails with CS4231, AD1845, etc. 310 */ 311 ad_write(sc, SP_MISC_INFO, 0); /* Mode2 = disabled */ 312 313 for (i = 0; i < 16; i++) 314 if ((tmp1 = ad_read(sc, i)) != (tmp2 = ad_read(sc, i + 16))) { 315 if (i != SP_TEST_AND_INIT) { 316 DPRINTF(("ad_detect_F(%d/%x/%x)\n", i, tmp1, tmp2)); 317 goto bad; 318 } 319 } 320 321 /* 322 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit 323 * The bit 0x80 is always 1 in CS4248, CS4231, and AD1845. 324 */ 325 ad_write(sc, SP_MISC_INFO, MODE2); /* Set mode2, clear 0x80 */ 326 327 tmp1 = ad_read(sc, SP_MISC_INFO); 328 if ((tmp1 & 0xc0) == (0x80 | MODE2)) { 329 /* 330 * CS4231 or AD1845 detected - is it? 331 * 332 * Verify that setting I2 doesn't change I18. 333 */ 334 ad_write(sc, 18, 0x88); /* Set I18 to known value */ 335 336 ad_write(sc, 2, 0x45); 337 if ((tmp2 = ad_read(sc, 18)) != 0x45) { /* No change -> CS4231? */ 338 ad_write(sc, 2, 0xaa); 339 if ((tmp2 = ad_read(sc, 18)) == 0xaa) { /* Rotten bits? */ 340 DPRINTF(("ad_detect_H(%x)\n", tmp2)); 341 goto bad; 342 } 343 344 sc->mode = 2; 345 346 /* 347 * It's a CS4231, or another clone with 32 registers. 348 * Let's find out which by checking I25. 349 */ 350 if ((tmp1 & 0x8f) == 0x8a) { 351 tmp1 = ad_read(sc, CS_VERSION_ID); 352 switch (tmp1 & 0xe7) { 353 case 0xA0: 354 sc->chip_name = "CS4231A"; 355 break; 356 case 0x80: 357 /* XXX I25 no good, AD1845 same as CS4231 */ 358 /* 359 * XXX 360 * This test is correct only after reset 361 */ 362 if (ad_read(sc, 17) & 0xf0) { 363 sc->chip_name = "AD1845"; 364 sc->is_ad1845 = 1; 365 } else 366 sc->chip_name = "CS4231"; 367 break; 368 case 0x82: 369 sc->chip_name = "CS4232"; 370 break; 371 case 0x03: 372 case 0x83: 373 sc->chip_name = "CS4236"; 374 375 /* 376 * Try to switch to mode3 (CS4236B or 377 * CS4237B) by setting CMS to 3. A 378 * plain CS4236 will not react to 379 * LLBM settings. 380 */ 381 ad_write(sc, SP_MISC_INFO, MODE3); 382 383 tmp1 = ad_read(sc, CS_LEFT_LINE_CONTROL); 384 ad_write(sc, CS_LEFT_LINE_CONTROL, 0xe0); 385 tmp2 = ad_read(sc, CS_LEFT_LINE_CONTROL); 386 if (tmp2 == 0xe0) { 387 /* 388 * it's a CS4237B or another 389 * clone supporting mode 3. 390 * Let's determine which by 391 * enabling extended registers 392 * and checking X25. 393 */ 394 tmp2 = ad_xread(sc, CS_X_CHIP_VERSION); 395 switch (tmp2 & X_CHIP_VERSIONF_CID) { 396 case X_CHIP_CID_CS4236BB: 397 sc->chip_name = "CS4236BrevB"; 398 break; 399 case X_CHIP_CID_CS4236B: 400 sc->chip_name = "CS4236B"; 401 break; 402 case X_CHIP_CID_CS4237B: 403 sc->chip_name = "CS4237B"; 404 break; 405 default: 406 sc->chip_name = "CS4236B compatible"; 407 DPRINTF(("cs4236: unknown mode 3 compatible codec, version 0x%02x\n", tmp2)); 408 break; 409 } 410 sc->mode = 3; 411 } 412 413 /* restore volume control information */ 414 ad_write(sc, CS_LEFT_LINE_CONTROL, tmp1); 415 break; 416 } 417 } 418 } 419 } 420 421 /* Wait for 1848 to init */ 422 while(ADREAD(sc, AD1848_IADDR) & SP_IN_INIT) 423 ; 424 425 /* Wait for 1848 to autocal */ 426 ADWRITE(sc, AD1848_IADDR, SP_TEST_AND_INIT); 427 while(ADREAD(sc, AD1848_IDATA) & AUTO_CAL_IN_PROG) 428 ; 429 430 return 1; 431 bad: 432 return 0; 433 } 434 435 /* Unmap the I/O ports */ 436 void 437 ad1848_isa_unmap(isc) 438 struct ad1848_isa_softc *isc; 439 { 440 struct ad1848_softc *sc = &isc->sc_ad1848; 441 bus_space_unmap(sc->sc_iot, sc->sc_ioh, AD1848_NPORT); 442 } 443 444 /* 445 * Attach hardware to driver, attach hardware driver to audio 446 * pseudo-device driver . 447 */ 448 void 449 ad1848_isa_attach(isc) 450 struct ad1848_isa_softc *isc; 451 { 452 struct ad1848_softc *sc = &isc->sc_ad1848; 453 454 sc->sc_readreg = ad1848_isa_read; 455 sc->sc_writereg = ad1848_isa_write; 456 457 if (isc->sc_playdrq != -1) 458 isc->sc_play_maxsize = isa_dmamaxsize(isc->sc_ic, 459 isc->sc_playdrq); 460 if (isc->sc_recdrq != -1 && isc->sc_recdrq != isc->sc_playdrq) 461 isc->sc_rec_maxsize = isa_dmamaxsize(isc->sc_ic, 462 isc->sc_recdrq); 463 464 ad1848_attach(sc); 465 } 466 467 int 468 ad1848_isa_open(addr, flags) 469 void *addr; 470 int flags; 471 { 472 struct ad1848_isa_softc *isc = addr; 473 struct ad1848_softc *sc = &isc->sc_ad1848; 474 int error, state; 475 476 DPRINTF(("ad1848_isa_open: sc=%p\n", isc)); 477 state = 0; 478 479 if (isc->sc_playdrq != -1) { 480 error = isa_dmamap_create(isc->sc_ic, isc->sc_playdrq, 481 isc->sc_play_maxsize, BUS_DMA_NOWAIT); 482 if (error) { 483 printf("%s: can't create map for drq %d\n", 484 sc->sc_dev.dv_xname, isc->sc_playdrq); 485 goto bad; 486 } 487 state |= 1; 488 } 489 if (isc->sc_recdrq != -1 && isc->sc_recdrq != isc->sc_playdrq) { 490 error = isa_dmamap_create(isc->sc_ic, isc->sc_recdrq, 491 isc->sc_rec_maxsize, BUS_DMA_NOWAIT); 492 if (error) { 493 printf("%s: can't create map for drq %d\n", 494 sc->sc_dev.dv_xname, isc->sc_recdrq); 495 goto bad; 496 } 497 state |= 2; 498 } 499 500 #ifndef AUDIO_NO_POWER_CTL 501 /* Power-up chip */ 502 if (isc->powerctl) 503 isc->powerctl(isc->powerarg, flags); 504 #endif 505 506 /* Init and mute wave output */ 507 ad1848_mute_wave_output(sc, WAVE_MUTE2_INIT, 1); 508 509 error = ad1848_open(sc, flags); 510 if (error) { 511 #ifndef AUDIO_NO_POWER_CTL 512 if (isc->powerctl) 513 isc->powerctl(isc->powerarg, 0); 514 #endif 515 goto bad; 516 } 517 518 DPRINTF(("ad1848_isa_open: opened\n")); 519 return (0); 520 521 bad: 522 if (state & 1) 523 isa_dmamap_destroy(isc->sc_ic, isc->sc_playdrq); 524 if (state & 2) 525 isa_dmamap_destroy(isc->sc_ic, isc->sc_recdrq); 526 527 return (error); 528 } 529 530 /* 531 * Close function is called at splaudio(). 532 */ 533 void 534 ad1848_isa_close(addr) 535 void *addr; 536 { 537 struct ad1848_isa_softc *isc = addr; 538 struct ad1848_softc *sc = &isc->sc_ad1848; 539 540 ad1848_isa_halt_output(isc); 541 ad1848_isa_halt_input(isc); 542 543 isc->sc_pintr = isc->sc_rintr = NULL; 544 545 if (isc->sc_playdrq != -1) 546 isa_dmamap_destroy(isc->sc_ic, isc->sc_playdrq); 547 if (isc->sc_recdrq != -1 && isc->sc_recdrq != isc->sc_playdrq) 548 isa_dmamap_destroy(isc->sc_ic, isc->sc_recdrq); 549 550 DPRINTF(("ad1848_isa_close: stop DMA\n")); 551 ad1848_close(sc); 552 553 #ifndef AUDIO_NO_POWER_CTL 554 /* Power-down chip */ 555 if (isc->powerctl) 556 isc->powerctl(isc->powerarg, 0); 557 #endif 558 } 559 560 int 561 ad1848_isa_trigger_input(addr, start, end, blksize, intr, arg, param) 562 void *addr; 563 void *start, *end; 564 int blksize; 565 void (*intr) __P((void *)); 566 void *arg; 567 struct audio_params *param; 568 { 569 struct ad1848_isa_softc *isc = addr; 570 struct ad1848_softc *sc = &isc->sc_ad1848; 571 u_int8_t reg; 572 573 isa_dmastart(isc->sc_ic, isc->sc_recdrq, start, 574 (char *)end - (char *)start, NULL, 575 DMAMODE_READ | DMAMODE_LOOPDEMAND, BUS_DMA_NOWAIT); 576 577 isc->sc_recrun = 1; 578 if (sc->mode == 2 && isc->sc_playdrq != isc->sc_recdrq) { 579 isc->sc_rintr = intr; 580 isc->sc_rarg = arg; 581 } else { 582 isc->sc_pintr = intr; 583 isc->sc_parg = arg; 584 } 585 586 587 /* 588 * Calculate number of transfers. 589 * Note that ADPCM is always transferred 4 bytes at at a time. 590 */ 591 blksize = (param->encoding == AUDIO_ENCODING_ADPCM) ? blksize / 4 - 1 : 592 (blksize * 8) / (param->precision * param->factor * param->channels) - 1; 593 594 if (sc->mode >= 2) { 595 ad_write(sc, CS_LOWER_REC_CNT, blksize & 0xff); 596 ad_write(sc, CS_UPPER_REC_CNT, blksize >> 8); 597 } else { 598 ad_write(sc, SP_LOWER_BASE_COUNT, blksize & 0xff); 599 ad_write(sc, SP_UPPER_BASE_COUNT, blksize >> 8); 600 } 601 602 reg = ad_read(sc, SP_INTERFACE_CONFIG); 603 ad_write(sc, SP_INTERFACE_CONFIG, CAPTURE_ENABLE|reg); 604 605 return (0); 606 } 607 608 int 609 ad1848_isa_trigger_output(addr, start, end, blksize, intr, arg, param) 610 void *addr; 611 void *start, *end; 612 int blksize; 613 void (*intr) __P((void *)); 614 void *arg; 615 struct audio_params *param; 616 { 617 struct ad1848_isa_softc *isc = addr; 618 struct ad1848_softc *sc = &isc->sc_ad1848; 619 u_int8_t reg; 620 621 isa_dmastart(isc->sc_ic, isc->sc_playdrq, start, 622 (char *)end - (char *)start, NULL, 623 DMAMODE_WRITE | DMAMODE_LOOPDEMAND, BUS_DMA_NOWAIT); 624 625 isc->sc_playrun = 1; 626 isc->sc_pintr = intr; 627 isc->sc_parg = arg; 628 629 /* 630 * Calculate number of transfers. 631 * Note that ADPCM is always transferred 4 bytes at at a time. 632 */ 633 blksize = (param->encoding == AUDIO_ENCODING_ADPCM) ? blksize / 4 - 1 : 634 (blksize * 8) / (param->precision * param->factor * param->channels) - 1; 635 636 ad_write(sc, SP_LOWER_BASE_COUNT, blksize & 0xff); 637 ad_write(sc, SP_UPPER_BASE_COUNT, blksize >> 8); 638 639 /* Unmute wave output */ 640 ad1848_mute_wave_output(sc, WAVE_MUTE2, 0); 641 642 reg = ad_read(sc, SP_INTERFACE_CONFIG); 643 ad_write(sc, SP_INTERFACE_CONFIG, PLAYBACK_ENABLE|reg); 644 645 return (0); 646 } 647 648 int 649 ad1848_isa_halt_input(addr) 650 void *addr; 651 { 652 struct ad1848_isa_softc *isc = addr; 653 struct ad1848_softc *sc = &isc->sc_ad1848; 654 655 if (isc->sc_recrun) { 656 ad1848_halt_input(sc); 657 isa_dmaabort(isc->sc_ic, isc->sc_recdrq); 658 isc->sc_recrun = 0; 659 } 660 661 return (0); 662 } 663 664 int 665 ad1848_isa_halt_output(addr) 666 void *addr; 667 { 668 struct ad1848_isa_softc *isc = addr; 669 struct ad1848_softc *sc = &isc->sc_ad1848; 670 671 if (isc->sc_playrun) { 672 /* Mute wave output */ 673 ad1848_mute_wave_output(sc, WAVE_MUTE2, 1); 674 675 ad1848_halt_output(sc); 676 isa_dmaabort(isc->sc_ic, isc->sc_playdrq); 677 isc->sc_playrun = 0; 678 } 679 680 return (0); 681 } 682 683 int 684 ad1848_isa_intr(arg) 685 void *arg; 686 { 687 struct ad1848_isa_softc *isc = arg; 688 struct ad1848_softc *sc = &isc->sc_ad1848; 689 int retval = 0; 690 u_char status; 691 692 /* Get intr status */ 693 status = ADREAD(sc, AD1848_STATUS); 694 695 #ifdef AUDIO_DEBUG 696 if (ad1848debug > 1) 697 printf("ad1848_isa_intr: pintr=%p rintr=%p status=%x\n", 698 isc->sc_pintr, isc->sc_rintr, status); 699 #endif 700 isc->sc_interrupts++; 701 702 /* Handle interrupt */ 703 if ((status & INTERRUPT_STATUS) != 0) { 704 if (sc->mode == 2 && isc->sc_playdrq != isc->sc_recdrq) { 705 status = ad_read(sc, CS_IRQ_STATUS); 706 if ((status & CS_IRQ_PI) && isc->sc_pintr != NULL) { 707 (*isc->sc_pintr)(isc->sc_parg); 708 retval = 1; 709 } 710 if ((status & CS_IRQ_CI) && isc->sc_rintr != NULL) { 711 (*isc->sc_rintr)(isc->sc_rarg); 712 retval = 1; 713 } 714 } else { 715 if (isc->sc_pintr != NULL) { 716 (*isc->sc_pintr)(isc->sc_parg); 717 retval = 1; 718 } 719 } 720 721 /* Clear interrupt */ 722 ADWRITE(sc, AD1848_STATUS, 0); 723 } 724 return(retval); 725 } 726 727 void * 728 ad1848_isa_malloc(addr, direction, size, pool, flags) 729 void *addr; 730 int direction; 731 size_t size; 732 int pool, flags; 733 { 734 struct ad1848_isa_softc *isc = addr; 735 int drq; 736 737 if (direction == AUMODE_PLAY) 738 drq = isc->sc_playdrq; 739 else 740 drq = isc->sc_recdrq; 741 return (isa_malloc(isc->sc_ic, drq, size, pool, flags)); 742 } 743 744 void 745 ad1848_isa_free(addr, ptr, pool) 746 void *addr; 747 void *ptr; 748 int pool; 749 { 750 isa_free(ptr, pool); 751 } 752 753 size_t 754 ad1848_isa_round_buffersize(addr, direction, size) 755 void *addr; 756 int direction; 757 size_t size; 758 { 759 struct ad1848_isa_softc *isc = addr; 760 bus_size_t maxsize; 761 762 if (direction == AUMODE_PLAY) 763 maxsize = isc->sc_play_maxsize; 764 else if (isc->sc_recdrq == isc->sc_playdrq) 765 maxsize = isc->sc_play_maxsize; 766 else 767 maxsize = isc->sc_rec_maxsize; 768 769 if (size > maxsize) 770 size = maxsize; 771 return (size); 772 } 773 774 paddr_t 775 ad1848_isa_mappage(addr, mem, off, prot) 776 void *addr; 777 void *mem; 778 off_t off; 779 int prot; 780 { 781 return isa_mappage(mem, off, prot); 782 } 783 784 int 785 ad1848_isa_get_props(addr) 786 void *addr; 787 { 788 struct ad1848_isa_softc *isc = addr; 789 790 return (AUDIO_PROP_MMAP | 791 (isc->sc_playdrq != isc->sc_recdrq ? AUDIO_PROP_FULLDUPLEX : 0)); 792 } 793