1 /* $NetBSD: addcom_isa.c,v 1.4 2002/01/07 21:47:03 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Michael Graff. All rights reserved. 5 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1995 Charles M. Hannum. All rights reserved. 7 * 8 * This code is derived from public-domain software written by 9 * Roland McGrath, and information provided by David Muir Sharnoff. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Charles M. Hannum. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * This code was written and tested with the Addonics FlexPort 8S. 39 * It has 8 ports, using 16650-compatible chips, sharing a single 40 * interrupt. 41 * 42 * An interrupt status register exists at 0x240, according to the 43 * skimpy documentation supplied. It doesn't change depending on 44 * io base address, so only one of these cards can ever be used at 45 * a time. 46 * 47 * This card is different from the boca or other cards in that ports 48 * 0..5 are from addresses 0x108..0x137, and 6..7 are from 0x200..0x20f, 49 * making a gap that the other cards do not have. 50 * 51 * The addresses which are documented are 0x108, 0x1108, 0x1d08, and 52 * 0x8508, for the base (port 0) address. 53 * 54 * --Michael <explorer@netbsd.org> -- April 21, 2000 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: addcom_isa.c,v 1.4 2002/01/07 21:47:03 thorpej Exp $"); 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/device.h> 63 #include <sys/termios.h> 64 65 #include <machine/bus.h> 66 #include <machine/intr.h> 67 68 #include <dev/ic/comreg.h> 69 #include <dev/ic/comvar.h> 70 71 #include <dev/isa/isavar.h> 72 #include <dev/isa/com_multi.h> 73 74 #define NSLAVES 8 75 76 /* 77 * Grr. This card always uses 0x420 for the status register, regardless 78 * of io base address. 79 */ 80 #define STATUS_IOADDR 0x420 81 #define STATUS_SIZE 8 /* May be bogus... */ 82 83 struct addcom_softc { 84 struct device sc_dev; 85 void *sc_ih; 86 87 bus_space_tag_t sc_iot; 88 int sc_iobase; 89 90 int sc_alive; /* mask of slave units attached */ 91 void *sc_slaves[NSLAVES]; /* com device unit numbers */ 92 bus_space_handle_t sc_slaveioh[NSLAVES]; 93 bus_space_handle_t sc_statusioh; 94 }; 95 96 #define SLAVE_IOBASE_OFFSET 0x108 97 static int slave_iobases[8] = { 98 0x108, /* port 0, base port */ 99 0x110, 100 0x118, 101 0x120, 102 0x128, 103 0x130, 104 0x200, /* port 7, note address skip... */ 105 0x208 106 }; 107 108 int addcomprobe __P((struct device *, struct cfdata *, void *)); 109 void addcomattach __P((struct device *, struct device *, void *)); 110 int addcomintr __P((void *)); 111 int addcomprint __P((void *, const char *)); 112 113 struct cfattach addcom_isa_ca = { 114 sizeof(struct addcom_softc), addcomprobe, addcomattach, 115 }; 116 117 int 118 addcomprobe(struct device *parent, struct cfdata *self, void *aux) 119 { 120 struct isa_attach_args *ia = aux; 121 bus_space_tag_t iot = ia->ia_iot; 122 bus_space_handle_t ioh; 123 int i, iobase, rv = 1; 124 125 /* 126 * Do the normal com probe for the first UART and assume 127 * its presence, and the ability to map the other UARTS, 128 * means there is a multiport board there. 129 * XXX Needs more robustness. 130 */ 131 132 if (ia->ia_nio < 1) 133 return (0); 134 if (ia->ia_nirq < 1) 135 return (0); 136 137 if (ISA_DIRECT_CONFIG(ia)) 138 return (0); 139 140 /* Disallow wildcarded i/o address. */ 141 if (ia->ia_io[0].ir_addr == ISACF_PORT_DEFAULT) 142 return (0); 143 if (ia->ia_irq[0].ir_irq == ISACF_IRQ_DEFAULT) 144 return (0); 145 146 iobase = ia->ia_io[0].ir_addr; 147 148 /* if the first port is in use as console, then it. */ 149 if (com_is_console(iot, iobase, 0)) 150 goto checkmappings; 151 152 if (bus_space_map(iot, iobase, COM_NPORTS, 0, &ioh)) { 153 rv = 0; 154 goto out; 155 } 156 rv = comprobe1(iot, ioh); 157 bus_space_unmap(iot, ioh, COM_NPORTS); 158 if (rv == 0) 159 goto out; 160 161 checkmappings: 162 for (i = 1; i < NSLAVES; i++) { 163 iobase += slave_iobases[i] - slave_iobases[i - 1]; 164 165 if (com_is_console(iot, iobase, 0)) 166 continue; 167 168 if (bus_space_map(iot, iobase, COM_NPORTS, 0, &ioh)) { 169 rv = 0; 170 goto out; 171 } 172 bus_space_unmap(iot, ioh, COM_NPORTS); 173 } 174 175 out: 176 if (rv) { 177 ia->ia_nio = 1; 178 ia->ia_io[0].ir_size = NSLAVES * COM_NPORTS; 179 180 ia->ia_nirq = 1; 181 182 ia->ia_niomem = 0; 183 ia->ia_ndrq = 0; 184 } 185 return (rv); 186 } 187 188 int 189 addcomprint(void *aux, const char *pnp) 190 { 191 struct commulti_attach_args *ca = aux; 192 193 if (pnp) 194 printf("com at %s", pnp); 195 printf(" slave %d", ca->ca_slave); 196 return (UNCONF); 197 } 198 199 void 200 addcomattach(struct device *parent, struct device *self, void *aux) 201 { 202 struct addcom_softc *sc = (void *)self; 203 struct isa_attach_args *ia = aux; 204 struct commulti_attach_args ca; 205 bus_space_tag_t iot = ia->ia_iot; 206 int i, iobase; 207 208 printf("\n"); 209 210 sc->sc_iot = ia->ia_iot; 211 sc->sc_iobase = ia->ia_io[0].ir_addr; 212 213 if (bus_space_map(iot, STATUS_IOADDR, STATUS_SIZE, 214 0, &sc->sc_statusioh)) { 215 printf("%s: can't map status space\n", sc->sc_dev.dv_xname); 216 return; 217 } 218 219 for (i = 0; i < NSLAVES; i++) { 220 iobase = sc->sc_iobase 221 + slave_iobases[i] 222 - SLAVE_IOBASE_OFFSET; 223 if (!com_is_console(iot, iobase, &sc->sc_slaveioh[i]) && 224 bus_space_map(iot, iobase, COM_NPORTS, 0, 225 &sc->sc_slaveioh[i])) { 226 printf("%s: can't map i/o space for slave %d\n", 227 sc->sc_dev.dv_xname, i); 228 return; 229 } 230 } 231 232 for (i = 0; i < NSLAVES; i++) { 233 ca.ca_slave = i; 234 ca.ca_iot = sc->sc_iot; 235 ca.ca_ioh = sc->sc_slaveioh[i]; 236 ca.ca_iobase = sc->sc_iobase 237 + slave_iobases[i] 238 - SLAVE_IOBASE_OFFSET; 239 ca.ca_noien = 0; 240 241 sc->sc_slaves[i] = config_found(self, &ca, addcomprint); 242 if (sc->sc_slaves[i] != NULL) 243 sc->sc_alive |= 1 << i; 244 } 245 246 sc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq[0].ir_irq, 247 IST_EDGE, IPL_SERIAL, addcomintr, sc); 248 } 249 250 int 251 addcomintr(void *arg) 252 { 253 struct addcom_softc *sc = arg; 254 bus_space_tag_t iot = sc->sc_iot; 255 int alive = sc->sc_alive; 256 int bits; 257 258 bits = bus_space_read_1(iot, sc->sc_statusioh, 0) & alive; 259 if (bits == 0) 260 return (0); 261 262 for (;;) { 263 #define TRY(n) \ 264 if (bits & (1 << (n))) \ 265 comintr(sc->sc_slaves[n]); 266 TRY(0); 267 TRY(1); 268 TRY(2); 269 TRY(3); 270 TRY(4); 271 TRY(5); 272 TRY(6); 273 TRY(7); 274 #undef TRY 275 bits = bus_space_read_1(iot, sc->sc_statusioh, 0) & alive; 276 if (bits == 0) 277 return (1); 278 } 279 } 280