1 /* $NetBSD: adv_isa.c,v 1.7 2002/10/02 02:14:45 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 5 * 6 * Author: Baldassare Dante Profeta <dante@mclink.it> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /* 37 * Device probe and attach routines for the following 38 * Advanced Systems Inc. SCSI controllers: 39 * 40 * Connectivity Products: 41 * ABP510/5150 - Bus-Master ISA (240 CDB) (Footnote 1) 42 * ABP5140 - Bus-Master ISA (16 CDB) (Footnote 1) (Footnote 2) 43 * ABP5142 - Bus-Master ISA with floppy (16 CDB) (Footnote 3) 44 * 45 * Single Channel Products: 46 * ABP542 - Bus-Master ISA with floppy (240 CDB) 47 * ABP842 - Bus-Master VL (240 CDB) 48 * 49 * Dual Channel Products: 50 * ABP852 - Dual Channel Bus-Master VL (240 CDB Per Channel) 51 * 52 * Footnotes: 53 * 1. This board has been shipped by HP with the 4020i CD-R drive. 54 * The board has no BIOS so it cannot control a boot device, but 55 * it can control any secondary SCSI device. 56 * 2. This board has been sold by SIIG as the i540 SpeedMaster. 57 * 3. This board has been sold by SIIG as the i542 SpeedMaster. 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: adv_isa.c,v 1.7 2002/10/02 02:14:45 thorpej Exp $"); 62 63 #include <sys/param.h> 64 #include <sys/systm.h> 65 #include <sys/kernel.h> 66 #include <sys/errno.h> 67 #include <sys/ioctl.h> 68 #include <sys/device.h> 69 #include <sys/buf.h> 70 #include <sys/proc.h> 71 #include <sys/user.h> 72 #include <sys/queue.h> 73 74 #include <machine/bus.h> 75 76 #include <dev/scsipi/scsi_all.h> 77 #include <dev/scsipi/scsipi_all.h> 78 #include <dev/scsipi/scsiconf.h> 79 80 #include <dev/isa/isavar.h> 81 82 #include <dev/ic/advlib.h> 83 #include <dev/ic/adv.h> 84 85 86 /* Possible port addresses an ISA or VL adapter can live at */ 87 static int asc_ioport[ASC_IOADR_TABLE_MAX_IX] = 88 { 89 0x100, 90 ASC_IOADR_1, /* First selection in BIOS setup */ 91 0x120, 92 ASC_IOADR_2, /* Second selection in BIOS setup */ 93 0x140, 94 ASC_IOADR_3, /* Third selection in BIOS setup */ 95 ASC_IOADR_4, /* Fourth selection in BIOS setup */ 96 ASC_IOADR_5, /* Fifth selection in BIOS setup */ 97 ASC_IOADR_6, /* Sixth selection in BIOS setup */ 98 ASC_IOADR_7, /* Seventh selection in BIOS setup */ 99 ASC_IOADR_8 /* Eighth and default selection in BIOS setup */ 100 }; 101 102 /******************************************************************************/ 103 104 int adv_isa_probe __P((struct device *, struct cfdata *, void *)); 105 void adv_isa_attach __P((struct device *, struct device *, void *)); 106 107 CFATTACH_DECL(adv_isa, sizeof(ASC_SOFTC), 108 adv_isa_probe, adv_isa_attach, NULL, NULL); 109 110 /******************************************************************************/ 111 112 int 113 adv_isa_probe(parent, match, aux) 114 struct device *parent; 115 struct cfdata *match; 116 void *aux; 117 { 118 struct isa_attach_args *ia = aux; 119 bus_space_tag_t iot = ia->ia_iot; 120 bus_space_handle_t ioh; 121 int port_index; 122 int iobase, irq, drq; 123 int rv = 0; 124 125 if (ia->ia_nio < 1) 126 return (0); 127 if (ia->ia_nirq < 1) 128 return (0); 129 if (ia->ia_ndrq < 1) 130 return (0); 131 132 if (ISA_DIRECT_CONFIG(ia)) 133 return (0); 134 135 /* 136 * If the I/O address is wildcarded, look for boards 137 * in ascending order. 138 */ 139 if (ia->ia_io[0].ir_addr == ISACF_PORT_DEFAULT) { 140 for (port_index = 0; port_index < ASC_IOADR_TABLE_MAX_IX; 141 port_index++) { 142 iobase = asc_ioport[port_index]; 143 144 if (iobase) { 145 if (bus_space_map(iot, iobase, ASC_IOADR_GAP, 146 0, &ioh)) 147 continue; 148 149 rv = AscFindSignature(iot, ioh); 150 151 if (rv) { 152 ia->ia_io[0].ir_addr = iobase; 153 break; 154 } 155 156 bus_space_unmap(iot, ioh, ASC_IOADR_GAP); 157 } 158 } 159 if (rv == 0) 160 return (0); 161 } else { 162 iobase = ia->ia_io[0].ir_addr; 163 if (bus_space_map(iot, iobase, ASC_IOADR_GAP, 0, &ioh)) 164 return (0); 165 166 rv = AscFindSignature(iot, ioh); 167 168 if (rv == 0) { 169 bus_space_unmap(iot, ioh, ASC_IOADR_GAP); 170 return (0); 171 } 172 } 173 174 /* XXXJRT Probe routines should not have side-effects!! */ 175 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 176 ASC_SET_CHIP_STATUS(iot, ioh, 0); 177 178 irq = AscGetChipIRQ(iot, ioh, ASC_IS_ISA); 179 drq = AscGetIsaDmaChannel(iot, ioh); 180 181 /* Verify that the IRQ/DRQ match (or are wildcarded). */ 182 if (ia->ia_irq[0].ir_irq != ISACF_IRQ_DEFAULT && 183 ia->ia_irq[0].ir_irq != irq) { 184 rv = 0; 185 goto out; 186 } 187 if (ia->ia_drq[0].ir_drq != ISACF_DRQ_DEFAULT && 188 ia->ia_drq[0].ir_drq != drq) { 189 rv = 0; 190 goto out; 191 } 192 193 ia->ia_nio = 1; 194 ia->ia_io[0].ir_addr = iobase; 195 ia->ia_io[0].ir_size = ASC_IOADR_GAP; 196 197 ia->ia_nirq = 1; 198 ia->ia_irq[0].ir_irq = irq; 199 200 ia->ia_ndrq = 1; 201 ia->ia_drq[0].ir_drq = drq; 202 203 ia->ia_niomem = 0; 204 205 out: 206 bus_space_unmap(iot, ioh, ASC_IOADR_GAP); 207 return rv; 208 } 209 210 211 void 212 adv_isa_attach(parent, self, aux) 213 struct device *parent, *self; 214 void *aux; 215 { 216 struct isa_attach_args *ia = aux; 217 ASC_SOFTC *sc = (void *) self; 218 bus_space_tag_t iot = ia->ia_iot; 219 bus_space_handle_t ioh; 220 isa_chipset_tag_t ic = ia->ia_ic; 221 int error; 222 223 printf("\n"); 224 225 sc->sc_flags = 0x0; 226 227 if (bus_space_map(iot, ia->ia_io[0].ir_addr, ASC_IOADR_GAP, 0, &ioh)) { 228 printf("%s: can't map i/o space\n", sc->sc_dev.dv_xname); 229 return; 230 } 231 232 sc->sc_iot = iot; 233 sc->sc_ioh = ioh; 234 sc->sc_dmat = ia->ia_dmat; 235 sc->bus_type = ASC_IS_ISA; 236 sc->chip_version = ASC_GET_CHIP_VER_NO(iot, ioh); 237 /* 238 * Memo: 239 * for EISA cards: 240 * sc->chip_version = (ASC_CHIP_MIN_VER_EISA - 1) + ea->ea_pid[1]; 241 */ 242 243 /* 244 * Initialize the board 245 */ 246 if (adv_init(sc)) { 247 printf("%s: adv_init failed\n", sc->sc_dev.dv_xname); 248 return; 249 } 250 251 if ((error = isa_dmacascade(ic, ia->ia_drq[0].ir_drq)) != 0) { 252 printf("%s: unable to cascade DRQ, error = %d\n", 253 sc->sc_dev.dv_xname, error); 254 return; 255 } 256 257 sc->sc_ih = isa_intr_establish(ic, ia->ia_irq[0].ir_irq, IST_EDGE, 258 IPL_BIO, adv_intr, sc); 259 if (sc->sc_ih == NULL) { 260 printf("%s: couldn't establish interrupt\n", 261 sc->sc_dev.dv_xname); 262 return; 263 } 264 265 adv_attach(sc); 266 } 267