1 /* $NetBSD: if_ecreg.h,v 1.1 1997/11/02 00:44:26 thorpej Exp $ */ 2 3 /* 4 * 3Com Etherlink II (3c503) register definitions. 5 * 6 * Copyright (C) 1993, David Greenman. This software may be used, modified, 7 * copied, distributed, and sold, in both source and binary form provided that 8 * the above copyright and these terms are retained. Under no circumstances is 9 * the author responsible for the proper functioning of this software, nor does 10 * the author assume any responsibility for damages incurred with its use. 11 */ 12 13 #ifndef _DEV_ISA_IF_ECREG_H_ 14 #define _DEV_ISA_IF_ECREG_H_ 15 16 #define ELINK2_NIC_OFFSET 0 17 #define ELINK2_ASIC_OFFSET 0x400 /* offset to nic i/o regs */ 18 19 /* 20 * XXX - The I/O address range is fragmented in the 3c503; this is the 21 * number of regs at iobase. 22 */ 23 #define ELINK2_NIC_PORTS 16 24 #define ELINK2_ASIC_PORTS 16 25 26 /* tx memory starts in second bank on 8bit cards */ 27 #define ELINK2_TX_PAGE_OFFSET_8BIT 0x20 28 29 /* tx memory starts in first bank on 16bit cards */ 30 #define ELINK2_TX_PAGE_OFFSET_16BIT 0x0 31 32 /* ...and rx memory starts in second bank */ 33 #define ELINK2_RX_PAGE_OFFSET_16BIT 0x20 34 35 36 /* 37 * Page Start Register. Must match PSTART in NIC. 38 */ 39 #define ELINK2_PSTR 0 40 41 /* 42 * Page Stop Register. Must match PSTOP in NIC. 43 */ 44 #define ELINK2_PSPR 1 45 46 /* 47 * DrQ Timer Register. Determines number of bytes to be transfered during a 48 * DMA burst. 49 */ 50 #define ELINK2_DQTR 2 51 52 /* 53 * Base Configuration Register. Read-only register which contains the 54 * board-configured I/O base address of the adapter. Bit encoded. 55 */ 56 #define ELINK2_BCFR 3 57 58 /* 59 * EPROM Configuration Register. Read-only register which contains the 60 * board-configured memory base address. Bit encoded. 61 */ 62 #define ELINK2_PCFR 4 63 64 /* 65 * GA Configuration Register. Gate-Array Configuration Register. 66 * 67 * mbs2 mbs1 mbs0 start address 68 * 0 0 0 0x0000 69 * 0 0 1 0x2000 70 * 0 1 0 0x4000 71 * 0 1 1 0x6000 72 * 73 * Note that with adapters with only 8K, the setting for 0x2000 must always be 74 * used. 75 */ 76 #define ELINK2_GACFR 5 77 78 #define ELINK2_GACFR_MBS0 0x01 79 #define ELINK2_GACFR_MBS1 0x02 80 #define ELINK2_GACFR_MBS2 0x04 81 82 #define ELINK2_GACFR_RSEL 0x08 /* enable shared memory */ 83 #define ELINK2_GACFR_TEST 0x10 /* for GA testing */ 84 #define ELINK2_GACFR_OWS 0x20 /* select 0WS access to GA */ 85 #define ELINK2_GACFR_TCM 0x40 /* Mask DMA interrupts */ 86 #define ELINK2_GACFR_NIM 0x80 /* Mask NIC interrupts */ 87 88 /* 89 * Control Register. Miscellaneous control functions. 90 */ 91 #define ELINK2_CR 6 92 93 #define ELINK2_CR_RST 0x01 /* Reset GA and NIC */ 94 #define ELINK2_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */ 95 #define ELINK2_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */ 96 #define ELINK2_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */ 97 #define ELINK2_CR_SHARE 0x10 /* select interrupt sharing option */ 98 #define ELINK2_CR_DBSEL 0x20 /* Double buffer select */ 99 #define ELINK2_CR_DDIR 0x40 /* DMA direction select */ 100 #define ELINK2_CR_START 0x80 /* Start DMA controller */ 101 102 /* 103 * Status Register. Miscellaneous status information. 104 */ 105 #define ELINK2_STREG 7 106 107 #define ELINK2_STREG_REV 0x07 /* GA revision */ 108 #define ELINK2_STREG_DIP 0x08 /* DMA in progress */ 109 #define ELINK2_STREG_DTC 0x10 /* DMA terminal count */ 110 #define ELINK2_STREG_OFLW 0x20 /* Overflow */ 111 #define ELINK2_STREG_UFLW 0x40 /* Underflow */ 112 #define ELINK2_STREG_DPRDY 0x80 /* Data port ready */ 113 114 /* 115 * Interrupt/DMA Configuration Register 116 */ 117 #define ELINK2_IDCFR 8 118 119 #define ELINK2_IDCFR_DRQ 0x07 /* DMA request */ 120 #define ELINK2_IDCFR_UNUSED 0x08 /* not used */ 121 #if 0 122 #define ELINK2_IDCFR_IRQ 0xF0 /* Interrupt request */ 123 #else 124 #define ELINK2_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */ 125 #define ELINK2_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */ 126 #define ELINK2_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */ 127 #define ELINK2_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */ 128 #endif 129 130 /* 131 * DMA Address Register MSB 132 */ 133 #define ELINK2_DAMSB 9 134 135 /* 136 * DMA Address Register LSB 137 */ 138 #define ELINK2_DALSB 0x0a 139 140 /* 141 * Vector Pointer Register 2 142 */ 143 #define ELINK2_VPTR2 0x0b 144 145 /* 146 * Vector Pointer Register 1 147 */ 148 #define ELINK2_VPTR1 0x0c 149 150 /* 151 * Vector Pointer Register 0 152 */ 153 #define ELINK2_VPTR0 0x0d 154 155 /* 156 * Register File Access MSB 157 */ 158 #define ELINK2_RFMSB 0x0e 159 160 /* 161 * Register File Access LSB 162 */ 163 #define ELINK2_RFLSB 0x0f 164 165 #endif /* _DEV_ISA_IF_ECREG_H_ */ 166