1 /* $NetBSD: if_ix.c,v 1.14 2002/01/08 17:20:44 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Rafal K. Boni. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: if_ix.c,v 1.14 2002/01/08 17:20:44 christos Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/mbuf.h> 45 #include <sys/errno.h> 46 #include <sys/device.h> 47 #include <sys/protosw.h> 48 #include <sys/socket.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_types.h> 53 #include <net/if_media.h> 54 #include <net/if_ether.h> 55 56 #include <machine/cpu.h> 57 #include <machine/bus.h> 58 #include <machine/intr.h> 59 60 #include <dev/isa/isareg.h> 61 #include <dev/isa/isavar.h> 62 63 #include <dev/ic/i82586reg.h> 64 #include <dev/ic/i82586var.h> 65 #include <dev/isa/if_ixreg.h> 66 67 #ifdef IX_DEBUG 68 #define DPRINTF(x) printf x 69 #else 70 #define DPRINTF(x) 71 #endif 72 73 int ix_media[] = { 74 IFM_ETHER | IFM_10_5, 75 IFM_ETHER | IFM_10_2, 76 IFM_ETHER | IFM_10_T, 77 }; 78 #define NIX_MEDIA (sizeof(ix_media) / sizeof(ix_media[0])) 79 80 struct ix_softc { 81 struct ie_softc sc_ie; 82 83 bus_space_tag_t sc_regt; /* space tag for registers */ 84 bus_space_handle_t sc_regh; /* space handle for registers */ 85 86 u_int8_t use_pio; /* use PIO rather than shared mem */ 87 u_int16_t irq_encoded; /* encoded IRQ */ 88 void *sc_ih; /* interrupt handle */ 89 }; 90 91 static void ix_reset __P((struct ie_softc *, int)); 92 static void ix_atten __P((struct ie_softc *, int)); 93 static int ix_intrhook __P((struct ie_softc *, int)); 94 95 static void ix_copyin __P((struct ie_softc *, void *, int, size_t)); 96 static void ix_copyout __P((struct ie_softc *, const void *, int, size_t)); 97 98 static void ix_bus_barrier __P((struct ie_softc *, int, int, int)); 99 100 static u_int16_t ix_read_16 __P((struct ie_softc *, int)); 101 static void ix_write_16 __P((struct ie_softc *, int, u_int16_t)); 102 static void ix_write_24 __P((struct ie_softc *, int, int)); 103 static void ix_zeromem __P((struct ie_softc *, int, int)); 104 105 static void ix_mediastatus __P((struct ie_softc *, struct ifmediareq *)); 106 107 static u_int16_t ix_read_eeprom __P((bus_space_tag_t, bus_space_handle_t, int)); 108 static void ix_eeprom_outbits __P((bus_space_tag_t, bus_space_handle_t, int, int)); 109 static int ix_eeprom_inbits __P((bus_space_tag_t, bus_space_handle_t)); 110 static void ix_eeprom_clock __P((bus_space_tag_t, bus_space_handle_t, int)); 111 112 int ix_match __P((struct device *, struct cfdata *, void *)); 113 void ix_attach __P((struct device *, struct device *, void *)); 114 115 /* 116 * EtherExpress/16 support routines 117 */ 118 static void 119 ix_reset(sc, why) 120 struct ie_softc *sc; 121 int why; 122 { 123 struct ix_softc* isc = (struct ix_softc *) sc; 124 125 switch (why) { 126 case CHIP_PROBE: 127 bus_space_write_1(isc->sc_regt, isc->sc_regh, IX_ECTRL, 128 IX_RESET_586); 129 delay(100); 130 bus_space_write_1(isc->sc_regt, isc->sc_regh, IX_ECTRL, 0); 131 delay(100); 132 break; 133 134 case CARD_RESET: 135 break; 136 } 137 } 138 139 static void 140 ix_atten(sc, why) 141 struct ie_softc *sc; 142 int why; 143 { 144 struct ix_softc* isc = (struct ix_softc *) sc; 145 bus_space_write_1(isc->sc_regt, isc->sc_regh, IX_ATTN, 0); 146 } 147 148 static u_int16_t 149 ix_read_eeprom(iot, ioh, location) 150 bus_space_tag_t iot; 151 bus_space_handle_t ioh; 152 int location; 153 { 154 int ectrl, edata; 155 156 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 157 ectrl &= IX_ECTRL_MASK; 158 ectrl |= IX_ECTRL_EECS; 159 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 160 161 ix_eeprom_outbits(iot, ioh, IX_EEPROM_READ, IX_EEPROM_OPSIZE1); 162 ix_eeprom_outbits(iot, ioh, location, IX_EEPROM_ADDR_SIZE); 163 edata = ix_eeprom_inbits(iot, ioh); 164 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 165 ectrl &= ~(IX_RESET_ASIC | IX_ECTRL_EEDI | IX_ECTRL_EECS); 166 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 167 ix_eeprom_clock(iot, ioh, 1); 168 ix_eeprom_clock(iot, ioh, 0); 169 return (edata); 170 } 171 172 static void 173 ix_eeprom_outbits(iot, ioh, edata, count) 174 bus_space_tag_t iot; 175 bus_space_handle_t ioh; 176 int edata, count; 177 { 178 int ectrl, i; 179 180 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 181 ectrl &= ~IX_RESET_ASIC; 182 for (i = count - 1; i >= 0; i--) { 183 ectrl &= ~IX_ECTRL_EEDI; 184 if (edata & (1 << i)) { 185 ectrl |= IX_ECTRL_EEDI; 186 } 187 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 188 delay(1); /* eeprom data must be setup for 0.4 uSec */ 189 ix_eeprom_clock(iot, ioh, 1); 190 ix_eeprom_clock(iot, ioh, 0); 191 } 192 ectrl &= ~IX_ECTRL_EEDI; 193 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 194 delay(1); /* eeprom data must be held for 0.4 uSec */ 195 } 196 197 static int 198 ix_eeprom_inbits(iot, ioh) 199 bus_space_tag_t iot; 200 bus_space_handle_t ioh; 201 { 202 int ectrl, edata, i; 203 204 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 205 ectrl &= ~IX_RESET_ASIC; 206 for (edata = 0, i = 0; i < 16; i++) { 207 edata = edata << 1; 208 ix_eeprom_clock(iot, ioh, 1); 209 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 210 if (ectrl & IX_ECTRL_EEDO) { 211 edata |= 1; 212 } 213 ix_eeprom_clock(iot, ioh, 0); 214 } 215 return (edata); 216 } 217 218 static void 219 ix_eeprom_clock(iot, ioh, state) 220 bus_space_tag_t iot; 221 bus_space_handle_t ioh; 222 int state; 223 { 224 int ectrl; 225 226 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 227 ectrl &= ~(IX_RESET_ASIC | IX_ECTRL_EESK); 228 if (state) { 229 ectrl |= IX_ECTRL_EESK; 230 } 231 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 232 delay(9); /* EESK must be stable for 8.38 uSec */ 233 } 234 235 static int 236 ix_intrhook(sc, where) 237 struct ie_softc *sc; 238 int where; 239 { 240 struct ix_softc* isc = (struct ix_softc *) sc; 241 242 switch (where) { 243 case INTR_ENTER: 244 /* entering ISR: disable card interrupts */ 245 bus_space_write_1(isc->sc_regt, isc->sc_regh, 246 IX_IRQ, isc->irq_encoded); 247 break; 248 249 case INTR_EXIT: 250 /* exiting ISR: re-enable card interrupts */ 251 bus_space_write_1(isc->sc_regt, isc->sc_regh, IX_IRQ, 252 isc->irq_encoded | IX_IRQ_ENABLE); 253 break; 254 } 255 256 return 1; 257 } 258 259 260 static void 261 ix_copyin (sc, dst, offset, size) 262 struct ie_softc *sc; 263 void *dst; 264 int offset; 265 size_t size; 266 { 267 int i, dribble; 268 u_int8_t* bptr = dst; 269 u_int16_t* wptr = dst; 270 struct ix_softc* isc = (struct ix_softc *) sc; 271 272 if (isc->use_pio) { 273 /* Reset read pointer to the specified offset */ 274 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 275 BUS_SPACE_BARRIER_READ); 276 bus_space_write_2(sc->bt, sc->bh, IX_READPTR, offset); 277 bus_space_barrier(sc->bt, sc->bh, IX_READPTR, 2, 278 BUS_SPACE_BARRIER_WRITE); 279 } else { 280 bus_space_barrier(sc->bt, sc->bh, offset, size, 281 BUS_SPACE_BARRIER_READ); 282 } 283 284 if (offset % 2) { 285 if (isc->use_pio) 286 *bptr = bus_space_read_1(sc->bt, sc->bh, IX_DATAPORT); 287 else 288 *bptr = bus_space_read_1(sc->bt, sc->bh, offset); 289 offset++; bptr++; size--; 290 } 291 292 dribble = size % 2; 293 wptr = (u_int16_t*) bptr; 294 295 if (isc->use_pio) { 296 for(i = 0; i < size / 2; i++) { 297 *wptr = bus_space_read_2(sc->bt, sc->bh, IX_DATAPORT); 298 wptr++; 299 } 300 } else { 301 bus_space_read_region_2(sc->bt, sc->bh, offset, 302 (u_int16_t *) bptr, size / 2); 303 } 304 305 if (dribble) { 306 bptr += size - 1; 307 offset += size - 1; 308 309 if (isc->use_pio) 310 *bptr = bus_space_read_1(sc->bt, sc->bh, IX_DATAPORT); 311 else 312 *bptr = bus_space_read_1(sc->bt, sc->bh, offset); 313 } 314 } 315 316 static void 317 ix_copyout (sc, src, offset, size) 318 struct ie_softc *sc; 319 const void *src; 320 int offset; 321 size_t size; 322 { 323 int i, dribble; 324 int osize = size; 325 int ooffset = offset; 326 const u_int8_t* bptr = src; 327 const u_int16_t* wptr = src; 328 struct ix_softc* isc = (struct ix_softc *) sc; 329 330 if (isc->use_pio) { 331 /* Reset write pointer to the specified offset */ 332 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); 333 bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, 334 BUS_SPACE_BARRIER_WRITE); 335 } 336 337 if (offset % 2) { 338 if (isc->use_pio) 339 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, *bptr); 340 else 341 bus_space_write_1(sc->bt, sc->bh, offset, *bptr); 342 offset++; bptr++; size--; 343 } 344 345 dribble = size % 2; 346 wptr = (u_int16_t*) bptr; 347 348 if (isc->use_pio) { 349 for(i = 0; i < size / 2; i++) { 350 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, *wptr); 351 wptr++; 352 } 353 } else { 354 bus_space_write_region_2(sc->bt, sc->bh, offset, 355 (u_int16_t *)bptr, size / 2); 356 } 357 358 if (dribble) { 359 bptr += size - 1; 360 offset += size - 1; 361 362 if (isc->use_pio) 363 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, *bptr); 364 else 365 bus_space_write_1(sc->bt, sc->bh, offset, *bptr); 366 } 367 368 if (isc->use_pio) 369 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 370 BUS_SPACE_BARRIER_WRITE); 371 else 372 bus_space_barrier(sc->bt, sc->bh, ooffset, osize, 373 BUS_SPACE_BARRIER_WRITE); 374 } 375 376 static void 377 ix_bus_barrier(sc, offset, length, flags) 378 struct ie_softc *sc; 379 int offset, length, flags; 380 { 381 struct ix_softc* isc = (struct ix_softc *) sc; 382 383 if (isc->use_pio) 384 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, flags); 385 else 386 bus_space_barrier(sc->bt, sc->bh, offset, length, flags); 387 } 388 389 static u_int16_t 390 ix_read_16 (sc, offset) 391 struct ie_softc *sc; 392 int offset; 393 { 394 struct ix_softc* isc = (struct ix_softc *) sc; 395 396 if (isc->use_pio) { 397 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 398 BUS_SPACE_BARRIER_READ); 399 400 /* Reset read pointer to the specified offset */ 401 bus_space_write_2(sc->bt, sc->bh, IX_READPTR, offset); 402 bus_space_barrier(sc->bt, sc->bh, IX_READPTR, 2, 403 BUS_SPACE_BARRIER_WRITE); 404 405 return bus_space_read_2(sc->bt, sc->bh, IX_DATAPORT); 406 } else { 407 bus_space_barrier(sc->bt, sc->bh, offset, 2, 408 BUS_SPACE_BARRIER_READ); 409 return bus_space_read_2(sc->bt, sc->bh, offset); 410 } 411 } 412 413 static void 414 ix_write_16 (sc, offset, value) 415 struct ie_softc *sc; 416 int offset; 417 u_int16_t value; 418 { 419 struct ix_softc* isc = (struct ix_softc *) sc; 420 421 if (isc->use_pio) { 422 /* Reset write pointer to the specified offset */ 423 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); 424 bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, 425 BUS_SPACE_BARRIER_WRITE); 426 427 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, value); 428 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 429 BUS_SPACE_BARRIER_WRITE); 430 } else { 431 bus_space_write_2(sc->bt, sc->bh, offset, value); 432 bus_space_barrier(sc->bt, sc->bh, offset, 2, 433 BUS_SPACE_BARRIER_WRITE); 434 } 435 } 436 437 static void 438 ix_write_24 (sc, offset, addr) 439 struct ie_softc *sc; 440 int offset, addr; 441 { 442 char* ptr; 443 struct ix_softc* isc = (struct ix_softc *) sc; 444 int val = addr + (u_long) sc->sc_maddr - (u_long) sc->sc_iobase; 445 446 if (isc->use_pio) { 447 /* Reset write pointer to the specified offset */ 448 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); 449 bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, 450 BUS_SPACE_BARRIER_WRITE); 451 452 ptr = (char*) &val; 453 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, 454 *((u_int16_t *)ptr)); 455 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, 456 *((u_int16_t *)(ptr + 2))); 457 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 458 BUS_SPACE_BARRIER_WRITE); 459 } else { 460 bus_space_write_4(sc->bt, sc->bh, offset, val); 461 bus_space_barrier(sc->bt, sc->bh, offset, 4, 462 BUS_SPACE_BARRIER_WRITE); 463 } 464 } 465 466 static void 467 ix_zeromem(sc, offset, count) 468 struct ie_softc *sc; 469 int offset, count; 470 { 471 int i; 472 int dribble; 473 struct ix_softc* isc = (struct ix_softc *) sc; 474 475 if (isc->use_pio) { 476 /* Reset write pointer to the specified offset */ 477 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); 478 bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, 479 BUS_SPACE_BARRIER_WRITE); 480 481 if (offset % 2) { 482 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, 0); 483 count--; 484 } 485 486 dribble = count % 2; 487 for(i = 0; i < count / 2; i++) 488 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, 0); 489 490 if (dribble) 491 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, 0); 492 493 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 494 BUS_SPACE_BARRIER_WRITE); 495 } else { 496 bus_space_set_region_1(sc->bt, sc->bh, offset, 0, count); 497 bus_space_barrier(sc->bt, sc->bh, offset, count, 498 BUS_SPACE_BARRIER_WRITE); 499 } 500 } 501 502 static void 503 ix_mediastatus(sc, ifmr) 504 struct ie_softc *sc; 505 struct ifmediareq *ifmr; 506 { 507 struct ifmedia *ifm = &sc->sc_media; 508 509 /* 510 * The currently selected media is always the active media. 511 */ 512 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 513 } 514 515 int 516 ix_match(parent, cf, aux) 517 struct device *parent; 518 struct cfdata *cf; 519 void *aux; 520 { 521 int i; 522 int rv = 0; 523 bus_addr_t maddr; 524 bus_size_t msize; 525 u_short checksum = 0; 526 bus_space_handle_t ioh; 527 bus_space_tag_t iot; 528 u_int8_t val, bart_config; 529 u_short pg, adjust, decode, edecode; 530 u_short board_id, id_var1, id_var2, irq, irq_encoded; 531 struct isa_attach_args * const ia = aux; 532 short irq_translate[] = {0, 0x09, 0x03, 0x04, 0x05, 0x0a, 0x0b, 0}; 533 534 if (ia->ia_nio < 1) 535 return (0); 536 if (ia->ia_niomem < 1) 537 return (0); 538 if (ia->ia_nirq < 1) 539 return (0); 540 541 if (ISA_DIRECT_CONFIG(ia)) 542 return (0); 543 544 iot = ia->ia_iot; 545 546 if (ia->ia_io[0].ir_addr == ISACF_PORT_DEFAULT) 547 return (0); 548 549 if (bus_space_map(iot, ia->ia_io[0].ir_addr, 550 IX_IOSIZE, 0, &ioh) != 0) { 551 DPRINTF(("Can't map io space at 0x%x\n", ia->ia_iobase)); 552 return (0); 553 } 554 555 /* XXX: reset any ee16 at the current iobase */ 556 bus_space_write_1(iot, ioh, IX_ECTRL, IX_RESET_ASIC); 557 bus_space_write_1(iot, ioh, IX_ECTRL, 0); 558 delay(240); 559 560 /* now look for ee16. */ 561 board_id = id_var1 = id_var2 = 0; 562 for (i = 0; i < 4 ; i++) { 563 id_var1 = bus_space_read_1(iot, ioh, IX_ID_PORT); 564 id_var2 = ((id_var1 & 0x03) << 2); 565 board_id |= (( id_var1 >> 4) << id_var2); 566 } 567 568 if (board_id != IX_ID) { 569 DPRINTF(("BART ID mismatch (got 0x%04x, expected 0x%04x)\n", 570 board_id, IX_ID)); 571 goto out; 572 } 573 574 /* 575 * The shared RAM size and location of the EE16 is encoded into 576 * EEPROM location 6. The location of the first set bit tells us 577 * the memory address (0xc0000 + (0x4000 * FSB)), where FSB is the 578 * number of the first set bit. The zeroes are then shifted out, 579 * and the results is the memory size (1 = 16k, 3 = 32k, 7 = 48k, 580 * 0x0f = 64k). 581 * 582 * Examples: 583 * 0x3c -> 64k@0xc8000, 0x70 -> 48k@0xd0000, 0xc0 -> 32k@0xd8000 584 * 0x80 -> 16k@0xdc000. 585 * 586 * Side note: this comes from reading the old driver rather than 587 * from a more definitive source, so it could be out-of-whack 588 * with what the card can do... 589 */ 590 591 val = ix_read_eeprom(iot, ioh, 6) & 0xff; 592 for(pg = 0; pg < 8; pg++) { 593 if (val & 1) 594 break; 595 val = val >> 1; 596 } 597 598 if (pg == 8) { 599 DPRINTF(("Invalid or unsupported memory config\n")); 600 goto out; 601 } 602 603 maddr = 0xc0000 + (pg * 0x4000); 604 605 switch (val) { 606 case 0x00: 607 msize = 0; 608 break; 609 610 case 0x01: 611 msize = 16 * 1024; 612 break; 613 614 case 0x03: 615 msize = 32 * 1024; 616 break; 617 618 case 0x07: 619 msize = 48 * 1024; 620 break; 621 622 case 0x0f: 623 msize = 64 * 1024; 624 break; 625 626 default: 627 DPRINTF(("invalid memory size %02x\n", val)); 628 goto out; 629 } 630 631 if (ia->ia_iomem[0].ir_addr != ISACF_IOMEM_DEFAULT && 632 ia->ia_iomem[0].ir_addr != maddr) { 633 DPRINTF(( 634 "ix_match: memaddr of board @ 0x%x doesn't match config\n", 635 ia->ia_iobase)); 636 goto out; 637 } 638 639 if (ia->ia_iomem[0].ir_size != ISACF_IOSIZ_DEFAULT && 640 ia->ia_iomem[0].ir_size != msize) { 641 DPRINTF(( 642 "ix_match: memsize of board @ 0x%x doesn't match config\n", 643 ia->ia_iobase)); 644 goto out; 645 } 646 647 /* need to put the 586 in RESET, and leave it */ 648 bus_space_write_1(iot, ioh, IX_ECTRL, IX_RESET_586); 649 650 /* read the eeprom and checksum it, should == IX_ID */ 651 for(i = 0; i < 0x40; i++) 652 checksum += ix_read_eeprom(iot, ioh, i); 653 654 if (checksum != IX_ID) { 655 DPRINTF(("checksum mismatch (got 0x%04x, expected 0x%04x\n", 656 checksum, IX_ID)); 657 goto out; 658 } 659 660 /* 661 * Only do the following bit if using memory-mapped access. For 662 * boards with no mapped memory, we use PIO. We also use PIO for 663 * boards with 16K of mapped memory, as those setups don't seem 664 * to work otherwise. 665 */ 666 if (msize != 0 && msize != 16384) { 667 /* Set board up with memory-mapping info */ 668 adjust = IX_MCTRL_FMCS16 | (pg & 0x3) << 2; 669 decode = ((1 << (ia->ia_iomem[0].ir_size / 16384)) - 1) << pg; 670 edecode = ((~decode >> 4) & 0xF0) | (decode >> 8); 671 672 bus_space_write_1(iot, ioh, IX_MEMDEC, decode & 0xFF); 673 bus_space_write_1(iot, ioh, IX_MCTRL, adjust); 674 bus_space_write_1(iot, ioh, IX_MPCTRL, (~decode & 0xFF)); 675 676 /* XXX disable Exxx */ 677 bus_space_write_1(iot, ioh, IX_MECTRL, edecode); 678 } 679 680 /* 681 * Get the encoded interrupt number from the EEPROM, check it 682 * against the passed in IRQ. Issue a warning if they do not 683 * match, and fail the probe. If irq is 'ISACF_IRQ_DEFAULT' then we 684 * use the EEPROM irq, and continue. 685 */ 686 irq_encoded = ix_read_eeprom(iot, ioh, IX_EEPROM_CONFIG1); 687 irq_encoded = (irq_encoded & IX_EEPROM_IRQ) >> IX_EEPROM_IRQ_SHIFT; 688 irq = irq_translate[irq_encoded]; 689 if (ia->ia_irq[0].ir_irq != ISACF_IRQ_DEFAULT && 690 irq != ia->ia_irq[0].ir_irq) { 691 DPRINTF(("board IRQ %d does not match config\n", irq)); 692 goto out; 693 } 694 695 /* disable the board interrupts */ 696 bus_space_write_1(iot, ioh, IX_IRQ, irq_encoded); 697 698 bart_config = bus_space_read_1(iot, ioh, IX_CONFIG); 699 bart_config |= IX_BART_LOOPBACK; 700 bart_config |= IX_BART_MCS16_TEST; /* inb doesn't get bit! */ 701 bus_space_write_1(iot, ioh, IX_CONFIG, bart_config); 702 bart_config = bus_space_read_1(iot, ioh, IX_CONFIG); 703 704 bus_space_write_1(iot, ioh, IX_ECTRL, 0); 705 delay(100); 706 707 rv = 1; 708 709 ia->ia_nio = 1; 710 ia->ia_io[0].ir_size = IX_IOSIZE; 711 712 ia->ia_niomem = 1; 713 ia->ia_iomem[0].ir_addr = maddr; 714 ia->ia_iomem[0].ir_size = msize; 715 716 ia->ia_nirq = 1; 717 ia->ia_irq[0].ir_irq = irq; 718 719 DPRINTF(("ix_match: found board @ 0x%x\n", ia->ia_iobase)); 720 721 out: 722 bus_space_unmap(iot, ioh, IX_IOSIZE); 723 return (rv); 724 } 725 726 void 727 ix_attach(parent, self, aux) 728 struct device *parent; 729 struct device *self; 730 void *aux; 731 { 732 struct ix_softc *isc = (void *)self; 733 struct ie_softc *sc = &isc->sc_ie; 734 struct isa_attach_args *ia = aux; 735 736 int media; 737 int i, memsize; 738 u_int8_t bart_config; 739 bus_space_tag_t iot; 740 u_int8_t bpat, bval; 741 u_int16_t wpat, wval; 742 bus_space_handle_t ioh, memh; 743 u_short irq_encoded; 744 u_int8_t ethaddr[ETHER_ADDR_LEN]; 745 746 iot = ia->ia_iot; 747 748 /* 749 * Shared memory access seems to fail on 16K mapped boards, so 750 * disable shared memory access if the board is in 16K mode. If 751 * no memory is mapped, we have no choice but to use PIO 752 */ 753 isc->use_pio = (ia->ia_iomem[0].ir_size <= (16 * 1024)); 754 755 if (bus_space_map(iot, ia->ia_io[0].ir_addr, 756 ia->ia_io[0].ir_size, 0, &ioh) != 0) { 757 758 DPRINTF(("\n%s: can't map i/o space 0x%x-0x%x\n", 759 sc->sc_dev.dv_xname, ia->ia_[0].ir_addr, 760 ia->ia_io[0].ir_addr + ia->ia_io[0].ir_size - 1)); 761 return; 762 } 763 764 /* We map memory even if using PIO so something else doesn't grab it */ 765 if (ia->ia_iomem[0].ir_size) { 766 if (bus_space_map(ia->ia_memt, ia->ia_iomem[0].ir_addr, 767 ia->ia_iomem[0].ir_size, 0, &memh) != 0) { 768 DPRINTF(("\n%s: can't map iomem space 0x%x-0x%x\n", 769 sc->sc_dev.dv_xname, ia->ia_iomem[0].ir_addr, 770 ia->ia_iomem[0].ir_addr + ia->ia_iomem[0].ir_size - 1)); 771 bus_space_unmap(iot, ioh, ia->ia_io[0].ir_size); 772 return; 773 } 774 } 775 776 isc->sc_regt = iot; 777 isc->sc_regh = ioh; 778 779 /* 780 * Get the hardware ethernet address from the EEPROM and 781 * save it in the softc for use by the 586 setup code. 782 */ 783 wval = ix_read_eeprom(iot, ioh, IX_EEPROM_ENET_HIGH); 784 ethaddr[1] = wval & 0xFF; 785 ethaddr[0] = wval >> 8; 786 wval = ix_read_eeprom(iot, ioh, IX_EEPROM_ENET_MID); 787 ethaddr[3] = wval & 0xFF; 788 ethaddr[2] = wval >> 8; 789 wval = ix_read_eeprom(iot, ioh, IX_EEPROM_ENET_LOW); 790 ethaddr[5] = wval & 0xFF; 791 ethaddr[4] = wval >> 8; 792 793 sc->hwinit = NULL; 794 sc->hwreset = ix_reset; 795 sc->chan_attn = ix_atten; 796 sc->intrhook = ix_intrhook; 797 798 sc->memcopyin = ix_copyin; 799 sc->memcopyout = ix_copyout; 800 801 /* If using PIO, make sure to setup single-byte read/write functions */ 802 if (isc->use_pio) { 803 sc->ie_bus_barrier = ix_bus_barrier; 804 } else { 805 sc->ie_bus_barrier = NULL; 806 } 807 808 sc->ie_bus_read16 = ix_read_16; 809 sc->ie_bus_write16 = ix_write_16; 810 sc->ie_bus_write24 = ix_write_24; 811 812 sc->do_xmitnopchain = 0; 813 814 sc->sc_mediachange = NULL; 815 sc->sc_mediastatus = ix_mediastatus; 816 817 if (isc->use_pio) { 818 sc->bt = iot; 819 sc->bh = ioh; 820 821 /* 822 * If using PIO, the memory size is bounded by on-card memory, 823 * not by how much is mapped into the memory-mapped region, so 824 * determine how much total memory we have to play with here. 825 */ 826 for(memsize = 64 * 1024; memsize; memsize -= 16 * 1024) { 827 /* warm up shared memory, the zero it all out */ 828 ix_zeromem(sc, 0, 32); 829 ix_zeromem(sc, 0, memsize); 830 831 /* Reset write pointer to the start of RAM */ 832 bus_space_write_2(iot, ioh, IX_WRITEPTR, 0); 833 bus_space_barrier(iot, ioh, IX_WRITEPTR, 2, 834 BUS_SPACE_BARRIER_WRITE); 835 836 /* write test pattern */ 837 for(i = 0, wpat = 1; i < memsize; i += 2) { 838 bus_space_write_2(iot, ioh, IX_DATAPORT, wpat); 839 wpat += 3; 840 } 841 842 /* Flush all reads & writes to data port */ 843 bus_space_barrier(iot, ioh, IX_DATAPORT, 2, 844 BUS_SPACE_BARRIER_READ | 845 BUS_SPACE_BARRIER_WRITE); 846 847 /* Reset read pointer to beginning of card RAM */ 848 bus_space_write_2(iot, ioh, IX_READPTR, 0); 849 bus_space_barrier(iot, ioh, IX_READPTR, 2, 850 BUS_SPACE_BARRIER_WRITE); 851 852 /* read and verify test pattern */ 853 for(i = 0, wpat = 1; i < memsize; i += 2) { 854 wval = bus_space_read_2(iot, ioh, IX_DATAPORT); 855 856 if (wval != wpat) 857 break; 858 859 wpat += 3; 860 } 861 862 /* If we failed, try next size down */ 863 if (i != memsize) 864 continue; 865 866 /* Now try it all with byte reads/writes */ 867 ix_zeromem(sc, 0, 32); 868 ix_zeromem(sc, 0, memsize); 869 870 /* Reset write pointer to start of card RAM */ 871 bus_space_write_2(iot, ioh, IX_WRITEPTR, 0); 872 bus_space_barrier(iot, ioh, IX_WRITEPTR, 2, 873 BUS_SPACE_BARRIER_WRITE); 874 875 /* write out test pattern */ 876 for(i = 0, bpat = 1; i < memsize; i++) { 877 bus_space_write_1(iot, ioh, IX_DATAPORT, bpat); 878 bpat += 3; 879 } 880 881 /* Flush all reads & writes to data port */ 882 bus_space_barrier(iot, ioh, IX_DATAPORT, 2, 883 BUS_SPACE_BARRIER_READ | 884 BUS_SPACE_BARRIER_WRITE); 885 886 /* Reset read pointer to beginning of card RAM */ 887 bus_space_write_2(iot, ioh, IX_READPTR, 0); 888 bus_space_barrier(iot, ioh, IX_READPTR, 2, 889 BUS_SPACE_BARRIER_WRITE); 890 891 /* read and verify test pattern */ 892 for(i = 0, bpat = 1; i < memsize; i++) { 893 bval = bus_space_read_1(iot, ioh, IX_DATAPORT); 894 895 if (bval != bpat) 896 bpat += 3; 897 } 898 899 /* If we got through all of memory, we're done! */ 900 if (i == memsize) 901 break; 902 } 903 904 /* Memory tests failed, punt... */ 905 if (memsize == 0) { 906 DPRINTF(("\n%s: can't determine size of on-card RAM\n", 907 sc->sc_dev.dv_xname)); 908 bus_space_unmap(iot, ioh, ia->ia_io[0].ir_size); 909 return; 910 } 911 912 sc->bt = iot; 913 sc->bh = ioh; 914 915 sc->sc_msize = memsize; 916 sc->sc_maddr = (void*) 0; 917 } else { 918 sc->bt = ia->ia_memt; 919 sc->bh = memh; 920 921 sc->sc_msize = ia->ia_iomem[0].ir_size; 922 sc->sc_maddr = (void *)memh; 923 } 924 925 /* Map i/o space. */ 926 sc->sc_iobase = (char *)sc->sc_maddr + sc->sc_msize - (1 << 24); 927 928 /* set up pointers to important on-card control structures */ 929 sc->iscp = 0; 930 sc->scb = IE_ISCP_SZ; 931 sc->scp = sc->sc_msize + IE_SCP_ADDR - (1 << 24); 932 933 sc->buf_area = sc->scb + IE_SCB_SZ; 934 sc->buf_area_sz = sc->sc_msize - IE_ISCP_SZ - IE_SCB_SZ - IE_SCP_SZ; 935 936 /* zero card memory */ 937 ix_zeromem(sc, 0, 32); 938 ix_zeromem(sc, 0, sc->sc_msize); 939 940 /* set card to 16-bit bus mode */ 941 if (isc->use_pio) { 942 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, 943 IE_SCP_BUS_USE((u_long)sc->scp)); 944 bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, 945 BUS_SPACE_BARRIER_WRITE); 946 947 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, 948 IE_SYSBUS_16BIT); 949 } else { 950 bus_space_write_1(sc->bt, sc->bh, 951 IE_SCP_BUS_USE((u_long)sc->scp), 952 IE_SYSBUS_16BIT); 953 } 954 955 /* set up pointers to key structures */ 956 ix_write_24(sc, IE_SCP_ISCP((u_long)sc->scp), (u_long) sc->iscp); 957 ix_write_16(sc, IE_ISCP_SCB((u_long)sc->iscp), (u_long) sc->scb); 958 ix_write_24(sc, IE_ISCP_BASE((u_long)sc->iscp), (u_long) sc->iscp); 959 960 /* flush setup of pointers, check if chip answers */ 961 if (isc->use_pio) { 962 bus_space_barrier(sc->bt, sc->bh, 0, IX_IOSIZE, 963 BUS_SPACE_BARRIER_WRITE); 964 } else { 965 bus_space_barrier(sc->bt, sc->bh, 0, sc->sc_msize, 966 BUS_SPACE_BARRIER_WRITE); 967 } 968 969 if (!i82586_proberam(sc)) { 970 DPRINTF(("\n%s: Can't talk to i82586!\n", 971 sc->sc_dev.dv_xname)); 972 bus_space_unmap(iot, ioh, ia->ia_io[0].ir_size); 973 974 if (ia->ia_iomem[0].ir_size) 975 bus_space_unmap(ia->ia_memt, memh, ia->ia_iomem[0].ir_size); 976 return; 977 } 978 979 /* Figure out which media is being used... */ 980 if (ix_read_eeprom(iot, ioh, IX_EEPROM_CONFIG1) & 981 IX_EEPROM_MEDIA_EXT) { 982 if (ix_read_eeprom(iot, ioh, IX_EEPROM_MEDIA) & 983 IX_EEPROM_MEDIA_TP) 984 media = IFM_ETHER | IFM_10_T; 985 else 986 media = IFM_ETHER | IFM_10_2; 987 } else 988 media = IFM_ETHER | IFM_10_5; 989 990 /* Take the card out of lookback */ 991 bart_config = bus_space_read_1(iot, ioh, IX_CONFIG); 992 bart_config &= ~IX_BART_LOOPBACK; 993 bart_config |= IX_BART_MCS16_TEST; /* inb doesn't get bit! */ 994 bus_space_write_1(iot, ioh, IX_CONFIG, bart_config); 995 bart_config = bus_space_read_1(iot, ioh, IX_CONFIG); 996 997 irq_encoded = ix_read_eeprom(iot, ioh, 998 IX_EEPROM_CONFIG1); 999 irq_encoded = (irq_encoded & IX_EEPROM_IRQ) >> IX_EEPROM_IRQ_SHIFT; 1000 1001 /* Enable interrupts */ 1002 bus_space_write_1(iot, ioh, IX_IRQ, 1003 irq_encoded | IX_IRQ_ENABLE); 1004 1005 /* Flush all writes to registers */ 1006 bus_space_barrier(iot, ioh, 0, ia->ia_io[0].ir_size, 1007 BUS_SPACE_BARRIER_WRITE); 1008 1009 isc->irq_encoded = irq_encoded; 1010 1011 i82586_attach(sc, "EtherExpress/16", ethaddr, 1012 ix_media, NIX_MEDIA, media); 1013 1014 if (isc->use_pio) 1015 printf("%s: unsupported memory config, using PIO to access %d bytes of memory\n", sc->sc_dev.dv_xname, sc->sc_msize); 1016 1017 isc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq[0].ir_irq, 1018 IST_EDGE, IPL_NET, i82586_intr, sc); 1019 if (isc->sc_ih == NULL) 1020 DPRINTF(("\n%s: can't establish interrupt\n", 1021 sc->sc_dev.dv_xname)); 1022 } 1023 1024 struct cfattach ix_ca = { 1025 sizeof(struct ix_softc), ix_match, ix_attach 1026 }; 1027