1 /* $NetBSD: if_mvgbe.c,v 1.36 2014/02/03 05:56:23 msaitoh Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008, 2013 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_mvgbe.c,v 1.36 2014/02/03 05:56:23 msaitoh Exp $"); 29 30 #include "opt_multiprocessor.h" 31 32 #if defined MULTIPROCESSOR 33 #warning Queue Management Method 'Counters' not support yet 34 #endif 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/callout.h> 39 #include <sys/device.h> 40 #include <sys/endian.h> 41 #include <sys/errno.h> 42 #include <sys/evcnt.h> 43 #include <sys/kernel.h> 44 #include <sys/kmem.h> 45 #include <sys/mutex.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 49 #include <dev/marvell/marvellreg.h> 50 #include <dev/marvell/marvellvar.h> 51 #include <dev/marvell/mvgbereg.h> 52 53 #include <net/if.h> 54 #include <net/if_ether.h> 55 #include <net/if_media.h> 56 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/ip.h> 60 61 #include <net/bpf.h> 62 #include <sys/rnd.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #include "locators.h" 68 69 /* #define MVGBE_DEBUG 3 */ 70 #ifdef MVGBE_DEBUG 71 #define DPRINTF(x) if (mvgbe_debug) printf x 72 #define DPRINTFN(n,x) if (mvgbe_debug >= (n)) printf x 73 int mvgbe_debug = MVGBE_DEBUG; 74 #else 75 #define DPRINTF(x) 76 #define DPRINTFN(n,x) 77 #endif 78 79 80 #define MVGBE_READ(sc, reg) \ 81 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 82 #define MVGBE_WRITE(sc, reg, val) \ 83 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 84 #define MVGBE_READ_FILTER(sc, reg, val, c) \ 85 bus_space_read_region_4((sc)->sc_iot, (sc)->sc_dafh, (reg), (val), (c)) 86 #define MVGBE_WRITE_FILTER(sc, reg, val, c) \ 87 bus_space_write_region_4((sc)->sc_iot, (sc)->sc_dafh, (reg), (val), (c)) 88 89 #define MVGBE_LINKUP_READ(sc) \ 90 bus_space_read_4((sc)->sc_iot, (sc)->sc_linkup.ioh, 0) 91 #define MVGBE_IS_LINKUP(sc) (MVGBE_LINKUP_READ(sc) & (sc)->sc_linkup.bit) 92 93 #define MVGBE_TX_RING_CNT 256 94 #define MVGBE_TX_RING_MSK (MVGBE_TX_RING_CNT - 1) 95 #define MVGBE_TX_RING_NEXT(x) (((x) + 1) & MVGBE_TX_RING_MSK) 96 #define MVGBE_RX_RING_CNT 256 97 #define MVGBE_RX_RING_MSK (MVGBE_RX_RING_CNT - 1) 98 #define MVGBE_RX_RING_NEXT(x) (((x) + 1) & MVGBE_RX_RING_MSK) 99 100 CTASSERT(MVGBE_TX_RING_CNT > 1 && MVGBE_TX_RING_NEXT(MVGBE_TX_RING_CNT) == 101 (MVGBE_TX_RING_CNT + 1) % MVGBE_TX_RING_CNT); 102 CTASSERT(MVGBE_RX_RING_CNT > 1 && MVGBE_RX_RING_NEXT(MVGBE_RX_RING_CNT) == 103 (MVGBE_RX_RING_CNT + 1) % MVGBE_RX_RING_CNT); 104 105 #define MVGBE_JSLOTS 384 /* XXXX */ 106 #define MVGBE_JLEN \ 107 ((MVGBE_MRU + MVGBE_HWHEADER_SIZE + MVGBE_RXBUF_ALIGN - 1) & \ 108 ~MVGBE_RXBUF_MASK) 109 #define MVGBE_NTXSEG 30 110 #define MVGBE_JPAGESZ PAGE_SIZE 111 #define MVGBE_RESID \ 112 (MVGBE_JPAGESZ - (MVGBE_JLEN * MVGBE_JSLOTS) % MVGBE_JPAGESZ) 113 #define MVGBE_JMEM \ 114 ((MVGBE_JLEN * MVGBE_JSLOTS) + MVGBE_RESID) 115 116 #define MVGBE_TX_RING_ADDR(sc, i) \ 117 ((sc)->sc_ring_map->dm_segs[0].ds_addr + \ 118 offsetof(struct mvgbe_ring_data, mvgbe_tx_ring[(i)])) 119 120 #define MVGBE_RX_RING_ADDR(sc, i) \ 121 ((sc)->sc_ring_map->dm_segs[0].ds_addr + \ 122 offsetof(struct mvgbe_ring_data, mvgbe_rx_ring[(i)])) 123 124 #define MVGBE_CDOFF(x) offsetof(struct mvgbe_ring_data, x) 125 #define MVGBE_CDTXOFF(x) MVGBE_CDOFF(mvgbe_tx_ring[(x)]) 126 #define MVGBE_CDRXOFF(x) MVGBE_CDOFF(mvgbe_rx_ring[(x)]) 127 128 #define MVGBE_CDTXSYNC(sc, x, n, ops) \ 129 do { \ 130 int __x, __n; \ 131 const int __descsize = sizeof(struct mvgbe_tx_desc); \ 132 \ 133 __x = (x); \ 134 __n = (n); \ 135 \ 136 /* If it will wrap around, sync to the end of the ring. */ \ 137 if ((__x + __n) > MVGBE_TX_RING_CNT) { \ 138 bus_dmamap_sync((sc)->sc_dmat, \ 139 (sc)->sc_ring_map, MVGBE_CDTXOFF(__x), \ 140 __descsize * (MVGBE_TX_RING_CNT - __x), (ops)); \ 141 __n -= (MVGBE_TX_RING_CNT - __x); \ 142 __x = 0; \ 143 } \ 144 \ 145 /* Now sync whatever is left. */ \ 146 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_ring_map, \ 147 MVGBE_CDTXOFF((__x)), __descsize * __n, (ops)); \ 148 } while (0 /*CONSTCOND*/) 149 150 #define MVGBE_CDRXSYNC(sc, x, ops) \ 151 do { \ 152 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_ring_map, \ 153 MVGBE_CDRXOFF((x)), sizeof(struct mvgbe_rx_desc), (ops)); \ 154 } while (/*CONSTCOND*/0) 155 156 #define MVGBE_IPGINTTX_DEFAULT 768 157 #define MVGBE_IPGINTRX_DEFAULT 768 158 159 #ifdef MVGBE_EVENT_COUNTERS 160 #define MVGBE_EVCNT_INCR(ev) (ev)->ev_count++ 161 #define MVGBE_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 162 #else 163 #define MVGBE_EVCNT_INCR(ev) /* nothing */ 164 #define MVGBE_EVCNT_ADD(ev, val) /* nothing */ 165 #endif 166 167 struct mvgbe_jpool_entry { 168 int slot; 169 LIST_ENTRY(mvgbe_jpool_entry) jpool_entries; 170 }; 171 172 struct mvgbe_chain { 173 void *mvgbe_desc; 174 struct mbuf *mvgbe_mbuf; 175 struct mvgbe_chain *mvgbe_next; 176 }; 177 178 struct mvgbe_txmap_entry { 179 bus_dmamap_t dmamap; 180 SIMPLEQ_ENTRY(mvgbe_txmap_entry) link; 181 }; 182 183 struct mvgbe_chain_data { 184 struct mvgbe_chain mvgbe_tx_chain[MVGBE_TX_RING_CNT]; 185 struct mvgbe_txmap_entry *mvgbe_tx_map[MVGBE_TX_RING_CNT]; 186 int mvgbe_tx_prod; 187 int mvgbe_tx_cons; 188 int mvgbe_tx_cnt; 189 190 struct mvgbe_chain mvgbe_rx_chain[MVGBE_RX_RING_CNT]; 191 bus_dmamap_t mvgbe_rx_map[MVGBE_RX_RING_CNT]; 192 bus_dmamap_t mvgbe_rx_jumbo_map; 193 int mvgbe_rx_prod; 194 int mvgbe_rx_cons; 195 int mvgbe_rx_cnt; 196 197 /* Stick the jumbo mem management stuff here too. */ 198 void *mvgbe_jslots[MVGBE_JSLOTS]; 199 void *mvgbe_jumbo_buf; 200 }; 201 202 struct mvgbe_ring_data { 203 struct mvgbe_tx_desc mvgbe_tx_ring[MVGBE_TX_RING_CNT]; 204 struct mvgbe_rx_desc mvgbe_rx_ring[MVGBE_RX_RING_CNT]; 205 }; 206 207 struct mvgbec_softc { 208 device_t sc_dev; 209 210 bus_space_tag_t sc_iot; 211 bus_space_handle_t sc_ioh; 212 213 kmutex_t sc_mtx; 214 215 int sc_flags; 216 }; 217 218 struct mvgbe_softc { 219 device_t sc_dev; 220 int sc_port; 221 uint32_t sc_version; 222 223 bus_space_tag_t sc_iot; 224 bus_space_handle_t sc_ioh; 225 bus_space_handle_t sc_dafh; /* dest address filter handle */ 226 bus_dma_tag_t sc_dmat; 227 228 struct ethercom sc_ethercom; 229 struct mii_data sc_mii; 230 u_int8_t sc_enaddr[ETHER_ADDR_LEN]; /* station addr */ 231 232 callout_t sc_tick_ch; /* tick callout */ 233 234 struct mvgbe_chain_data sc_cdata; 235 struct mvgbe_ring_data *sc_rdata; 236 bus_dmamap_t sc_ring_map; 237 int sc_if_flags; 238 unsigned int sc_ipginttx; 239 unsigned int sc_ipgintrx; 240 int sc_wdogsoft; 241 242 LIST_HEAD(__mvgbe_jfreehead, mvgbe_jpool_entry) sc_jfree_listhead; 243 LIST_HEAD(__mvgbe_jinusehead, mvgbe_jpool_entry) sc_jinuse_listhead; 244 SIMPLEQ_HEAD(__mvgbe_txmaphead, mvgbe_txmap_entry) sc_txmap_head; 245 246 struct { 247 bus_space_handle_t ioh; 248 uint32_t bit; 249 } sc_linkup; 250 uint32_t sc_cmdsts_opts; 251 252 krndsource_t sc_rnd_source; 253 struct sysctllog *mvgbe_clog; 254 #ifdef MVGBE_EVENT_COUNTERS 255 struct evcnt sc_ev_rxoverrun; 256 struct evcnt sc_ev_wdogsoft; 257 #endif 258 }; 259 260 261 /* Gigabit Ethernet Unit Global part functions */ 262 263 static int mvgbec_match(device_t, struct cfdata *, void *); 264 static void mvgbec_attach(device_t, device_t, void *); 265 266 static int mvgbec_print(void *, const char *); 267 static int mvgbec_search(device_t, cfdata_t, const int *, void *); 268 269 /* MII funcstions */ 270 static int mvgbec_miibus_readreg(device_t, int, int); 271 static void mvgbec_miibus_writereg(device_t, int, int, int); 272 static void mvgbec_miibus_statchg(struct ifnet *); 273 274 static void mvgbec_wininit(struct mvgbec_softc *); 275 276 /* Gigabit Ethernet Port part functions */ 277 278 static int mvgbe_match(device_t, struct cfdata *, void *); 279 static void mvgbe_attach(device_t, device_t, void *); 280 281 static void mvgbe_tick(void *); 282 static int mvgbe_intr(void *); 283 284 static void mvgbe_start(struct ifnet *); 285 static int mvgbe_ioctl(struct ifnet *, u_long, void *); 286 static int mvgbe_init(struct ifnet *); 287 static void mvgbe_stop(struct ifnet *, int); 288 static void mvgbe_watchdog(struct ifnet *); 289 290 static int mvgbe_ifflags_cb(struct ethercom *); 291 292 static int mvgbe_mediachange(struct ifnet *); 293 static void mvgbe_mediastatus(struct ifnet *, struct ifmediareq *); 294 295 static int mvgbe_init_rx_ring(struct mvgbe_softc *); 296 static int mvgbe_init_tx_ring(struct mvgbe_softc *); 297 static int mvgbe_newbuf(struct mvgbe_softc *, int, struct mbuf *, bus_dmamap_t); 298 static int mvgbe_alloc_jumbo_mem(struct mvgbe_softc *); 299 static void *mvgbe_jalloc(struct mvgbe_softc *); 300 static void mvgbe_jfree(struct mbuf *, void *, size_t, void *); 301 static int mvgbe_encap(struct mvgbe_softc *, struct mbuf *, uint32_t *); 302 static void mvgbe_rxeof(struct mvgbe_softc *); 303 static void mvgbe_txeof(struct mvgbe_softc *); 304 static uint8_t mvgbe_crc8(const uint8_t *, size_t); 305 static void mvgbe_filter_setup(struct mvgbe_softc *); 306 #ifdef MVGBE_DEBUG 307 static void mvgbe_dump_txdesc(struct mvgbe_tx_desc *, int); 308 #endif 309 static int mvgbe_ipginttx(struct mvgbec_softc *, struct mvgbe_softc *, 310 unsigned int); 311 static int mvgbe_ipgintrx(struct mvgbec_softc *, struct mvgbe_softc *, 312 unsigned int); 313 static void sysctl_mvgbe_init(struct mvgbe_softc *); 314 static int mvgbe_sysctl_ipginttx(SYSCTLFN_PROTO); 315 static int mvgbe_sysctl_ipgintrx(SYSCTLFN_PROTO); 316 317 CFATTACH_DECL_NEW(mvgbec_gt, sizeof(struct mvgbec_softc), 318 mvgbec_match, mvgbec_attach, NULL, NULL); 319 CFATTACH_DECL_NEW(mvgbec_mbus, sizeof(struct mvgbec_softc), 320 mvgbec_match, mvgbec_attach, NULL, NULL); 321 322 CFATTACH_DECL_NEW(mvgbe, sizeof(struct mvgbe_softc), 323 mvgbe_match, mvgbe_attach, NULL, NULL); 324 325 device_t mvgbec0 = NULL; 326 static int mvgbe_root_num; 327 328 struct mvgbe_port { 329 int model; 330 int unit; 331 int ports; 332 int irqs[3]; 333 int flags; 334 #define FLAGS_FIX_TQTB (1 << 0) 335 #define FLAGS_FIX_MTU (1 << 1) 336 #define FLAGS_IPG1 (1 << 2) 337 #define FLAGS_IPG2 (1 << 3) 338 #define FLAGS_HAS_PV (1 << 4) /* Has Port Version Register */ 339 } mvgbe_ports[] = { 340 { MARVELL_DISCOVERY_II, 0, 3, { 32, 33, 34 }, 0 }, 341 { MARVELL_DISCOVERY_III, 0, 3, { 32, 33, 34 }, 0 }, 342 #if 0 343 { MARVELL_DISCOVERY_LT, 0, ?, { }, 0 }, 344 { MARVELL_DISCOVERY_V, 0, ?, { }, 0 }, 345 { MARVELL_DISCOVERY_VI, 0, ?, { }, 0 }, 346 #endif 347 { MARVELL_ORION_1_88F5082, 0, 1, { 21 }, FLAGS_FIX_MTU }, 348 { MARVELL_ORION_1_88F5180N, 0, 1, { 21 }, FLAGS_FIX_MTU }, 349 { MARVELL_ORION_1_88F5181, 0, 1, { 21 }, FLAGS_FIX_MTU | FLAGS_IPG1 }, 350 { MARVELL_ORION_1_88F5182, 0, 1, { 21 }, FLAGS_FIX_MTU | FLAGS_IPG1 }, 351 { MARVELL_ORION_2_88F5281, 0, 1, { 21 }, FLAGS_FIX_MTU | FLAGS_IPG1 }, 352 { MARVELL_ORION_1_88F6082, 0, 1, { 21 }, FLAGS_FIX_MTU }, 353 { MARVELL_ORION_1_88W8660, 0, 1, { 21 }, FLAGS_FIX_MTU }, 354 355 { MARVELL_KIRKWOOD_88F6180, 0, 1, { 11 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 356 { MARVELL_KIRKWOOD_88F6192, 0, 1, { 11 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 357 { MARVELL_KIRKWOOD_88F6192, 1, 1, { 15 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 358 { MARVELL_KIRKWOOD_88F6281, 0, 1, { 11 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 359 { MARVELL_KIRKWOOD_88F6281, 1, 1, { 15 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 360 { MARVELL_KIRKWOOD_88F6282, 0, 1, { 11 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 361 { MARVELL_KIRKWOOD_88F6282, 1, 1, { 15 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 362 363 { MARVELL_MV78XX0_MV78100, 0, 1, { 40 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 364 { MARVELL_MV78XX0_MV78100, 1, 1, { 44 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 365 { MARVELL_MV78XX0_MV78200, 0, 1, { 40 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 366 { MARVELL_MV78XX0_MV78200, 1, 1, { 44 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 367 { MARVELL_MV78XX0_MV78200, 2, 1, { 48 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 368 { MARVELL_MV78XX0_MV78200, 3, 1, { 52 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 369 370 { MARVELL_ARMADAXP_MV78130, 0, 1, { 66 }, FLAGS_HAS_PV }, 371 { MARVELL_ARMADAXP_MV78130, 1, 1, { 70 }, FLAGS_HAS_PV }, 372 { MARVELL_ARMADAXP_MV78130, 2, 1, { 74 }, FLAGS_HAS_PV }, 373 { MARVELL_ARMADAXP_MV78160, 0, 1, { 66 }, FLAGS_HAS_PV }, 374 { MARVELL_ARMADAXP_MV78160, 1, 1, { 70 }, FLAGS_HAS_PV }, 375 { MARVELL_ARMADAXP_MV78160, 2, 1, { 74 }, FLAGS_HAS_PV }, 376 { MARVELL_ARMADAXP_MV78160, 3, 1, { 78 }, FLAGS_HAS_PV }, 377 { MARVELL_ARMADAXP_MV78230, 0, 1, { 66 }, FLAGS_HAS_PV }, 378 { MARVELL_ARMADAXP_MV78230, 1, 1, { 70 }, FLAGS_HAS_PV }, 379 { MARVELL_ARMADAXP_MV78230, 2, 1, { 74 }, FLAGS_HAS_PV }, 380 { MARVELL_ARMADAXP_MV78260, 0, 1, { 66 }, FLAGS_HAS_PV }, 381 { MARVELL_ARMADAXP_MV78260, 1, 1, { 70 }, FLAGS_HAS_PV }, 382 { MARVELL_ARMADAXP_MV78260, 2, 1, { 74 }, FLAGS_HAS_PV }, 383 { MARVELL_ARMADAXP_MV78260, 3, 1, { 78 }, FLAGS_HAS_PV }, 384 { MARVELL_ARMADAXP_MV78460, 0, 1, { 66 }, FLAGS_HAS_PV }, 385 { MARVELL_ARMADAXP_MV78460, 1, 1, { 70 }, FLAGS_HAS_PV }, 386 { MARVELL_ARMADAXP_MV78460, 2, 1, { 74 }, FLAGS_HAS_PV }, 387 { MARVELL_ARMADAXP_MV78460, 3, 1, { 78 }, FLAGS_HAS_PV }, 388 }; 389 390 391 /* ARGSUSED */ 392 static int 393 mvgbec_match(device_t parent, cfdata_t match, void *aux) 394 { 395 struct marvell_attach_args *mva = aux; 396 int i; 397 398 if (strcmp(mva->mva_name, match->cf_name) != 0) 399 return 0; 400 if (mva->mva_offset == MVA_OFFSET_DEFAULT) 401 return 0; 402 403 for (i = 0; i < __arraycount(mvgbe_ports); i++) 404 if (mva->mva_model == mvgbe_ports[i].model) { 405 mva->mva_size = MVGBE_SIZE; 406 return 1; 407 } 408 return 0; 409 } 410 411 /* ARGSUSED */ 412 static void 413 mvgbec_attach(device_t parent, device_t self, void *aux) 414 { 415 struct mvgbec_softc *csc = device_private(self); 416 struct marvell_attach_args *mva = aux, gbea; 417 struct mvgbe_softc *port; 418 struct mii_softc *mii; 419 device_t child; 420 uint32_t phyaddr; 421 int i, j; 422 423 aprint_naive("\n"); 424 aprint_normal(": Marvell Gigabit Ethernet Controller\n"); 425 426 csc->sc_dev = self; 427 csc->sc_iot = mva->mva_iot; 428 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset, 429 mva->mva_size, &csc->sc_ioh)) { 430 aprint_error_dev(self, "Cannot map registers\n"); 431 return; 432 } 433 434 if (mvgbec0 == NULL) 435 mvgbec0 = self; 436 437 phyaddr = 0; 438 MVGBE_WRITE(csc, MVGBE_PHYADDR, phyaddr); 439 440 mutex_init(&csc->sc_mtx, MUTEX_DEFAULT, IPL_NET); 441 442 /* Disable and clear Gigabit Ethernet Unit interrupts */ 443 MVGBE_WRITE(csc, MVGBE_EUIM, 0); 444 MVGBE_WRITE(csc, MVGBE_EUIC, 0); 445 446 mvgbec_wininit(csc); 447 448 memset(&gbea, 0, sizeof(gbea)); 449 for (i = 0; i < __arraycount(mvgbe_ports); i++) { 450 if (mvgbe_ports[i].model != mva->mva_model || 451 mvgbe_ports[i].unit != mva->mva_unit) 452 continue; 453 454 csc->sc_flags = mvgbe_ports[i].flags; 455 456 for (j = 0; j < mvgbe_ports[i].ports; j++) { 457 gbea.mva_name = "mvgbe"; 458 gbea.mva_model = mva->mva_model; 459 gbea.mva_iot = csc->sc_iot; 460 gbea.mva_ioh = csc->sc_ioh; 461 gbea.mva_unit = j; 462 gbea.mva_dmat = mva->mva_dmat; 463 gbea.mva_irq = mvgbe_ports[i].irqs[j]; 464 child = config_found_sm_loc(csc->sc_dev, "mvgbec", NULL, 465 &gbea, mvgbec_print, mvgbec_search); 466 if (child) { 467 port = device_private(child); 468 mii = LIST_FIRST(&port->sc_mii.mii_phys); 469 if (mii != NULL) 470 phyaddr |= MVGBE_PHYADDR_PHYAD(j, 471 mii->mii_phy); 472 } 473 } 474 break; 475 } 476 MVGBE_WRITE(csc, MVGBE_PHYADDR, phyaddr); 477 } 478 479 static int 480 mvgbec_print(void *aux, const char *pnp) 481 { 482 struct marvell_attach_args *gbea = aux; 483 484 if (pnp) 485 aprint_normal("%s at %s port %d", 486 gbea->mva_name, pnp, gbea->mva_unit); 487 else { 488 if (gbea->mva_unit != MVGBECCF_PORT_DEFAULT) 489 aprint_normal(" port %d", gbea->mva_unit); 490 if (gbea->mva_irq != MVGBECCF_IRQ_DEFAULT) 491 aprint_normal(" irq %d", gbea->mva_irq); 492 } 493 return UNCONF; 494 } 495 496 /* ARGSUSED */ 497 static int 498 mvgbec_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 499 { 500 struct marvell_attach_args *gbea = aux; 501 502 if (cf->cf_loc[MVGBECCF_PORT] == gbea->mva_unit && 503 cf->cf_loc[MVGBECCF_IRQ] != MVGBECCF_IRQ_DEFAULT) 504 gbea->mva_irq = cf->cf_loc[MVGBECCF_IRQ]; 505 506 return config_match(parent, cf, aux); 507 } 508 509 static int 510 mvgbec_miibus_readreg(device_t dev, int phy, int reg) 511 { 512 struct mvgbe_softc *sc = device_private(dev); 513 struct mvgbec_softc *csc; 514 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 515 uint32_t smi, val; 516 int i; 517 518 if (mvgbec0 == NULL) { 519 aprint_error_ifnet(ifp, "SMI mvgbec0 not found\n"); 520 return -1; 521 } 522 csc = device_private(mvgbec0); 523 524 mutex_enter(&csc->sc_mtx); 525 526 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 527 DELAY(1); 528 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 529 break; 530 } 531 if (i == MVGBE_PHY_TIMEOUT) { 532 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 533 mutex_exit(&csc->sc_mtx); 534 return -1; 535 } 536 537 smi = 538 MVGBE_SMI_PHYAD(phy) | MVGBE_SMI_REGAD(reg) | MVGBE_SMI_OPCODE_READ; 539 MVGBE_WRITE(csc, MVGBE_SMI, smi); 540 541 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 542 DELAY(1); 543 smi = MVGBE_READ(csc, MVGBE_SMI); 544 if (smi & MVGBE_SMI_READVALID) 545 break; 546 } 547 548 mutex_exit(&csc->sc_mtx); 549 550 DPRINTFN(9, ("mvgbec_miibus_readreg: i=%d, timeout=%d\n", 551 i, MVGBE_PHY_TIMEOUT)); 552 553 val = smi & MVGBE_SMI_DATA_MASK; 554 555 DPRINTFN(9, ("mvgbec_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 556 phy, reg, val)); 557 558 return val; 559 } 560 561 static void 562 mvgbec_miibus_writereg(device_t dev, int phy, int reg, int val) 563 { 564 struct mvgbe_softc *sc = device_private(dev); 565 struct mvgbec_softc *csc; 566 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 567 uint32_t smi; 568 int i; 569 570 if (mvgbec0 == NULL) { 571 aprint_error_ifnet(ifp, "SMI mvgbec0 not found\n"); 572 return; 573 } 574 csc = device_private(mvgbec0); 575 576 DPRINTFN(9, ("mvgbec_miibus_writereg phy=%d reg=%#x val=%#x\n", 577 phy, reg, val)); 578 579 mutex_enter(&csc->sc_mtx); 580 581 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 582 DELAY(1); 583 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 584 break; 585 } 586 if (i == MVGBE_PHY_TIMEOUT) { 587 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 588 mutex_exit(&csc->sc_mtx); 589 return; 590 } 591 592 smi = MVGBE_SMI_PHYAD(phy) | MVGBE_SMI_REGAD(reg) | 593 MVGBE_SMI_OPCODE_WRITE | (val & MVGBE_SMI_DATA_MASK); 594 MVGBE_WRITE(csc, MVGBE_SMI, smi); 595 596 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 597 DELAY(1); 598 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 599 break; 600 } 601 602 mutex_exit(&csc->sc_mtx); 603 604 if (i == MVGBE_PHY_TIMEOUT) 605 aprint_error_ifnet(ifp, "phy write timed out\n"); 606 } 607 608 static void 609 mvgbec_miibus_statchg(struct ifnet *ifp) 610 { 611 612 /* nothing to do */ 613 } 614 615 616 static void 617 mvgbec_wininit(struct mvgbec_softc *sc) 618 { 619 device_t pdev = device_parent(sc->sc_dev); 620 uint64_t base; 621 uint32_t en, ac, size; 622 int window, target, attr, rv, i; 623 static int tags[] = { 624 MARVELL_TAG_SDRAM_CS0, 625 MARVELL_TAG_SDRAM_CS1, 626 MARVELL_TAG_SDRAM_CS2, 627 MARVELL_TAG_SDRAM_CS3, 628 629 MARVELL_TAG_UNDEFINED, 630 }; 631 632 /* First disable all address decode windows */ 633 en = MVGBE_BARE_EN_MASK; 634 MVGBE_WRITE(sc, MVGBE_BARE, en); 635 636 ac = 0; 637 for (window = 0, i = 0; 638 tags[i] != MARVELL_TAG_UNDEFINED && window < MVGBE_NWINDOW; i++) { 639 rv = marvell_winparams_by_tag(pdev, tags[i], 640 &target, &attr, &base, &size); 641 if (rv != 0 || size == 0) 642 continue; 643 644 if (base > 0xffffffffULL) { 645 if (window >= MVGBE_NREMAP) { 646 aprint_error_dev(sc->sc_dev, 647 "can't remap window %d\n", window); 648 continue; 649 } 650 MVGBE_WRITE(sc, MVGBE_HA(window), 651 (base >> 32) & 0xffffffff); 652 } 653 654 MVGBE_WRITE(sc, MVGBE_BASEADDR(window), 655 MVGBE_BASEADDR_TARGET(target) | 656 MVGBE_BASEADDR_ATTR(attr) | 657 MVGBE_BASEADDR_BASE(base)); 658 MVGBE_WRITE(sc, MVGBE_S(window), MVGBE_S_SIZE(size)); 659 660 en &= ~(1 << window); 661 /* set full access (r/w) */ 662 ac |= MVGBE_EPAP_EPAR(window, MVGBE_EPAP_AC_FA); 663 window++; 664 } 665 /* allow to access decode window */ 666 MVGBE_WRITE(sc, MVGBE_EPAP, ac); 667 668 MVGBE_WRITE(sc, MVGBE_BARE, en); 669 } 670 671 672 /* ARGSUSED */ 673 static int 674 mvgbe_match(device_t parent, cfdata_t match, void *aux) 675 { 676 struct marvell_attach_args *mva = aux; 677 uint32_t pbase, maddrh, maddrl; 678 679 pbase = MVGBE_PORTR_BASE + mva->mva_unit * MVGBE_PORTR_SIZE; 680 maddrh = 681 bus_space_read_4(mva->mva_iot, mva->mva_ioh, pbase + MVGBE_MACAH); 682 maddrl = 683 bus_space_read_4(mva->mva_iot, mva->mva_ioh, pbase + MVGBE_MACAL); 684 if ((maddrh | maddrl) == 0) 685 return 0; 686 687 return 1; 688 } 689 690 /* ARGSUSED */ 691 static void 692 mvgbe_attach(device_t parent, device_t self, void *aux) 693 { 694 struct mvgbec_softc *csc = device_private(parent); 695 struct mvgbe_softc *sc = device_private(self); 696 struct marvell_attach_args *mva = aux; 697 struct mvgbe_txmap_entry *entry; 698 struct ifnet *ifp; 699 bus_dma_segment_t seg; 700 bus_dmamap_t dmamap; 701 int rseg, i; 702 uint32_t maddrh, maddrl; 703 void *kva; 704 705 aprint_naive("\n"); 706 aprint_normal("\n"); 707 708 sc->sc_dev = self; 709 sc->sc_port = mva->mva_unit; 710 sc->sc_iot = mva->mva_iot; 711 callout_init(&sc->sc_tick_ch, 0); 712 callout_setfunc(&sc->sc_tick_ch, mvgbe_tick, sc); 713 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 714 MVGBE_PORTR_BASE + mva->mva_unit * MVGBE_PORTR_SIZE, 715 MVGBE_PORTR_SIZE, &sc->sc_ioh)) { 716 aprint_error_dev(self, "Cannot map registers\n"); 717 return; 718 } 719 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 720 MVGBE_PORTDAFR_BASE + mva->mva_unit * MVGBE_PORTDAFR_SIZE, 721 MVGBE_PORTDAFR_SIZE, &sc->sc_dafh)) { 722 aprint_error_dev(self, 723 "Cannot map destination address filter registers\n"); 724 return; 725 } 726 sc->sc_dmat = mva->mva_dmat; 727 728 if (csc->sc_flags & FLAGS_HAS_PV) { 729 /* GbE port has Port Version register. */ 730 sc->sc_version = MVGBE_READ(sc, MVGBE_PV); 731 aprint_normal_dev(self, "Port Version 0x%x\n", sc->sc_version); 732 } 733 734 if (sc->sc_version >= 0x10) { 735 /* 736 * Armada XP 737 */ 738 739 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 740 MVGBE_PS0, sizeof(uint32_t), &sc->sc_linkup.ioh)) { 741 aprint_error_dev(self, "Cannot map linkup register\n"); 742 return; 743 } 744 sc->sc_linkup.bit = MVGBE_PS0_LINKUP; 745 csc->sc_flags |= FLAGS_IPG2; 746 } else { 747 if (bus_space_subregion(mva->mva_iot, sc->sc_ioh, 748 MVGBE_PS, sizeof(uint32_t), &sc->sc_linkup.ioh)) { 749 aprint_error_dev(self, "Cannot map linkup register\n"); 750 return; 751 } 752 sc->sc_linkup.bit = MVGBE_PS_LINKUP; 753 } 754 755 maddrh = MVGBE_READ(sc, MVGBE_MACAH); 756 maddrl = MVGBE_READ(sc, MVGBE_MACAL); 757 sc->sc_enaddr[0] = maddrh >> 24; 758 sc->sc_enaddr[1] = maddrh >> 16; 759 sc->sc_enaddr[2] = maddrh >> 8; 760 sc->sc_enaddr[3] = maddrh >> 0; 761 sc->sc_enaddr[4] = maddrl >> 8; 762 sc->sc_enaddr[5] = maddrl >> 0; 763 aprint_normal_dev(self, "Ethernet address %s\n", 764 ether_sprintf(sc->sc_enaddr)); 765 766 /* clear all ethernet port interrupts */ 767 MVGBE_WRITE(sc, MVGBE_IC, 0); 768 MVGBE_WRITE(sc, MVGBE_ICE, 0); 769 770 marvell_intr_establish(mva->mva_irq, IPL_NET, mvgbe_intr, sc); 771 772 /* Allocate the descriptor queues. */ 773 if (bus_dmamem_alloc(sc->sc_dmat, sizeof(struct mvgbe_ring_data), 774 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 775 aprint_error_dev(self, "can't alloc rx buffers\n"); 776 return; 777 } 778 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, 779 sizeof(struct mvgbe_ring_data), &kva, BUS_DMA_NOWAIT)) { 780 aprint_error_dev(self, "can't map dma buffers (%lu bytes)\n", 781 (u_long)sizeof(struct mvgbe_ring_data)); 782 goto fail1; 783 } 784 if (bus_dmamap_create(sc->sc_dmat, sizeof(struct mvgbe_ring_data), 1, 785 sizeof(struct mvgbe_ring_data), 0, BUS_DMA_NOWAIT, 786 &sc->sc_ring_map)) { 787 aprint_error_dev(self, "can't create dma map\n"); 788 goto fail2; 789 } 790 if (bus_dmamap_load(sc->sc_dmat, sc->sc_ring_map, kva, 791 sizeof(struct mvgbe_ring_data), NULL, BUS_DMA_NOWAIT)) { 792 aprint_error_dev(self, "can't load dma map\n"); 793 goto fail3; 794 } 795 for (i = 0; i < MVGBE_RX_RING_CNT; i++) 796 sc->sc_cdata.mvgbe_rx_chain[i].mvgbe_mbuf = NULL; 797 798 SIMPLEQ_INIT(&sc->sc_txmap_head); 799 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 800 sc->sc_cdata.mvgbe_tx_chain[i].mvgbe_mbuf = NULL; 801 802 if (bus_dmamap_create(sc->sc_dmat, 803 MVGBE_JLEN, MVGBE_NTXSEG, MVGBE_JLEN, 0, 804 BUS_DMA_NOWAIT, &dmamap)) { 805 aprint_error_dev(self, "Can't create TX dmamap\n"); 806 goto fail4; 807 } 808 809 entry = kmem_alloc(sizeof(*entry), KM_SLEEP); 810 if (!entry) { 811 aprint_error_dev(self, "Can't alloc txmap entry\n"); 812 bus_dmamap_destroy(sc->sc_dmat, dmamap); 813 goto fail4; 814 } 815 entry->dmamap = dmamap; 816 SIMPLEQ_INSERT_HEAD(&sc->sc_txmap_head, entry, link); 817 } 818 819 sc->sc_rdata = (struct mvgbe_ring_data *)kva; 820 memset(sc->sc_rdata, 0, sizeof(struct mvgbe_ring_data)); 821 822 /* 823 * We can support 802.1Q VLAN-sized frames and jumbo 824 * Ethernet frames. 825 */ 826 sc->sc_ethercom.ec_capabilities |= 827 ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU; 828 829 /* Try to allocate memory for jumbo buffers. */ 830 if (mvgbe_alloc_jumbo_mem(sc)) { 831 aprint_error_dev(self, "jumbo buffer allocation failed\n"); 832 goto fail4; 833 } 834 835 ifp = &sc->sc_ethercom.ec_if; 836 ifp->if_softc = sc; 837 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 838 ifp->if_start = mvgbe_start; 839 ifp->if_ioctl = mvgbe_ioctl; 840 ifp->if_init = mvgbe_init; 841 ifp->if_stop = mvgbe_stop; 842 ifp->if_watchdog = mvgbe_watchdog; 843 /* 844 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 845 */ 846 sc->sc_ethercom.ec_if.if_capabilities |= 847 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 848 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 849 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 850 /* 851 * But, IPv6 packets in the stream can cause incorrect TCPv4 Tx sums. 852 */ 853 sc->sc_ethercom.ec_if.if_capabilities &= ~IFCAP_CSUM_TCPv4_Tx; 854 IFQ_SET_MAXLEN(&ifp->if_snd, max(MVGBE_TX_RING_CNT - 1, IFQ_MAXLEN)); 855 IFQ_SET_READY(&ifp->if_snd); 856 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 857 858 mvgbe_stop(ifp, 0); 859 860 /* 861 * Do MII setup. 862 */ 863 sc->sc_mii.mii_ifp = ifp; 864 sc->sc_mii.mii_readreg = mvgbec_miibus_readreg; 865 sc->sc_mii.mii_writereg = mvgbec_miibus_writereg; 866 sc->sc_mii.mii_statchg = mvgbec_miibus_statchg; 867 868 sc->sc_ethercom.ec_mii = &sc->sc_mii; 869 ifmedia_init(&sc->sc_mii.mii_media, 0, 870 mvgbe_mediachange, mvgbe_mediastatus); 871 mii_attach(self, &sc->sc_mii, 0xffffffff, 872 MII_PHY_ANY, parent == mvgbec0 ? 0 : 1, 0); 873 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 874 aprint_error_dev(self, "no PHY found!\n"); 875 ifmedia_add(&sc->sc_mii.mii_media, 876 IFM_ETHER|IFM_MANUAL, 0, NULL); 877 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 878 } else 879 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 880 881 /* 882 * Call MI attach routines. 883 */ 884 if_attach(ifp); 885 886 ether_ifattach(ifp, sc->sc_enaddr); 887 ether_set_ifflags_cb(&sc->sc_ethercom, mvgbe_ifflags_cb); 888 889 sysctl_mvgbe_init(sc); 890 #ifdef MVGBE_EVENT_COUNTERS 891 /* Attach event counters. */ 892 evcnt_attach_dynamic(&sc->sc_ev_rxoverrun, EVCNT_TYPE_MISC, 893 NULL, device_xname(sc->sc_dev), "rxoverrrun"); 894 evcnt_attach_dynamic(&sc->sc_ev_wdogsoft, EVCNT_TYPE_MISC, 895 NULL, device_xname(sc->sc_dev), "wdogsoft"); 896 #endif 897 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 898 RND_TYPE_NET, 0); 899 900 return; 901 902 fail4: 903 while ((entry = SIMPLEQ_FIRST(&sc->sc_txmap_head)) != NULL) { 904 SIMPLEQ_REMOVE_HEAD(&sc->sc_txmap_head, link); 905 bus_dmamap_destroy(sc->sc_dmat, entry->dmamap); 906 } 907 bus_dmamap_unload(sc->sc_dmat, sc->sc_ring_map); 908 fail3: 909 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ring_map); 910 fail2: 911 bus_dmamem_unmap(sc->sc_dmat, kva, sizeof(struct mvgbe_ring_data)); 912 fail1: 913 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 914 return; 915 } 916 917 static int 918 mvgbe_ipginttx(struct mvgbec_softc *csc, struct mvgbe_softc *sc, 919 unsigned int ipginttx) 920 { 921 uint32_t reg; 922 reg = MVGBE_READ(sc, MVGBE_PTFUT); 923 924 if (csc->sc_flags & FLAGS_IPG2) { 925 if (ipginttx > MVGBE_PTFUT_IPGINTTX_V2_MAX) 926 return -1; 927 reg &= ~MVGBE_PTFUT_IPGINTTX_V2_MASK; 928 reg |= MVGBE_PTFUT_IPGINTTX_V2(ipginttx); 929 } else if (csc->sc_flags & FLAGS_IPG1) { 930 if (ipginttx > MVGBE_PTFUT_IPGINTTX_V1_MAX) 931 return -1; 932 reg &= ~MVGBE_PTFUT_IPGINTTX_V1_MASK; 933 reg |= MVGBE_PTFUT_IPGINTTX_V1(ipginttx); 934 } 935 MVGBE_WRITE(sc, MVGBE_PTFUT, reg); 936 937 return 0; 938 } 939 940 static int 941 mvgbe_ipgintrx(struct mvgbec_softc *csc, struct mvgbe_softc *sc, 942 unsigned int ipgintrx) 943 { 944 uint32_t reg; 945 reg = MVGBE_READ(sc, MVGBE_SDC); 946 947 if (csc->sc_flags & FLAGS_IPG2) { 948 if (ipgintrx > MVGBE_SDC_IPGINTRX_V2_MAX) 949 return -1; 950 reg &= ~MVGBE_SDC_IPGINTRX_V2_MASK; 951 reg |= MVGBE_SDC_IPGINTRX_V2(ipgintrx); 952 } else if (csc->sc_flags & FLAGS_IPG1) { 953 if (ipgintrx > MVGBE_SDC_IPGINTRX_V1_MAX) 954 return -1; 955 reg &= ~MVGBE_SDC_IPGINTRX_V1_MASK; 956 reg |= MVGBE_SDC_IPGINTRX_V1(ipgintrx); 957 } 958 MVGBE_WRITE(sc, MVGBE_SDC, reg); 959 960 return 0; 961 } 962 963 static void 964 mvgbe_tick(void *arg) 965 { 966 struct mvgbe_softc *sc = arg; 967 struct mii_data *mii = &sc->sc_mii; 968 int s; 969 970 s = splnet(); 971 mii_tick(mii); 972 /* Need more work */ 973 MVGBE_EVCNT_ADD(&sc->sc_ev_rxoverrun, MVGBE_READ(sc, MVGBE_POFC)); 974 splx(s); 975 976 callout_schedule(&sc->sc_tick_ch, hz); 977 } 978 979 static int 980 mvgbe_intr(void *arg) 981 { 982 struct mvgbe_softc *sc = arg; 983 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 984 uint32_t ic, ice, datum = 0; 985 int claimed = 0; 986 987 for (;;) { 988 ice = MVGBE_READ(sc, MVGBE_ICE); 989 ic = MVGBE_READ(sc, MVGBE_IC); 990 991 DPRINTFN(3, ("mvgbe_intr: ic=%#x, ice=%#x\n", ic, ice)); 992 if (ic == 0 && ice == 0) 993 break; 994 995 datum = datum ^ ic ^ ice; 996 997 MVGBE_WRITE(sc, MVGBE_IC, ~ic); 998 MVGBE_WRITE(sc, MVGBE_ICE, ~ice); 999 1000 claimed = 1; 1001 1002 if (!(ifp->if_flags & IFF_RUNNING)) 1003 break; 1004 1005 if (ice & MVGBE_ICE_LINKCHG) { 1006 if (MVGBE_IS_LINKUP(sc)) { 1007 /* Enable port RX and TX. */ 1008 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_ENQ(0)); 1009 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0)); 1010 } else { 1011 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_DISQ(0)); 1012 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ(0)); 1013 } 1014 1015 /* Notify link change event to mii layer */ 1016 mii_pollstat(&sc->sc_mii); 1017 } 1018 1019 if (ic & (MVGBE_IC_RXBUF | MVGBE_IC_RXERROR)) 1020 mvgbe_rxeof(sc); 1021 1022 if (ice & (MVGBE_ICE_TXBUF_MASK | MVGBE_ICE_TXERR_MASK)) 1023 mvgbe_txeof(sc); 1024 } 1025 1026 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1027 mvgbe_start(ifp); 1028 1029 rnd_add_uint32(&sc->sc_rnd_source, datum); 1030 1031 return claimed; 1032 } 1033 1034 static void 1035 mvgbe_start(struct ifnet *ifp) 1036 { 1037 struct mvgbe_softc *sc = ifp->if_softc; 1038 struct mbuf *m_head = NULL; 1039 uint32_t idx = sc->sc_cdata.mvgbe_tx_prod; 1040 int pkts = 0; 1041 1042 DPRINTFN(3, ("mvgbe_start (idx %d, tx_chain[idx] %p)\n", idx, 1043 sc->sc_cdata.mvgbe_tx_chain[idx].mvgbe_mbuf)); 1044 1045 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1046 return; 1047 /* If Link is DOWN, can't start TX */ 1048 if (!MVGBE_IS_LINKUP(sc)) 1049 return; 1050 1051 while (sc->sc_cdata.mvgbe_tx_chain[idx].mvgbe_mbuf == NULL) { 1052 IFQ_POLL(&ifp->if_snd, m_head); 1053 if (m_head == NULL) 1054 break; 1055 1056 /* 1057 * Pack the data into the transmit ring. If we 1058 * don't have room, set the OACTIVE flag and wait 1059 * for the NIC to drain the ring. 1060 */ 1061 if (mvgbe_encap(sc, m_head, &idx)) { 1062 if (sc->sc_cdata.mvgbe_tx_cnt > 0) 1063 ifp->if_flags |= IFF_OACTIVE; 1064 break; 1065 } 1066 1067 /* now we are committed to transmit the packet */ 1068 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1069 pkts++; 1070 1071 /* 1072 * If there's a BPF listener, bounce a copy of this frame 1073 * to him. 1074 */ 1075 bpf_mtap(ifp, m_head); 1076 } 1077 if (pkts == 0) 1078 return; 1079 1080 /* Transmit at Queue 0 */ 1081 if (idx != sc->sc_cdata.mvgbe_tx_prod) { 1082 sc->sc_cdata.mvgbe_tx_prod = idx; 1083 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0)); 1084 1085 /* 1086 * Set a timeout in case the chip goes out to lunch. 1087 */ 1088 ifp->if_timer = 1; 1089 sc->sc_wdogsoft = 1; 1090 } 1091 } 1092 1093 static int 1094 mvgbe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1095 { 1096 struct mvgbe_softc *sc = ifp->if_softc; 1097 struct ifreq *ifr = data; 1098 int s, error = 0; 1099 1100 s = splnet(); 1101 1102 switch (cmd) { 1103 case SIOCGIFMEDIA: 1104 case SIOCSIFMEDIA: 1105 DPRINTFN(2, ("mvgbe_ioctl MEDIA\n")); 1106 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1107 break; 1108 default: 1109 DPRINTFN(2, ("mvgbe_ioctl ETHER\n")); 1110 error = ether_ioctl(ifp, cmd, data); 1111 if (error == ENETRESET) { 1112 if (ifp->if_flags & IFF_RUNNING) { 1113 mvgbe_filter_setup(sc); 1114 } 1115 error = 0; 1116 } 1117 break; 1118 } 1119 1120 splx(s); 1121 1122 return error; 1123 } 1124 1125 static int 1126 mvgbe_init(struct ifnet *ifp) 1127 { 1128 struct mvgbe_softc *sc = ifp->if_softc; 1129 struct mvgbec_softc *csc = device_private(device_parent(sc->sc_dev)); 1130 struct mii_data *mii = &sc->sc_mii; 1131 uint32_t reg; 1132 int i; 1133 1134 DPRINTFN(2, ("mvgbe_init\n")); 1135 1136 /* Cancel pending I/O and free all RX/TX buffers. */ 1137 mvgbe_stop(ifp, 0); 1138 1139 /* clear all ethernet port interrupts */ 1140 MVGBE_WRITE(sc, MVGBE_IC, 0); 1141 MVGBE_WRITE(sc, MVGBE_ICE, 0); 1142 1143 /* Init TX/RX descriptors */ 1144 if (mvgbe_init_tx_ring(sc) == ENOBUFS) { 1145 aprint_error_ifnet(ifp, 1146 "initialization failed: no memory for tx buffers\n"); 1147 return ENOBUFS; 1148 } 1149 if (mvgbe_init_rx_ring(sc) == ENOBUFS) { 1150 aprint_error_ifnet(ifp, 1151 "initialization failed: no memory for rx buffers\n"); 1152 return ENOBUFS; 1153 } 1154 1155 if ((csc->sc_flags & FLAGS_IPG1) || (csc->sc_flags & FLAGS_IPG2)) { 1156 sc->sc_ipginttx = MVGBE_IPGINTTX_DEFAULT; 1157 sc->sc_ipgintrx = MVGBE_IPGINTRX_DEFAULT; 1158 } 1159 if (csc->sc_flags & FLAGS_FIX_MTU) 1160 MVGBE_WRITE(sc, MVGBE_MTU, 0); /* hw reset value is wrong */ 1161 if (sc->sc_version >= 0x10) { 1162 MVGBE_WRITE(csc, MVGBE_PANC, 1163 MVGBE_PANC_FORCELINKPASS | 1164 MVGBE_PANC_INBANDANBYPASSEN | 1165 MVGBE_PANC_SETMIISPEED | 1166 MVGBE_PANC_SETGMIISPEED | 1167 MVGBE_PANC_ANSPEEDEN | 1168 MVGBE_PANC_SETFCEN | 1169 MVGBE_PANC_PAUSEADV | 1170 MVGBE_PANC_SETFULLDX | 1171 MVGBE_PANC_ANDUPLEXEN | 1172 MVGBE_PANC_RESERVED); 1173 MVGBE_WRITE(csc, MVGBE_PMACC0, 1174 MVGBE_PMACC0_RESERVED | 1175 MVGBE_PMACC0_FRAMESIZELIMIT(1600)); 1176 MVGBE_WRITE(csc, MVGBE_PMACC2, 1177 MVGBE_PMACC2_PCSEN | 1178 MVGBE_PMACC2_RESERVED | 1179 MVGBE_PMACC2_RGMIIEN); 1180 1181 MVGBE_WRITE(sc, MVGBE_PXCX, 1182 MVGBE_READ(sc, MVGBE_PXCX) & ~MVGBE_PXCX_TXCRCDIS); 1183 1184 #ifndef MULTIPROCESSOR 1185 MVGBE_WRITE(sc, MVGBE_PACC, MVGVE_PACC_ACCELERATIONMODE_BM); 1186 #else 1187 MVGBE_WRITE(sc, MVGBE_PACC, MVGVE_PACC_ACCELERATIONMODE_EDM); 1188 #endif 1189 } else { 1190 MVGBE_WRITE(sc, MVGBE_PSC, 1191 MVGBE_PSC_ANFC | /* Enable Auto-Neg Flow Ctrl */ 1192 MVGBE_PSC_RESERVED | /* Must be set to 1 */ 1193 MVGBE_PSC_FLFAIL | /* Do NOT Force Link Fail */ 1194 MVGBE_PSC_MRU(MVGBE_PSC_MRU_9022) | /* we want 9k */ 1195 MVGBE_PSC_SETFULLDX); /* Set_FullDx */ 1196 /* XXXX: mvgbe(4) always use RGMII. */ 1197 MVGBE_WRITE(sc, MVGBE_PSC1, 1198 MVGBE_READ(sc, MVGBE_PSC1) | MVGBE_PSC1_RGMIIEN); 1199 /* XXXX: Also always Weighted Round-Robin Priority Mode */ 1200 MVGBE_WRITE(sc, MVGBE_TQFPC, MVGBE_TQFPC_EN(0)); 1201 1202 sc->sc_cmdsts_opts = MVGBE_TX_GENERATE_CRC; 1203 } 1204 1205 MVGBE_WRITE(sc, MVGBE_CRDP(0), MVGBE_RX_RING_ADDR(sc, 0)); 1206 MVGBE_WRITE(sc, MVGBE_TCQDP, MVGBE_TX_RING_ADDR(sc, 0)); 1207 1208 if (csc->sc_flags & FLAGS_FIX_TQTB) { 1209 /* 1210 * Queue 0 (offset 0x72700) must be programmed to 0x3fffffff. 1211 * And offset 0x72704 must be programmed to 0x03ffffff. 1212 * Queue 1 through 7 must be programmed to 0x0. 1213 */ 1214 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(0), 0x3fffffff); 1215 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(0), 0x03ffffff); 1216 for (i = 1; i < 8; i++) { 1217 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x0); 1218 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0x0); 1219 } 1220 } else if (sc->sc_version < 0x10) 1221 for (i = 1; i < 8; i++) { 1222 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x3fffffff); 1223 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0xffff7fff); 1224 MVGBE_WRITE(sc, MVGBE_TQAC(i), 0xfc0000ff); 1225 } 1226 1227 MVGBE_WRITE(sc, MVGBE_PXC, MVGBE_PXC_RXCS); 1228 MVGBE_WRITE(sc, MVGBE_PXCX, 0); 1229 1230 /* Set SDC register except IPGINT bits */ 1231 MVGBE_WRITE(sc, MVGBE_SDC, 1232 MVGBE_SDC_RXBSZ_16_64BITWORDS | 1233 #if BYTE_ORDER == LITTLE_ENDIAN 1234 MVGBE_SDC_BLMR | /* Big/Little Endian Receive Mode: No swap */ 1235 MVGBE_SDC_BLMT | /* Big/Little Endian Transmit Mode: No swap */ 1236 #endif 1237 MVGBE_SDC_TXBSZ_16_64BITWORDS); 1238 /* And then set IPGINT bits */ 1239 mvgbe_ipgintrx(csc, sc, sc->sc_ipgintrx); 1240 1241 /* Tx side */ 1242 MVGBE_WRITE(sc, MVGBE_PTFUT, 0); 1243 mvgbe_ipginttx(csc, sc, sc->sc_ipginttx); 1244 1245 mvgbe_filter_setup(sc); 1246 1247 mii_mediachg(mii); 1248 1249 /* Enable port */ 1250 if (sc->sc_version >= 0x10) { 1251 reg = MVGBE_READ(csc, MVGBE_PMACC0); 1252 MVGBE_WRITE(csc, MVGBE_PMACC0, reg | MVGBE_PMACC0_PORTEN); 1253 } else { 1254 reg = MVGBE_READ(sc, MVGBE_PSC); 1255 MVGBE_WRITE(sc, MVGBE_PSC, reg | MVGBE_PSC_PORTEN); 1256 } 1257 1258 /* If Link is UP, Start RX and TX traffic */ 1259 if (MVGBE_IS_LINKUP(sc)) { 1260 /* Enable port RX/TX. */ 1261 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_ENQ(0)); 1262 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0)); 1263 } 1264 1265 /* Enable interrupt masks */ 1266 MVGBE_WRITE(sc, MVGBE_PIM, 1267 MVGBE_IC_RXBUF | 1268 MVGBE_IC_EXTEND | 1269 MVGBE_IC_RXBUFQ_MASK | 1270 MVGBE_IC_RXERROR | 1271 MVGBE_IC_RXERRQ_MASK); 1272 MVGBE_WRITE(sc, MVGBE_PEIM, 1273 MVGBE_ICE_TXBUF_MASK | 1274 MVGBE_ICE_TXERR_MASK | 1275 MVGBE_ICE_LINKCHG); 1276 1277 callout_schedule(&sc->sc_tick_ch, hz); 1278 1279 ifp->if_flags |= IFF_RUNNING; 1280 ifp->if_flags &= ~IFF_OACTIVE; 1281 1282 return 0; 1283 } 1284 1285 /* ARGSUSED */ 1286 static void 1287 mvgbe_stop(struct ifnet *ifp, int disable) 1288 { 1289 struct mvgbe_softc *sc = ifp->if_softc; 1290 struct mvgbec_softc *csc = device_private(device_parent(sc->sc_dev)); 1291 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1292 uint32_t reg, txinprog, txfifoemp; 1293 int i, cnt; 1294 1295 DPRINTFN(2, ("mvgbe_stop\n")); 1296 1297 callout_stop(&sc->sc_tick_ch); 1298 1299 /* Stop Rx port activity. Check port Rx activity. */ 1300 reg = MVGBE_READ(sc, MVGBE_RQC); 1301 if (reg & MVGBE_RQC_ENQ_MASK) 1302 /* Issue stop command for active channels only */ 1303 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_DISQ_DISABLE(reg)); 1304 1305 /* Stop Tx port activity. Check port Tx activity. */ 1306 if (MVGBE_READ(sc, MVGBE_TQC) & MVGBE_TQC_ENQ(0)) 1307 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ(0)); 1308 1309 /* Force link down */ 1310 if (sc->sc_version >= 0x10) { 1311 reg = MVGBE_READ(csc, MVGBE_PANC); 1312 MVGBE_WRITE(csc, MVGBE_PANC, reg | MVGBE_PANC_FORCELINKFAIL); 1313 1314 txinprog = MVGBE_PS_TXINPROG_(0); 1315 txfifoemp = MVGBE_PS_TXFIFOEMP_(0); 1316 } else { 1317 reg = MVGBE_READ(sc, MVGBE_PSC); 1318 MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_FLFAIL); 1319 1320 txinprog = MVGBE_PS_TXINPROG; 1321 txfifoemp = MVGBE_PS_TXFIFOEMP; 1322 } 1323 1324 #define RX_DISABLE_TIMEOUT 0x1000000 1325 #define TX_FIFO_EMPTY_TIMEOUT 0x1000000 1326 /* Wait for all Rx activity to terminate. */ 1327 cnt = 0; 1328 do { 1329 if (cnt >= RX_DISABLE_TIMEOUT) { 1330 aprint_error_ifnet(ifp, 1331 "timeout for RX stopped. rqc 0x%x\n", reg); 1332 break; 1333 } 1334 cnt++; 1335 1336 /* 1337 * Check Receive Queue Command register that all Rx queues 1338 * are stopped 1339 */ 1340 reg = MVGBE_READ(sc, MVGBE_RQC); 1341 } while (reg & 0xff); 1342 1343 /* Double check to verify that TX FIFO is empty */ 1344 cnt = 0; 1345 while (1) { 1346 do { 1347 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) { 1348 aprint_error_ifnet(ifp, 1349 "timeout for TX FIFO empty. status 0x%x\n", 1350 reg); 1351 break; 1352 } 1353 cnt++; 1354 1355 reg = MVGBE_READ(sc, MVGBE_PS); 1356 } while (!(reg & txfifoemp) || reg & txinprog); 1357 1358 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) 1359 break; 1360 1361 /* Double check */ 1362 reg = MVGBE_READ(sc, MVGBE_PS); 1363 if (reg & txfifoemp && !(reg & txinprog)) 1364 break; 1365 else 1366 aprint_error_ifnet(ifp, 1367 "TX FIFO empty double check failed." 1368 " %d loops, status 0x%x\n", cnt, reg); 1369 } 1370 1371 /* Reset the Enable bit */ 1372 if (sc->sc_version >= 0x10) { 1373 reg = MVGBE_READ(csc, MVGBE_PMACC0); 1374 MVGBE_WRITE(csc, MVGBE_PMACC0, reg & ~MVGBE_PMACC0_PORTEN); 1375 } else { 1376 reg = MVGBE_READ(sc, MVGBE_PSC); 1377 MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_PORTEN); 1378 } 1379 1380 /* 1381 * Disable and clear interrupts 1382 * 0) controller interrupt 1383 * 1) port interrupt cause 1384 * 2) port interrupt mask 1385 */ 1386 MVGBE_WRITE(csc, MVGBE_EUIM, 0); 1387 MVGBE_WRITE(csc, MVGBE_EUIC, 0); 1388 MVGBE_WRITE(sc, MVGBE_IC, 0); 1389 MVGBE_WRITE(sc, MVGBE_ICE, 0); 1390 MVGBE_WRITE(sc, MVGBE_PIM, 0); 1391 MVGBE_WRITE(sc, MVGBE_PEIM, 0); 1392 1393 /* Free RX and TX mbufs still in the queues. */ 1394 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1395 if (cdata->mvgbe_rx_chain[i].mvgbe_mbuf != NULL) { 1396 m_freem(cdata->mvgbe_rx_chain[i].mvgbe_mbuf); 1397 cdata->mvgbe_rx_chain[i].mvgbe_mbuf = NULL; 1398 } 1399 } 1400 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 1401 if (cdata->mvgbe_tx_chain[i].mvgbe_mbuf != NULL) { 1402 m_freem(cdata->mvgbe_tx_chain[i].mvgbe_mbuf); 1403 cdata->mvgbe_tx_chain[i].mvgbe_mbuf = NULL; 1404 } 1405 } 1406 1407 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1408 } 1409 1410 static void 1411 mvgbe_watchdog(struct ifnet *ifp) 1412 { 1413 struct mvgbe_softc *sc = ifp->if_softc; 1414 1415 /* 1416 * Reclaim first as there is a possibility of losing Tx completion 1417 * interrupts. 1418 */ 1419 mvgbe_txeof(sc); 1420 if (sc->sc_cdata.mvgbe_tx_cnt != 0) { 1421 if (sc->sc_wdogsoft) { 1422 /* 1423 * There is race condition between CPU and DMA 1424 * engine. When DMA engine encounters queue end, 1425 * it clears MVGBE_TQC_ENQ bit. 1426 */ 1427 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0)); 1428 ifp->if_timer = 5; 1429 sc->sc_wdogsoft = 0; 1430 MVGBE_EVCNT_INCR(&sc->sc_ev_wdogsoft); 1431 } else { 1432 aprint_error_ifnet(ifp, "watchdog timeout\n"); 1433 1434 ifp->if_oerrors++; 1435 1436 mvgbe_init(ifp); 1437 } 1438 } 1439 } 1440 1441 static int 1442 mvgbe_ifflags_cb(struct ethercom *ec) 1443 { 1444 struct ifnet *ifp = &ec->ec_if; 1445 struct mvgbe_softc *sc = ifp->if_softc; 1446 int change = ifp->if_flags ^ sc->sc_if_flags; 1447 1448 if (change != 0) 1449 sc->sc_if_flags = ifp->if_flags; 1450 1451 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 1452 return ENETRESET; 1453 1454 if ((change & IFF_PROMISC) != 0) 1455 mvgbe_filter_setup(sc); 1456 1457 return 0; 1458 } 1459 1460 /* 1461 * Set media options. 1462 */ 1463 static int 1464 mvgbe_mediachange(struct ifnet *ifp) 1465 { 1466 return ether_mediachange(ifp); 1467 } 1468 1469 /* 1470 * Report current media status. 1471 */ 1472 static void 1473 mvgbe_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1474 { 1475 ether_mediastatus(ifp, ifmr); 1476 } 1477 1478 1479 static int 1480 mvgbe_init_rx_ring(struct mvgbe_softc *sc) 1481 { 1482 struct mvgbe_chain_data *cd = &sc->sc_cdata; 1483 struct mvgbe_ring_data *rd = sc->sc_rdata; 1484 int i; 1485 1486 memset(rd->mvgbe_rx_ring, 0, 1487 sizeof(struct mvgbe_rx_desc) * MVGBE_RX_RING_CNT); 1488 1489 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1490 cd->mvgbe_rx_chain[i].mvgbe_desc = 1491 &rd->mvgbe_rx_ring[i]; 1492 if (i == MVGBE_RX_RING_CNT - 1) { 1493 cd->mvgbe_rx_chain[i].mvgbe_next = 1494 &cd->mvgbe_rx_chain[0]; 1495 rd->mvgbe_rx_ring[i].nextdescptr = 1496 MVGBE_RX_RING_ADDR(sc, 0); 1497 } else { 1498 cd->mvgbe_rx_chain[i].mvgbe_next = 1499 &cd->mvgbe_rx_chain[i + 1]; 1500 rd->mvgbe_rx_ring[i].nextdescptr = 1501 MVGBE_RX_RING_ADDR(sc, i + 1); 1502 } 1503 } 1504 1505 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1506 if (mvgbe_newbuf(sc, i, NULL, 1507 sc->sc_cdata.mvgbe_rx_jumbo_map) == ENOBUFS) { 1508 aprint_error_ifnet(&sc->sc_ethercom.ec_if, 1509 "failed alloc of %dth mbuf\n", i); 1510 return ENOBUFS; 1511 } 1512 } 1513 sc->sc_cdata.mvgbe_rx_prod = 0; 1514 sc->sc_cdata.mvgbe_rx_cons = 0; 1515 1516 return 0; 1517 } 1518 1519 static int 1520 mvgbe_init_tx_ring(struct mvgbe_softc *sc) 1521 { 1522 struct mvgbe_chain_data *cd = &sc->sc_cdata; 1523 struct mvgbe_ring_data *rd = sc->sc_rdata; 1524 int i; 1525 1526 memset(sc->sc_rdata->mvgbe_tx_ring, 0, 1527 sizeof(struct mvgbe_tx_desc) * MVGBE_TX_RING_CNT); 1528 1529 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 1530 cd->mvgbe_tx_chain[i].mvgbe_desc = 1531 &rd->mvgbe_tx_ring[i]; 1532 if (i == MVGBE_TX_RING_CNT - 1) { 1533 cd->mvgbe_tx_chain[i].mvgbe_next = 1534 &cd->mvgbe_tx_chain[0]; 1535 rd->mvgbe_tx_ring[i].nextdescptr = 1536 MVGBE_TX_RING_ADDR(sc, 0); 1537 } else { 1538 cd->mvgbe_tx_chain[i].mvgbe_next = 1539 &cd->mvgbe_tx_chain[i + 1]; 1540 rd->mvgbe_tx_ring[i].nextdescptr = 1541 MVGBE_TX_RING_ADDR(sc, i + 1); 1542 } 1543 rd->mvgbe_tx_ring[i].cmdsts = MVGBE_BUFFER_OWNED_BY_HOST; 1544 } 1545 1546 sc->sc_cdata.mvgbe_tx_prod = 0; 1547 sc->sc_cdata.mvgbe_tx_cons = 0; 1548 sc->sc_cdata.mvgbe_tx_cnt = 0; 1549 1550 MVGBE_CDTXSYNC(sc, 0, MVGBE_TX_RING_CNT, 1551 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1552 1553 return 0; 1554 } 1555 1556 static int 1557 mvgbe_newbuf(struct mvgbe_softc *sc, int i, struct mbuf *m, 1558 bus_dmamap_t dmamap) 1559 { 1560 struct mbuf *m_new = NULL; 1561 struct mvgbe_chain *c; 1562 struct mvgbe_rx_desc *r; 1563 int align; 1564 vaddr_t offset; 1565 1566 if (m == NULL) { 1567 void *buf = NULL; 1568 1569 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1570 if (m_new == NULL) { 1571 aprint_error_ifnet(&sc->sc_ethercom.ec_if, 1572 "no memory for rx list -- packet dropped!\n"); 1573 return ENOBUFS; 1574 } 1575 1576 /* Allocate the jumbo buffer */ 1577 buf = mvgbe_jalloc(sc); 1578 if (buf == NULL) { 1579 m_freem(m_new); 1580 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 1581 "dropped!\n", sc->sc_ethercom.ec_if.if_xname)); 1582 return ENOBUFS; 1583 } 1584 1585 /* Attach the buffer to the mbuf */ 1586 m_new->m_len = m_new->m_pkthdr.len = MVGBE_JLEN; 1587 MEXTADD(m_new, buf, MVGBE_JLEN, 0, mvgbe_jfree, sc); 1588 } else { 1589 /* 1590 * We're re-using a previously allocated mbuf; 1591 * be sure to re-init pointers and lengths to 1592 * default values. 1593 */ 1594 m_new = m; 1595 m_new->m_len = m_new->m_pkthdr.len = MVGBE_JLEN; 1596 m_new->m_data = m_new->m_ext.ext_buf; 1597 } 1598 align = (u_long)m_new->m_data & MVGBE_RXBUF_MASK; 1599 if (align != 0) { 1600 DPRINTFN(1,("align = %d\n", align)); 1601 m_adj(m_new, MVGBE_RXBUF_ALIGN - align); 1602 } 1603 1604 c = &sc->sc_cdata.mvgbe_rx_chain[i]; 1605 r = c->mvgbe_desc; 1606 c->mvgbe_mbuf = m_new; 1607 offset = (vaddr_t)m_new->m_data - (vaddr_t)sc->sc_cdata.mvgbe_jumbo_buf; 1608 r->bufptr = dmamap->dm_segs[0].ds_addr + offset; 1609 r->bufsize = MVGBE_JLEN & ~MVGBE_RXBUF_MASK; 1610 r->cmdsts = MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_ENABLE_INTERRUPT; 1611 1612 /* Invalidate RX buffer */ 1613 bus_dmamap_sync(sc->sc_dmat, dmamap, offset, r->bufsize, 1614 BUS_DMASYNC_PREREAD); 1615 1616 MVGBE_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1617 1618 return 0; 1619 } 1620 1621 /* 1622 * Memory management for jumbo frames. 1623 */ 1624 1625 static int 1626 mvgbe_alloc_jumbo_mem(struct mvgbe_softc *sc) 1627 { 1628 char *ptr, *kva; 1629 bus_dma_segment_t seg; 1630 int i, rseg, state, error; 1631 struct mvgbe_jpool_entry *entry; 1632 1633 state = error = 0; 1634 1635 /* Grab a big chunk o' storage. */ 1636 if (bus_dmamem_alloc(sc->sc_dmat, MVGBE_JMEM, PAGE_SIZE, 0, 1637 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1638 aprint_error_dev(sc->sc_dev, "can't alloc rx buffers\n"); 1639 return ENOBUFS; 1640 } 1641 1642 state = 1; 1643 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, MVGBE_JMEM, 1644 (void **)&kva, BUS_DMA_NOWAIT)) { 1645 aprint_error_dev(sc->sc_dev, 1646 "can't map dma buffers (%d bytes)\n", MVGBE_JMEM); 1647 error = ENOBUFS; 1648 goto out; 1649 } 1650 1651 state = 2; 1652 if (bus_dmamap_create(sc->sc_dmat, MVGBE_JMEM, 1, MVGBE_JMEM, 0, 1653 BUS_DMA_NOWAIT, &sc->sc_cdata.mvgbe_rx_jumbo_map)) { 1654 aprint_error_dev(sc->sc_dev, "can't create dma map\n"); 1655 error = ENOBUFS; 1656 goto out; 1657 } 1658 1659 state = 3; 1660 if (bus_dmamap_load(sc->sc_dmat, sc->sc_cdata.mvgbe_rx_jumbo_map, 1661 kva, MVGBE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1662 aprint_error_dev(sc->sc_dev, "can't load dma map\n"); 1663 error = ENOBUFS; 1664 goto out; 1665 } 1666 1667 state = 4; 1668 sc->sc_cdata.mvgbe_jumbo_buf = (void *)kva; 1669 DPRINTFN(1,("mvgbe_jumbo_buf = %p\n", sc->sc_cdata.mvgbe_jumbo_buf)); 1670 1671 LIST_INIT(&sc->sc_jfree_listhead); 1672 LIST_INIT(&sc->sc_jinuse_listhead); 1673 1674 /* 1675 * Now divide it up into 9K pieces and save the addresses 1676 * in an array. 1677 */ 1678 ptr = sc->sc_cdata.mvgbe_jumbo_buf; 1679 for (i = 0; i < MVGBE_JSLOTS; i++) { 1680 sc->sc_cdata.mvgbe_jslots[i] = ptr; 1681 ptr += MVGBE_JLEN; 1682 entry = kmem_alloc(sizeof(struct mvgbe_jpool_entry), KM_SLEEP); 1683 if (entry == NULL) { 1684 aprint_error_dev(sc->sc_dev, 1685 "no memory for jumbo buffer queue!\n"); 1686 error = ENOBUFS; 1687 goto out; 1688 } 1689 entry->slot = i; 1690 if (i) 1691 LIST_INSERT_HEAD(&sc->sc_jfree_listhead, entry, 1692 jpool_entries); 1693 else 1694 LIST_INSERT_HEAD(&sc->sc_jinuse_listhead, entry, 1695 jpool_entries); 1696 } 1697 out: 1698 if (error != 0) { 1699 switch (state) { 1700 case 4: 1701 bus_dmamap_unload(sc->sc_dmat, 1702 sc->sc_cdata.mvgbe_rx_jumbo_map); 1703 case 3: 1704 bus_dmamap_destroy(sc->sc_dmat, 1705 sc->sc_cdata.mvgbe_rx_jumbo_map); 1706 case 2: 1707 bus_dmamem_unmap(sc->sc_dmat, kva, MVGBE_JMEM); 1708 case 1: 1709 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1710 break; 1711 default: 1712 break; 1713 } 1714 } 1715 1716 return error; 1717 } 1718 1719 /* 1720 * Allocate a jumbo buffer. 1721 */ 1722 static void * 1723 mvgbe_jalloc(struct mvgbe_softc *sc) 1724 { 1725 struct mvgbe_jpool_entry *entry; 1726 1727 entry = LIST_FIRST(&sc->sc_jfree_listhead); 1728 1729 if (entry == NULL) 1730 return NULL; 1731 1732 LIST_REMOVE(entry, jpool_entries); 1733 LIST_INSERT_HEAD(&sc->sc_jinuse_listhead, entry, jpool_entries); 1734 return sc->sc_cdata.mvgbe_jslots[entry->slot]; 1735 } 1736 1737 /* 1738 * Release a jumbo buffer. 1739 */ 1740 static void 1741 mvgbe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1742 { 1743 struct mvgbe_jpool_entry *entry; 1744 struct mvgbe_softc *sc; 1745 int i, s; 1746 1747 /* Extract the softc struct pointer. */ 1748 sc = (struct mvgbe_softc *)arg; 1749 1750 if (sc == NULL) 1751 panic("%s: can't find softc pointer!", __func__); 1752 1753 /* calculate the slot this buffer belongs to */ 1754 1755 i = ((vaddr_t)buf - (vaddr_t)sc->sc_cdata.mvgbe_jumbo_buf) / MVGBE_JLEN; 1756 1757 if ((i < 0) || (i >= MVGBE_JSLOTS)) 1758 panic("%s: asked to free buffer that we don't manage!", 1759 __func__); 1760 1761 s = splvm(); 1762 entry = LIST_FIRST(&sc->sc_jinuse_listhead); 1763 if (entry == NULL) 1764 panic("%s: buffer not in use!", __func__); 1765 entry->slot = i; 1766 LIST_REMOVE(entry, jpool_entries); 1767 LIST_INSERT_HEAD(&sc->sc_jfree_listhead, entry, jpool_entries); 1768 1769 if (__predict_true(m != NULL)) 1770 pool_cache_put(mb_cache, m); 1771 splx(s); 1772 } 1773 1774 static int 1775 mvgbe_encap(struct mvgbe_softc *sc, struct mbuf *m_head, 1776 uint32_t *txidx) 1777 { 1778 struct mvgbe_tx_desc *f = NULL; 1779 struct mvgbe_txmap_entry *entry; 1780 bus_dma_segment_t *txseg; 1781 bus_dmamap_t txmap; 1782 uint32_t first, current, last, cmdsts; 1783 int m_csumflags, i; 1784 bool needs_defrag = false; 1785 1786 DPRINTFN(3, ("mvgbe_encap\n")); 1787 1788 entry = SIMPLEQ_FIRST(&sc->sc_txmap_head); 1789 if (entry == NULL) { 1790 DPRINTFN(2, ("mvgbe_encap: no txmap available\n")); 1791 return ENOBUFS; 1792 } 1793 txmap = entry->dmamap; 1794 1795 first = current = last = *txidx; 1796 1797 /* 1798 * Preserve m_pkthdr.csum_flags here since m_head might be 1799 * updated by m_defrag() 1800 */ 1801 m_csumflags = m_head->m_pkthdr.csum_flags; 1802 1803 do_defrag: 1804 if (__predict_false(needs_defrag == true)) { 1805 /* A small unaligned segment was detected. */ 1806 struct mbuf *m_new; 1807 m_new = m_defrag(m_head, M_DONTWAIT); 1808 if (m_new == NULL) 1809 return EFBIG; 1810 m_head = m_new; 1811 } 1812 1813 /* 1814 * Start packing the mbufs in this chain into 1815 * the fragment pointers. Stop when we run out 1816 * of fragments or hit the end of the mbuf chain. 1817 */ 1818 if (bus_dmamap_load_mbuf(sc->sc_dmat, txmap, m_head, BUS_DMA_NOWAIT)) { 1819 DPRINTFN(1, ("mvgbe_encap: dmamap failed\n")); 1820 return ENOBUFS; 1821 } 1822 1823 txseg = txmap->dm_segs; 1824 1825 if (__predict_true(needs_defrag == false)) { 1826 /* 1827 * Detect rarely encountered DMA limitation. 1828 */ 1829 for (i = 0; i < txmap->dm_nsegs; i++) { 1830 if (((txseg[i].ds_addr & 7) != 0) && 1831 (txseg[i].ds_len <= 8) && 1832 (txseg[i].ds_len >= 1) 1833 ) { 1834 txseg = NULL; 1835 bus_dmamap_unload(sc->sc_dmat, txmap); 1836 needs_defrag = true; 1837 goto do_defrag; 1838 } 1839 } 1840 } 1841 1842 /* Sync the DMA map. */ 1843 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize, 1844 BUS_DMASYNC_PREWRITE); 1845 1846 if (sc->sc_cdata.mvgbe_tx_cnt + txmap->dm_nsegs >= 1847 MVGBE_TX_RING_CNT) { 1848 DPRINTFN(2, ("mvgbe_encap: too few descriptors free\n")); 1849 bus_dmamap_unload(sc->sc_dmat, txmap); 1850 return ENOBUFS; 1851 } 1852 1853 1854 DPRINTFN(2, ("mvgbe_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1855 1856 for (i = 0; i < txmap->dm_nsegs; i++) { 1857 f = &sc->sc_rdata->mvgbe_tx_ring[current]; 1858 f->bufptr = txseg[i].ds_addr; 1859 f->bytecnt = txseg[i].ds_len; 1860 if (i != 0) 1861 f->cmdsts = MVGBE_BUFFER_OWNED_BY_DMA; 1862 last = current; 1863 current = MVGBE_TX_RING_NEXT(current); 1864 } 1865 1866 cmdsts = sc->sc_cmdsts_opts; 1867 if (m_csumflags & M_CSUM_IPv4) 1868 cmdsts |= MVGBE_TX_GENERATE_IP_CHKSUM; 1869 if (m_csumflags & M_CSUM_TCPv4) 1870 cmdsts |= 1871 MVGBE_TX_GENERATE_L4_CHKSUM | MVGBE_TX_L4_TYPE_TCP; 1872 if (m_csumflags & M_CSUM_UDPv4) 1873 cmdsts |= 1874 MVGBE_TX_GENERATE_L4_CHKSUM | MVGBE_TX_L4_TYPE_UDP; 1875 if (m_csumflags & (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1876 const int iphdr_unitlen = sizeof(struct ip) / sizeof(uint32_t); 1877 1878 cmdsts |= MVGBE_TX_IP_NO_FRAG | 1879 MVGBE_TX_IP_HEADER_LEN(iphdr_unitlen); /* unit is 4B */ 1880 } 1881 if (txmap->dm_nsegs == 1) 1882 f->cmdsts = cmdsts | 1883 MVGBE_TX_ENABLE_INTERRUPT | 1884 MVGBE_TX_ZERO_PADDING | 1885 MVGBE_TX_FIRST_DESC | 1886 MVGBE_TX_LAST_DESC; 1887 else { 1888 f = &sc->sc_rdata->mvgbe_tx_ring[first]; 1889 f->cmdsts = cmdsts | MVGBE_TX_FIRST_DESC; 1890 1891 f = &sc->sc_rdata->mvgbe_tx_ring[last]; 1892 f->cmdsts = 1893 MVGBE_BUFFER_OWNED_BY_DMA | 1894 MVGBE_TX_ENABLE_INTERRUPT | 1895 MVGBE_TX_ZERO_PADDING | 1896 MVGBE_TX_LAST_DESC; 1897 1898 /* Sync descriptors except first */ 1899 MVGBE_CDTXSYNC(sc, 1900 (MVGBE_TX_RING_CNT - 1 == *txidx) ? 0 : (*txidx) + 1, 1901 txmap->dm_nsegs - 1, 1902 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1903 } 1904 1905 sc->sc_cdata.mvgbe_tx_chain[last].mvgbe_mbuf = m_head; 1906 SIMPLEQ_REMOVE_HEAD(&sc->sc_txmap_head, link); 1907 sc->sc_cdata.mvgbe_tx_map[last] = entry; 1908 1909 /* Finally, sync first descriptor */ 1910 sc->sc_rdata->mvgbe_tx_ring[first].cmdsts |= 1911 MVGBE_BUFFER_OWNED_BY_DMA; 1912 MVGBE_CDTXSYNC(sc, *txidx, 1, 1913 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1914 1915 sc->sc_cdata.mvgbe_tx_cnt += i; 1916 *txidx = current; 1917 1918 DPRINTFN(3, ("mvgbe_encap: completed successfully\n")); 1919 1920 return 0; 1921 } 1922 1923 static void 1924 mvgbe_rxeof(struct mvgbe_softc *sc) 1925 { 1926 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1927 struct mvgbe_rx_desc *cur_rx; 1928 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1929 struct mbuf *m; 1930 bus_dmamap_t dmamap; 1931 uint32_t rxstat; 1932 uint16_t bufsize; 1933 int idx, cur, total_len; 1934 1935 idx = sc->sc_cdata.mvgbe_rx_prod; 1936 1937 DPRINTFN(3, ("mvgbe_rxeof %d\n", idx)); 1938 1939 for (;;) { 1940 cur = idx; 1941 1942 /* Sync the descriptor */ 1943 MVGBE_CDRXSYNC(sc, idx, 1944 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1945 1946 cur_rx = &sc->sc_rdata->mvgbe_rx_ring[idx]; 1947 1948 if ((cur_rx->cmdsts & MVGBE_BUFFER_OWNED_MASK) == 1949 MVGBE_BUFFER_OWNED_BY_DMA) { 1950 /* Invalidate the descriptor -- it's not ready yet */ 1951 MVGBE_CDRXSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1952 sc->sc_cdata.mvgbe_rx_prod = idx; 1953 break; 1954 } 1955 #ifdef DIAGNOSTIC 1956 if ((cur_rx->cmdsts & 1957 (MVGBE_RX_LAST_DESC | MVGBE_RX_FIRST_DESC)) != 1958 (MVGBE_RX_LAST_DESC | MVGBE_RX_FIRST_DESC)) 1959 panic( 1960 "mvgbe_rxeof: buffer size is smaller than packet"); 1961 #endif 1962 1963 dmamap = sc->sc_cdata.mvgbe_rx_jumbo_map; 1964 1965 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1966 BUS_DMASYNC_POSTREAD); 1967 1968 m = cdata->mvgbe_rx_chain[idx].mvgbe_mbuf; 1969 cdata->mvgbe_rx_chain[idx].mvgbe_mbuf = NULL; 1970 total_len = cur_rx->bytecnt - ETHER_CRC_LEN; 1971 rxstat = cur_rx->cmdsts; 1972 bufsize = cur_rx->bufsize; 1973 1974 cdata->mvgbe_rx_map[idx] = NULL; 1975 1976 idx = MVGBE_RX_RING_NEXT(idx); 1977 1978 if (rxstat & MVGBE_ERROR_SUMMARY) { 1979 #if 0 1980 int err = rxstat & MVGBE_RX_ERROR_CODE_MASK; 1981 1982 if (err == MVGBE_RX_CRC_ERROR) 1983 ifp->if_ierrors++; 1984 if (err == MVGBE_RX_OVERRUN_ERROR) 1985 ifp->if_ierrors++; 1986 if (err == MVGBE_RX_MAX_FRAME_LEN_ERROR) 1987 ifp->if_ierrors++; 1988 if (err == MVGBE_RX_RESOURCE_ERROR) 1989 ifp->if_ierrors++; 1990 #else 1991 ifp->if_ierrors++; 1992 #endif 1993 mvgbe_newbuf(sc, cur, m, dmamap); 1994 continue; 1995 } 1996 1997 if (rxstat & MVGBE_RX_IP_FRAME_TYPE) { 1998 int flgs = 0; 1999 2000 /* Check IPv4 header checksum */ 2001 flgs |= M_CSUM_IPv4; 2002 if (!(rxstat & MVGBE_RX_IP_HEADER_OK)) 2003 flgs |= M_CSUM_IPv4_BAD; 2004 else if ((bufsize & MVGBE_RX_IP_FRAGMENT) == 0) { 2005 /* 2006 * Check TCPv4/UDPv4 checksum for 2007 * non-fragmented packet only. 2008 * 2009 * It seemd that sometimes 2010 * MVGBE_RX_L4_CHECKSUM_OK bit was set to 0 2011 * even if the checksum is correct and the 2012 * packet was not fragmented. So we don't set 2013 * M_CSUM_TCP_UDP_BAD even if csum bit is 0. 2014 */ 2015 2016 if (((rxstat & MVGBE_RX_L4_TYPE_MASK) == 2017 MVGBE_RX_L4_TYPE_TCP) && 2018 ((rxstat & MVGBE_RX_L4_CHECKSUM_OK) != 0)) 2019 flgs |= M_CSUM_TCPv4; 2020 else if (((rxstat & MVGBE_RX_L4_TYPE_MASK) == 2021 MVGBE_RX_L4_TYPE_UDP) && 2022 ((rxstat & MVGBE_RX_L4_CHECKSUM_OK) != 0)) 2023 flgs |= M_CSUM_UDPv4; 2024 } 2025 m->m_pkthdr.csum_flags = flgs; 2026 } 2027 2028 /* 2029 * Try to allocate a new jumbo buffer. If that 2030 * fails, copy the packet to mbufs and put the 2031 * jumbo buffer back in the ring so it can be 2032 * re-used. If allocating mbufs fails, then we 2033 * have to drop the packet. 2034 */ 2035 if (mvgbe_newbuf(sc, cur, NULL, dmamap) == ENOBUFS) { 2036 struct mbuf *m0; 2037 2038 m0 = m_devget(mtod(m, char *), total_len, 0, ifp, NULL); 2039 mvgbe_newbuf(sc, cur, m, dmamap); 2040 if (m0 == NULL) { 2041 aprint_error_ifnet(ifp, 2042 "no receive buffers available --" 2043 " packet dropped!\n"); 2044 ifp->if_ierrors++; 2045 continue; 2046 } 2047 m = m0; 2048 } else { 2049 m->m_pkthdr.rcvif = ifp; 2050 m->m_pkthdr.len = m->m_len = total_len; 2051 } 2052 2053 /* Skip on first 2byte (HW header) */ 2054 m_adj(m, MVGBE_HWHEADER_SIZE); 2055 2056 ifp->if_ipackets++; 2057 2058 bpf_mtap(ifp, m); 2059 2060 /* pass it on. */ 2061 (*ifp->if_input)(ifp, m); 2062 } 2063 } 2064 2065 static void 2066 mvgbe_txeof(struct mvgbe_softc *sc) 2067 { 2068 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 2069 struct mvgbe_tx_desc *cur_tx; 2070 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2071 struct mvgbe_txmap_entry *entry; 2072 int idx; 2073 2074 DPRINTFN(3, ("mvgbe_txeof\n")); 2075 2076 /* 2077 * Go through our tx ring and free mbufs for those 2078 * frames that have been sent. 2079 */ 2080 idx = cdata->mvgbe_tx_cons; 2081 while (idx != cdata->mvgbe_tx_prod) { 2082 MVGBE_CDTXSYNC(sc, idx, 1, 2083 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2084 2085 cur_tx = &sc->sc_rdata->mvgbe_tx_ring[idx]; 2086 #ifdef MVGBE_DEBUG 2087 if (mvgbe_debug >= 3) 2088 mvgbe_dump_txdesc(cur_tx, idx); 2089 #endif 2090 if ((cur_tx->cmdsts & MVGBE_BUFFER_OWNED_MASK) == 2091 MVGBE_BUFFER_OWNED_BY_DMA) { 2092 MVGBE_CDTXSYNC(sc, idx, 1, BUS_DMASYNC_PREREAD); 2093 break; 2094 } 2095 if (cur_tx->cmdsts & MVGBE_TX_LAST_DESC) 2096 ifp->if_opackets++; 2097 if (cur_tx->cmdsts & MVGBE_ERROR_SUMMARY) { 2098 int err = cur_tx->cmdsts & MVGBE_TX_ERROR_CODE_MASK; 2099 2100 if (err == MVGBE_TX_LATE_COLLISION_ERROR) 2101 ifp->if_collisions++; 2102 if (err == MVGBE_TX_UNDERRUN_ERROR) 2103 ifp->if_oerrors++; 2104 if (err == MVGBE_TX_EXCESSIVE_COLLISION_ERRO) 2105 ifp->if_collisions++; 2106 } 2107 if (cdata->mvgbe_tx_chain[idx].mvgbe_mbuf != NULL) { 2108 entry = cdata->mvgbe_tx_map[idx]; 2109 2110 m_freem(cdata->mvgbe_tx_chain[idx].mvgbe_mbuf); 2111 cdata->mvgbe_tx_chain[idx].mvgbe_mbuf = NULL; 2112 2113 bus_dmamap_sync(sc->sc_dmat, entry->dmamap, 0, 2114 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2115 2116 bus_dmamap_unload(sc->sc_dmat, entry->dmamap); 2117 SIMPLEQ_INSERT_TAIL(&sc->sc_txmap_head, entry, link); 2118 cdata->mvgbe_tx_map[idx] = NULL; 2119 } 2120 cdata->mvgbe_tx_cnt--; 2121 idx = MVGBE_TX_RING_NEXT(idx); 2122 } 2123 if (cdata->mvgbe_tx_cnt == 0) 2124 ifp->if_timer = 0; 2125 2126 if (cdata->mvgbe_tx_cnt < MVGBE_TX_RING_CNT - 2) 2127 ifp->if_flags &= ~IFF_OACTIVE; 2128 2129 cdata->mvgbe_tx_cons = idx; 2130 } 2131 2132 static uint8_t 2133 mvgbe_crc8(const uint8_t *data, size_t size) 2134 { 2135 int bit; 2136 uint8_t byte; 2137 uint8_t crc = 0; 2138 const uint8_t poly = 0x07; 2139 2140 while(size--) 2141 for (byte = *data++, bit = NBBY-1; bit >= 0; bit--) 2142 crc = (crc << 1) ^ ((((crc >> 7) ^ (byte >> bit)) & 1) ? poly : 0); 2143 2144 return crc; 2145 } 2146 2147 CTASSERT(MVGBE_NDFSMT == MVGBE_NDFOMT); 2148 2149 static void 2150 mvgbe_filter_setup(struct mvgbe_softc *sc) 2151 { 2152 struct ethercom *ec = &sc->sc_ethercom; 2153 struct ifnet *ifp= &sc->sc_ethercom.ec_if; 2154 struct ether_multi *enm; 2155 struct ether_multistep step; 2156 uint32_t dfut[MVGBE_NDFUT], dfsmt[MVGBE_NDFSMT], dfomt[MVGBE_NDFOMT]; 2157 uint32_t pxc; 2158 int i; 2159 const uint8_t special[ETHER_ADDR_LEN] = {0x01,0x00,0x5e,0x00,0x00,0x00}; 2160 2161 memset(dfut, 0, sizeof(dfut)); 2162 memset(dfsmt, 0, sizeof(dfsmt)); 2163 memset(dfomt, 0, sizeof(dfomt)); 2164 2165 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 2166 goto allmulti; 2167 } 2168 2169 ETHER_FIRST_MULTI(step, ec, enm); 2170 while (enm != NULL) { 2171 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2172 /* ranges are complex and somewhat rare */ 2173 goto allmulti; 2174 } 2175 /* chip handles some IPv4 multicast specially */ 2176 if (memcmp(enm->enm_addrlo, special, 5) == 0) { 2177 i = enm->enm_addrlo[5]; 2178 dfsmt[i>>2] |= 2179 MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 2180 } else { 2181 i = mvgbe_crc8(enm->enm_addrlo, ETHER_ADDR_LEN); 2182 dfomt[i>>2] |= 2183 MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 2184 } 2185 2186 ETHER_NEXT_MULTI(step, enm); 2187 } 2188 goto set; 2189 2190 allmulti: 2191 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 2192 for (i = 0; i < MVGBE_NDFSMT; i++) { 2193 dfsmt[i] = dfomt[i] = 2194 MVGBE_DF(0, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 2195 MVGBE_DF(1, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 2196 MVGBE_DF(2, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 2197 MVGBE_DF(3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 2198 } 2199 } 2200 2201 set: 2202 pxc = MVGBE_READ(sc, MVGBE_PXC); 2203 pxc &= ~MVGBE_PXC_UPM; 2204 pxc |= MVGBE_PXC_RB | MVGBE_PXC_RBIP | MVGBE_PXC_RBARP; 2205 if (ifp->if_flags & IFF_BROADCAST) { 2206 pxc &= ~(MVGBE_PXC_RB | MVGBE_PXC_RBIP | MVGBE_PXC_RBARP); 2207 } 2208 if (ifp->if_flags & IFF_PROMISC) { 2209 pxc |= MVGBE_PXC_UPM; 2210 } 2211 MVGBE_WRITE(sc, MVGBE_PXC, pxc); 2212 2213 /* Set Destination Address Filter Unicast Table */ 2214 i = sc->sc_enaddr[5] & 0xf; /* last nibble */ 2215 dfut[i>>2] = MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 2216 MVGBE_WRITE_FILTER(sc, MVGBE_DFUT, dfut, MVGBE_NDFUT); 2217 2218 /* Set Destination Address Filter Multicast Tables */ 2219 MVGBE_WRITE_FILTER(sc, MVGBE_DFSMT, dfsmt, MVGBE_NDFSMT); 2220 MVGBE_WRITE_FILTER(sc, MVGBE_DFOMT, dfomt, MVGBE_NDFOMT); 2221 } 2222 2223 #ifdef MVGBE_DEBUG 2224 static void 2225 mvgbe_dump_txdesc(struct mvgbe_tx_desc *desc, int idx) 2226 { 2227 #define DESC_PRINT(X) \ 2228 if (X) \ 2229 printf("txdesc[%d]." #X "=%#x\n", idx, X); 2230 2231 #if BYTE_ORDER == BIG_ENDIAN 2232 DESC_PRINT(desc->bytecnt); 2233 DESC_PRINT(desc->l4ichk); 2234 DESC_PRINT(desc->cmdsts); 2235 DESC_PRINT(desc->nextdescptr); 2236 DESC_PRINT(desc->bufptr); 2237 #else /* LITTLE_ENDIAN */ 2238 DESC_PRINT(desc->cmdsts); 2239 DESC_PRINT(desc->l4ichk); 2240 DESC_PRINT(desc->bytecnt); 2241 DESC_PRINT(desc->bufptr); 2242 DESC_PRINT(desc->nextdescptr); 2243 #endif 2244 #undef DESC_PRINT 2245 } 2246 #endif 2247 2248 SYSCTL_SETUP(sysctl_mvgbe, "sysctl mvgbe subtree setup") 2249 { 2250 int rc; 2251 const struct sysctlnode *node; 2252 2253 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 2254 0, CTLTYPE_NODE, "hw", NULL, 2255 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 2256 goto err; 2257 } 2258 2259 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2260 0, CTLTYPE_NODE, "mvgbe", 2261 SYSCTL_DESCR("mvgbe interface controls"), 2262 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2263 goto err; 2264 } 2265 2266 mvgbe_root_num = node->sysctl_num; 2267 return; 2268 2269 err: 2270 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2271 } 2272 2273 static void 2274 sysctl_mvgbe_init(struct mvgbe_softc *sc) 2275 { 2276 const struct sysctlnode *node; 2277 int mvgbe_nodenum; 2278 2279 if (sysctl_createv(&sc->mvgbe_clog, 0, NULL, &node, 2280 0, CTLTYPE_NODE, device_xname(sc->sc_dev), 2281 SYSCTL_DESCR("mvgbe per-controller controls"), 2282 NULL, 0, NULL, 0, CTL_HW, mvgbe_root_num, CTL_CREATE, 2283 CTL_EOL) != 0) { 2284 aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 2285 return; 2286 } 2287 mvgbe_nodenum = node->sysctl_num; 2288 2289 /* interrupt moderation sysctls */ 2290 if (sysctl_createv(&sc->mvgbe_clog, 0, NULL, &node, 2291 CTLFLAG_READWRITE, CTLTYPE_INT, "ipginttx", 2292 SYSCTL_DESCR("mvgbe TX interrupt moderation timer"), 2293 mvgbe_sysctl_ipginttx, 0, (void *)sc, 2294 0, CTL_HW, mvgbe_root_num, mvgbe_nodenum, CTL_CREATE, 2295 CTL_EOL) != 0) { 2296 aprint_normal_dev(sc->sc_dev, 2297 "couldn't create ipginttx sysctl node\n"); 2298 } 2299 if (sysctl_createv(&sc->mvgbe_clog, 0, NULL, &node, 2300 CTLFLAG_READWRITE, CTLTYPE_INT, "ipgintrx", 2301 SYSCTL_DESCR("mvgbe RX interrupt moderation timer"), 2302 mvgbe_sysctl_ipgintrx, 0, (void *)sc, 2303 0, CTL_HW, mvgbe_root_num, mvgbe_nodenum, CTL_CREATE, 2304 CTL_EOL) != 0) { 2305 aprint_normal_dev(sc->sc_dev, 2306 "couldn't create ipginttx sysctl node\n"); 2307 } 2308 } 2309 2310 static int 2311 mvgbe_sysctl_ipginttx(SYSCTLFN_ARGS) 2312 { 2313 int error; 2314 unsigned int t; 2315 struct sysctlnode node; 2316 struct mvgbec_softc *csc; 2317 struct mvgbe_softc *sc; 2318 2319 node = *rnode; 2320 sc = node.sysctl_data; 2321 csc = device_private(device_parent(sc->sc_dev)); 2322 t = sc->sc_ipginttx; 2323 node.sysctl_data = &t; 2324 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2325 if (error || newp == NULL) 2326 return error; 2327 2328 if (mvgbe_ipginttx(csc, sc, t) < 0) 2329 return EINVAL; 2330 /* 2331 * update the softc with sysctl-changed value, and mark 2332 * for hardware update 2333 */ 2334 sc->sc_ipginttx = t; 2335 2336 return 0; 2337 } 2338 2339 static int 2340 mvgbe_sysctl_ipgintrx(SYSCTLFN_ARGS) 2341 { 2342 int error; 2343 unsigned int t; 2344 struct sysctlnode node; 2345 struct mvgbec_softc *csc; 2346 struct mvgbe_softc *sc; 2347 2348 node = *rnode; 2349 sc = node.sysctl_data; 2350 csc = device_private(device_parent(sc->sc_dev)); 2351 t = sc->sc_ipgintrx; 2352 node.sysctl_data = &t; 2353 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2354 if (error || newp == NULL) 2355 return error; 2356 2357 if (mvgbe_ipgintrx(csc, sc, t) < 0) 2358 return EINVAL; 2359 /* 2360 * update the softc with sysctl-changed value, and mark 2361 * for hardware update 2362 */ 2363 sc->sc_ipgintrx = t; 2364 2365 return 0; 2366 } 2367