1 /* $NetBSD: if_mvgbe.c,v 1.35 2013/12/23 02:23:25 kiyohara Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008, 2013 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_mvgbe.c,v 1.35 2013/12/23 02:23:25 kiyohara Exp $"); 29 30 #include "opt_multiprocessor.h" 31 32 #if defined MULTIPROCESSOR 33 #warning Queue Management Method 'Counters' not support yet 34 #endif 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/callout.h> 39 #include <sys/device.h> 40 #include <sys/endian.h> 41 #include <sys/errno.h> 42 #include <sys/evcnt.h> 43 #include <sys/kernel.h> 44 #include <sys/kmem.h> 45 #include <sys/mutex.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 49 #include <dev/marvell/marvellreg.h> 50 #include <dev/marvell/marvellvar.h> 51 #include <dev/marvell/mvgbereg.h> 52 53 #include <net/if.h> 54 #include <net/if_ether.h> 55 #include <net/if_media.h> 56 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/ip.h> 60 61 #include <net/bpf.h> 62 #include <sys/rnd.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #include "locators.h" 68 69 /* #define MVGBE_DEBUG 3 */ 70 #ifdef MVGBE_DEBUG 71 #define DPRINTF(x) if (mvgbe_debug) printf x 72 #define DPRINTFN(n,x) if (mvgbe_debug >= (n)) printf x 73 int mvgbe_debug = MVGBE_DEBUG; 74 #else 75 #define DPRINTF(x) 76 #define DPRINTFN(n,x) 77 #endif 78 79 80 #define MVGBE_READ(sc, reg) \ 81 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 82 #define MVGBE_WRITE(sc, reg, val) \ 83 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 84 #define MVGBE_READ_FILTER(sc, reg, val, c) \ 85 bus_space_read_region_4((sc)->sc_iot, (sc)->sc_dafh, (reg), (val), (c)) 86 #define MVGBE_WRITE_FILTER(sc, reg, val, c) \ 87 bus_space_write_region_4((sc)->sc_iot, (sc)->sc_dafh, (reg), (val), (c)) 88 89 #define MVGBE_LINKUP_READ(sc) \ 90 bus_space_read_4((sc)->sc_iot, (sc)->sc_linkup.ioh, 0) 91 #define MVGBE_IS_LINKUP(sc) (MVGBE_LINKUP_READ(sc) & (sc)->sc_linkup.bit) 92 93 #define MVGBE_TX_RING_CNT 256 94 #define MVGBE_TX_RING_MSK (MVGBE_TX_RING_CNT - 1) 95 #define MVGBE_TX_RING_NEXT(x) (((x) + 1) & MVGBE_TX_RING_MSK) 96 #define MVGBE_RX_RING_CNT 256 97 #define MVGBE_RX_RING_MSK (MVGBE_RX_RING_CNT - 1) 98 #define MVGBE_RX_RING_NEXT(x) (((x) + 1) & MVGBE_RX_RING_MSK) 99 100 CTASSERT(MVGBE_TX_RING_CNT > 1 && MVGBE_TX_RING_NEXT(MVGBE_TX_RING_CNT) == 101 (MVGBE_TX_RING_CNT + 1) % MVGBE_TX_RING_CNT); 102 CTASSERT(MVGBE_RX_RING_CNT > 1 && MVGBE_RX_RING_NEXT(MVGBE_RX_RING_CNT) == 103 (MVGBE_RX_RING_CNT + 1) % MVGBE_RX_RING_CNT); 104 105 #define MVGBE_JSLOTS 384 /* XXXX */ 106 #define MVGBE_JLEN \ 107 ((MVGBE_MRU + MVGBE_HWHEADER_SIZE + MVGBE_RXBUF_ALIGN - 1) & \ 108 ~MVGBE_RXBUF_MASK) 109 #define MVGBE_NTXSEG 30 110 #define MVGBE_JPAGESZ PAGE_SIZE 111 #define MVGBE_RESID \ 112 (MVGBE_JPAGESZ - (MVGBE_JLEN * MVGBE_JSLOTS) % MVGBE_JPAGESZ) 113 #define MVGBE_JMEM \ 114 ((MVGBE_JLEN * MVGBE_JSLOTS) + MVGBE_RESID) 115 116 #define MVGBE_TX_RING_ADDR(sc, i) \ 117 ((sc)->sc_ring_map->dm_segs[0].ds_addr + \ 118 offsetof(struct mvgbe_ring_data, mvgbe_tx_ring[(i)])) 119 120 #define MVGBE_RX_RING_ADDR(sc, i) \ 121 ((sc)->sc_ring_map->dm_segs[0].ds_addr + \ 122 offsetof(struct mvgbe_ring_data, mvgbe_rx_ring[(i)])) 123 124 #define MVGBE_CDOFF(x) offsetof(struct mvgbe_ring_data, x) 125 #define MVGBE_CDTXOFF(x) MVGBE_CDOFF(mvgbe_tx_ring[(x)]) 126 #define MVGBE_CDRXOFF(x) MVGBE_CDOFF(mvgbe_rx_ring[(x)]) 127 128 #define MVGBE_CDTXSYNC(sc, x, n, ops) \ 129 do { \ 130 int __x, __n; \ 131 const int __descsize = sizeof(struct mvgbe_tx_desc); \ 132 \ 133 __x = (x); \ 134 __n = (n); \ 135 \ 136 /* If it will wrap around, sync to the end of the ring. */ \ 137 if ((__x + __n) > MVGBE_TX_RING_CNT) { \ 138 bus_dmamap_sync((sc)->sc_dmat, \ 139 (sc)->sc_ring_map, MVGBE_CDTXOFF(__x), \ 140 __descsize * (MVGBE_TX_RING_CNT - __x), (ops)); \ 141 __n -= (MVGBE_TX_RING_CNT - __x); \ 142 __x = 0; \ 143 } \ 144 \ 145 /* Now sync whatever is left. */ \ 146 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_ring_map, \ 147 MVGBE_CDTXOFF((__x)), __descsize * __n, (ops)); \ 148 } while (0 /*CONSTCOND*/) 149 150 #define MVGBE_CDRXSYNC(sc, x, ops) \ 151 do { \ 152 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_ring_map, \ 153 MVGBE_CDRXOFF((x)), sizeof(struct mvgbe_rx_desc), (ops)); \ 154 } while (/*CONSTCOND*/0) 155 156 #define MVGBE_IPGINTTX_DEFAULT 768 157 #define MVGBE_IPGINTRX_DEFAULT 768 158 159 #ifdef MVGBE_EVENT_COUNTERS 160 #define MVGBE_EVCNT_INCR(ev) (ev)->ev_count++ 161 #define MVGBE_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 162 #else 163 #define MVGBE_EVCNT_INCR(ev) /* nothing */ 164 #define MVGBE_EVCNT_ADD(ev, val) /* nothing */ 165 #endif 166 167 struct mvgbe_jpool_entry { 168 int slot; 169 LIST_ENTRY(mvgbe_jpool_entry) jpool_entries; 170 }; 171 172 struct mvgbe_chain { 173 void *mvgbe_desc; 174 struct mbuf *mvgbe_mbuf; 175 struct mvgbe_chain *mvgbe_next; 176 }; 177 178 struct mvgbe_txmap_entry { 179 bus_dmamap_t dmamap; 180 SIMPLEQ_ENTRY(mvgbe_txmap_entry) link; 181 }; 182 183 struct mvgbe_chain_data { 184 struct mvgbe_chain mvgbe_tx_chain[MVGBE_TX_RING_CNT]; 185 struct mvgbe_txmap_entry *mvgbe_tx_map[MVGBE_TX_RING_CNT]; 186 int mvgbe_tx_prod; 187 int mvgbe_tx_cons; 188 int mvgbe_tx_cnt; 189 190 struct mvgbe_chain mvgbe_rx_chain[MVGBE_RX_RING_CNT]; 191 bus_dmamap_t mvgbe_rx_map[MVGBE_RX_RING_CNT]; 192 bus_dmamap_t mvgbe_rx_jumbo_map; 193 int mvgbe_rx_prod; 194 int mvgbe_rx_cons; 195 int mvgbe_rx_cnt; 196 197 /* Stick the jumbo mem management stuff here too. */ 198 void *mvgbe_jslots[MVGBE_JSLOTS]; 199 void *mvgbe_jumbo_buf; 200 }; 201 202 struct mvgbe_ring_data { 203 struct mvgbe_tx_desc mvgbe_tx_ring[MVGBE_TX_RING_CNT]; 204 struct mvgbe_rx_desc mvgbe_rx_ring[MVGBE_RX_RING_CNT]; 205 }; 206 207 struct mvgbec_softc { 208 device_t sc_dev; 209 210 bus_space_tag_t sc_iot; 211 bus_space_handle_t sc_ioh; 212 213 kmutex_t sc_mtx; 214 215 int sc_flags; 216 }; 217 218 struct mvgbe_softc { 219 device_t sc_dev; 220 int sc_port; 221 uint32_t sc_version; 222 223 bus_space_tag_t sc_iot; 224 bus_space_handle_t sc_ioh; 225 bus_space_handle_t sc_dafh; /* dest address filter handle */ 226 bus_dma_tag_t sc_dmat; 227 228 struct ethercom sc_ethercom; 229 struct mii_data sc_mii; 230 u_int8_t sc_enaddr[ETHER_ADDR_LEN]; /* station addr */ 231 232 callout_t sc_tick_ch; /* tick callout */ 233 234 struct mvgbe_chain_data sc_cdata; 235 struct mvgbe_ring_data *sc_rdata; 236 bus_dmamap_t sc_ring_map; 237 int sc_if_flags; 238 unsigned int sc_ipginttx; 239 unsigned int sc_ipgintrx; 240 int sc_wdogsoft; 241 242 LIST_HEAD(__mvgbe_jfreehead, mvgbe_jpool_entry) sc_jfree_listhead; 243 LIST_HEAD(__mvgbe_jinusehead, mvgbe_jpool_entry) sc_jinuse_listhead; 244 SIMPLEQ_HEAD(__mvgbe_txmaphead, mvgbe_txmap_entry) sc_txmap_head; 245 246 struct { 247 bus_space_handle_t ioh; 248 uint32_t bit; 249 } sc_linkup; 250 uint32_t sc_cmdsts_opts; 251 252 krndsource_t sc_rnd_source; 253 struct sysctllog *mvgbe_clog; 254 #ifdef MVGBE_EVENT_COUNTERS 255 struct evcnt sc_ev_rxoverrun; 256 struct evcnt sc_ev_wdogsoft; 257 #endif 258 }; 259 260 261 /* Gigabit Ethernet Unit Global part functions */ 262 263 static int mvgbec_match(device_t, struct cfdata *, void *); 264 static void mvgbec_attach(device_t, device_t, void *); 265 266 static int mvgbec_print(void *, const char *); 267 static int mvgbec_search(device_t, cfdata_t, const int *, void *); 268 269 /* MII funcstions */ 270 static int mvgbec_miibus_readreg(device_t, int, int); 271 static void mvgbec_miibus_writereg(device_t, int, int, int); 272 static void mvgbec_miibus_statchg(struct ifnet *); 273 274 static void mvgbec_wininit(struct mvgbec_softc *); 275 276 /* Gigabit Ethernet Port part functions */ 277 278 static int mvgbe_match(device_t, struct cfdata *, void *); 279 static void mvgbe_attach(device_t, device_t, void *); 280 281 static void mvgbe_tick(void *); 282 static int mvgbe_intr(void *); 283 284 static void mvgbe_start(struct ifnet *); 285 static int mvgbe_ioctl(struct ifnet *, u_long, void *); 286 static int mvgbe_init(struct ifnet *); 287 static void mvgbe_stop(struct ifnet *, int); 288 static void mvgbe_watchdog(struct ifnet *); 289 290 static int mvgbe_ifflags_cb(struct ethercom *); 291 292 static int mvgbe_mediachange(struct ifnet *); 293 static void mvgbe_mediastatus(struct ifnet *, struct ifmediareq *); 294 295 static int mvgbe_init_rx_ring(struct mvgbe_softc *); 296 static int mvgbe_init_tx_ring(struct mvgbe_softc *); 297 static int mvgbe_newbuf(struct mvgbe_softc *, int, struct mbuf *, bus_dmamap_t); 298 static int mvgbe_alloc_jumbo_mem(struct mvgbe_softc *); 299 static void *mvgbe_jalloc(struct mvgbe_softc *); 300 static void mvgbe_jfree(struct mbuf *, void *, size_t, void *); 301 static int mvgbe_encap(struct mvgbe_softc *, struct mbuf *, uint32_t *); 302 static void mvgbe_rxeof(struct mvgbe_softc *); 303 static void mvgbe_txeof(struct mvgbe_softc *); 304 static uint8_t mvgbe_crc8(const uint8_t *, size_t); 305 static void mvgbe_filter_setup(struct mvgbe_softc *); 306 #ifdef MVGBE_DEBUG 307 static void mvgbe_dump_txdesc(struct mvgbe_tx_desc *, int); 308 #endif 309 static int mvgbe_ipginttx(struct mvgbec_softc *, struct mvgbe_softc *, 310 unsigned int); 311 static int mvgbe_ipgintrx(struct mvgbec_softc *, struct mvgbe_softc *, 312 unsigned int); 313 static void sysctl_mvgbe_init(struct mvgbe_softc *); 314 static int mvgbe_sysctl_ipginttx(SYSCTLFN_PROTO); 315 static int mvgbe_sysctl_ipgintrx(SYSCTLFN_PROTO); 316 317 CFATTACH_DECL_NEW(mvgbec_gt, sizeof(struct mvgbec_softc), 318 mvgbec_match, mvgbec_attach, NULL, NULL); 319 CFATTACH_DECL_NEW(mvgbec_mbus, sizeof(struct mvgbec_softc), 320 mvgbec_match, mvgbec_attach, NULL, NULL); 321 322 CFATTACH_DECL_NEW(mvgbe, sizeof(struct mvgbe_softc), 323 mvgbe_match, mvgbe_attach, NULL, NULL); 324 325 device_t mvgbec0 = NULL; 326 static int mvgbe_root_num; 327 328 struct mvgbe_port { 329 int model; 330 int unit; 331 int ports; 332 int irqs[3]; 333 int flags; 334 #define FLAGS_FIX_TQTB (1 << 0) 335 #define FLAGS_FIX_MTU (1 << 1) 336 #define FLAGS_IPG1 (1 << 2) 337 #define FLAGS_IPG2 (1 << 3) 338 #define FLAGS_HAS_PV (1 << 4) /* Has Port Version Register */ 339 } mvgbe_ports[] = { 340 { MARVELL_DISCOVERY_II, 0, 3, { 32, 33, 34 }, 0 }, 341 { MARVELL_DISCOVERY_III, 0, 3, { 32, 33, 34 }, 0 }, 342 #if 0 343 { MARVELL_DISCOVERY_LT, 0, ?, { }, 0 }, 344 { MARVELL_DISCOVERY_V, 0, ?, { }, 0 }, 345 { MARVELL_DISCOVERY_VI, 0, ?, { }, 0 }, 346 #endif 347 { MARVELL_ORION_1_88F5082, 0, 1, { 21 }, FLAGS_FIX_MTU }, 348 { MARVELL_ORION_1_88F5180N, 0, 1, { 21 }, FLAGS_FIX_MTU }, 349 { MARVELL_ORION_1_88F5181, 0, 1, { 21 }, FLAGS_FIX_MTU | FLAGS_IPG1 }, 350 { MARVELL_ORION_1_88F5182, 0, 1, { 21 }, FLAGS_FIX_MTU | FLAGS_IPG1 }, 351 { MARVELL_ORION_2_88F5281, 0, 1, { 21 }, FLAGS_FIX_MTU | FLAGS_IPG1 }, 352 { MARVELL_ORION_1_88F6082, 0, 1, { 21 }, FLAGS_FIX_MTU }, 353 { MARVELL_ORION_1_88W8660, 0, 1, { 21 }, FLAGS_FIX_MTU }, 354 355 { MARVELL_KIRKWOOD_88F6180, 0, 1, { 11 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 356 { MARVELL_KIRKWOOD_88F6192, 0, 1, { 11 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 357 { MARVELL_KIRKWOOD_88F6192, 1, 1, { 15 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 358 { MARVELL_KIRKWOOD_88F6281, 0, 1, { 11 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 359 { MARVELL_KIRKWOOD_88F6281, 1, 1, { 15 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 360 { MARVELL_KIRKWOOD_88F6282, 0, 1, { 11 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 361 { MARVELL_KIRKWOOD_88F6282, 1, 1, { 15 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 362 363 { MARVELL_MV78XX0_MV78100, 0, 1, { 40 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 364 { MARVELL_MV78XX0_MV78100, 1, 1, { 44 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 365 { MARVELL_MV78XX0_MV78200, 0, 1, { 40 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 366 { MARVELL_MV78XX0_MV78200, 1, 1, { 44 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 367 { MARVELL_MV78XX0_MV78200, 2, 1, { 48 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 368 { MARVELL_MV78XX0_MV78200, 3, 1, { 52 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 369 370 { MARVELL_ARMADAXP_MV78130, 0, 1, { 66 }, FLAGS_HAS_PV }, 371 { MARVELL_ARMADAXP_MV78130, 1, 1, { 70 }, FLAGS_HAS_PV }, 372 { MARVELL_ARMADAXP_MV78130, 2, 1, { 74 }, FLAGS_HAS_PV }, 373 { MARVELL_ARMADAXP_MV78160, 0, 1, { 66 }, FLAGS_HAS_PV }, 374 { MARVELL_ARMADAXP_MV78160, 1, 1, { 70 }, FLAGS_HAS_PV }, 375 { MARVELL_ARMADAXP_MV78160, 2, 1, { 74 }, FLAGS_HAS_PV }, 376 { MARVELL_ARMADAXP_MV78160, 3, 1, { 78 }, FLAGS_HAS_PV }, 377 { MARVELL_ARMADAXP_MV78230, 0, 1, { 66 }, FLAGS_HAS_PV }, 378 { MARVELL_ARMADAXP_MV78230, 1, 1, { 70 }, FLAGS_HAS_PV }, 379 { MARVELL_ARMADAXP_MV78230, 2, 1, { 74 }, FLAGS_HAS_PV }, 380 { MARVELL_ARMADAXP_MV78260, 0, 1, { 66 }, FLAGS_HAS_PV }, 381 { MARVELL_ARMADAXP_MV78260, 1, 1, { 70 }, FLAGS_HAS_PV }, 382 { MARVELL_ARMADAXP_MV78260, 2, 1, { 74 }, FLAGS_HAS_PV }, 383 { MARVELL_ARMADAXP_MV78260, 3, 1, { 78 }, FLAGS_HAS_PV }, 384 { MARVELL_ARMADAXP_MV78460, 0, 1, { 66 }, FLAGS_HAS_PV }, 385 { MARVELL_ARMADAXP_MV78460, 1, 1, { 70 }, FLAGS_HAS_PV }, 386 { MARVELL_ARMADAXP_MV78460, 2, 1, { 74 }, FLAGS_HAS_PV }, 387 { MARVELL_ARMADAXP_MV78460, 3, 1, { 78 }, FLAGS_HAS_PV }, 388 }; 389 390 391 /* ARGSUSED */ 392 static int 393 mvgbec_match(device_t parent, cfdata_t match, void *aux) 394 { 395 struct marvell_attach_args *mva = aux; 396 int i; 397 398 if (strcmp(mva->mva_name, match->cf_name) != 0) 399 return 0; 400 if (mva->mva_offset == MVA_OFFSET_DEFAULT) 401 return 0; 402 403 for (i = 0; i < __arraycount(mvgbe_ports); i++) 404 if (mva->mva_model == mvgbe_ports[i].model) { 405 mva->mva_size = MVGBE_SIZE; 406 return 1; 407 } 408 return 0; 409 } 410 411 /* ARGSUSED */ 412 static void 413 mvgbec_attach(device_t parent, device_t self, void *aux) 414 { 415 struct mvgbec_softc *csc = device_private(self); 416 struct marvell_attach_args *mva = aux, gbea; 417 struct mvgbe_softc *port; 418 struct mii_softc *mii; 419 device_t child; 420 uint32_t phyaddr; 421 int i, j; 422 423 aprint_naive("\n"); 424 aprint_normal(": Marvell Gigabit Ethernet Controller\n"); 425 426 csc->sc_dev = self; 427 csc->sc_iot = mva->mva_iot; 428 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset, 429 mva->mva_size, &csc->sc_ioh)) { 430 aprint_error_dev(self, "Cannot map registers\n"); 431 return; 432 } 433 434 if (mvgbec0 == NULL) 435 mvgbec0 = self; 436 437 phyaddr = 0; 438 MVGBE_WRITE(csc, MVGBE_PHYADDR, phyaddr); 439 440 mutex_init(&csc->sc_mtx, MUTEX_DEFAULT, IPL_NET); 441 442 /* Disable and clear Gigabit Ethernet Unit interrupts */ 443 MVGBE_WRITE(csc, MVGBE_EUIM, 0); 444 MVGBE_WRITE(csc, MVGBE_EUIC, 0); 445 446 mvgbec_wininit(csc); 447 448 memset(&gbea, 0, sizeof(gbea)); 449 for (i = 0; i < __arraycount(mvgbe_ports); i++) { 450 if (mvgbe_ports[i].model != mva->mva_model || 451 mvgbe_ports[i].unit != mva->mva_unit) 452 continue; 453 454 csc->sc_flags = mvgbe_ports[i].flags; 455 456 for (j = 0; j < mvgbe_ports[i].ports; j++) { 457 gbea.mva_name = "mvgbe"; 458 gbea.mva_model = mva->mva_model; 459 gbea.mva_iot = csc->sc_iot; 460 gbea.mva_ioh = csc->sc_ioh; 461 gbea.mva_unit = j; 462 gbea.mva_dmat = mva->mva_dmat; 463 gbea.mva_irq = mvgbe_ports[i].irqs[j]; 464 child = config_found_sm_loc(csc->sc_dev, "mvgbec", NULL, 465 &gbea, mvgbec_print, mvgbec_search); 466 if (child) { 467 port = device_private(child); 468 mii = LIST_FIRST(&port->sc_mii.mii_phys); 469 if (mii != NULL) 470 phyaddr |= MVGBE_PHYADDR_PHYAD(j, 471 mii->mii_phy); 472 } 473 } 474 break; 475 } 476 MVGBE_WRITE(csc, MVGBE_PHYADDR, phyaddr); 477 } 478 479 static int 480 mvgbec_print(void *aux, const char *pnp) 481 { 482 struct marvell_attach_args *gbea = aux; 483 484 if (pnp) 485 aprint_normal("%s at %s port %d", 486 gbea->mva_name, pnp, gbea->mva_unit); 487 else { 488 if (gbea->mva_unit != MVGBECCF_PORT_DEFAULT) 489 aprint_normal(" port %d", gbea->mva_unit); 490 if (gbea->mva_irq != MVGBECCF_IRQ_DEFAULT) 491 aprint_normal(" irq %d", gbea->mva_irq); 492 } 493 return UNCONF; 494 } 495 496 /* ARGSUSED */ 497 static int 498 mvgbec_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 499 { 500 struct marvell_attach_args *gbea = aux; 501 502 if (cf->cf_loc[MVGBECCF_PORT] == gbea->mva_unit && 503 cf->cf_loc[MVGBECCF_IRQ] != MVGBECCF_IRQ_DEFAULT) 504 gbea->mva_irq = cf->cf_loc[MVGBECCF_IRQ]; 505 506 return config_match(parent, cf, aux); 507 } 508 509 static int 510 mvgbec_miibus_readreg(device_t dev, int phy, int reg) 511 { 512 struct mvgbe_softc *sc = device_private(dev); 513 struct mvgbec_softc *csc; 514 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 515 uint32_t smi, val; 516 int i; 517 518 if (mvgbec0 == NULL) { 519 aprint_error_ifnet(ifp, "SMI mvgbec0 not found\n"); 520 return -1; 521 } 522 csc = device_private(mvgbec0); 523 524 mutex_enter(&csc->sc_mtx); 525 526 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 527 DELAY(1); 528 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 529 break; 530 } 531 if (i == MVGBE_PHY_TIMEOUT) { 532 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 533 mutex_exit(&csc->sc_mtx); 534 return -1; 535 } 536 537 smi = 538 MVGBE_SMI_PHYAD(phy) | MVGBE_SMI_REGAD(reg) | MVGBE_SMI_OPCODE_READ; 539 MVGBE_WRITE(csc, MVGBE_SMI, smi); 540 541 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 542 DELAY(1); 543 smi = MVGBE_READ(csc, MVGBE_SMI); 544 if (smi & MVGBE_SMI_READVALID) 545 break; 546 } 547 548 mutex_exit(&csc->sc_mtx); 549 550 DPRINTFN(9, ("mvgbec_miibus_readreg: i=%d, timeout=%d\n", 551 i, MVGBE_PHY_TIMEOUT)); 552 553 val = smi & MVGBE_SMI_DATA_MASK; 554 555 DPRINTFN(9, ("mvgbec_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 556 phy, reg, val)); 557 558 return val; 559 } 560 561 static void 562 mvgbec_miibus_writereg(device_t dev, int phy, int reg, int val) 563 { 564 struct mvgbe_softc *sc = device_private(dev); 565 struct mvgbec_softc *csc; 566 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 567 uint32_t smi; 568 int i; 569 570 if (mvgbec0 == NULL) { 571 aprint_error_ifnet(ifp, "SMI mvgbec0 not found\n"); 572 return; 573 } 574 csc = device_private(mvgbec0); 575 576 DPRINTFN(9, ("mvgbec_miibus_writereg phy=%d reg=%#x val=%#x\n", 577 phy, reg, val)); 578 579 mutex_enter(&csc->sc_mtx); 580 581 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 582 DELAY(1); 583 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 584 break; 585 } 586 if (i == MVGBE_PHY_TIMEOUT) { 587 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 588 mutex_exit(&csc->sc_mtx); 589 return; 590 } 591 592 smi = MVGBE_SMI_PHYAD(phy) | MVGBE_SMI_REGAD(reg) | 593 MVGBE_SMI_OPCODE_WRITE | (val & MVGBE_SMI_DATA_MASK); 594 MVGBE_WRITE(csc, MVGBE_SMI, smi); 595 596 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 597 DELAY(1); 598 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 599 break; 600 } 601 602 mutex_exit(&csc->sc_mtx); 603 604 if (i == MVGBE_PHY_TIMEOUT) 605 aprint_error_ifnet(ifp, "phy write timed out\n"); 606 } 607 608 static void 609 mvgbec_miibus_statchg(struct ifnet *ifp) 610 { 611 612 /* nothing to do */ 613 } 614 615 616 static void 617 mvgbec_wininit(struct mvgbec_softc *sc) 618 { 619 device_t pdev = device_parent(sc->sc_dev); 620 uint64_t base; 621 uint32_t en, ac, size; 622 int window, target, attr, rv, i; 623 static int tags[] = { 624 MARVELL_TAG_SDRAM_CS0, 625 MARVELL_TAG_SDRAM_CS1, 626 MARVELL_TAG_SDRAM_CS2, 627 MARVELL_TAG_SDRAM_CS3, 628 629 MARVELL_TAG_UNDEFINED, 630 }; 631 632 /* First disable all address decode windows */ 633 en = MVGBE_BARE_EN_MASK; 634 MVGBE_WRITE(sc, MVGBE_BARE, en); 635 636 ac = 0; 637 for (window = 0, i = 0; 638 tags[i] != MARVELL_TAG_UNDEFINED && window < MVGBE_NWINDOW; i++) { 639 rv = marvell_winparams_by_tag(pdev, tags[i], 640 &target, &attr, &base, &size); 641 if (rv != 0 || size == 0) 642 continue; 643 644 if (base > 0xffffffffULL) { 645 if (window >= MVGBE_NREMAP) { 646 aprint_error_dev(sc->sc_dev, 647 "can't remap window %d\n", window); 648 continue; 649 } 650 MVGBE_WRITE(sc, MVGBE_HA(window), 651 (base >> 32) & 0xffffffff); 652 } 653 654 MVGBE_WRITE(sc, MVGBE_BASEADDR(window), 655 MVGBE_BASEADDR_TARGET(target) | 656 MVGBE_BASEADDR_ATTR(attr) | 657 MVGBE_BASEADDR_BASE(base)); 658 MVGBE_WRITE(sc, MVGBE_S(window), MVGBE_S_SIZE(size)); 659 660 en &= ~(1 << window); 661 /* set full access (r/w) */ 662 ac |= MVGBE_EPAP_EPAR(window, MVGBE_EPAP_AC_FA); 663 window++; 664 } 665 /* allow to access decode window */ 666 MVGBE_WRITE(sc, MVGBE_EPAP, ac); 667 668 MVGBE_WRITE(sc, MVGBE_BARE, en); 669 } 670 671 672 /* ARGSUSED */ 673 static int 674 mvgbe_match(device_t parent, cfdata_t match, void *aux) 675 { 676 struct marvell_attach_args *mva = aux; 677 uint32_t pbase, maddrh, maddrl; 678 679 pbase = MVGBE_PORTR_BASE + mva->mva_unit * MVGBE_PORTR_SIZE; 680 maddrh = 681 bus_space_read_4(mva->mva_iot, mva->mva_ioh, pbase + MVGBE_MACAH); 682 maddrl = 683 bus_space_read_4(mva->mva_iot, mva->mva_ioh, pbase + MVGBE_MACAL); 684 if ((maddrh | maddrl) == 0) 685 return 0; 686 687 return 1; 688 } 689 690 /* ARGSUSED */ 691 static void 692 mvgbe_attach(device_t parent, device_t self, void *aux) 693 { 694 struct mvgbec_softc *csc = device_private(parent); 695 struct mvgbe_softc *sc = device_private(self); 696 struct marvell_attach_args *mva = aux; 697 struct mvgbe_txmap_entry *entry; 698 struct ifnet *ifp; 699 bus_dma_segment_t seg; 700 bus_dmamap_t dmamap; 701 int rseg, i; 702 uint32_t maddrh, maddrl; 703 void *kva; 704 705 aprint_naive("\n"); 706 aprint_normal("\n"); 707 708 sc->sc_dev = self; 709 sc->sc_port = mva->mva_unit; 710 sc->sc_iot = mva->mva_iot; 711 callout_init(&sc->sc_tick_ch, 0); 712 callout_setfunc(&sc->sc_tick_ch, mvgbe_tick, sc); 713 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 714 MVGBE_PORTR_BASE + mva->mva_unit * MVGBE_PORTR_SIZE, 715 MVGBE_PORTR_SIZE, &sc->sc_ioh)) { 716 aprint_error_dev(self, "Cannot map registers\n"); 717 return; 718 } 719 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 720 MVGBE_PORTDAFR_BASE + mva->mva_unit * MVGBE_PORTDAFR_SIZE, 721 MVGBE_PORTDAFR_SIZE, &sc->sc_dafh)) { 722 aprint_error_dev(self, 723 "Cannot map destination address filter registers\n"); 724 return; 725 } 726 sc->sc_dmat = mva->mva_dmat; 727 728 if (csc->sc_flags & FLAGS_HAS_PV) { 729 /* GbE port has Port Version register. */ 730 sc->sc_version = MVGBE_READ(sc, MVGBE_PV); 731 aprint_normal_dev(self, "Port Version 0x%x\n", sc->sc_version); 732 } 733 734 if (sc->sc_version >= 0x10) { 735 /* 736 * Armada XP 737 */ 738 739 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 740 MVGBE_PS0, sizeof(uint32_t), &sc->sc_linkup.ioh)) { 741 aprint_error_dev(self, "Cannot map linkup register\n"); 742 return; 743 } 744 sc->sc_linkup.bit = MVGBE_PS0_LINKUP; 745 csc->sc_flags |= FLAGS_IPG2; 746 } else { 747 if (bus_space_subregion(mva->mva_iot, sc->sc_ioh, 748 MVGBE_PS, sizeof(uint32_t), &sc->sc_linkup.ioh)) { 749 aprint_error_dev(self, "Cannot map linkup register\n"); 750 return; 751 } 752 sc->sc_linkup.bit = MVGBE_PS_LINKUP; 753 } 754 755 maddrh = MVGBE_READ(sc, MVGBE_MACAH); 756 maddrl = MVGBE_READ(sc, MVGBE_MACAL); 757 sc->sc_enaddr[0] = maddrh >> 24; 758 sc->sc_enaddr[1] = maddrh >> 16; 759 sc->sc_enaddr[2] = maddrh >> 8; 760 sc->sc_enaddr[3] = maddrh >> 0; 761 sc->sc_enaddr[4] = maddrl >> 8; 762 sc->sc_enaddr[5] = maddrl >> 0; 763 aprint_normal_dev(self, "Ethernet address %s\n", 764 ether_sprintf(sc->sc_enaddr)); 765 766 /* clear all ethernet port interrupts */ 767 MVGBE_WRITE(sc, MVGBE_IC, 0); 768 MVGBE_WRITE(sc, MVGBE_ICE, 0); 769 770 marvell_intr_establish(mva->mva_irq, IPL_NET, mvgbe_intr, sc); 771 772 /* Allocate the descriptor queues. */ 773 if (bus_dmamem_alloc(sc->sc_dmat, sizeof(struct mvgbe_ring_data), 774 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 775 aprint_error_dev(self, "can't alloc rx buffers\n"); 776 return; 777 } 778 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, 779 sizeof(struct mvgbe_ring_data), &kva, BUS_DMA_NOWAIT)) { 780 aprint_error_dev(self, "can't map dma buffers (%lu bytes)\n", 781 (u_long)sizeof(struct mvgbe_ring_data)); 782 goto fail1; 783 } 784 if (bus_dmamap_create(sc->sc_dmat, sizeof(struct mvgbe_ring_data), 1, 785 sizeof(struct mvgbe_ring_data), 0, BUS_DMA_NOWAIT, 786 &sc->sc_ring_map)) { 787 aprint_error_dev(self, "can't create dma map\n"); 788 goto fail2; 789 } 790 if (bus_dmamap_load(sc->sc_dmat, sc->sc_ring_map, kva, 791 sizeof(struct mvgbe_ring_data), NULL, BUS_DMA_NOWAIT)) { 792 aprint_error_dev(self, "can't load dma map\n"); 793 goto fail3; 794 } 795 for (i = 0; i < MVGBE_RX_RING_CNT; i++) 796 sc->sc_cdata.mvgbe_rx_chain[i].mvgbe_mbuf = NULL; 797 798 SIMPLEQ_INIT(&sc->sc_txmap_head); 799 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 800 sc->sc_cdata.mvgbe_tx_chain[i].mvgbe_mbuf = NULL; 801 802 if (bus_dmamap_create(sc->sc_dmat, 803 MVGBE_JLEN, MVGBE_NTXSEG, MVGBE_JLEN, 0, 804 BUS_DMA_NOWAIT, &dmamap)) { 805 aprint_error_dev(self, "Can't create TX dmamap\n"); 806 goto fail4; 807 } 808 809 entry = kmem_alloc(sizeof(*entry), KM_SLEEP); 810 if (!entry) { 811 aprint_error_dev(self, "Can't alloc txmap entry\n"); 812 bus_dmamap_destroy(sc->sc_dmat, dmamap); 813 goto fail4; 814 } 815 entry->dmamap = dmamap; 816 SIMPLEQ_INSERT_HEAD(&sc->sc_txmap_head, entry, link); 817 } 818 819 sc->sc_rdata = (struct mvgbe_ring_data *)kva; 820 memset(sc->sc_rdata, 0, sizeof(struct mvgbe_ring_data)); 821 822 /* 823 * We can support 802.1Q VLAN-sized frames and jumbo 824 * Ethernet frames. 825 */ 826 sc->sc_ethercom.ec_capabilities |= 827 ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU; 828 829 /* Try to allocate memory for jumbo buffers. */ 830 if (mvgbe_alloc_jumbo_mem(sc)) { 831 aprint_error_dev(self, "jumbo buffer allocation failed\n"); 832 goto fail4; 833 } 834 835 ifp = &sc->sc_ethercom.ec_if; 836 ifp->if_softc = sc; 837 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 838 ifp->if_start = mvgbe_start; 839 ifp->if_ioctl = mvgbe_ioctl; 840 ifp->if_init = mvgbe_init; 841 ifp->if_stop = mvgbe_stop; 842 ifp->if_watchdog = mvgbe_watchdog; 843 /* 844 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 845 */ 846 sc->sc_ethercom.ec_if.if_capabilities |= 847 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 848 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 849 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 850 /* 851 * But, IPv6 packets in the stream can cause incorrect TCPv4 Tx sums. 852 */ 853 sc->sc_ethercom.ec_if.if_capabilities &= ~IFCAP_CSUM_TCPv4_Tx; 854 IFQ_SET_MAXLEN(&ifp->if_snd, max(MVGBE_TX_RING_CNT - 1, IFQ_MAXLEN)); 855 IFQ_SET_READY(&ifp->if_snd); 856 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 857 858 mvgbe_stop(ifp, 0); 859 860 /* 861 * Do MII setup. 862 */ 863 sc->sc_mii.mii_ifp = ifp; 864 sc->sc_mii.mii_readreg = mvgbec_miibus_readreg; 865 sc->sc_mii.mii_writereg = mvgbec_miibus_writereg; 866 sc->sc_mii.mii_statchg = mvgbec_miibus_statchg; 867 868 sc->sc_ethercom.ec_mii = &sc->sc_mii; 869 ifmedia_init(&sc->sc_mii.mii_media, 0, 870 mvgbe_mediachange, mvgbe_mediastatus); 871 mii_attach(self, &sc->sc_mii, 0xffffffff, 872 MII_PHY_ANY, parent == mvgbec0 ? 0 : 1, 0); 873 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 874 aprint_error_dev(self, "no PHY found!\n"); 875 ifmedia_add(&sc->sc_mii.mii_media, 876 IFM_ETHER|IFM_MANUAL, 0, NULL); 877 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 878 } else 879 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 880 881 /* 882 * Call MI attach routines. 883 */ 884 if_attach(ifp); 885 886 ether_ifattach(ifp, sc->sc_enaddr); 887 ether_set_ifflags_cb(&sc->sc_ethercom, mvgbe_ifflags_cb); 888 889 sysctl_mvgbe_init(sc); 890 #ifdef MVGBE_EVENT_COUNTERS 891 /* Attach event counters. */ 892 evcnt_attach_dynamic(&sc->sc_ev_rxoverrun, EVCNT_TYPE_MISC, 893 NULL, device_xname(sc->sc_dev), "rxoverrrun"); 894 evcnt_attach_dynamic(&sc->sc_ev_wdogsoft, EVCNT_TYPE_MISC, 895 NULL, device_xname(sc->sc_dev), "wdogsoft"); 896 #endif 897 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 898 RND_TYPE_NET, 0); 899 900 return; 901 902 fail4: 903 while ((entry = SIMPLEQ_FIRST(&sc->sc_txmap_head)) != NULL) { 904 SIMPLEQ_REMOVE_HEAD(&sc->sc_txmap_head, link); 905 bus_dmamap_destroy(sc->sc_dmat, entry->dmamap); 906 } 907 bus_dmamap_unload(sc->sc_dmat, sc->sc_ring_map); 908 fail3: 909 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ring_map); 910 fail2: 911 bus_dmamem_unmap(sc->sc_dmat, kva, sizeof(struct mvgbe_ring_data)); 912 fail1: 913 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 914 return; 915 } 916 917 static int 918 mvgbe_ipginttx(struct mvgbec_softc *csc, struct mvgbe_softc *sc, 919 unsigned int ipginttx) 920 { 921 uint32_t reg; 922 reg = MVGBE_READ(sc, MVGBE_PTFUT); 923 924 if (csc->sc_flags & FLAGS_IPG2) { 925 if (ipginttx > MVGBE_PTFUT_IPGINTTX_V2_MAX) 926 return -1; 927 reg &= ~MVGBE_PTFUT_IPGINTTX_V2_MASK; 928 reg |= MVGBE_PTFUT_IPGINTTX_V2(ipginttx); 929 } else if (csc->sc_flags & FLAGS_IPG1) { 930 if (ipginttx > MVGBE_PTFUT_IPGINTTX_V1_MAX) 931 return -1; 932 reg &= ~MVGBE_PTFUT_IPGINTTX_V1_MASK; 933 reg |= MVGBE_PTFUT_IPGINTTX_V1(ipginttx); 934 } 935 MVGBE_WRITE(sc, MVGBE_PTFUT, reg); 936 937 return 0; 938 } 939 940 static int 941 mvgbe_ipgintrx(struct mvgbec_softc *csc, struct mvgbe_softc *sc, 942 unsigned int ipgintrx) 943 { 944 uint32_t reg; 945 reg = MVGBE_READ(sc, MVGBE_SDC); 946 947 if (csc->sc_flags & FLAGS_IPG2) { 948 if (ipgintrx > MVGBE_SDC_IPGINTRX_V2_MAX) 949 return -1; 950 reg &= ~MVGBE_SDC_IPGINTRX_V2_MASK; 951 reg |= MVGBE_SDC_IPGINTRX_V2(ipgintrx); 952 } else if (csc->sc_flags & FLAGS_IPG1) { 953 if (ipgintrx > MVGBE_SDC_IPGINTRX_V1_MAX) 954 return -1; 955 reg &= ~MVGBE_SDC_IPGINTRX_V1_MASK; 956 reg |= MVGBE_SDC_IPGINTRX_V1(ipgintrx); 957 } 958 MVGBE_WRITE(sc, MVGBE_SDC, reg); 959 960 return 0; 961 } 962 963 static void 964 mvgbe_tick(void *arg) 965 { 966 struct mvgbe_softc *sc = arg; 967 struct mii_data *mii = &sc->sc_mii; 968 int s; 969 970 s = splnet(); 971 mii_tick(mii); 972 /* Need more work */ 973 MVGBE_EVCNT_ADD(&sc->sc_ev_rxoverrun, MVGBE_READ(sc, MVGBE_POFC)); 974 splx(s); 975 976 callout_schedule(&sc->sc_tick_ch, hz); 977 } 978 979 static int 980 mvgbe_intr(void *arg) 981 { 982 struct mvgbe_softc *sc = arg; 983 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 984 uint32_t ic, ice, datum = 0; 985 int claimed = 0; 986 987 for (;;) { 988 ice = MVGBE_READ(sc, MVGBE_ICE); 989 ic = MVGBE_READ(sc, MVGBE_IC); 990 991 DPRINTFN(3, ("mvgbe_intr: ic=%#x, ice=%#x\n", ic, ice)); 992 if (ic == 0 && ice == 0) 993 break; 994 995 datum = datum ^ ic ^ ice; 996 997 MVGBE_WRITE(sc, MVGBE_IC, ~ic); 998 MVGBE_WRITE(sc, MVGBE_ICE, ~ice); 999 1000 claimed = 1; 1001 1002 if (!(ifp->if_flags & IFF_RUNNING)) 1003 break; 1004 1005 if (ice & MVGBE_ICE_LINKCHG) { 1006 if (MVGBE_IS_LINKUP(sc)) { 1007 /* Enable port RX and TX. */ 1008 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_ENQ(0)); 1009 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0)); 1010 } else { 1011 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_DISQ(0)); 1012 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ(0)); 1013 } 1014 1015 /* Notify link change event to mii layer */ 1016 mii_pollstat(&sc->sc_mii); 1017 } 1018 1019 if (ic & (MVGBE_IC_RXBUF | MVGBE_IC_RXERROR)) 1020 mvgbe_rxeof(sc); 1021 1022 if (ice & (MVGBE_ICE_TXBUF_MASK | MVGBE_ICE_TXERR_MASK)) 1023 mvgbe_txeof(sc); 1024 } 1025 1026 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1027 mvgbe_start(ifp); 1028 1029 rnd_add_uint32(&sc->sc_rnd_source, datum); 1030 1031 return claimed; 1032 } 1033 1034 static void 1035 mvgbe_start(struct ifnet *ifp) 1036 { 1037 struct mvgbe_softc *sc = ifp->if_softc; 1038 struct mbuf *m_head = NULL; 1039 uint32_t idx = sc->sc_cdata.mvgbe_tx_prod; 1040 int pkts = 0; 1041 1042 DPRINTFN(3, ("mvgbe_start (idx %d, tx_chain[idx] %p)\n", idx, 1043 sc->sc_cdata.mvgbe_tx_chain[idx].mvgbe_mbuf)); 1044 1045 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1046 return; 1047 /* If Link is DOWN, can't start TX */ 1048 if (!MVGBE_IS_LINKUP(sc)) 1049 return; 1050 1051 while (sc->sc_cdata.mvgbe_tx_chain[idx].mvgbe_mbuf == NULL) { 1052 IFQ_POLL(&ifp->if_snd, m_head); 1053 if (m_head == NULL) 1054 break; 1055 1056 /* 1057 * Pack the data into the transmit ring. If we 1058 * don't have room, set the OACTIVE flag and wait 1059 * for the NIC to drain the ring. 1060 */ 1061 if (mvgbe_encap(sc, m_head, &idx)) { 1062 ifp->if_flags |= IFF_OACTIVE; 1063 break; 1064 } 1065 1066 /* now we are committed to transmit the packet */ 1067 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1068 pkts++; 1069 1070 /* 1071 * If there's a BPF listener, bounce a copy of this frame 1072 * to him. 1073 */ 1074 bpf_mtap(ifp, m_head); 1075 } 1076 if (pkts == 0) 1077 return; 1078 1079 /* Transmit at Queue 0 */ 1080 if (idx != sc->sc_cdata.mvgbe_tx_prod) { 1081 sc->sc_cdata.mvgbe_tx_prod = idx; 1082 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0)); 1083 1084 /* 1085 * Set a timeout in case the chip goes out to lunch. 1086 */ 1087 ifp->if_timer = 1; 1088 sc->sc_wdogsoft = 1; 1089 } 1090 } 1091 1092 static int 1093 mvgbe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1094 { 1095 struct mvgbe_softc *sc = ifp->if_softc; 1096 struct ifreq *ifr = data; 1097 int s, error = 0; 1098 1099 s = splnet(); 1100 1101 switch (cmd) { 1102 case SIOCGIFMEDIA: 1103 case SIOCSIFMEDIA: 1104 DPRINTFN(2, ("mvgbe_ioctl MEDIA\n")); 1105 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1106 break; 1107 default: 1108 DPRINTFN(2, ("mvgbe_ioctl ETHER\n")); 1109 error = ether_ioctl(ifp, cmd, data); 1110 if (error == ENETRESET) { 1111 if (ifp->if_flags & IFF_RUNNING) { 1112 mvgbe_filter_setup(sc); 1113 } 1114 error = 0; 1115 } 1116 break; 1117 } 1118 1119 splx(s); 1120 1121 return error; 1122 } 1123 1124 static int 1125 mvgbe_init(struct ifnet *ifp) 1126 { 1127 struct mvgbe_softc *sc = ifp->if_softc; 1128 struct mvgbec_softc *csc = device_private(device_parent(sc->sc_dev)); 1129 struct mii_data *mii = &sc->sc_mii; 1130 uint32_t reg; 1131 int i; 1132 1133 DPRINTFN(2, ("mvgbe_init\n")); 1134 1135 /* Cancel pending I/O and free all RX/TX buffers. */ 1136 mvgbe_stop(ifp, 0); 1137 1138 /* clear all ethernet port interrupts */ 1139 MVGBE_WRITE(sc, MVGBE_IC, 0); 1140 MVGBE_WRITE(sc, MVGBE_ICE, 0); 1141 1142 /* Init TX/RX descriptors */ 1143 if (mvgbe_init_tx_ring(sc) == ENOBUFS) { 1144 aprint_error_ifnet(ifp, 1145 "initialization failed: no memory for tx buffers\n"); 1146 return ENOBUFS; 1147 } 1148 if (mvgbe_init_rx_ring(sc) == ENOBUFS) { 1149 aprint_error_ifnet(ifp, 1150 "initialization failed: no memory for rx buffers\n"); 1151 return ENOBUFS; 1152 } 1153 1154 if ((csc->sc_flags & FLAGS_IPG1) || (csc->sc_flags & FLAGS_IPG2)) { 1155 sc->sc_ipginttx = MVGBE_IPGINTTX_DEFAULT; 1156 sc->sc_ipgintrx = MVGBE_IPGINTRX_DEFAULT; 1157 } 1158 if (csc->sc_flags & FLAGS_FIX_MTU) 1159 MVGBE_WRITE(sc, MVGBE_MTU, 0); /* hw reset value is wrong */ 1160 if (sc->sc_version >= 0x10) { 1161 MVGBE_WRITE(csc, MVGBE_PANC, 1162 MVGBE_PANC_FORCELINKPASS | 1163 MVGBE_PANC_INBANDANBYPASSEN | 1164 MVGBE_PANC_SETMIISPEED | 1165 MVGBE_PANC_SETGMIISPEED | 1166 MVGBE_PANC_ANSPEEDEN | 1167 MVGBE_PANC_SETFCEN | 1168 MVGBE_PANC_PAUSEADV | 1169 MVGBE_PANC_SETFULLDX | 1170 MVGBE_PANC_ANDUPLEXEN | 1171 MVGBE_PANC_RESERVED); 1172 MVGBE_WRITE(csc, MVGBE_PMACC0, 1173 MVGBE_PMACC0_RESERVED | 1174 MVGBE_PMACC0_FRAMESIZELIMIT(1600)); 1175 MVGBE_WRITE(csc, MVGBE_PMACC2, 1176 MVGBE_PMACC2_PCSEN | 1177 MVGBE_PMACC2_RESERVED | 1178 MVGBE_PMACC2_RGMIIEN); 1179 1180 MVGBE_WRITE(sc, MVGBE_PXCX, 1181 MVGBE_READ(sc, MVGBE_PXCX) & ~MVGBE_PXCX_TXCRCDIS); 1182 1183 #ifndef MULTIPROCESSOR 1184 MVGBE_WRITE(sc, MVGBE_PACC, MVGVE_PACC_ACCELERATIONMODE_BM); 1185 #else 1186 MVGBE_WRITE(sc, MVGBE_PACC, MVGVE_PACC_ACCELERATIONMODE_EDM); 1187 #endif 1188 } else { 1189 MVGBE_WRITE(sc, MVGBE_PSC, 1190 MVGBE_PSC_ANFC | /* Enable Auto-Neg Flow Ctrl */ 1191 MVGBE_PSC_RESERVED | /* Must be set to 1 */ 1192 MVGBE_PSC_FLFAIL | /* Do NOT Force Link Fail */ 1193 MVGBE_PSC_MRU(MVGBE_PSC_MRU_9022) | /* we want 9k */ 1194 MVGBE_PSC_SETFULLDX); /* Set_FullDx */ 1195 /* XXXX: mvgbe(4) always use RGMII. */ 1196 MVGBE_WRITE(sc, MVGBE_PSC1, 1197 MVGBE_READ(sc, MVGBE_PSC1) | MVGBE_PSC1_RGMIIEN); 1198 /* XXXX: Also always Weighted Round-Robin Priority Mode */ 1199 MVGBE_WRITE(sc, MVGBE_TQFPC, MVGBE_TQFPC_EN(0)); 1200 1201 sc->sc_cmdsts_opts = MVGBE_TX_GENERATE_CRC; 1202 } 1203 1204 MVGBE_WRITE(sc, MVGBE_CRDP(0), MVGBE_RX_RING_ADDR(sc, 0)); 1205 MVGBE_WRITE(sc, MVGBE_TCQDP, MVGBE_TX_RING_ADDR(sc, 0)); 1206 1207 if (csc->sc_flags & FLAGS_FIX_TQTB) { 1208 /* 1209 * Queue 0 (offset 0x72700) must be programmed to 0x3fffffff. 1210 * And offset 0x72704 must be programmed to 0x03ffffff. 1211 * Queue 1 through 7 must be programmed to 0x0. 1212 */ 1213 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(0), 0x3fffffff); 1214 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(0), 0x03ffffff); 1215 for (i = 1; i < 8; i++) { 1216 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x0); 1217 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0x0); 1218 } 1219 } else if (sc->sc_version < 0x10) 1220 for (i = 1; i < 8; i++) { 1221 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x3fffffff); 1222 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0xffff7fff); 1223 MVGBE_WRITE(sc, MVGBE_TQAC(i), 0xfc0000ff); 1224 } 1225 1226 MVGBE_WRITE(sc, MVGBE_PXC, MVGBE_PXC_RXCS); 1227 MVGBE_WRITE(sc, MVGBE_PXCX, 0); 1228 1229 /* Set SDC register except IPGINT bits */ 1230 MVGBE_WRITE(sc, MVGBE_SDC, 1231 MVGBE_SDC_RXBSZ_16_64BITWORDS | 1232 #if BYTE_ORDER == LITTLE_ENDIAN 1233 MVGBE_SDC_BLMR | /* Big/Little Endian Receive Mode: No swap */ 1234 MVGBE_SDC_BLMT | /* Big/Little Endian Transmit Mode: No swap */ 1235 #endif 1236 MVGBE_SDC_TXBSZ_16_64BITWORDS); 1237 /* And then set IPGINT bits */ 1238 mvgbe_ipgintrx(csc, sc, sc->sc_ipgintrx); 1239 1240 /* Tx side */ 1241 MVGBE_WRITE(sc, MVGBE_PTFUT, 0); 1242 mvgbe_ipginttx(csc, sc, sc->sc_ipginttx); 1243 1244 mvgbe_filter_setup(sc); 1245 1246 mii_mediachg(mii); 1247 1248 /* Enable port */ 1249 if (sc->sc_version >= 0x10) { 1250 reg = MVGBE_READ(csc, MVGBE_PMACC0); 1251 MVGBE_WRITE(csc, MVGBE_PMACC0, reg | MVGBE_PMACC0_PORTEN); 1252 } else { 1253 reg = MVGBE_READ(sc, MVGBE_PSC); 1254 MVGBE_WRITE(sc, MVGBE_PSC, reg | MVGBE_PSC_PORTEN); 1255 } 1256 1257 /* If Link is UP, Start RX and TX traffic */ 1258 if (MVGBE_IS_LINKUP(sc)) { 1259 /* Enable port RX/TX. */ 1260 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_ENQ(0)); 1261 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0)); 1262 } 1263 1264 /* Enable interrupt masks */ 1265 MVGBE_WRITE(sc, MVGBE_PIM, 1266 MVGBE_IC_RXBUF | 1267 MVGBE_IC_EXTEND | 1268 MVGBE_IC_RXBUFQ_MASK | 1269 MVGBE_IC_RXERROR | 1270 MVGBE_IC_RXERRQ_MASK); 1271 MVGBE_WRITE(sc, MVGBE_PEIM, 1272 MVGBE_ICE_TXBUF_MASK | 1273 MVGBE_ICE_TXERR_MASK | 1274 MVGBE_ICE_LINKCHG); 1275 1276 callout_schedule(&sc->sc_tick_ch, hz); 1277 1278 ifp->if_flags |= IFF_RUNNING; 1279 ifp->if_flags &= ~IFF_OACTIVE; 1280 1281 return 0; 1282 } 1283 1284 /* ARGSUSED */ 1285 static void 1286 mvgbe_stop(struct ifnet *ifp, int disable) 1287 { 1288 struct mvgbe_softc *sc = ifp->if_softc; 1289 struct mvgbec_softc *csc = device_private(device_parent(sc->sc_dev)); 1290 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1291 uint32_t reg, txinprog, txfifoemp; 1292 int i, cnt; 1293 1294 DPRINTFN(2, ("mvgbe_stop\n")); 1295 1296 callout_stop(&sc->sc_tick_ch); 1297 1298 /* Stop Rx port activity. Check port Rx activity. */ 1299 reg = MVGBE_READ(sc, MVGBE_RQC); 1300 if (reg & MVGBE_RQC_ENQ_MASK) 1301 /* Issue stop command for active channels only */ 1302 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_DISQ_DISABLE(reg)); 1303 1304 /* Stop Tx port activity. Check port Tx activity. */ 1305 if (MVGBE_READ(sc, MVGBE_TQC) & MVGBE_TQC_ENQ(0)) 1306 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ(0)); 1307 1308 /* Force link down */ 1309 if (sc->sc_version >= 0x10) { 1310 reg = MVGBE_READ(csc, MVGBE_PANC); 1311 MVGBE_WRITE(csc, MVGBE_PANC, reg | MVGBE_PANC_FORCELINKFAIL); 1312 1313 txinprog = MVGBE_PS_TXINPROG_(0); 1314 txfifoemp = MVGBE_PS_TXFIFOEMP_(0); 1315 } else { 1316 reg = MVGBE_READ(sc, MVGBE_PSC); 1317 MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_FLFAIL); 1318 1319 txinprog = MVGBE_PS_TXINPROG; 1320 txfifoemp = MVGBE_PS_TXFIFOEMP; 1321 } 1322 1323 #define RX_DISABLE_TIMEOUT 0x1000000 1324 #define TX_FIFO_EMPTY_TIMEOUT 0x1000000 1325 /* Wait for all Rx activity to terminate. */ 1326 cnt = 0; 1327 do { 1328 if (cnt >= RX_DISABLE_TIMEOUT) { 1329 aprint_error_ifnet(ifp, 1330 "timeout for RX stopped. rqc 0x%x\n", reg); 1331 break; 1332 } 1333 cnt++; 1334 1335 /* 1336 * Check Receive Queue Command register that all Rx queues 1337 * are stopped 1338 */ 1339 reg = MVGBE_READ(sc, MVGBE_RQC); 1340 } while (reg & 0xff); 1341 1342 /* Double check to verify that TX FIFO is empty */ 1343 cnt = 0; 1344 while (1) { 1345 do { 1346 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) { 1347 aprint_error_ifnet(ifp, 1348 "timeout for TX FIFO empty. status 0x%x\n", 1349 reg); 1350 break; 1351 } 1352 cnt++; 1353 1354 reg = MVGBE_READ(sc, MVGBE_PS); 1355 } while (!(reg & txfifoemp) || reg & txinprog); 1356 1357 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) 1358 break; 1359 1360 /* Double check */ 1361 reg = MVGBE_READ(sc, MVGBE_PS); 1362 if (reg & txfifoemp && !(reg & txinprog)) 1363 break; 1364 else 1365 aprint_error_ifnet(ifp, 1366 "TX FIFO empty double check failed." 1367 " %d loops, status 0x%x\n", cnt, reg); 1368 } 1369 1370 /* Reset the Enable bit */ 1371 if (sc->sc_version >= 0x10) { 1372 reg = MVGBE_READ(csc, MVGBE_PMACC0); 1373 MVGBE_WRITE(csc, MVGBE_PMACC0, reg & ~MVGBE_PMACC0_PORTEN); 1374 } else { 1375 reg = MVGBE_READ(sc, MVGBE_PSC); 1376 MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_PORTEN); 1377 } 1378 1379 /* 1380 * Disable and clear interrupts 1381 * 0) controller interrupt 1382 * 1) port interrupt cause 1383 * 2) port interrupt mask 1384 */ 1385 MVGBE_WRITE(csc, MVGBE_EUIM, 0); 1386 MVGBE_WRITE(csc, MVGBE_EUIC, 0); 1387 MVGBE_WRITE(sc, MVGBE_IC, 0); 1388 MVGBE_WRITE(sc, MVGBE_ICE, 0); 1389 MVGBE_WRITE(sc, MVGBE_PIM, 0); 1390 MVGBE_WRITE(sc, MVGBE_PEIM, 0); 1391 1392 /* Free RX and TX mbufs still in the queues. */ 1393 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1394 if (cdata->mvgbe_rx_chain[i].mvgbe_mbuf != NULL) { 1395 m_freem(cdata->mvgbe_rx_chain[i].mvgbe_mbuf); 1396 cdata->mvgbe_rx_chain[i].mvgbe_mbuf = NULL; 1397 } 1398 } 1399 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 1400 if (cdata->mvgbe_tx_chain[i].mvgbe_mbuf != NULL) { 1401 m_freem(cdata->mvgbe_tx_chain[i].mvgbe_mbuf); 1402 cdata->mvgbe_tx_chain[i].mvgbe_mbuf = NULL; 1403 } 1404 } 1405 1406 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1407 } 1408 1409 static void 1410 mvgbe_watchdog(struct ifnet *ifp) 1411 { 1412 struct mvgbe_softc *sc = ifp->if_softc; 1413 1414 /* 1415 * Reclaim first as there is a possibility of losing Tx completion 1416 * interrupts. 1417 */ 1418 mvgbe_txeof(sc); 1419 if (sc->sc_cdata.mvgbe_tx_cnt != 0) { 1420 if (sc->sc_wdogsoft) { 1421 /* 1422 * There is race condition between CPU and DMA 1423 * engine. When DMA engine encounters queue end, 1424 * it clears MVGBE_TQC_ENQ bit. 1425 */ 1426 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0)); 1427 ifp->if_timer = 5; 1428 sc->sc_wdogsoft = 0; 1429 MVGBE_EVCNT_INCR(&sc->sc_ev_wdogsoft); 1430 } else { 1431 aprint_error_ifnet(ifp, "watchdog timeout\n"); 1432 1433 ifp->if_oerrors++; 1434 1435 mvgbe_init(ifp); 1436 } 1437 } 1438 } 1439 1440 static int 1441 mvgbe_ifflags_cb(struct ethercom *ec) 1442 { 1443 struct ifnet *ifp = &ec->ec_if; 1444 struct mvgbe_softc *sc = ifp->if_softc; 1445 int change = ifp->if_flags ^ sc->sc_if_flags; 1446 1447 if (change != 0) 1448 sc->sc_if_flags = ifp->if_flags; 1449 1450 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 1451 return ENETRESET; 1452 1453 if ((change & IFF_PROMISC) != 0) 1454 mvgbe_filter_setup(sc); 1455 1456 return 0; 1457 } 1458 1459 /* 1460 * Set media options. 1461 */ 1462 static int 1463 mvgbe_mediachange(struct ifnet *ifp) 1464 { 1465 return ether_mediachange(ifp); 1466 } 1467 1468 /* 1469 * Report current media status. 1470 */ 1471 static void 1472 mvgbe_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1473 { 1474 ether_mediastatus(ifp, ifmr); 1475 } 1476 1477 1478 static int 1479 mvgbe_init_rx_ring(struct mvgbe_softc *sc) 1480 { 1481 struct mvgbe_chain_data *cd = &sc->sc_cdata; 1482 struct mvgbe_ring_data *rd = sc->sc_rdata; 1483 int i; 1484 1485 memset(rd->mvgbe_rx_ring, 0, 1486 sizeof(struct mvgbe_rx_desc) * MVGBE_RX_RING_CNT); 1487 1488 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1489 cd->mvgbe_rx_chain[i].mvgbe_desc = 1490 &rd->mvgbe_rx_ring[i]; 1491 if (i == MVGBE_RX_RING_CNT - 1) { 1492 cd->mvgbe_rx_chain[i].mvgbe_next = 1493 &cd->mvgbe_rx_chain[0]; 1494 rd->mvgbe_rx_ring[i].nextdescptr = 1495 MVGBE_RX_RING_ADDR(sc, 0); 1496 } else { 1497 cd->mvgbe_rx_chain[i].mvgbe_next = 1498 &cd->mvgbe_rx_chain[i + 1]; 1499 rd->mvgbe_rx_ring[i].nextdescptr = 1500 MVGBE_RX_RING_ADDR(sc, i + 1); 1501 } 1502 } 1503 1504 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1505 if (mvgbe_newbuf(sc, i, NULL, 1506 sc->sc_cdata.mvgbe_rx_jumbo_map) == ENOBUFS) { 1507 aprint_error_ifnet(&sc->sc_ethercom.ec_if, 1508 "failed alloc of %dth mbuf\n", i); 1509 return ENOBUFS; 1510 } 1511 } 1512 sc->sc_cdata.mvgbe_rx_prod = 0; 1513 sc->sc_cdata.mvgbe_rx_cons = 0; 1514 1515 return 0; 1516 } 1517 1518 static int 1519 mvgbe_init_tx_ring(struct mvgbe_softc *sc) 1520 { 1521 struct mvgbe_chain_data *cd = &sc->sc_cdata; 1522 struct mvgbe_ring_data *rd = sc->sc_rdata; 1523 int i; 1524 1525 memset(sc->sc_rdata->mvgbe_tx_ring, 0, 1526 sizeof(struct mvgbe_tx_desc) * MVGBE_TX_RING_CNT); 1527 1528 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 1529 cd->mvgbe_tx_chain[i].mvgbe_desc = 1530 &rd->mvgbe_tx_ring[i]; 1531 if (i == MVGBE_TX_RING_CNT - 1) { 1532 cd->mvgbe_tx_chain[i].mvgbe_next = 1533 &cd->mvgbe_tx_chain[0]; 1534 rd->mvgbe_tx_ring[i].nextdescptr = 1535 MVGBE_TX_RING_ADDR(sc, 0); 1536 } else { 1537 cd->mvgbe_tx_chain[i].mvgbe_next = 1538 &cd->mvgbe_tx_chain[i + 1]; 1539 rd->mvgbe_tx_ring[i].nextdescptr = 1540 MVGBE_TX_RING_ADDR(sc, i + 1); 1541 } 1542 rd->mvgbe_tx_ring[i].cmdsts = MVGBE_BUFFER_OWNED_BY_HOST; 1543 } 1544 1545 sc->sc_cdata.mvgbe_tx_prod = 0; 1546 sc->sc_cdata.mvgbe_tx_cons = 0; 1547 sc->sc_cdata.mvgbe_tx_cnt = 0; 1548 1549 MVGBE_CDTXSYNC(sc, 0, MVGBE_TX_RING_CNT, 1550 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1551 1552 return 0; 1553 } 1554 1555 static int 1556 mvgbe_newbuf(struct mvgbe_softc *sc, int i, struct mbuf *m, 1557 bus_dmamap_t dmamap) 1558 { 1559 struct mbuf *m_new = NULL; 1560 struct mvgbe_chain *c; 1561 struct mvgbe_rx_desc *r; 1562 int align; 1563 vaddr_t offset; 1564 1565 if (m == NULL) { 1566 void *buf = NULL; 1567 1568 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1569 if (m_new == NULL) { 1570 aprint_error_ifnet(&sc->sc_ethercom.ec_if, 1571 "no memory for rx list -- packet dropped!\n"); 1572 return ENOBUFS; 1573 } 1574 1575 /* Allocate the jumbo buffer */ 1576 buf = mvgbe_jalloc(sc); 1577 if (buf == NULL) { 1578 m_freem(m_new); 1579 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 1580 "dropped!\n", sc->sc_ethercom.ec_if.if_xname)); 1581 return ENOBUFS; 1582 } 1583 1584 /* Attach the buffer to the mbuf */ 1585 m_new->m_len = m_new->m_pkthdr.len = MVGBE_JLEN; 1586 MEXTADD(m_new, buf, MVGBE_JLEN, 0, mvgbe_jfree, sc); 1587 } else { 1588 /* 1589 * We're re-using a previously allocated mbuf; 1590 * be sure to re-init pointers and lengths to 1591 * default values. 1592 */ 1593 m_new = m; 1594 m_new->m_len = m_new->m_pkthdr.len = MVGBE_JLEN; 1595 m_new->m_data = m_new->m_ext.ext_buf; 1596 } 1597 align = (u_long)m_new->m_data & MVGBE_RXBUF_MASK; 1598 if (align != 0) { 1599 DPRINTFN(1,("align = %d\n", align)); 1600 m_adj(m_new, MVGBE_RXBUF_ALIGN - align); 1601 } 1602 1603 c = &sc->sc_cdata.mvgbe_rx_chain[i]; 1604 r = c->mvgbe_desc; 1605 c->mvgbe_mbuf = m_new; 1606 offset = (vaddr_t)m_new->m_data - (vaddr_t)sc->sc_cdata.mvgbe_jumbo_buf; 1607 r->bufptr = dmamap->dm_segs[0].ds_addr + offset; 1608 r->bufsize = MVGBE_JLEN & ~MVGBE_RXBUF_MASK; 1609 r->cmdsts = MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_ENABLE_INTERRUPT; 1610 1611 /* Invalidate RX buffer */ 1612 bus_dmamap_sync(sc->sc_dmat, dmamap, offset, r->bufsize, 1613 BUS_DMASYNC_PREREAD); 1614 1615 MVGBE_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1616 1617 return 0; 1618 } 1619 1620 /* 1621 * Memory management for jumbo frames. 1622 */ 1623 1624 static int 1625 mvgbe_alloc_jumbo_mem(struct mvgbe_softc *sc) 1626 { 1627 char *ptr, *kva; 1628 bus_dma_segment_t seg; 1629 int i, rseg, state, error; 1630 struct mvgbe_jpool_entry *entry; 1631 1632 state = error = 0; 1633 1634 /* Grab a big chunk o' storage. */ 1635 if (bus_dmamem_alloc(sc->sc_dmat, MVGBE_JMEM, PAGE_SIZE, 0, 1636 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1637 aprint_error_dev(sc->sc_dev, "can't alloc rx buffers\n"); 1638 return ENOBUFS; 1639 } 1640 1641 state = 1; 1642 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, MVGBE_JMEM, 1643 (void **)&kva, BUS_DMA_NOWAIT)) { 1644 aprint_error_dev(sc->sc_dev, 1645 "can't map dma buffers (%d bytes)\n", MVGBE_JMEM); 1646 error = ENOBUFS; 1647 goto out; 1648 } 1649 1650 state = 2; 1651 if (bus_dmamap_create(sc->sc_dmat, MVGBE_JMEM, 1, MVGBE_JMEM, 0, 1652 BUS_DMA_NOWAIT, &sc->sc_cdata.mvgbe_rx_jumbo_map)) { 1653 aprint_error_dev(sc->sc_dev, "can't create dma map\n"); 1654 error = ENOBUFS; 1655 goto out; 1656 } 1657 1658 state = 3; 1659 if (bus_dmamap_load(sc->sc_dmat, sc->sc_cdata.mvgbe_rx_jumbo_map, 1660 kva, MVGBE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1661 aprint_error_dev(sc->sc_dev, "can't load dma map\n"); 1662 error = ENOBUFS; 1663 goto out; 1664 } 1665 1666 state = 4; 1667 sc->sc_cdata.mvgbe_jumbo_buf = (void *)kva; 1668 DPRINTFN(1,("mvgbe_jumbo_buf = %p\n", sc->sc_cdata.mvgbe_jumbo_buf)); 1669 1670 LIST_INIT(&sc->sc_jfree_listhead); 1671 LIST_INIT(&sc->sc_jinuse_listhead); 1672 1673 /* 1674 * Now divide it up into 9K pieces and save the addresses 1675 * in an array. 1676 */ 1677 ptr = sc->sc_cdata.mvgbe_jumbo_buf; 1678 for (i = 0; i < MVGBE_JSLOTS; i++) { 1679 sc->sc_cdata.mvgbe_jslots[i] = ptr; 1680 ptr += MVGBE_JLEN; 1681 entry = kmem_alloc(sizeof(struct mvgbe_jpool_entry), KM_SLEEP); 1682 if (entry == NULL) { 1683 aprint_error_dev(sc->sc_dev, 1684 "no memory for jumbo buffer queue!\n"); 1685 error = ENOBUFS; 1686 goto out; 1687 } 1688 entry->slot = i; 1689 if (i) 1690 LIST_INSERT_HEAD(&sc->sc_jfree_listhead, entry, 1691 jpool_entries); 1692 else 1693 LIST_INSERT_HEAD(&sc->sc_jinuse_listhead, entry, 1694 jpool_entries); 1695 } 1696 out: 1697 if (error != 0) { 1698 switch (state) { 1699 case 4: 1700 bus_dmamap_unload(sc->sc_dmat, 1701 sc->sc_cdata.mvgbe_rx_jumbo_map); 1702 case 3: 1703 bus_dmamap_destroy(sc->sc_dmat, 1704 sc->sc_cdata.mvgbe_rx_jumbo_map); 1705 case 2: 1706 bus_dmamem_unmap(sc->sc_dmat, kva, MVGBE_JMEM); 1707 case 1: 1708 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1709 break; 1710 default: 1711 break; 1712 } 1713 } 1714 1715 return error; 1716 } 1717 1718 /* 1719 * Allocate a jumbo buffer. 1720 */ 1721 static void * 1722 mvgbe_jalloc(struct mvgbe_softc *sc) 1723 { 1724 struct mvgbe_jpool_entry *entry; 1725 1726 entry = LIST_FIRST(&sc->sc_jfree_listhead); 1727 1728 if (entry == NULL) 1729 return NULL; 1730 1731 LIST_REMOVE(entry, jpool_entries); 1732 LIST_INSERT_HEAD(&sc->sc_jinuse_listhead, entry, jpool_entries); 1733 return sc->sc_cdata.mvgbe_jslots[entry->slot]; 1734 } 1735 1736 /* 1737 * Release a jumbo buffer. 1738 */ 1739 static void 1740 mvgbe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1741 { 1742 struct mvgbe_jpool_entry *entry; 1743 struct mvgbe_softc *sc; 1744 int i, s; 1745 1746 /* Extract the softc struct pointer. */ 1747 sc = (struct mvgbe_softc *)arg; 1748 1749 if (sc == NULL) 1750 panic("%s: can't find softc pointer!", __func__); 1751 1752 /* calculate the slot this buffer belongs to */ 1753 1754 i = ((vaddr_t)buf - (vaddr_t)sc->sc_cdata.mvgbe_jumbo_buf) / MVGBE_JLEN; 1755 1756 if ((i < 0) || (i >= MVGBE_JSLOTS)) 1757 panic("%s: asked to free buffer that we don't manage!", 1758 __func__); 1759 1760 s = splvm(); 1761 entry = LIST_FIRST(&sc->sc_jinuse_listhead); 1762 if (entry == NULL) 1763 panic("%s: buffer not in use!", __func__); 1764 entry->slot = i; 1765 LIST_REMOVE(entry, jpool_entries); 1766 LIST_INSERT_HEAD(&sc->sc_jfree_listhead, entry, jpool_entries); 1767 1768 if (__predict_true(m != NULL)) 1769 pool_cache_put(mb_cache, m); 1770 splx(s); 1771 } 1772 1773 static int 1774 mvgbe_encap(struct mvgbe_softc *sc, struct mbuf *m_head, 1775 uint32_t *txidx) 1776 { 1777 struct mvgbe_tx_desc *f = NULL; 1778 struct mvgbe_txmap_entry *entry; 1779 bus_dma_segment_t *txseg; 1780 bus_dmamap_t txmap; 1781 uint32_t first, current, last, cmdsts; 1782 int m_csumflags, i; 1783 bool needs_defrag = false; 1784 1785 DPRINTFN(3, ("mvgbe_encap\n")); 1786 1787 entry = SIMPLEQ_FIRST(&sc->sc_txmap_head); 1788 if (entry == NULL) { 1789 DPRINTFN(2, ("mvgbe_encap: no txmap available\n")); 1790 return ENOBUFS; 1791 } 1792 txmap = entry->dmamap; 1793 1794 first = current = last = *txidx; 1795 1796 /* 1797 * Preserve m_pkthdr.csum_flags here since m_head might be 1798 * updated by m_defrag() 1799 */ 1800 m_csumflags = m_head->m_pkthdr.csum_flags; 1801 1802 do_defrag: 1803 if (__predict_false(needs_defrag == true)) { 1804 /* A small unaligned segment was detected. */ 1805 struct mbuf *m_new; 1806 m_new = m_defrag(m_head, M_DONTWAIT); 1807 if (m_new == NULL) 1808 return EFBIG; 1809 m_head = m_new; 1810 } 1811 1812 /* 1813 * Start packing the mbufs in this chain into 1814 * the fragment pointers. Stop when we run out 1815 * of fragments or hit the end of the mbuf chain. 1816 */ 1817 if (bus_dmamap_load_mbuf(sc->sc_dmat, txmap, m_head, BUS_DMA_NOWAIT)) { 1818 DPRINTFN(1, ("mvgbe_encap: dmamap failed\n")); 1819 return ENOBUFS; 1820 } 1821 1822 txseg = txmap->dm_segs; 1823 1824 if (__predict_true(needs_defrag == false)) { 1825 /* 1826 * Detect rarely encountered DMA limitation. 1827 */ 1828 for (i = 0; i < txmap->dm_nsegs; i++) { 1829 if (((txseg[i].ds_addr & 7) != 0) && 1830 (txseg[i].ds_len <= 8) && 1831 (txseg[i].ds_len >= 1) 1832 ) { 1833 txseg = NULL; 1834 bus_dmamap_unload(sc->sc_dmat, txmap); 1835 needs_defrag = true; 1836 goto do_defrag; 1837 } 1838 } 1839 } 1840 1841 /* Sync the DMA map. */ 1842 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize, 1843 BUS_DMASYNC_PREWRITE); 1844 1845 if (sc->sc_cdata.mvgbe_tx_cnt + txmap->dm_nsegs >= 1846 MVGBE_TX_RING_CNT) { 1847 DPRINTFN(2, ("mvgbe_encap: too few descriptors free\n")); 1848 bus_dmamap_unload(sc->sc_dmat, txmap); 1849 return ENOBUFS; 1850 } 1851 1852 1853 DPRINTFN(2, ("mvgbe_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1854 1855 for (i = 0; i < txmap->dm_nsegs; i++) { 1856 f = &sc->sc_rdata->mvgbe_tx_ring[current]; 1857 f->bufptr = txseg[i].ds_addr; 1858 f->bytecnt = txseg[i].ds_len; 1859 if (i != 0) 1860 f->cmdsts = MVGBE_BUFFER_OWNED_BY_DMA; 1861 last = current; 1862 current = MVGBE_TX_RING_NEXT(current); 1863 } 1864 1865 cmdsts = sc->sc_cmdsts_opts; 1866 if (m_csumflags & M_CSUM_IPv4) 1867 cmdsts |= MVGBE_TX_GENERATE_IP_CHKSUM; 1868 if (m_csumflags & M_CSUM_TCPv4) 1869 cmdsts |= 1870 MVGBE_TX_GENERATE_L4_CHKSUM | MVGBE_TX_L4_TYPE_TCP; 1871 if (m_csumflags & M_CSUM_UDPv4) 1872 cmdsts |= 1873 MVGBE_TX_GENERATE_L4_CHKSUM | MVGBE_TX_L4_TYPE_UDP; 1874 if (m_csumflags & (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1875 const int iphdr_unitlen = sizeof(struct ip) / sizeof(uint32_t); 1876 1877 cmdsts |= MVGBE_TX_IP_NO_FRAG | 1878 MVGBE_TX_IP_HEADER_LEN(iphdr_unitlen); /* unit is 4B */ 1879 } 1880 if (txmap->dm_nsegs == 1) 1881 f->cmdsts = cmdsts | 1882 MVGBE_TX_ENABLE_INTERRUPT | 1883 MVGBE_TX_ZERO_PADDING | 1884 MVGBE_TX_FIRST_DESC | 1885 MVGBE_TX_LAST_DESC; 1886 else { 1887 f = &sc->sc_rdata->mvgbe_tx_ring[first]; 1888 f->cmdsts = cmdsts | MVGBE_TX_FIRST_DESC; 1889 1890 f = &sc->sc_rdata->mvgbe_tx_ring[last]; 1891 f->cmdsts = 1892 MVGBE_BUFFER_OWNED_BY_DMA | 1893 MVGBE_TX_ENABLE_INTERRUPT | 1894 MVGBE_TX_ZERO_PADDING | 1895 MVGBE_TX_LAST_DESC; 1896 1897 /* Sync descriptors except first */ 1898 MVGBE_CDTXSYNC(sc, 1899 (MVGBE_TX_RING_CNT - 1 == *txidx) ? 0 : (*txidx) + 1, 1900 txmap->dm_nsegs - 1, 1901 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1902 } 1903 1904 sc->sc_cdata.mvgbe_tx_chain[last].mvgbe_mbuf = m_head; 1905 SIMPLEQ_REMOVE_HEAD(&sc->sc_txmap_head, link); 1906 sc->sc_cdata.mvgbe_tx_map[last] = entry; 1907 1908 /* Finally, sync first descriptor */ 1909 sc->sc_rdata->mvgbe_tx_ring[first].cmdsts |= 1910 MVGBE_BUFFER_OWNED_BY_DMA; 1911 MVGBE_CDTXSYNC(sc, *txidx, 1, 1912 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1913 1914 sc->sc_cdata.mvgbe_tx_cnt += i; 1915 *txidx = current; 1916 1917 DPRINTFN(3, ("mvgbe_encap: completed successfully\n")); 1918 1919 return 0; 1920 } 1921 1922 static void 1923 mvgbe_rxeof(struct mvgbe_softc *sc) 1924 { 1925 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1926 struct mvgbe_rx_desc *cur_rx; 1927 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1928 struct mbuf *m; 1929 bus_dmamap_t dmamap; 1930 uint32_t rxstat; 1931 uint16_t bufsize; 1932 int idx, cur, total_len; 1933 1934 idx = sc->sc_cdata.mvgbe_rx_prod; 1935 1936 DPRINTFN(3, ("mvgbe_rxeof %d\n", idx)); 1937 1938 for (;;) { 1939 cur = idx; 1940 1941 /* Sync the descriptor */ 1942 MVGBE_CDRXSYNC(sc, idx, 1943 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1944 1945 cur_rx = &sc->sc_rdata->mvgbe_rx_ring[idx]; 1946 1947 if ((cur_rx->cmdsts & MVGBE_BUFFER_OWNED_MASK) == 1948 MVGBE_BUFFER_OWNED_BY_DMA) { 1949 /* Invalidate the descriptor -- it's not ready yet */ 1950 MVGBE_CDRXSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1951 sc->sc_cdata.mvgbe_rx_prod = idx; 1952 break; 1953 } 1954 #ifdef DIAGNOSTIC 1955 if ((cur_rx->cmdsts & 1956 (MVGBE_RX_LAST_DESC | MVGBE_RX_FIRST_DESC)) != 1957 (MVGBE_RX_LAST_DESC | MVGBE_RX_FIRST_DESC)) 1958 panic( 1959 "mvgbe_rxeof: buffer size is smaller than packet"); 1960 #endif 1961 1962 dmamap = sc->sc_cdata.mvgbe_rx_jumbo_map; 1963 1964 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1965 BUS_DMASYNC_POSTREAD); 1966 1967 m = cdata->mvgbe_rx_chain[idx].mvgbe_mbuf; 1968 cdata->mvgbe_rx_chain[idx].mvgbe_mbuf = NULL; 1969 total_len = cur_rx->bytecnt - ETHER_CRC_LEN; 1970 rxstat = cur_rx->cmdsts; 1971 bufsize = cur_rx->bufsize; 1972 1973 cdata->mvgbe_rx_map[idx] = NULL; 1974 1975 idx = MVGBE_RX_RING_NEXT(idx); 1976 1977 if (rxstat & MVGBE_ERROR_SUMMARY) { 1978 #if 0 1979 int err = rxstat & MVGBE_RX_ERROR_CODE_MASK; 1980 1981 if (err == MVGBE_RX_CRC_ERROR) 1982 ifp->if_ierrors++; 1983 if (err == MVGBE_RX_OVERRUN_ERROR) 1984 ifp->if_ierrors++; 1985 if (err == MVGBE_RX_MAX_FRAME_LEN_ERROR) 1986 ifp->if_ierrors++; 1987 if (err == MVGBE_RX_RESOURCE_ERROR) 1988 ifp->if_ierrors++; 1989 #else 1990 ifp->if_ierrors++; 1991 #endif 1992 mvgbe_newbuf(sc, cur, m, dmamap); 1993 continue; 1994 } 1995 1996 if (rxstat & MVGBE_RX_IP_FRAME_TYPE) { 1997 int flgs = 0; 1998 1999 /* Check IPv4 header checksum */ 2000 flgs |= M_CSUM_IPv4; 2001 if (!(rxstat & MVGBE_RX_IP_HEADER_OK)) 2002 flgs |= M_CSUM_IPv4_BAD; 2003 else if ((bufsize & MVGBE_RX_IP_FRAGMENT) == 0) { 2004 /* 2005 * Check TCPv4/UDPv4 checksum for 2006 * non-fragmented packet only. 2007 * 2008 * It seemd that sometimes 2009 * MVGBE_RX_L4_CHECKSUM_OK bit was set to 0 2010 * even if the checksum is correct and the 2011 * packet was not fragmented. So we don't set 2012 * M_CSUM_TCP_UDP_BAD even if csum bit is 0. 2013 */ 2014 2015 if (((rxstat & MVGBE_RX_L4_TYPE_MASK) == 2016 MVGBE_RX_L4_TYPE_TCP) && 2017 ((rxstat & MVGBE_RX_L4_CHECKSUM_OK) != 0)) 2018 flgs |= M_CSUM_TCPv4; 2019 else if (((rxstat & MVGBE_RX_L4_TYPE_MASK) == 2020 MVGBE_RX_L4_TYPE_UDP) && 2021 ((rxstat & MVGBE_RX_L4_CHECKSUM_OK) != 0)) 2022 flgs |= M_CSUM_UDPv4; 2023 } 2024 m->m_pkthdr.csum_flags = flgs; 2025 } 2026 2027 /* 2028 * Try to allocate a new jumbo buffer. If that 2029 * fails, copy the packet to mbufs and put the 2030 * jumbo buffer back in the ring so it can be 2031 * re-used. If allocating mbufs fails, then we 2032 * have to drop the packet. 2033 */ 2034 if (mvgbe_newbuf(sc, cur, NULL, dmamap) == ENOBUFS) { 2035 struct mbuf *m0; 2036 2037 m0 = m_devget(mtod(m, char *), total_len, 0, ifp, NULL); 2038 mvgbe_newbuf(sc, cur, m, dmamap); 2039 if (m0 == NULL) { 2040 aprint_error_ifnet(ifp, 2041 "no receive buffers available --" 2042 " packet dropped!\n"); 2043 ifp->if_ierrors++; 2044 continue; 2045 } 2046 m = m0; 2047 } else { 2048 m->m_pkthdr.rcvif = ifp; 2049 m->m_pkthdr.len = m->m_len = total_len; 2050 } 2051 2052 /* Skip on first 2byte (HW header) */ 2053 m_adj(m, MVGBE_HWHEADER_SIZE); 2054 2055 ifp->if_ipackets++; 2056 2057 bpf_mtap(ifp, m); 2058 2059 /* pass it on. */ 2060 (*ifp->if_input)(ifp, m); 2061 } 2062 } 2063 2064 static void 2065 mvgbe_txeof(struct mvgbe_softc *sc) 2066 { 2067 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 2068 struct mvgbe_tx_desc *cur_tx; 2069 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2070 struct mvgbe_txmap_entry *entry; 2071 int idx; 2072 2073 DPRINTFN(3, ("mvgbe_txeof\n")); 2074 2075 /* 2076 * Go through our tx ring and free mbufs for those 2077 * frames that have been sent. 2078 */ 2079 idx = cdata->mvgbe_tx_cons; 2080 while (idx != cdata->mvgbe_tx_prod) { 2081 MVGBE_CDTXSYNC(sc, idx, 1, 2082 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2083 2084 cur_tx = &sc->sc_rdata->mvgbe_tx_ring[idx]; 2085 #ifdef MVGBE_DEBUG 2086 if (mvgbe_debug >= 3) 2087 mvgbe_dump_txdesc(cur_tx, idx); 2088 #endif 2089 if ((cur_tx->cmdsts & MVGBE_BUFFER_OWNED_MASK) == 2090 MVGBE_BUFFER_OWNED_BY_DMA) { 2091 MVGBE_CDTXSYNC(sc, idx, 1, BUS_DMASYNC_PREREAD); 2092 break; 2093 } 2094 if (cur_tx->cmdsts & MVGBE_TX_LAST_DESC) 2095 ifp->if_opackets++; 2096 if (cur_tx->cmdsts & MVGBE_ERROR_SUMMARY) { 2097 int err = cur_tx->cmdsts & MVGBE_TX_ERROR_CODE_MASK; 2098 2099 if (err == MVGBE_TX_LATE_COLLISION_ERROR) 2100 ifp->if_collisions++; 2101 if (err == MVGBE_TX_UNDERRUN_ERROR) 2102 ifp->if_oerrors++; 2103 if (err == MVGBE_TX_EXCESSIVE_COLLISION_ERRO) 2104 ifp->if_collisions++; 2105 } 2106 if (cdata->mvgbe_tx_chain[idx].mvgbe_mbuf != NULL) { 2107 entry = cdata->mvgbe_tx_map[idx]; 2108 2109 m_freem(cdata->mvgbe_tx_chain[idx].mvgbe_mbuf); 2110 cdata->mvgbe_tx_chain[idx].mvgbe_mbuf = NULL; 2111 2112 bus_dmamap_sync(sc->sc_dmat, entry->dmamap, 0, 2113 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2114 2115 bus_dmamap_unload(sc->sc_dmat, entry->dmamap); 2116 SIMPLEQ_INSERT_TAIL(&sc->sc_txmap_head, entry, link); 2117 cdata->mvgbe_tx_map[idx] = NULL; 2118 } 2119 cdata->mvgbe_tx_cnt--; 2120 idx = MVGBE_TX_RING_NEXT(idx); 2121 } 2122 if (cdata->mvgbe_tx_cnt == 0) 2123 ifp->if_timer = 0; 2124 2125 if (cdata->mvgbe_tx_cnt < MVGBE_TX_RING_CNT - 2) 2126 ifp->if_flags &= ~IFF_OACTIVE; 2127 2128 cdata->mvgbe_tx_cons = idx; 2129 } 2130 2131 static uint8_t 2132 mvgbe_crc8(const uint8_t *data, size_t size) 2133 { 2134 int bit; 2135 uint8_t byte; 2136 uint8_t crc = 0; 2137 const uint8_t poly = 0x07; 2138 2139 while(size--) 2140 for (byte = *data++, bit = NBBY-1; bit >= 0; bit--) 2141 crc = (crc << 1) ^ ((((crc >> 7) ^ (byte >> bit)) & 1) ? poly : 0); 2142 2143 return crc; 2144 } 2145 2146 CTASSERT(MVGBE_NDFSMT == MVGBE_NDFOMT); 2147 2148 static void 2149 mvgbe_filter_setup(struct mvgbe_softc *sc) 2150 { 2151 struct ethercom *ec = &sc->sc_ethercom; 2152 struct ifnet *ifp= &sc->sc_ethercom.ec_if; 2153 struct ether_multi *enm; 2154 struct ether_multistep step; 2155 uint32_t dfut[MVGBE_NDFUT], dfsmt[MVGBE_NDFSMT], dfomt[MVGBE_NDFOMT]; 2156 uint32_t pxc; 2157 int i; 2158 const uint8_t special[ETHER_ADDR_LEN] = {0x01,0x00,0x5e,0x00,0x00,0x00}; 2159 2160 memset(dfut, 0, sizeof(dfut)); 2161 memset(dfsmt, 0, sizeof(dfsmt)); 2162 memset(dfomt, 0, sizeof(dfomt)); 2163 2164 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 2165 goto allmulti; 2166 } 2167 2168 ETHER_FIRST_MULTI(step, ec, enm); 2169 while (enm != NULL) { 2170 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2171 /* ranges are complex and somewhat rare */ 2172 goto allmulti; 2173 } 2174 /* chip handles some IPv4 multicast specially */ 2175 if (memcmp(enm->enm_addrlo, special, 5) == 0) { 2176 i = enm->enm_addrlo[5]; 2177 dfsmt[i>>2] |= 2178 MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 2179 } else { 2180 i = mvgbe_crc8(enm->enm_addrlo, ETHER_ADDR_LEN); 2181 dfomt[i>>2] |= 2182 MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 2183 } 2184 2185 ETHER_NEXT_MULTI(step, enm); 2186 } 2187 goto set; 2188 2189 allmulti: 2190 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 2191 for (i = 0; i < MVGBE_NDFSMT; i++) { 2192 dfsmt[i] = dfomt[i] = 2193 MVGBE_DF(0, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 2194 MVGBE_DF(1, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 2195 MVGBE_DF(2, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 2196 MVGBE_DF(3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 2197 } 2198 } 2199 2200 set: 2201 pxc = MVGBE_READ(sc, MVGBE_PXC); 2202 pxc &= ~MVGBE_PXC_UPM; 2203 pxc |= MVGBE_PXC_RB | MVGBE_PXC_RBIP | MVGBE_PXC_RBARP; 2204 if (ifp->if_flags & IFF_BROADCAST) { 2205 pxc &= ~(MVGBE_PXC_RB | MVGBE_PXC_RBIP | MVGBE_PXC_RBARP); 2206 } 2207 if (ifp->if_flags & IFF_PROMISC) { 2208 pxc |= MVGBE_PXC_UPM; 2209 } 2210 MVGBE_WRITE(sc, MVGBE_PXC, pxc); 2211 2212 /* Set Destination Address Filter Unicast Table */ 2213 i = sc->sc_enaddr[5] & 0xf; /* last nibble */ 2214 dfut[i>>2] = MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 2215 MVGBE_WRITE_FILTER(sc, MVGBE_DFUT, dfut, MVGBE_NDFUT); 2216 2217 /* Set Destination Address Filter Multicast Tables */ 2218 MVGBE_WRITE_FILTER(sc, MVGBE_DFSMT, dfsmt, MVGBE_NDFSMT); 2219 MVGBE_WRITE_FILTER(sc, MVGBE_DFOMT, dfomt, MVGBE_NDFOMT); 2220 } 2221 2222 #ifdef MVGBE_DEBUG 2223 static void 2224 mvgbe_dump_txdesc(struct mvgbe_tx_desc *desc, int idx) 2225 { 2226 #define DESC_PRINT(X) \ 2227 if (X) \ 2228 printf("txdesc[%d]." #X "=%#x\n", idx, X); 2229 2230 #if BYTE_ORDER == BIG_ENDIAN 2231 DESC_PRINT(desc->bytecnt); 2232 DESC_PRINT(desc->l4ichk); 2233 DESC_PRINT(desc->cmdsts); 2234 DESC_PRINT(desc->nextdescptr); 2235 DESC_PRINT(desc->bufptr); 2236 #else /* LITTLE_ENDIAN */ 2237 DESC_PRINT(desc->cmdsts); 2238 DESC_PRINT(desc->l4ichk); 2239 DESC_PRINT(desc->bytecnt); 2240 DESC_PRINT(desc->bufptr); 2241 DESC_PRINT(desc->nextdescptr); 2242 #endif 2243 #undef DESC_PRINT 2244 } 2245 #endif 2246 2247 SYSCTL_SETUP(sysctl_mvgbe, "sysctl mvgbe subtree setup") 2248 { 2249 int rc; 2250 const struct sysctlnode *node; 2251 2252 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 2253 0, CTLTYPE_NODE, "hw", NULL, 2254 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 2255 goto err; 2256 } 2257 2258 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2259 0, CTLTYPE_NODE, "mvgbe", 2260 SYSCTL_DESCR("mvgbe interface controls"), 2261 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2262 goto err; 2263 } 2264 2265 mvgbe_root_num = node->sysctl_num; 2266 return; 2267 2268 err: 2269 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2270 } 2271 2272 static void 2273 sysctl_mvgbe_init(struct mvgbe_softc *sc) 2274 { 2275 const struct sysctlnode *node; 2276 int mvgbe_nodenum; 2277 2278 if (sysctl_createv(&sc->mvgbe_clog, 0, NULL, &node, 2279 0, CTLTYPE_NODE, device_xname(sc->sc_dev), 2280 SYSCTL_DESCR("mvgbe per-controller controls"), 2281 NULL, 0, NULL, 0, CTL_HW, mvgbe_root_num, CTL_CREATE, 2282 CTL_EOL) != 0) { 2283 aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 2284 return; 2285 } 2286 mvgbe_nodenum = node->sysctl_num; 2287 2288 /* interrupt moderation sysctls */ 2289 if (sysctl_createv(&sc->mvgbe_clog, 0, NULL, &node, 2290 CTLFLAG_READWRITE, CTLTYPE_INT, "ipginttx", 2291 SYSCTL_DESCR("mvgbe TX interrupt moderation timer"), 2292 mvgbe_sysctl_ipginttx, 0, (void *)sc, 2293 0, CTL_HW, mvgbe_root_num, mvgbe_nodenum, CTL_CREATE, 2294 CTL_EOL) != 0) { 2295 aprint_normal_dev(sc->sc_dev, 2296 "couldn't create ipginttx sysctl node\n"); 2297 } 2298 if (sysctl_createv(&sc->mvgbe_clog, 0, NULL, &node, 2299 CTLFLAG_READWRITE, CTLTYPE_INT, "ipgintrx", 2300 SYSCTL_DESCR("mvgbe RX interrupt moderation timer"), 2301 mvgbe_sysctl_ipgintrx, 0, (void *)sc, 2302 0, CTL_HW, mvgbe_root_num, mvgbe_nodenum, CTL_CREATE, 2303 CTL_EOL) != 0) { 2304 aprint_normal_dev(sc->sc_dev, 2305 "couldn't create ipginttx sysctl node\n"); 2306 } 2307 } 2308 2309 static int 2310 mvgbe_sysctl_ipginttx(SYSCTLFN_ARGS) 2311 { 2312 int error; 2313 unsigned int t; 2314 struct sysctlnode node; 2315 struct mvgbec_softc *csc; 2316 struct mvgbe_softc *sc; 2317 2318 node = *rnode; 2319 sc = node.sysctl_data; 2320 csc = device_private(device_parent(sc->sc_dev)); 2321 t = sc->sc_ipginttx; 2322 node.sysctl_data = &t; 2323 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2324 if (error || newp == NULL) 2325 return error; 2326 2327 if (mvgbe_ipginttx(csc, sc, t) < 0) 2328 return EINVAL; 2329 /* 2330 * update the softc with sysctl-changed value, and mark 2331 * for hardware update 2332 */ 2333 sc->sc_ipginttx = t; 2334 2335 return 0; 2336 } 2337 2338 static int 2339 mvgbe_sysctl_ipgintrx(SYSCTLFN_ARGS) 2340 { 2341 int error; 2342 unsigned int t; 2343 struct sysctlnode node; 2344 struct mvgbec_softc *csc; 2345 struct mvgbe_softc *sc; 2346 2347 node = *rnode; 2348 sc = node.sysctl_data; 2349 csc = device_private(device_parent(sc->sc_dev)); 2350 t = sc->sc_ipgintrx; 2351 node.sysctl_data = &t; 2352 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2353 if (error || newp == NULL) 2354 return error; 2355 2356 if (mvgbe_ipgintrx(csc, sc, t) < 0) 2357 return EINVAL; 2358 /* 2359 * update the softc with sysctl-changed value, and mark 2360 * for hardware update 2361 */ 2362 sc->sc_ipgintrx = t; 2363 2364 return 0; 2365 } 2366