1 /* $NetBSD: edc_mca.c,v 1.21 2002/11/01 11:31:58 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Jaromir Dolecek. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * Driver for MCA ESDI controllers and disks conforming to IBM DASD 38 * spec. 39 * 40 * The driver was written with DASD Storage Interface Specification 41 * for MCA rev. 2.2 in hands, thanks to Scott Telford <st@epcc.ed.ac.uk>. 42 * 43 * TODO: 44 * - improve error recovery 45 * Issue soft reset on error or timeout? 46 * - test with > 1 disk (this is supported by some controllers) 47 * - test with > 1 ESDI controller in machine; shared interrupts 48 * necessary for this to work should be supported - edc_intr() specifically 49 * checks if the interrupt is for this controller 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: edc_mca.c,v 1.21 2002/11/01 11:31:58 mrg Exp $"); 54 55 #include "rnd.h" 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/errno.h> 60 #include <sys/device.h> 61 #include <sys/malloc.h> 62 #include <sys/endian.h> 63 #include <sys/disklabel.h> 64 #include <sys/disk.h> 65 #include <sys/syslog.h> 66 #include <sys/proc.h> 67 #include <sys/vnode.h> 68 #include <sys/kernel.h> 69 #include <sys/kthread.h> 70 #if NRND > 0 71 #include <sys/rnd.h> 72 #endif 73 74 #include <machine/bus.h> 75 #include <machine/intr.h> 76 77 #include <dev/mca/mcareg.h> 78 #include <dev/mca/mcavar.h> 79 #include <dev/mca/mcadevs.h> 80 81 #include <dev/mca/edcreg.h> 82 #include <dev/mca/edvar.h> 83 #include <dev/mca/edcvar.h> 84 85 #define EDC_ATTN_MAXTRIES 10000 /* How many times check for unbusy */ 86 #define EDC_MAX_CMD_RES_LEN 8 87 88 struct edc_mca_softc { 89 struct device sc_dev; 90 91 bus_space_tag_t sc_iot; 92 bus_space_handle_t sc_ioh; 93 94 /* DMA related stuff */ 95 bus_dma_tag_t sc_dmat; /* DMA tag as passed by parent */ 96 bus_dmamap_t sc_dmamap_xfer; /* transfer dma map */ 97 98 void *sc_ih; /* interrupt handle */ 99 100 int sc_flags; 101 #define DASD_QUIET 0x01 /* don't dump cmd error info */ 102 103 #define DASD_MAXDEVS 8 104 struct ed_softc *sc_ed[DASD_MAXDEVS]; 105 int sc_maxdevs; /* max number of disks attached to this 106 * controller */ 107 108 /* I/O results variables */ 109 volatile int sc_stat; 110 #define STAT_START 0 111 #define STAT_ERROR 1 112 #define STAT_DONE 2 113 volatile int sc_resblk; /* residual block count */ 114 115 /* CMD status block - only set & used in edc_intr() */ 116 u_int16_t status_block[EDC_MAX_CMD_RES_LEN]; 117 }; 118 119 int edc_mca_probe __P((struct device *, struct cfdata *, void *)); 120 void edc_mca_attach __P((struct device *, struct device *, void *)); 121 122 CFATTACH_DECL(edc_mca, sizeof(struct edc_mca_softc), 123 edc_mca_probe, edc_mca_attach, NULL, NULL); 124 125 static int edc_intr __P((void *)); 126 static void edc_dump_status_block __P((struct edc_mca_softc *, 127 u_int16_t *, int)); 128 static int edc_do_attn __P((struct edc_mca_softc *, int, int, int)); 129 static void edc_cmd_wait __P((struct edc_mca_softc *, int, int)); 130 static void edcworker __P((void *)); 131 static void edc_spawn_worker __P((void *)); 132 133 int 134 edc_mca_probe(parent, match, aux) 135 struct device *parent; 136 struct cfdata *match; 137 void *aux; 138 { 139 struct mca_attach_args *ma = aux; 140 141 switch (ma->ma_id) { 142 case MCA_PRODUCT_IBM_ESDIC: 143 case MCA_PRODUCT_IBM_ESDIC_IG: 144 return (1); 145 default: 146 return (0); 147 } 148 } 149 150 void 151 edc_mca_attach(parent, self, aux) 152 struct device *parent, *self; 153 void *aux; 154 { 155 struct edc_mca_softc *sc = (void *) self; 156 struct mca_attach_args *ma = aux; 157 struct ed_attach_args eda; 158 int pos2, pos3, pos4; 159 int irq, drq, iobase; 160 const char *typestr; 161 int devno, error; 162 163 pos2 = mca_conf_read(ma->ma_mc, ma->ma_slot, 2); 164 pos3 = mca_conf_read(ma->ma_mc, ma->ma_slot, 3); 165 pos4 = mca_conf_read(ma->ma_mc, ma->ma_slot, 4); 166 167 /* 168 * POS register 2: (adf pos0) 169 * 170 * 7 6 5 4 3 2 1 0 171 * \ \____/ \ \__ enable: 0=adapter disabled, 1=adapter enabled 172 * \ \ \___ Primary/Alternate Port Adresses: 173 * \ \ 0=0x3510-3517 1=0x3518-0x351f 174 * \ \_____ DMA Arbitration Level: 0101=5 0110=6 0111=7 175 * \ 0000=0 0001=1 0011=3 0100=4 176 * \_________ Fairness On/Off: 1=On 0=Off 177 * 178 * POS register 3: (adf pos1) 179 * 180 * 7 6 5 4 3 2 1 0 181 * 0 0 \_/ 182 * \__________ DMA Burst Pacing Interval: 10=24ms 11=31ms 183 * 01=16ms 00=Burst Disabled 184 * 185 * POS register 4: (adf pos2) 186 * 187 * 7 6 5 4 3 2 1 0 188 * \_/ \__ DMA Pacing Control: 1=Disabled 0=Enabled 189 * \____ Time to Release: 1X=6ms 01=3ms 00=Immediate 190 * 191 * IRQ is fixed to 14 (0x0e). 192 */ 193 194 switch (ma->ma_id) { 195 case MCA_PRODUCT_IBM_ESDIC: 196 typestr = "IBM ESDI Fixed Disk Controller"; 197 break; 198 case MCA_PRODUCT_IBM_ESDIC_IG: 199 typestr = "IBM Integ. ESDI Fixed Disk & Controller"; 200 break; 201 default: 202 /* never reached */ ; 203 } 204 205 irq = ESDIC_IRQ; 206 iobase = (pos2 & IO_IS_ALT) ? ESDIC_IOALT : ESDIC_IOPRM; 207 drq = (pos2 & DRQ_MASK) >> 2; 208 209 printf(" slot %d irq %d drq %d: %s\n", ma->ma_slot+1, 210 irq, drq, typestr); 211 212 #ifdef DIAGNOSTIC 213 /* 214 * It's not strictly necessary to check this, machine configuration 215 * utility uses only valid adresses. 216 */ 217 if (drq == 2 || drq >= 8) { 218 printf("%s: invalid DMA Arbitration Level %d\n", 219 sc->sc_dev.dv_xname, drq); 220 return; 221 } 222 #endif 223 224 printf("%s: Fairness %s, Release %s, ", 225 sc->sc_dev.dv_xname, 226 (pos2 & FAIRNESS_ENABLE) ? "On" : "Off", 227 (pos4 & RELEASE_1) ? "6ms" 228 : ((pos4 & RELEASE_2) ? "3ms" : "Immediate") 229 ); 230 if ((pos4 & PACING_CTRL_DISABLE) == 0) { 231 static const char * const pacint[] = 232 { "disabled", "16ms", "24ms", "31ms"}; 233 printf("DMA burst pacing interval %s\n", 234 pacint[(pos3 & PACING_INT_MASK) >> 4]); 235 } else 236 printf("DMA pacing control disabled\n"); 237 238 sc->sc_iot = ma->ma_iot; 239 240 if (bus_space_map(sc->sc_iot, iobase, 241 ESDIC_REG_NPORTS, 0, &sc->sc_ioh)) { 242 printf("%s: couldn't map registers\n", 243 sc->sc_dev.dv_xname); 244 return; 245 } 246 247 sc->sc_ih = mca_intr_establish(ma->ma_mc, irq, IPL_BIO, edc_intr, sc); 248 if (sc->sc_ih == NULL) { 249 printf("%s: couldn't establish interrupt handler\n", 250 sc->sc_dev.dv_xname); 251 return; 252 } 253 254 /* Create a MCA DMA map, used for data transfer */ 255 sc->sc_dmat = ma->ma_dmat; 256 if ((error = mca_dmamap_create(sc->sc_dmat, MAXPHYS, 257 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW | MCABUS_DMA_16BIT, 258 &sc->sc_dmamap_xfer, drq)) != 0){ 259 printf("%s: couldn't create DMA map - error %d\n", 260 sc->sc_dev.dv_xname, error); 261 return; 262 } 263 264 /* 265 * Integrated ESDI controller supports only one disk, other 266 * controllers support two disks. 267 */ 268 if (ma->ma_id == MCA_PRODUCT_IBM_ESDIC_IG) 269 sc->sc_maxdevs = 1; 270 else 271 sc->sc_maxdevs = 2; 272 273 /* 274 * Reset controller and attach individual disks. ed attach routine 275 * uses polling so that this works with interrupts disabled. 276 */ 277 278 /* Do a reset to ensure sane state after warm boot. */ 279 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_BUSY) { 280 /* hard reset */ 281 printf("%s: controller busy, performing hardware reset ...\n", 282 sc->sc_dev.dv_xname); 283 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 284 BCR_INT_ENABLE|BCR_RESET); 285 } else { 286 /* "SOFT" reset */ 287 edc_do_attn(sc, ATN_RESET_ATTACHMENT, DASD_DEVNO_CONTROLLER,0); 288 } 289 290 /* 291 * Since interrupts are disabled, it's necessary 292 * to detect the interrupt request and call edc_intr() 293 * explicitly. See also edc_run_cmd(). 294 */ 295 while(bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_BUSY) { 296 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_INTR) 297 edc_intr(sc); 298 299 delay(100); 300 } 301 302 /* be quiet during probes */ 303 sc->sc_flags |= DASD_QUIET; 304 305 /* check for attached disks */ 306 for(devno=0; devno < sc->sc_maxdevs; devno++) { 307 eda.edc_drive = devno; 308 sc->sc_ed[devno] = 309 (void *) config_found_sm(self, &eda, NULL, NULL); 310 311 /* If initialization did not succeed, NULL the pointer. */ 312 if (sc->sc_ed[devno] 313 && (sc->sc_ed[devno]->sc_flags & EDF_INIT) == 0) 314 sc->sc_ed[devno] = NULL; 315 } 316 317 /* enable full error dumps again */ 318 sc->sc_flags &= ~DASD_QUIET; 319 320 /* 321 * Check if there are any disks attached. If not, disestablish 322 * the interrupt. 323 */ 324 for(devno=0; devno < sc->sc_maxdevs; devno++) { 325 if (sc->sc_ed[devno]) 326 break; 327 } 328 329 if (devno == sc->sc_maxdevs) { 330 printf("%s: disabling controller (no drives attached)\n", 331 sc->sc_dev.dv_xname); 332 mca_intr_disestablish(ma->ma_mc, sc->sc_ih); 333 return; 334 } 335 336 /* 337 * Run the worker thread. 338 */ 339 config_pending_incr(); 340 kthread_create(edc_spawn_worker, (void *) sc); 341 } 342 343 void 344 edc_add_disk(sc, ed) 345 struct edc_mca_softc *sc; 346 struct ed_softc *ed; 347 { 348 sc->sc_ed[ed->sc_devno] = ed; 349 } 350 351 static int 352 edc_intr(arg) 353 void *arg; 354 { 355 struct edc_mca_softc *sc = arg; 356 u_int8_t isr, intr_id; 357 u_int16_t sifr; 358 int cmd=-1, devno; 359 360 /* 361 * Check if the interrupt was for us. 362 */ 363 if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_INTR) == 0) 364 return (0); 365 366 /* 367 * Read ISR to find out interrupt type. This also clears the interrupt 368 * condition and BSR_INTR flag. Accordings to docs interrupt ID of 0, 2 369 * and 4 are reserved and not used. 370 */ 371 isr = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ISR); 372 intr_id = isr & ISR_INTR_ID_MASK; 373 374 #ifdef EDC_DEBUG 375 if (intr_id == 0 || intr_id == 2 || intr_id == 4) { 376 printf("%s: bogus interrupt id %d\n", sc->sc_dev.dv_xname, 377 (int) intr_id); 378 return (0); 379 } 380 #endif 381 382 /* Get number of device whose intr this was */ 383 devno = (isr & 0xe0) >> 5; 384 385 /* 386 * Get Status block. Higher byte always says how long the status 387 * block is, rest is device number and command code. 388 * Check the status block length against our supported maximum length 389 * and fetch the data. 390 */ 391 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh,BSR) & BSR_SIFR_FULL) { 392 size_t len; 393 int i; 394 395 sifr = le16toh(bus_space_read_2(sc->sc_iot, sc->sc_ioh, SIFR)); 396 len = (sifr & 0xff00) >> 8; 397 #ifdef DEBUG 398 if (len > EDC_MAX_CMD_RES_LEN) 399 panic("%s: maximum Status Length exceeded: %d > %d", 400 sc->sc_dev.dv_xname, 401 len, EDC_MAX_CMD_RES_LEN); 402 #endif 403 404 /* Get command code */ 405 cmd = sifr & SIFR_CMD_MASK; 406 407 /* Read whole status block */ 408 sc->status_block[0] = sifr; 409 for(i=1; i < len; i++) { 410 while((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 411 & BSR_SIFR_FULL) == 0) 412 ; 413 414 sc->status_block[i] = le16toh( 415 bus_space_read_2(sc->sc_iot, sc->sc_ioh, SIFR)); 416 } 417 /* zero out rest */ 418 if (i < EDC_MAX_CMD_RES_LEN) { 419 memset(&sc->status_block[i], 0, 420 (EDC_MAX_CMD_RES_LEN-i)*sizeof(u_int16_t)); 421 } 422 } 423 424 switch (intr_id) { 425 case ISR_DATA_TRANSFER_RDY: 426 /* 427 * Ready to do DMA. The DMA controller has already been 428 * setup, now just kick disk controller to do the transfer. 429 */ 430 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 431 BCR_INT_ENABLE|BCR_DMA_ENABLE); 432 break; 433 434 case ISR_COMPLETED: 435 case ISR_COMPLETED_WITH_ECC: 436 case ISR_COMPLETED_RETRIES: 437 case ISR_COMPLETED_WARNING: 438 /* 439 * Copy device config data if appropriate. sc->sc_ed[] 440 * entry might be NULL during probe. 441 */ 442 if (cmd == CMD_GET_DEV_CONF && sc->sc_ed[devno]) { 443 memcpy(sc->sc_ed[devno]->sense_data, sc->status_block, 444 sizeof(sc->sc_ed[devno]->sense_data)); 445 } 446 447 sc->sc_stat = STAT_DONE; 448 break; 449 450 case ISR_RESET_COMPLETED: 451 case ISR_ABORT_COMPLETED: 452 /* nothing to do */ 453 break; 454 455 case ISR_ATTN_ERROR: 456 /* 457 * Basically, this means driver bug or something seriously 458 * hosed. panic rather than extending the lossage. 459 * No status block available, so no further info. 460 */ 461 panic("%s: dev %d: attention error", 462 sc->sc_dev.dv_xname, 463 devno); 464 /* NOTREACHED */ 465 break; 466 467 default: 468 if ((sc->sc_flags & DASD_QUIET) == 0) 469 edc_dump_status_block(sc, sc->status_block, intr_id); 470 471 sc->sc_stat = STAT_ERROR; 472 break; 473 } 474 475 /* 476 * Unless the interrupt is for Data Transfer Ready or 477 * Attention Error, finish by assertion EOI. This makes 478 * attachment aware the interrupt is processed and system 479 * is ready to accept another one. 480 */ 481 if (intr_id != ISR_DATA_TRANSFER_RDY && intr_id != ISR_ATTN_ERROR) 482 edc_do_attn(sc, ATN_END_INT, devno, intr_id); 483 484 /* If Read or Write Data, wakeup worker thread to finish it */ 485 if (intr_id != ISR_DATA_TRANSFER_RDY) { 486 if (cmd == CMD_READ_DATA || cmd == CMD_WRITE_DATA) 487 sc->sc_resblk = sc->status_block[SB_RESBLKCNT_IDX]; 488 wakeup_one(sc); 489 } 490 491 return (1); 492 } 493 494 /* 495 * This follows the exact order for Attention Request as 496 * written in DASD Storage Interface Specification MC (Rev 2.2). 497 */ 498 static int 499 edc_do_attn(sc, attn_type, devno, intr_id) 500 struct edc_mca_softc *sc; 501 int attn_type, devno, intr_id; 502 { 503 int tries; 504 505 /* 1. Disable interrupts in BCR. */ 506 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 0); 507 508 /* 509 * 2. Assure NOT BUSY and NO INTERRUPT PENDING, unless acknowledging 510 * a RESET COMPLETED interrupt. 511 */ 512 if (intr_id != ISR_RESET_COMPLETED) { 513 #ifdef EDC_DEBUG 514 if (attn_type == ATN_CMD_REQ 515 && (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 516 & BSR_INT_PENDING)) 517 panic("%s: edc int pending", sc->sc_dev.dv_xname); 518 #endif 519 520 for(tries=1; tries < EDC_ATTN_MAXTRIES; tries++) { 521 if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 522 & BSR_BUSY) == 0) 523 break; 524 } 525 526 if (tries == EDC_ATTN_MAXTRIES) { 527 printf("%s: edc_do_attn: timeout waiting for attachment to become available\n", 528 sc->sc_ed[devno]->sc_dev.dv_xname); 529 return (EIO); 530 } 531 } 532 533 /* 534 * 3. Write proper DEVICE NUMBER and Attention number to ATN. 535 */ 536 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ATN, attn_type | (devno<<5)); 537 538 /* 539 * 4. Enable interrupts via BCR. 540 */ 541 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, BCR_INT_ENABLE); 542 543 return (0); 544 } 545 546 /* 547 * Wait until command is processed, timeout after 'secs' seconds. 548 * We use mono_time, since we don't need actual RTC, just time 549 * interval. 550 */ 551 static void 552 edc_cmd_wait(sc, secs, poll) 553 struct edc_mca_softc *sc; 554 int secs, poll; 555 { 556 int val; 557 558 if (!poll) { 559 int s; 560 561 /* Not polling, can sleep. Sleep until we are awakened, 562 * but maximum secs seconds. 563 */ 564 s = splbio(); 565 if (sc->sc_stat != STAT_DONE) 566 (void) tsleep(sc, PRIBIO, "edcwcmd", secs * hz); 567 splx(s); 568 } 569 570 /* Wait until the command is completely finished */ 571 while((val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR)) 572 & BSR_CMD_INPROGRESS) { 573 if (poll && (val & BSR_INTR)) 574 edc_intr(sc); 575 } 576 } 577 578 /* 579 * Command controller to execute specified command on a device. 580 */ 581 int 582 edc_run_cmd(sc, cmd, devno, cmd_args, cmd_len, poll) 583 struct edc_mca_softc *sc; 584 int cmd; 585 int devno; 586 u_int16_t cmd_args[]; 587 int cmd_len, poll; 588 { 589 int i, error, tries; 590 u_int16_t cmd0; 591 592 sc->sc_stat = STAT_START; 593 594 /* Do Attention Request for Command Request. */ 595 if ((error = edc_do_attn(sc, ATN_CMD_REQ, devno, 0))) 596 return (error); 597 598 /* 599 * Construct the command. The bits are like this: 600 * 601 * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 602 * \_/ 0 0 1 0 \__/ \_____/ 603 * \ \__________/ \ \_ Command Code (see CMD_*) 604 * \ \ \__ Device: 0 common, 7 controller 605 * \ \__ Options: reserved, bit 10=cache bypass bit 606 * \_ Type: 00=2B, 01=4B, 10 and 11 reserved 607 * 608 * We always use device 0 or 1, so difference is made only by Command 609 * Code, Command Options and command length. 610 */ 611 cmd0 = ((cmd_len == 4) ? (CIFR_LONG_CMD) : 0) 612 | (devno << 5) 613 | (cmd_args[0] << 8) | cmd; 614 cmd_args[0] = cmd0; 615 616 /* 617 * Write word of CMD to the CIFR. This sets "Command 618 * Interface Register Full (CMD IN)" in BSR. Once the attachment 619 * detects it, it reads the word and clears CMD IN. This all should 620 * be quite fast, so don't sleep in !poll case neither. 621 */ 622 for(i=0; i < cmd_len; i++) { 623 bus_space_write_2(sc->sc_iot, sc->sc_ioh, CIFR, 624 htole16(cmd_args[i])); 625 626 /* Wait until CMD IN is cleared. */ 627 tries = 0; 628 for(; (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 629 & BSR_CIFR_FULL) && tries < 10000 ; tries++) 630 delay(poll ? 1000 : 1); 631 ; 632 633 if (tries == 10000 634 && bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 635 & BSR_CIFR_FULL) { 636 printf("%s: device too slow to accept command %d\n", 637 sc->sc_dev.dv_xname, cmd); 638 return (EIO); 639 } 640 } 641 642 /* Wait for command to complete, but maximum 15 seconds. */ 643 edc_cmd_wait(sc, 15, poll); 644 645 return ((sc->sc_stat != STAT_DONE) ? EIO : 0); 646 } 647 648 #ifdef EDC_DEBUG 649 static const char * const edc_commands[] = { 650 "Invalid Command", 651 "Read Data", 652 "Write Data", 653 "Read Verify", 654 "Write with Verify", 655 "Seek", 656 "Park Head", 657 "Get Command Complete Status", 658 "Get Device Status", 659 "Get Device Configuration", 660 "Get POS Information", 661 "Translate RBA", 662 "Write Attachment Buffer", 663 "Read Attachment Buffer", 664 "Run Diagnostic Test", 665 "Get Diagnostic Status Block", 666 "Get MFG Header", 667 "Format Unit", 668 "Format Prepare", 669 "Set MAX RBA", 670 "Set Power Saving Mode", 671 "Power Conservation Command", 672 }; 673 674 static const char * const edc_cmd_status[256] = { 675 "Reserved", 676 "Command completed successfully", 677 "Reserved", 678 "Command completed successfully with ECC applied", 679 "Reserved", 680 "Command completed successfully with retries", 681 "Format Command partially completed", /* Status available */ 682 "Command completed successfully with ECC and retries", 683 "Command completed with Warning", /* Command Error is available */ 684 "Aborted", 685 "Reset completed", 686 "Data Transfer Ready", /* No Status Block available */ 687 "Command terminated with failure", /* Device Error is available */ 688 "DMA Error", /* Retry entire command as recovery */ 689 "Command Block Error", 690 "Attention Error (Illegal Attention Code)", 691 /* 0x14 - 0xff reserved */ 692 }; 693 694 static const char * const edc_cmd_error[256] = { 695 "No Error", 696 "Invalid parameter in the command block", 697 "Reserved", 698 "Command not supported", 699 "Command Aborted per request", 700 "Reserved", 701 "Command rejected", /* Attachment diagnostic failure */ 702 "Format Rejected", /* Prepare Format command is required */ 703 "Format Error (Primary Map is not readable)", 704 "Format Error (Secondary map is not readable)", 705 "Format Error (Diagnostic Failure)", 706 "Format Warning (Secondary Map Overflow)", 707 "Reserved" 708 "Format Error (Host Checksum Error)", 709 "Reserved", 710 "Format Warning (Push table overflow)", 711 "Format Warning (More pushes than allowed)", 712 "Reserved", 713 "Format Warning (Error during verifying)", 714 "Invalid device number for the command", 715 /* 0x14-0xff reserved */ 716 }; 717 718 static const char * const edc_dev_errors[] = { 719 "No Error", 720 "Seek Fault", /* Device report */ 721 "Interface Fault (Parity, Attn, or Cmd Complete Error)", 722 "Block not found (ID not found)", 723 "Block not found (AM not found)", 724 "Data ECC Error (hard error)", 725 "ID CRC Error", 726 "RBA Out of Range", 727 "Reserved", 728 "Defective Block", 729 "Reserved", 730 "Selection Error", 731 "Reserved", 732 "Write Fault", 733 "No index or sector pulse", 734 "Device Not Ready", 735 "Seek Error", /* Attachment report */ 736 "Bad Format", 737 "Volume Overflow", 738 "No Data AM Found", 739 "Block not found (No ID AM or ID CRC error occurred)", 740 "Reserved", 741 "Reserved", 742 "No ID found on track (ID search)", 743 /* 0x19 - 0xff reserved */ 744 }; 745 #endif /* EDC_DEBUG */ 746 747 static void 748 edc_dump_status_block(sc, status_block, intr_id) 749 struct edc_mca_softc *sc; 750 u_int16_t *status_block; 751 int intr_id; 752 { 753 #ifdef EDC_DEBUG 754 printf("%s: Command: %s, Status: %s (intr %d)\n", 755 sc->sc_dev.dv_xname, 756 edc_commands[status_block[0] & 0x1f], 757 edc_cmd_status[SB_GET_CMD_STATUS(status_block)], 758 intr_id 759 ); 760 #else 761 printf("%s: Command: %d, Status: %d (intr %d)\n", 762 sc->sc_dev.dv_xname, 763 status_block[0] & 0x1f, 764 SB_GET_CMD_STATUS(status_block), 765 intr_id 766 ); 767 #endif 768 printf("%s: # left blocks: %u, last processed RBA: %u\n", 769 sc->sc_dev.dv_xname, 770 status_block[SB_RESBLKCNT_IDX], 771 (status_block[5] << 16) | status_block[4]); 772 773 if (intr_id == ISR_COMPLETED_WARNING) { 774 #ifdef EDC_DEBUG 775 printf("%s: Command Error Code: %s\n", 776 sc->sc_dev.dv_xname, 777 edc_cmd_error[status_block[1] & 0xff]); 778 #else 779 printf("%s: Command Error Code: %d\n", 780 sc->sc_dev.dv_xname, 781 status_block[1] & 0xff); 782 #endif 783 } 784 785 if (intr_id == ISR_CMD_FAILED) { 786 #ifdef EDC_DEBUG 787 char buf[100]; 788 789 printf("%s: Device Error Code: %s\n", 790 sc->sc_dev.dv_xname, 791 edc_dev_errors[status_block[2] & 0xff]); 792 bitmask_snprintf((status_block[2] & 0xff00) >> 8, 793 "\20" 794 "\01SeekOrCmdComplete" 795 "\02Track0Flag" 796 "\03WriteFault" 797 "\04Selected" 798 "\05Ready" 799 "\06Reserved0" 800 "\07STANDBY" 801 "\010Reserved0", 802 buf, sizeof(buf)); 803 printf("%s: Device Status: %s\n", 804 sc->sc_dev.dv_xname, buf); 805 #else 806 printf("%s: Device Error Code: %d, Device Status: %d\n", 807 sc->sc_dev.dv_xname, 808 status_block[2] & 0xff, 809 (status_block[2] & 0xff00) >> 8); 810 #endif 811 } 812 } 813 814 static void 815 edc_spawn_worker(arg) 816 void *arg; 817 { 818 struct edc_mca_softc *sc = (struct edc_mca_softc *) arg; 819 int error; 820 struct proc *wrk; 821 822 /* Now, everything is ready, start a kthread */ 823 if ((error = kthread_create1(edcworker, sc, &wrk, 824 "%s", sc->sc_dev.dv_xname))) { 825 printf("%s: cannot spawn worker thread: errno=%d\n", 826 sc->sc_dev.dv_xname, error); 827 panic("edc_spawn_worker"); 828 } 829 } 830 831 /* 832 * Main worker thread function. 833 */ 834 void 835 edcworker(arg) 836 void *arg; 837 { 838 struct edc_mca_softc *sc = (struct edc_mca_softc *) arg; 839 struct ed_softc *ed; 840 struct buf *bp; 841 int i, error; 842 843 config_pending_decr(); 844 845 for(;;) { 846 /* Wait until awakened */ 847 (void) tsleep(sc, PRIBIO, "edcidle", 0); 848 849 for(i=0; i<sc->sc_maxdevs; ) { 850 if ((ed = sc->sc_ed[i]) == NULL) { 851 i++; 852 continue; 853 } 854 855 /* Is there a buf for us ? */ 856 simple_lock(&ed->sc_q_lock); 857 if ((bp = BUFQ_GET(&ed->sc_q)) == NULL) { 858 simple_unlock(&ed->sc_q_lock); 859 i++; 860 continue; 861 } 862 simple_unlock(&ed->sc_q_lock); 863 864 /* Instrumentation. */ 865 disk_busy(&ed->sc_dk); 866 867 error = edc_bio(sc, ed, bp->b_data, bp->b_bcount, 868 bp->b_rawblkno, (bp->b_flags & B_READ), 0); 869 870 if (error) { 871 bp->b_error = error; 872 bp->b_flags |= B_ERROR; 873 } else { 874 /* Set resid, most commonly to zero. */ 875 bp->b_resid = sc->sc_resblk * DEV_BSIZE; 876 } 877 878 disk_unbusy(&ed->sc_dk, (bp->b_bcount - bp->b_resid), 879 (bp->b_flags & B_READ)); 880 #if NRND > 0 881 rnd_add_uint32(&ed->rnd_source, bp->b_blkno); 882 #endif 883 biodone(bp); 884 } 885 } 886 } 887 888 int 889 edc_bio(struct edc_mca_softc *sc, struct ed_softc *ed, void *data, 890 size_t bcount, daddr_t rawblkno, int isread, int poll) 891 { 892 u_int16_t cmd_args[4]; 893 int error=0, fl; 894 u_int16_t track; 895 u_int16_t cyl; 896 u_int8_t head; 897 u_int8_t sector; 898 899 mca_disk_busy(); 900 901 /* set WAIT and R/W flag appropriately for the DMA transfer */ 902 fl = ((poll) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK) 903 | ((isread) ? BUS_DMA_READ : BUS_DMA_WRITE); 904 905 /* Load the buffer for DMA transfer. */ 906 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_xfer, data, 907 bcount, NULL, BUS_DMA_STREAMING|fl))) { 908 printf("%s: ed_bio: unable to load DMA buffer - error %d\n", 909 ed->sc_dev.dv_xname, error); 910 goto out; 911 } 912 913 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_xfer, 0, 914 bcount, (isread) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 915 916 track = rawblkno / ed->sectors; 917 head = track % ed->heads; 918 cyl = track / ed->heads; 919 sector = rawblkno % ed->sectors; 920 921 /* Read or Write Data command */ 922 cmd_args[0] = 2; /* Options 0000010 */ 923 cmd_args[1] = bcount / DEV_BSIZE; 924 cmd_args[2] = ((cyl & 0x1f) << 11) | (head << 5) | sector; 925 cmd_args[3] = ((cyl & 0x3E0) >> 5); 926 error = edc_run_cmd(sc, 927 (isread) ? CMD_READ_DATA : CMD_WRITE_DATA, 928 ed->sc_devno, cmd_args, 4, poll); 929 930 /* Sync the DMA memory */ 931 if (!error) { 932 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_xfer, 0, bcount, 933 (isread)? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 934 } 935 936 /* We are done, unload buffer from DMA map */ 937 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_xfer); 938 939 out: 940 mca_disk_unbusy(); 941 942 return (error); 943 } 944