1 /* $NetBSD: edcreg.h,v 1.2 2001/04/22 11:32:49 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Jaromir Dolecek. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * Driver for MCA ESDI controllers and disks. 38 */ 39 40 #define ESDIC_IOPRM 0x3510 41 #define ESDIC_IOALT 0x3518 42 #define ESDIC_REG_NPORTS 8 43 #define ESDIC_IRQ 14 /* this is fixed */ 44 45 /* pos2 */ 46 #define IO_IS_ALT 0x02 47 #define DRQ_MASK 0x3c 48 #define FAIRNESS_ENABLE 0x40 49 50 /* pos3 */ 51 #define PACING_INT_MASK 0x30 52 53 /* pos4 */ 54 #define PACING_CTRL_DISABLE 0x01 55 #define RELEASE_2 0x02 /* lower bit of Time to Release */ 56 #define RELEASE_1 0x04 /* higher bit of Time to Release */ 57 58 /* controller registers */ 59 #define SIFR 0 /* read Status Interface Register, 60 2 bytes, little endian */ 61 #define SIFR_CMD_MASK 0x2f 62 63 #define CIFR 0 /* write - Command Interface Reg, 64 2 bytes, little endian */ 65 #define CIFR_LONG_CMD (1<<14) /* 4 word command */ 66 67 /* Command Codes */ 68 #define CMD_READ_DATA 0x01 /* uses DMA */ 69 #define CMD_WRITE_DATA 0x02 /* uses DMA */ 70 #define CMD_READ_VERIFY 0x03 71 #define CMD_WRITE_VERIFY 0x04 /* uses DMA */ 72 #define CMD_SEEK 0x05 73 #define CMD_PARK_HEAD 0x06 74 #define CMD_GET_CMD_COMP_STATUS 0x07 75 #define CMD_GET_DEV_STATUS 0x08 76 #define CMD_GET_DEV_CONF 0x09 77 #define CMD_GET_POS_INFO 0x0A 78 #define CMD_TRANSLATE_RBA 0x0B 79 #define CMD_WRITE_ATTACH_BUFF 0x10 /* uses DMA */ 80 #define CMD_READ_ATTACH_BUFF 0x11 /* uses DMA */ 81 #define CMD_RUN_DIAG_TEST 0x12 82 #define CMD_GET_DIAG_STAT_BLOCK 0x14 83 #define CMD_GET_MFG_HEADER 0x15 /* uses DMA */ 84 #define CMD_FORMAT_UNIT 0x16 /* uses DMA */ 85 #define CMD_FORMAT_PREPARE 0x17 86 #define CMD_SET_MAX_RBA 0x1A 87 #define CMD_SET_PWR_SAV_MODE 0x1B /* optional */ 88 #define CMD_POWER_CONS_CMD 0x1C /* optional */ 89 90 #define BCR 2 /* write */ 91 #define BCR_INT_ENABLE 0x01 92 #define BCR_DMA_ENABLE 0x02 93 #define BCR_RESET 0x80 94 95 #define BSR 2 /* read */ 96 #define BSR_DMA_ENABLED 0x80 97 #define BSR_INT_PENDING 0x40 98 #define BSR_CMD_INPROGRESS 0x20 99 #define BSR_BUSY 0x10 100 #define BSR_SIFR_FULL 0x08 /* also called STATUS OUT */ 101 #define BSR_CIFR_FULL 0x04 102 #define BSR_TRANSFER_REQ 0x02 103 #define BSR_INTR 0x01 104 105 #define ISR 3 /* read, Interrupt Status Register */ 106 #define ISR_DEV_SELECT_MASK 0xE0 107 #define ISR_ATTACH_ERR 0x10 108 #define ISR_INTR_ID_MASK 0x0F 109 #define ISR_COMPLETED 0x01 110 #define ISR_COMPLETED_WITH_ECC 0x03 111 #define ISR_COMPLETED_RETRIES 0x05 112 #define ISR_PARTIAL_FORMAT 0x06 /* Status available */ 113 #define ISR_COMPLETED_WARNING 0x08 114 #define ISR_ABORT_COMPLETED 0x09 115 #define ISR_RESET_COMPLETED 0x0A 116 #define ISR_DATA_TRANSFER_RDY 0x0B /* No Status Block */ 117 #define ISR_CMD_FAILED 0x0C 118 #define ISR_DMA_ERROR 0x0D 119 #define ISR_CMD_BLOCK_ERROR 0x0E 120 #define ISR_ATTN_ERROR 0x0F 121 122 /* Macros to get info from command status block */ 123 #define SB_GET_CMD_STATUS(sb) (((sb)[1] & 0xff00) >> 8) 124 #define SB_RESBLKCNT_IDX 3 125 126 #define ATN 3 /* write, Attention register */ 127 #define ATN_CMD_REQ 1 128 #define ATN_END_INT 2 /* End of Interrupt (EOI) */ 129 #define ATN_ABORT_CMD 3 130 #define ATN_RESET_ATTACHMENT 4 131 132 #define DASD_DEVNO_CONTROLLER 7 /* Device number for controller */ 133