1 /* $NetBSD: etphy.c,v 1.1 2010/11/13 00:47:24 jnemeth Exp $ */ 2 /* $OpenBSD: etphy.c,v 1.4 2008/04/02 20:12:58 brad Exp $ */ 3 4 /* 5 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 6 * 7 * This code is derived from software contributed to The DragonFly Project 8 * by Sepherosa Ziehau <sepherosa@gmail.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in 18 * the documentation and/or other materials provided with the 19 * distribution. 20 * 3. Neither the name of The DragonFly Project nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific, prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 27 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 28 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 30 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 31 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 32 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 34 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $DragonFly: src/sys/dev/netif/mii_layer/truephy.c,v 1.1 2007/10/12 14:12:42 sephe Exp $ 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: etphy.c,v 1.1 2010/11/13 00:47:24 jnemeth Exp $"); 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/device.h> 47 #include <sys/socket.h> 48 49 #include <net/if.h> 50 #include <net/if_media.h> 51 52 #include <dev/mii/mii.h> 53 #include <dev/mii/miivar.h> 54 #include <dev/mii/miidevs.h> 55 56 #define ETPHY_INDEX 0x10 /* XXX reserved in DS */ 57 #define ETPHY_INDEX_MAGIC 0x402 58 #define ETPHY_DATA 0x11 /* XXX reserved in DS */ 59 60 #define ETPHY_CTRL 0x12 61 #define ETPHY_CTRL_DIAG 0x0004 62 #define ETPHY_CTRL_RSV1 0x0002 /* XXX reserved */ 63 #define ETPHY_CTRL_RSV0 0x0001 /* XXX reserved */ 64 65 #define ETPHY_CONF 0x16 66 #define ETPHY_CONF_TXFIFO_MASK 0x3000 67 #define ETPHY_CONF_TXFIFO_8 0x0000 68 #define ETPHY_CONF_TXFIFO_16 0x1000 69 #define ETPHY_CONF_TXFIFO_24 0x2000 70 #define ETPHY_CONF_TXFIFO_32 0x3000 71 72 #define ETPHY_SR 0x1a 73 #define ETPHY_SR_SPD_MASK 0x0300 74 #define ETPHY_SR_SPD_1000T 0x0200 75 #define ETPHY_SR_SPD_100TX 0x0100 76 #define ETPHY_SR_SPD_10T 0x0000 77 #define ETPHY_SR_FDX 0x0080 78 79 80 int etphy_service(struct mii_softc *, struct mii_data *, int); 81 void etphy_attach(device_t, device_t, void *); 82 int etphy_match(device_t, cfdata_t, void *); 83 void etphy_reset(struct mii_softc *); 84 void etphy_status(struct mii_softc *); 85 86 const struct mii_phy_funcs etphy_funcs = { 87 etphy_service, etphy_status, etphy_reset, 88 }; 89 90 static const struct mii_phydesc etphys[] = { 91 { MII_OUI_AGERE, MII_MODEL_AGERE_ET1011, 92 MII_STR_AGERE_ET1011 }, 93 { 0, 0, 94 NULL }, 95 }; 96 97 CFATTACH_DECL_NEW(etphy, sizeof(struct mii_softc), 98 etphy_match, etphy_attach, mii_phy_detach, mii_phy_activate); 99 100 static const struct etphy_dsp { 101 uint16_t index; 102 uint16_t data; 103 } etphy_dspcode[] = { 104 { 0x880b, 0x0926 }, /* AfeIfCreg4B1000Msbs */ 105 { 0x880c, 0x0926 }, /* AfeIfCreg4B100Msbs */ 106 { 0x880d, 0x0926 }, /* AfeIfCreg4B10Msbs */ 107 108 { 0x880e, 0xb4d3 }, /* AfeIfCreg4B1000Lsbs */ 109 { 0x880f, 0xb4d3 }, /* AfeIfCreg4B100Lsbs */ 110 { 0x8810, 0xb4d3 }, /* AfeIfCreg4B10Lsbs */ 111 112 { 0x8805, 0xb03e }, /* AfeIfCreg3B1000Msbs */ 113 { 0x8806, 0xb03e }, /* AfeIfCreg3B100Msbs */ 114 { 0x8807, 0xff00 }, /* AfeIfCreg3B10Msbs */ 115 116 { 0x8808, 0xe090 }, /* AfeIfCreg3B1000Lsbs */ 117 { 0x8809, 0xe110 }, /* AfeIfCreg3B100Lsbs */ 118 { 0x880a, 0x0000 }, /* AfeIfCreg3B10Lsbs */ 119 120 { 0x300d, 1 }, /* DisableNorm */ 121 122 { 0x280c, 0x0180 }, /* LinkHoldEnd */ 123 124 { 0x1c21, 0x0002 }, /* AlphaM */ 125 126 { 0x3821, 6 }, /* FfeLkgTx0 */ 127 { 0x381d, 1 }, /* FfeLkg1g4 */ 128 { 0x381e, 1 }, /* FfeLkg1g5 */ 129 { 0x381f, 1 }, /* FfeLkg1g6 */ 130 { 0x3820, 1 }, /* FfeLkg1g7 */ 131 132 { 0x8402, 0x01f0 }, /* Btinact */ 133 { 0x800e, 20 }, /* LftrainTime */ 134 { 0x800f, 24 }, /* DvguardTime */ 135 { 0x8010, 46 } /* IdlguardTime */ 136 }; 137 138 int 139 etphy_match(device_t parent, cfdata_t match, void *aux) 140 { 141 struct mii_attach_args *ma = aux; 142 143 if (mii_phy_match(ma, etphys) != NULL) 144 return 10; 145 146 return 0; 147 } 148 149 void 150 etphy_attach(device_t parent, device_t self, void *aux) 151 { 152 struct mii_softc *sc = device_private(self); 153 struct mii_attach_args *ma = aux; 154 struct mii_data *mii = ma->mii_data; 155 const struct mii_phydesc *mpd; 156 157 mpd = mii_phy_match(ma, etphys); 158 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 159 160 sc->mii_dev = self; 161 sc->mii_inst = mii->mii_instance; 162 sc->mii_phy = ma->mii_phyno; 163 sc->mii_funcs = &etphy_funcs; 164 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 165 sc->mii_pdata = mii; 166 sc->mii_flags = ma->mii_flags; 167 168 sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP; 169 170 PHY_RESET(sc); 171 172 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 173 if (sc->mii_capabilities & BMSR_EXTSTAT) { 174 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 175 /* No 1000baseT half-duplex support */ 176 sc->mii_extcapabilities &= ~EXTSR_1000THDX; 177 } 178 aprint_normal_dev(self, ""); 179 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0) 180 aprint_error("no media present"); 181 else 182 mii_phy_add_media(sc); 183 aprint_normal("\n"); 184 185 if (!pmf_device_register(self, NULL, mii_phy_resume)) 186 aprint_error_dev(self, "couldn't establish power handler\n"); 187 } 188 189 int 190 etphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 191 { 192 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 193 int bmcr; 194 195 switch (cmd) { 196 case MII_POLLSTAT: 197 /* 198 * If we're not polling our PHY instance, just return. 199 */ 200 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 201 return 0; 202 break; 203 204 case MII_MEDIACHG: 205 /* 206 * If the media indicates a different PHY instance, 207 * isolate ourselves. 208 */ 209 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 210 bmcr = PHY_READ(sc, MII_BMCR); 211 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO); 212 return 0; 213 } 214 215 /* 216 * If the interface is not up, don't do anything. 217 */ 218 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 219 break; 220 221 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 222 bmcr = PHY_READ(sc, MII_BMCR) & ~BMCR_AUTOEN; 223 PHY_WRITE(sc, MII_BMCR, bmcr); 224 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_PDOWN); 225 } 226 227 mii_phy_setmedia(sc); 228 229 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 230 bmcr = PHY_READ(sc, MII_BMCR) & ~BMCR_PDOWN; 231 PHY_WRITE(sc, MII_BMCR, bmcr); 232 233 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) { 234 PHY_WRITE(sc, MII_BMCR, 235 bmcr | BMCR_AUTOEN | BMCR_STARTNEG); 236 } 237 } 238 break; 239 240 case MII_TICK: 241 /* 242 * If we're not currently selected, just return. 243 */ 244 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 245 return 0; 246 247 if (mii_phy_tick(sc) == EJUSTRETURN) 248 return 0; 249 break; 250 } 251 252 /* Update the media status. */ 253 mii_phy_status(sc); 254 255 /* Callback if something changed. */ 256 mii_phy_update(sc, cmd); 257 return 0; 258 } 259 260 void 261 etphy_reset(struct mii_softc *sc) 262 { 263 int i; 264 265 for (i = 0; i < 2; ++i) { 266 PHY_READ(sc, MII_PHYIDR1); 267 PHY_READ(sc, MII_PHYIDR2); 268 269 PHY_READ(sc, ETPHY_CTRL); 270 PHY_WRITE(sc, ETPHY_CTRL, 271 ETPHY_CTRL_DIAG | ETPHY_CTRL_RSV1); 272 273 PHY_WRITE(sc, ETPHY_INDEX, ETPHY_INDEX_MAGIC); 274 PHY_READ(sc, ETPHY_DATA); 275 276 PHY_WRITE(sc, ETPHY_CTRL, ETPHY_CTRL_RSV1); 277 } 278 279 PHY_READ(sc, MII_BMCR); 280 PHY_READ(sc, ETPHY_CTRL); 281 PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_PDOWN | BMCR_S1000); 282 PHY_WRITE(sc, ETPHY_CTRL, 283 ETPHY_CTRL_DIAG | ETPHY_CTRL_RSV1 | ETPHY_CTRL_RSV0); 284 285 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0])) 286 287 for (i = 0; i < N(etphy_dspcode); ++i) { 288 const struct etphy_dsp *dsp = &etphy_dspcode[i]; 289 290 PHY_WRITE(sc, ETPHY_INDEX, dsp->index); 291 PHY_WRITE(sc, ETPHY_DATA, dsp->data); 292 293 PHY_WRITE(sc, ETPHY_INDEX, dsp->index); 294 PHY_READ(sc, ETPHY_DATA); 295 } 296 297 #undef N 298 299 PHY_READ(sc, MII_BMCR); 300 PHY_READ(sc, ETPHY_CTRL); 301 PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_S1000); 302 PHY_WRITE(sc, ETPHY_CTRL, ETPHY_CTRL_RSV1); 303 304 mii_phy_reset(sc); 305 } 306 307 void 308 etphy_status(struct mii_softc *sc) 309 { 310 struct mii_data *mii = sc->mii_pdata; 311 int bmsr, bmcr, sr; 312 313 mii->mii_media_status = IFM_AVALID; 314 mii->mii_media_active = IFM_ETHER; 315 316 sr = PHY_READ(sc, ETPHY_SR); 317 bmcr = PHY_READ(sc, MII_BMCR); 318 319 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 320 if (bmsr & BMSR_LINK) 321 mii->mii_media_status |= IFM_ACTIVE; 322 323 if (bmcr & BMCR_AUTOEN) { 324 if ((bmsr & BMSR_ACOMP) == 0) { 325 mii->mii_media_active |= IFM_NONE; 326 return; 327 } 328 } 329 330 switch (sr & ETPHY_SR_SPD_MASK) { 331 case ETPHY_SR_SPD_1000T: 332 mii->mii_media_active |= IFM_1000_T; 333 break; 334 case ETPHY_SR_SPD_100TX: 335 mii->mii_media_active |= IFM_100_TX; 336 break; 337 case ETPHY_SR_SPD_10T: 338 mii->mii_media_active |= IFM_10_T; 339 break; 340 default: 341 mii->mii_media_active |= IFM_NONE; 342 return; 343 } 344 345 if (sr & ETPHY_SR_FDX) 346 mii->mii_media_active |= IFM_FDX; 347 else 348 mii->mii_media_active |= IFM_HDX; 349 } 350