1 /* $NetBSD: inbmphyreg.h,v 1.2 2010/03/07 11:07:01 msaitoh Exp $ */ 2 /******************************************************************************* 3 Copyright (c) 2001-2005, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 *******************************************************************************/ 32 33 /* 34 * Copied from the Intel code, and then modified to match NetBSD 35 * style for MII registers more. 36 */ 37 38 #ifndef _DEV_MII_INBMPHYREG_H_ 39 #define _DEV_MII_INBMPHYREG_H_ 40 41 /* Bits... 42 * 15-5: page 43 * 4-0: register offset 44 */ 45 #define BME1000_PAGE_SHIFT 5 46 #define BME1000_REG(page, reg) \ 47 (((page) << BME1000_PAGE_SHIFT) | ((reg) & BME1000_MAX_REG_ADDRESS)) 48 49 #define BME1000_MAX_REG_ADDRESS 0x1f /* 5 bit address bus (0-0x1f) */ 50 #define BME1000_MAX_MULTI_PAGE_REG 0xf /* Registers equal on all pages */ 51 52 #define BM_PHY_REG_PAGE(offset) \ 53 ((uint16_t)(((offset) >> BME1000_PAGE_SHIFT) & 0xffff)) 54 #define BM_PHY_REG_NUM(offset) \ 55 ((uint16_t)((offset) & BME1000_MAX_REG_ADDRESS) \ 56 | (((offset) >> (21 - BME1000_PAGE_SHIFT)) & ~BME1000_MAX_REG_ADDRESS)) 57 58 /* BME1000 Specific Registers */ 59 #define BME1000_PHY_SPEC_CTRL BME1000_REG(0, 16) /* PHY Specific Control */ 60 #define BME1000_PSCR_DISABLE_JABBER 0x0001 /* 1=Disable Jabber */ 61 #define BME1000_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Polarity Reversal Disabled */ 62 #define BME1000_PSCR_POWER_DOWN 0x0004 /* 1=Power Down */ 63 #define BME1000_PSCR_COPPER_TRANSMITER_DISABLE 0x0008 /* 1=Transmitter Disabled */ 64 #define BME1000_PSCR_CROSSOVER_MODE_MASK 0x0060 65 #define BME1000_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI configuration */ 66 #define BME1000_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX configuration */ 67 #define BME1000_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Automatic crossover */ 68 #define BME1000_PSCR_ENALBE_EXTENDED_DISTANCE 0x0080 /* 1=Enable Extended Distance */ 69 #define BME1000_PSCR_ENERGY_DETECT_MASK 0x0300 70 #define BME1000_PSCR_ENERGY_DETECT_OFF 0x0000 /* 00,01=Off */ 71 #define BME1000_PSCR_ENERGY_DETECT_RX 0x0200 /* 10=Sense on Rx only (Energy Detect) */ 72 #define BME1000_PSCR_ENERGY_DETECT_RX_TM 0x0300 /* 11=Sense and Tx NLP */ 73 #define BME1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force Link Good */ 74 #define BME1000_PSCR_DOWNSHIFT_ENABLE 0x0800 /* 1=Enable Downshift */ 75 #define BME1000_PSCR_DOWNSHIFT_COUNTER_MASK 0x7000 76 #define BME1000_PSCR_DOWNSHIFT_COUNTER_SHIFT 12 77 78 #define BME1000_PHY_PAGE_SELECT BME1000_REG(0, 22) /* Page Select */ 79 80 #define BME1000_BIAS_SETTING 29 81 #define BME1000_BIAS_SETTING2 30 82 83 #define I82578_ADDR_REG 29 84 #define I82577_ADDR_REG 16 85 #define I82577_CFG_REG 22 86 87 #define HV_OEM_BITS BME1000_REG(0, 25) 88 #define HV_OEM_BITS_LPLU (1 << 2) 89 #define HV_OEM_BITS_A1KDIS (1 << 6) 90 #define HV_OEM_BITS_ANEGNOW (1 << 10) 91 92 #define HV_INTC_FC_PAGE_START 768 93 #define BM_PORT_CTRL_PAGE 769 94 95 #define IGP3_KMRN_DIAG BME1000_REG(770, 19) 96 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS (1 << 1) 97 98 #define HV_MUX_DATA_CTRL BME1000_REG(776, 16) 99 #define HV_MUX_DATA_CTRL_FORCE_SPEED (1 << 2) 100 #define HV_MUX_DATA_CTRL_GEN_TO_MAC (1 << 10) 101 102 #define BM_WUC_PAGE 800 103 #define BM_WUC BME1000_REG(BM_WUC_PAGE, 1) 104 #define BM_WUC_ADDRESS_OPCODE 0x11 105 #define BM_WUC_DATA_OPCODE 0x12 106 #define BM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE 107 #define BM_WUC_ENABLE_REG 17 108 #define BM_WUC_ENABLE_BIT (1 << 2) 109 #define BM_WUC_HOST_WU_BIT (1 << 4) 110 111 #endif /* _DEV_MII_INBMPHYREG_H_ */ 112