1 /* $NetBSD: vme_two_isr.c,v 1.2 2002/03/24 17:22:32 scw Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Split off from vme_two.c specifically to deal with hardware assisted 41 * soft interrupts when the user hasn't specified `vmetwo0' in the 42 * kernel config file (mvme1[67]2 only). 43 */ 44 45 #include "vmetwo.h" 46 47 #include <sys/param.h> 48 #include <sys/kernel.h> 49 #include <sys/systm.h> 50 #include <sys/device.h> 51 #include <sys/malloc.h> 52 53 #include <machine/cpu.h> 54 #include <machine/bus.h> 55 56 #include <dev/vme/vmereg.h> 57 #include <dev/vme/vmevar.h> 58 59 #include <dev/mvme/mvmebus.h> 60 #include <dev/mvme/vme_tworeg.h> 61 #include <dev/mvme/vme_twovar.h> 62 63 /* 64 * Non-zero if there is no VMEChip2 on this board. 65 */ 66 int vmetwo_not_present; 67 68 /* 69 * Array of interrupt handlers registered with us for the non-VMEbus 70 * vectored interrupts. Eg. ABORT Switch, SYSFAIL etc. 71 * 72 * We can't just install a caller's handler directly, since these 73 * interrupts have to be manually cleared, so we have a trampoline 74 * which does the clearing automatically. 75 */ 76 static struct vme_two_handler { 77 int (*isr_hand) __P((void *)); 78 void *isr_arg; 79 } vme_two_handlers[(VME2_VECTOR_LOCAL_MAX - VME2_VECTOR_LOCAL_MIN) + 1]; 80 81 #define VMETWO_HANDLERS_SZ (sizeof(vme_two_handlers) / \ 82 sizeof(struct vme_two_handler)) 83 84 static int vmetwo_local_isr_trampoline(void *); 85 static void vmetwo_softintr_assert(void); 86 87 static struct vmetwo_softc *vmetwo_sc; 88 89 int 90 vmetwo_probe(bus_space_tag_t bt, bus_addr_t offset) 91 { 92 bus_space_handle_t bh; 93 94 bus_space_map(bt, offset + VME2REG_LCSR_OFFSET, VME2LCSR_SIZE, 0, &bh); 95 96 if (bus_space_peek_4(bt, bh, VME2LCSR_MISC_STATUS, NULL) != 0) { 97 #if defined(MVME162) || defined(MVME172) 98 #if defined(MVME167) || defined(MVME177) 99 if (machineid == MVME_162 || machineid == MVME_172) 100 #endif 101 { 102 /* 103 * No VMEChip2 on mvme162/172 is not too big a 104 * deal; we can fall back on timer4 in the 105 * mcchip for h/w assisted soft interrupts... 106 */ 107 extern void pcctwosoftintrinit(void); 108 bus_space_unmap(bt, bh, VME2LCSR_SIZE); 109 vmetwo_not_present = 1; 110 pcctwosoftintrinit(); 111 return (0); 112 } 113 #endif 114 #if defined(MVME167) || defined(MVME177) || defined(MVME88K) 115 /* 116 * No VMEChip2 on mvme167/177, however, is a Big Deal. 117 * In fact, it means the hardware's shot since the 118 * VMEChip2 is not a `build-option' on those boards. 119 */ 120 panic("VMEChip2 not responding! Faulty board?"); 121 /* NOTREACHED */ 122 #endif 123 #if defined(MVMEPPC) 124 /* 125 * No VMEChip2 on mvmeppc is no big deal. 126 */ 127 bus_space_unmap(bt, bh, VME2LCSR_SIZE); 128 vmetwo_not_present = 1; 129 return (0); 130 #endif 131 } 132 #if NVMETWO == 0 133 else { 134 /* 135 * The kernel config file has no `vmetwo0' device, but 136 * there is a VMEChip2 on the board. Fix up things 137 * just enough to hook VMEChip2 local interrupts. 138 */ 139 struct vmetwo_softc *sc; 140 141 /* XXX Should check sc != NULL here... */ 142 MALLOC(sc, struct vmetwo_softc *, sizeof(*sc), M_DEVBUF, 143 M_NOWAIT); 144 145 sc->sc_mvmebus.sc_bust = bt; 146 sc->sc_lcrh = bh; 147 vmetwo_intr_init(sc); 148 return 0; 149 } 150 #else 151 bus_space_unmap(bt, bh, VME2LCSR_SIZE); 152 return (1); 153 #endif 154 } 155 156 void 157 vmetwo_intr_init(struct vmetwo_softc *sc) 158 { 159 u_int32_t reg; 160 int i; 161 162 vmetwo_sc = sc; 163 164 /* Clear out the ISR handler array */ 165 for (i = 0; i < VMETWO_HANDLERS_SZ; i++) 166 vme_two_handlers[i].isr_hand = NULL; 167 168 /* 169 * Initialize the chip. 170 * Firstly, disable all VMEChip2 Interrupts 171 */ 172 reg = vme2_lcsr_read(sc, VME2LCSR_MISC_STATUS) & ~VME2_MISC_STATUS_MIEN; 173 vme2_lcsr_write(sc, VME2LCSR_MISC_STATUS, reg); 174 vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE, 0); 175 vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR, 176 VME2_LOCAL_INTERRUPT_CLEAR_ALL); 177 178 /* Zap all the IRQ level registers */ 179 for (i = 0; i < VME2_NUM_IL_REGS; i++) 180 vme2_lcsr_write(sc, VME2LCSR_INTERRUPT_LEVEL_BASE + (i * 4), 0); 181 182 /* Disable the tick timers */ 183 reg = vme2_lcsr_read(sc, VME2LCSR_TIMER_CONTROL); 184 reg &= ~VME2_TIMER_CONTROL_EN(0); 185 reg &= ~VME2_TIMER_CONTROL_EN(1); 186 vme2_lcsr_write(sc, VME2LCSR_TIMER_CONTROL, reg); 187 188 /* Set the VMEChip2's vector base register to the required value */ 189 reg = vme2_lcsr_read(sc, VME2LCSR_VECTOR_BASE); 190 reg &= ~VME2_VECTOR_BASE_MASK; 191 reg |= VME2_VECTOR_BASE_REG_VALUE; 192 vme2_lcsr_write(sc, VME2LCSR_VECTOR_BASE, reg); 193 194 /* Set the Master Interrupt Enable bit now */ 195 reg = vme2_lcsr_read(sc, VME2LCSR_MISC_STATUS) | VME2_MISC_STATUS_MIEN; 196 vme2_lcsr_write(sc, VME2LCSR_MISC_STATUS, reg); 197 198 /* Allow the MD code the chance to do some initialising */ 199 vmetwo_md_intr_init(sc); 200 201 #if defined(MVME167) || defined(MVME177) 202 #if defined(MVME162) || defined(MVME172) 203 if (machineid != MVME_162 && machineid != MVME_172) 204 #endif 205 { 206 /* 207 * Let the NMI handler deal with level 7 ABORT switch 208 * interrupts 209 */ 210 vmetwo_intr_establish(sc, 7, 7, VME2_VEC_ABORT, 1, 211 nmihand, NULL, NULL); 212 } 213 #endif 214 215 /* Setup hardware assisted soft interrupts */ 216 vmetwo_intr_establish(sc, 1, 1, VME2_VEC_SOFT0, 1, 217 (int (*)(void *))softintr_dispatch, NULL, NULL); 218 _softintr_chipset_assert = vmetwo_softintr_assert; 219 } 220 221 static int 222 vmetwo_local_isr_trampoline(arg) 223 void *arg; 224 { 225 struct vme_two_handler *isr; 226 int vec; 227 228 vec = (int) arg; /* 0x08 <= vec <= 0x1f */ 229 230 /* Clear the interrupt source */ 231 vme2_lcsr_write(vmetwo_sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR, 232 VME2_LOCAL_INTERRUPT(vec)); 233 234 isr = &vme_two_handlers[vec - VME2_VECTOR_LOCAL_OFFSET]; 235 if (isr->isr_hand) 236 (void) (*isr->isr_hand) (isr->isr_arg); 237 else 238 printf("vmetwo: Spurious local interrupt, vector 0x%x\n", vec); 239 240 return (1); 241 } 242 243 void 244 vmetwo_local_intr_establish(pri, vec, hand, arg, evcnt) 245 int pri, vec; 246 int (*hand)(void *); 247 void *arg; 248 struct evcnt *evcnt; 249 { 250 251 vmetwo_intr_establish(vmetwo_sc, pri, pri, vec, 1, hand, arg, evcnt); 252 } 253 254 /* ARGSUSED */ 255 void 256 vmetwo_intr_establish(csc, prior, lvl, vec, first, hand, arg, evcnt) 257 void *csc; 258 int prior, lvl, vec, first; 259 int (*hand)(void *); 260 void *arg; 261 struct evcnt *evcnt; 262 { 263 struct vmetwo_softc *sc = csc; 264 u_int32_t reg; 265 int bitoff; 266 int iloffset, ilshift; 267 int s; 268 269 s = splhigh(); 270 271 #if NVMETWO > 0 272 /* 273 * Sort out interrupts generated locally by the VMEChip2 from 274 * those generated by VMEbus devices... 275 */ 276 if (vec >= VME2_VECTOR_LOCAL_MIN && vec <= VME2_VECTOR_LOCAL_MAX) { 277 #endif 278 /* 279 * Local interrupts need to be bounced through some 280 * trampoline code which acknowledges/clears them. 281 */ 282 vme_two_handlers[vec - VME2_VECTOR_LOCAL_MIN].isr_hand = hand; 283 vme_two_handlers[vec - VME2_VECTOR_LOCAL_MIN].isr_arg = arg; 284 hand = vmetwo_local_isr_trampoline; 285 arg = (void *) (vec - VME2_VECTOR_BASE); 286 287 /* 288 * Interrupt enable/clear bit offset is 0x08 - 0x1f 289 */ 290 bitoff = vec - VME2_VECTOR_BASE; 291 #if NVMETWO > 0 292 first = 1; /* Force the interrupt to be enabled */ 293 } else { 294 /* 295 * Interrupts originating from the VMEbus are 296 * controlled by an offset of 0x00 - 0x07 297 */ 298 bitoff = lvl - 1; 299 } 300 #endif 301 302 /* Hook the interrupt */ 303 (*sc->sc_isrlink)(sc->sc_isrcookie, hand, arg, prior, vec, evcnt); 304 305 /* 306 * Do we need to tell the VMEChip2 to let the interrupt through? 307 * (This is always true for locally-generated interrupts, but only 308 * needs doing once for each VMEbus interrupt level which is hooked) 309 */ 310 #if NVMETWO > 0 311 if (first) { 312 if (evcnt) 313 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 314 (*sc->sc_isrevcnt)(sc->sc_isrcookie, prior), 315 sc->sc_mvmebus.sc_dev.dv_xname, 316 mvmebus_irq_name[lvl]); 317 #endif 318 iloffset = VME2_ILOFFSET_FROM_VECTOR(bitoff) + 319 VME2LCSR_INTERRUPT_LEVEL_BASE; 320 ilshift = VME2_ILSHIFT_FROM_VECTOR(bitoff); 321 322 /* Program the specified interrupt to signal at 'prior' */ 323 reg = vme2_lcsr_read(sc, iloffset); 324 reg &= ~(VME2_INTERRUPT_LEVEL_MASK << ilshift); 325 reg |= (prior << ilshift); 326 vme2_lcsr_write(sc, iloffset, reg); 327 328 /* Clear it */ 329 vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR, 330 VME2_LOCAL_INTERRUPT(bitoff)); 331 332 /* Enable it. */ 333 reg = vme2_lcsr_read(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE); 334 reg |= VME2_LOCAL_INTERRUPT(bitoff); 335 vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE, reg); 336 #if NVMETWO > 0 337 } 338 #ifdef DIAGNOSTIC 339 else { 340 /* Verify the interrupt priority is the same */ 341 iloffset = VME2_ILOFFSET_FROM_VECTOR(bitoff) + 342 VME2LCSR_INTERRUPT_LEVEL_BASE; 343 ilshift = VME2_ILSHIFT_FROM_VECTOR(bitoff); 344 345 reg = vme2_lcsr_read(sc, iloffset); 346 reg &= (VME2_INTERRUPT_LEVEL_MASK << ilshift); 347 348 if ((prior << ilshift) != reg) 349 panic("vmetwo_intr_establish: priority mismatch!"); 350 } 351 #endif 352 #endif 353 splx(s); 354 } 355 356 void 357 vmetwo_intr_disestablish(csc, lvl, vec, last, evcnt) 358 void *csc; 359 int lvl, vec, last; 360 struct evcnt *evcnt; 361 { 362 struct vmetwo_softc *sc = csc; 363 u_int32_t reg; 364 int iloffset, ilshift; 365 int bitoff; 366 int s; 367 368 s = splhigh(); 369 370 #if NVMETWO > 0 371 /* 372 * Sort out interrupts generated locally by the VMEChip2 from 373 * those generated by VMEbus devices... 374 */ 375 if (vec >= VME2_VECTOR_LOCAL_MIN && vec <= VME2_VECTOR_LOCAL_MAX) { 376 #endif 377 /* 378 * Interrupt enable/clear bit offset is 0x08 - 0x1f 379 */ 380 bitoff = vec - VME2_VECTOR_BASE; 381 vme_two_handlers[vec - VME2_VECTOR_LOCAL_MIN].isr_hand = NULL; 382 last = 1; /* Force the interrupt to be cleared */ 383 #if NVMETWO > 0 384 } else { 385 /* 386 * Interrupts originating from the VMEbus are 387 * controlled by an offset of 0x00 - 0x07 388 */ 389 bitoff = lvl - 1; 390 } 391 #endif 392 393 /* 394 * Do we need to tell the VMEChip2 to block the interrupt? 395 * (This is always true for locally-generated interrupts, but only 396 * needs doing once when the last VMEbus handler for any given level 397 * has been unhooked.) 398 */ 399 if (last) { 400 iloffset = VME2_ILOFFSET_FROM_VECTOR(bitoff) + 401 VME2LCSR_INTERRUPT_LEVEL_BASE; 402 ilshift = VME2_ILSHIFT_FROM_VECTOR(bitoff); 403 404 /* Disable it. */ 405 reg = vme2_lcsr_read(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE); 406 reg &= ~VME2_LOCAL_INTERRUPT(bitoff); 407 vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE, reg); 408 409 /* Set the interrupt's level to zero */ 410 reg = vme2_lcsr_read(sc, iloffset); 411 reg &= ~(VME2_INTERRUPT_LEVEL_MASK << ilshift); 412 vme2_lcsr_write(sc, iloffset, reg); 413 414 /* Clear it */ 415 vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR, 416 VME2_LOCAL_INTERRUPT(vec)); 417 418 if (evcnt) 419 evcnt_detach(evcnt); 420 } 421 /* Un-hook it */ 422 (*sc->sc_isrunlink)(sc->sc_isrcookie, vec); 423 424 splx(s); 425 } 426 427 static void 428 vmetwo_softintr_assert(void) 429 { 430 431 vme2_lcsr_write(vmetwo_sc, VME2LCSR_SOFTINT_SET, VME2_SOFTINT_SET(0)); 432 } 433