1 /* $NetBSD: vme_tworeg.h,v 1.1 2002/02/12 20:38:51 scw Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _MVME_VME_TWOREG_H 40 #define _MVME_VME_TWOREG_H 41 42 /* 43 * Where the VMEchip2's registers live relative to the start 44 * of the VMEChip2's register space. 45 */ 46 #define VME2REG_LCSR_OFFSET 0x0000 47 #define VME2REG_GCSR_OFFSET 0x0100 48 49 50 /* 51 * Register map of the Type 2 VMEchip found on many MVME boards. 52 * Note: Only responds to D32 accesses. 53 */ 54 55 /* 56 * Slave window configuration registers 57 */ 58 #define VME2_SLAVE_WINDOWS 2 59 #define VME2LCSR_SLAVE_ADDRESS(x) (0x00 + ((x) * 4)) 60 #define VME2_SLAVE_ADDRESS_START_SHIFT 16 61 #define VME2_SLAVE_ADDRESS_START_MASK (0x0000ffffu) 62 #define VME2_SLAVE_ADDRESS_END_SHIFT 0 63 #define VME2_SLAVE_ADDRESS_END_MASK (0xffff0000u) 64 65 #define VME2LCSR_SLAVE_TRANS(x) (0x08 + ((x) * 4)) 66 #define VME2_SLAVE_TRANS_SELECT_SHIFT 16 67 #define VME2_SLAVE_TRANS_SELECT_MASK (0x0000ffffu) 68 #define VME2_SLAVE_TRANS_ADDRESS_SHIFT 0 69 #define VME2_SLAVE_TRANS_ADDRESS_MASK (0xffff0000u) 70 71 #define VME2LCSR_SLAVE_CTRL 0x10 72 #define VME2_SLAVE_AMSEL_DAT(x) (1u << (0 + ((x) * 16))) 73 #define VME2_SLAVE_AMSEL_PGM(x) (1u << (1 + ((x) * 16))) 74 #define VME2_SLAVE_AMSEL_BLK(x) (1u << (2 + ((x) * 16))) 75 #define VME2_SLAVE_AMSEL_BLKD64(x) (1u << (3 + ((x) * 16))) 76 #define VME2_SLAVE_AMSEL_A24(x) (1u << (4 + ((x) * 16))) 77 #define VME2_SLAVE_AMSEL_A32(x) (1u << (5 + ((x) * 16))) 78 #define VME2_SLAVE_AMSEL_USR(x) (1u << (6 + ((x) * 16))) 79 #define VME2_SLAVE_AMSEL_SUP(x) (1u << (7 + ((x) * 16))) 80 #define VME2_SLAVE_CTRL_WP(x) (1u << (8 + ((x) * 16))) 81 #define VME2_SLAVE_CTRL_SNOOP_INHIBIT(x) (0u << (9 + ((x) * 16))) 82 #define VME2_SLAVE_CTRL_SNOOP_WRSINK(x) (1u << (9 + ((x) * 16))) 83 #define VME2_SLAVE_CTRL_SNOOP_WRINVAL(x) (2u << (9 + ((x) * 16))) 84 #define VME2_SLAVE_CTRL_ADDER(x) (1u << (11 + ((x) * 16))) 85 86 /* 87 * Master window address control registers 88 */ 89 #define VME2_MASTER_WINDOWS 4 90 #define VME2LCSR_MASTER_ADDRESS(x) (0x14 + ((x) * 4)) 91 #define VME2_MAST_ADDRESS_START_SHIFT 16 92 #define VME2_MAST_ADDRESS_START_MASK (0x0000ffffu) 93 #define VME2_MAST_ADDRESS_END_SHIFT 0 94 #define VME2_MAST_ADDRESS_END_MASK (0xffff0000u) 95 96 #define VME2LCSR_MAST4_TRANS 0x24 97 #define VME2_MAST4_TRANS_SELECT_SHIFT 16 98 #define VME2_MAST4_TRANS_SELECT_MASK (0x0000ffffu) 99 #define VME2_MAST4_TRANS_ADDRESS_SHIFT 0 100 #define VME2_MAST4_TRANS_ADDRESS_MASK (0xffff0000u) 101 102 /* 103 * VMEbus master attribute control register 104 */ 105 #define VME2LCSR_MASTER_ATTR 0x28 106 #define VME2_MASTER_ATTR_AM_SHIFT(x) ((x) * 8) 107 #define VME2_MASTER_ATTR_AM_MASK (0x0000003fu) 108 #define VME2_MASTER_ATTR_WP (1u << 6) 109 #define VME2_MASTER_ATTR_D16 (1u << 7) 110 111 /* 112 * GCSR Group/Board addresses, and 113 * VMEbus Master Enable Control register, and 114 * Local to VMEbus I/O Control register, and 115 * ROM Control register (unused). 116 */ 117 #define VME2LCSR_GCSR_ADDRESS 0x2c 118 #define VME2_GCSR_ADDRESS_SHIFT 16 119 #define VME2_GCSR_ADDRESS_MASK (0xfff00000u) 120 121 #define VME2LCSR_MASTER_ENABLE 0x2c 122 #define VME2_MASTER_ENABLE_MASK (0x000f0000u) 123 #define VME2_MASTER_ENABLE(x) (1u << ((x) + 16)) 124 125 #define VME2LCSR_IO_CONTROL 0x2c 126 #define VME2_IO_CONTROL_SHIFT 8 127 #define VME2_IO_CONTROL_MASK (0x0000ff00u) 128 #define VME2_IO_CONTROL_I1SU (1u << 8) 129 #define VME2_IO_CONTROL_I1WP (1u << 9) 130 #define VME2_IO_CONTROL_I1D16 (1u << 10) 131 #define VME2_IO_CONTROL_I1EN (1u << 11) 132 #define VME2_IO_CONTROL_I2PD (1u << 12) 133 #define VME2_IO_CONTROL_I2SU (1u << 13) 134 #define VME2_IO_CONTROL_I2WP (1u << 14) 135 #define VME2_IO_CONTROL_I2EN (1u << 15) 136 137 /* 138 * VMEChip2 PROM Decoder, SRAM and DMA Control register 139 */ 140 #define VME2LCSR_PROM_SRAM_DMA_CTRL 0x30 141 #define VME2_PSD_SRAMS_MASK (0x00ff0000u) 142 #define VME2_PSD_SRAMS_CLKS6 (0u << 16) 143 #define VME2_PSD_SRAMS_CLKS5 (1u << 16) 144 #define VME2_PSD_SRAMS_CLKS4 (2u << 16) 145 #define VME2_PSD_SRAMS_CLKS3 (3u << 16) 146 #define VME2_PSD_TBLSC_INHIB (0u << 18) 147 #define VME2_PSD_TBLSC_WRSINK (1u << 18) 148 #define VME2_PSD_TBLSC_WRINV (2u << 18) 149 #define VME2_PSD_ROM0 (1u << 20) 150 #define VME2_PSD_WAITRMW (1u << 21) 151 152 /* 153 * VMEbus requester control register 154 */ 155 #define VME2LCSR_VME_REQUESTER_CONTROL 0x30 156 #define VME2_VMEREQ_CTRL_MASK (0x0000ff00u) 157 #define VME2_VMEREQ_CTRL_LVREQL_MASK (0x00000300u) 158 #define VME2_VMEREQ_CTRL_LVREQL(x) ((u_int)(x) << 8) 159 #define VME2_VMEREQ_CTRL_LVRWD (1u << 10) 160 #define VME2_VMEREQ_CTRL_LVFAIR (1u << 11) 161 #define VME2_VMEREQ_CTRL_DWB (1u << 13) 162 #define VME2_VMEREQ_CTRL_DHB (1u << 14) 163 #define VME2_VMEREQ_CTRL_ROBN (1u << 15) 164 165 /* 166 * DMAC control register 167 */ 168 #define VME2LCSR_DMAC_CONTROL1 0x30 169 #define VME2_DMAC_CTRL1_MASK (0x000000ffu) 170 #define VME2_DMAC_CTRL1_DREQL_MASK (0x00000003u) 171 #define VME2_DMAC_CTRL1_DREQL(x) ((u_int)(x) << 0) 172 #define VME2_DMAC_CTRL1_DRELM_MASK (0x0000000cu) 173 #define VME2_DMAC_CTRL1_DRELM(x) ((u_int)(x) << 2) 174 #define VME2_DMAC_CTRL1_DFAIR (1u << 4) 175 #define VME2_DMAC_CTRL1_DTBL (1u << 5) 176 #define VME2_DMAC_CTRL1_DEN (1u << 6) 177 #define VME2_DMAC_CTRL1_DHALT (1u << 7) 178 179 /* 180 * DMA Control register #2 181 */ 182 #define VME2LCSR_DMAC_CONTROL2 0x34 183 #define VME2_DMAC_CTRL2_MASK (0x0000ffffu) 184 #define VME2_DMAC_CTRL2_SHIFT 0 185 #define VME2_DMAC_CTRL2_AM_MASK (0x0000003fu) 186 #define VME2_DMAC_CTRL2_BLK_D32 (1u << 6) 187 #define VME2_DMAC_CTRL2_BLK_D64 (3u << 6) 188 #define VME2_DMAC_CTRL2_D16 (1u << 8) 189 #define VME2_DMAC_CTRL2_TVME (1u << 9) 190 #define VME2_DMAC_CTRL2_LINC (1u << 10) 191 #define VME2_DMAC_CTRL2_VINC (1u << 11) 192 #define VME2_DMAC_CTRL2_SNOOP_INHIB (0u << 13) 193 #define VME2_DMAC_CTRL2_SNOOP_WRSNK (1u << 13) 194 #define VME2_DMAC_CTRL2_SNOOP_WRINV (2u << 13) 195 #define VME2_DMAC_CTRL2_INTE (1u << 15) 196 197 /* 198 * DMA Controller Local Bus and VMEbus Addresses, Byte 199 * Counter and Table Address Counter registers 200 */ 201 #define VME2LCSR_DMAC_LOCAL_ADDRESS 0x38 202 #define VME2LCSR_DMAC_VME_ADDRESS 0x3c 203 #define VME2LCSR_DMAC_BYTE_COUNTER 0x40 204 #define VME2LCSR_DMAC_TABLE_ADDRESS 0x44 205 206 /* 207 * VMEbus Interrupter Control register 208 */ 209 #define VME2LCSR_INTERRUPT_CONTROL 0x48 210 #define VME2_INT_CTRL_MASK (0xff000000u) 211 #define VME2_INT_CTRL_SHIFT 24 212 #define VME2_INT_CTRL_IRQL_MASK (0x07000000u) 213 #define VME2_INT_CTRL_IRQS (1u << 27) 214 #define VME2_INT_CTRL_IRQC (1u << 28) 215 #define VME2_INT_CTRL_IRQ1S_INT (0u << 29) 216 #define VME2_INT_CTRL_IRQ1S_TICK1 (1u << 29) 217 #define VME2_INT_CTRL_IRQ1S_TICK2 (3u << 29) 218 219 /* 220 * VMEbus Interrupt Vector register 221 */ 222 #define VME2LCSR_INTERRUPT_VECTOR 0x48 223 #define VME2_INTERRUPT_VECTOR_MASK (0x00ff0000u) 224 #define VME2_INTERRUPT_VECTOR_SHIFT 16 225 226 /* 227 * MPU Status register 228 */ 229 #define VME2LCSR_MPU_STATUS 0x48 230 #define VME2_MPU_STATUS_MLOB (1u << 0) 231 #define VME2_MPU_STATUS_MLPE (1u << 1) 232 #define VME2_MPU_STATUS_MLBE (1u << 2) 233 #define VME2_MPU_STATUS_MCLR (1u << 3) 234 235 /* 236 * DMA Interrupt Count register 237 */ 238 #define VME2LCSR_DMAC_INTERRUPT_CONTROL 0x48 239 #define VME2_DMAC_INT_COUNT_MASK (0x0000f000u) 240 #define VME2_DMAC_INT_COUNT_SHIFT 12 241 242 /* 243 * DMA Controller Status register 244 */ 245 #define VME2LCSR_DMAC_STATUS 0x48 246 #define VME2_DMAC_STATUS_DONE (1u << 0) 247 #define VME2_DMAC_STATUS_VME (1u << 1) 248 #define VME2_DMAC_STATUS_TBL (1u << 2) 249 #define VME2_DMAC_STATUS_DLTO (1u << 3) 250 #define VME2_DMAC_STATUS_DLOB (1u << 4) 251 #define VME2_DMAC_STATUS_DLPE (1u << 5) 252 #define VME2_DMAC_STATUS_DLBE (1u << 6) 253 #define VME2_DMAC_STATUS_MLTO (1u << 7) 254 255 256 /* 257 * VMEbus Arbiter Time-out register 258 */ 259 #define VME2LCSR_VME_ARB_TIMEOUT 0x4c 260 #define VME2_VME_ARB_TIMEOUT_ENAB (1u << 24) 261 262 /* 263 * DMA Controller Timers and VMEbus Global Time-out Control registers 264 */ 265 #define VME2LCSR_DMAC_TIME_ONOFF 0x4c 266 #define VME2_DMAC_TIME_ON_MASK (0x001c0000u) 267 #define VME2_DMAC_TIME_ON_16US (0u << 18) 268 #define VME2_DMAC_TIME_ON_32US (1u << 18) 269 #define VME2_DMAC_TIME_ON_64US (2u << 18) 270 #define VME2_DMAC_TIME_ON_128US (3u << 18) 271 #define VME2_DMAC_TIME_ON_256US (4u << 18) 272 #define VME2_DMAC_TIME_ON_512US (5u << 18) 273 #define VME2_DMAC_TIME_ON_1024US (6u << 18) 274 #define VME2_DMAC_TIME_ON_DONE (7u << 18) 275 #define VME2_DMAC_TIME_OFF_MASK (0x00e00000u) 276 #define VME2_DMAC_TIME_OFF_0US (0u << 21) 277 #define VME2_DMAC_TIME_OFF_16US (1u << 21) 278 #define VME2_DMAC_TIME_OFF_32US (2u << 21) 279 #define VME2_DMAC_TIME_OFF_64US (3u << 21) 280 #define VME2_DMAC_TIME_OFF_128US (4u << 21) 281 #define VME2_DMAC_TIME_OFF_256US (5u << 21) 282 #define VME2_DMAC_TIME_OFF_512US (6u << 21) 283 #define VME2_DMAC_TIME_OFF_1024US (7u << 21) 284 #define VME2_VME_GLOBAL_TO_MASK (0x00030000u) 285 #define VME2_VME_GLOBAL_TO_8US (0u << 16) 286 #define VME2_VME_GLOBAL_TO_16US (1u << 16) 287 #define VME2_VME_GLOBAL_TO_256US (2u << 16) 288 #define VME2_VME_GLOBAL_TO_DISABLE (3u << 16) 289 290 /* 291 * VME Access, Local Bus and Watchdog Time-out Control register 292 */ 293 #define VME2LCSR_VME_ACCESS_TIMEOUT 0x4c 294 #define VME2_VME_ACCESS_TIMEOUT_MASK (0x0000c000u) 295 #define VME2_VME_ACCESS_TIMEOUT_64US (0u << 14) 296 #define VME2_VME_ACCESS_TIMEOUT_1MS (1u << 14) 297 #define VME2_VME_ACCESS_TIMEOUT_32MS (2u << 14) 298 #define VME2_VME_ACCESS_TIMEOUT_DISABLE (3u << 14) 299 300 #define VME2LCSR_LOCAL_BUS_TIMEOUT 0x4c 301 #define VME2_LOCAL_BUS_TIMEOUT_MASK (0x00003000u) 302 #define VME2_LOCAL_BUS_TIMEOUT_64US (0u << 12) 303 #define VME2_LOCAL_BUS_TIMEOUT_1MS (1u << 12) 304 #define VME2_LOCAL_BUS_TIMEOUT_32MS (2u << 12) 305 #define VME2_LOCAL_BUS_TIMEOUT_DISABLE (3u << 12) 306 307 #define VME2LCSR_WATCHDOG_TIMEOUT 0x4c 308 #define VME2_WATCHDOG_TIMEOUT_MASK (0x00000f00u) 309 #define VME2_WATCHDOG_TIMEOUT_512US (0u << 8) 310 #define VME2_WATCHDOG_TIMEOUT_1MS (1u << 8) 311 #define VME2_WATCHDOG_TIMEOUT_2MS (2u << 8) 312 #define VME2_WATCHDOG_TIMEOUT_4MS (3u << 8) 313 #define VME2_WATCHDOG_TIMEOUT_8MS (4u << 8) 314 #define VME2_WATCHDOG_TIMEOUT_16MS (5u << 8) 315 #define VME2_WATCHDOG_TIMEOUT_32MS (6u << 8) 316 #define VME2_WATCHDOG_TIMEOUT_64MS (7u << 8) 317 #define VME2_WATCHDOG_TIMEOUT_128MS (8u << 8) 318 #define VME2_WATCHDOG_TIMEOUT_256MS (9u << 8) 319 #define VME2_WATCHDOG_TIMEOUT_512MS (10u << 8) 320 #define VME2_WATCHDOG_TIMEOUT_1S (11u << 8) 321 #define VME2_WATCHDOG_TIMEOUT_4S (12u << 8) 322 #define VME2_WATCHDOG_TIMEOUT_16S (13u << 8) 323 #define VME2_WATCHDOG_TIMEOUT_32S (14u << 8) 324 #define VME2_WATCHDOG_TIMEOUT_64S (15u << 8) 325 326 /* 327 * Prescaler Control register 328 */ 329 #define VME2LCSR_PRESCALER_CONTROL 0x4c 330 #define VME2_PRESCALER_MASK (0x000000ffu) 331 #define VME2_PRESCALER_SHIFT 0 332 #define VME2_PRESCALER_CTRL(c) (256 - (c)) 333 334 /* 335 * Tick Timer registers 336 */ 337 #define VME2LCSR_TIMER_COMPARE(x) (0x50 + ((x) * 8)) 338 #define VME2LCSR_TIMER_COUNTER(x) (0x54 + ((x) * 8)) 339 340 341 /* 342 * Board Control register 343 */ 344 #define VME2LCSR_BOARD_CONTROL 0x60 345 #define VME2_BOARD_CONTROL_RSWE (1u << 24) 346 #define VME2_BOARD_CONTROL_BDFLO (1u << 25) 347 #define VME2_BOARD_CONTROL_CPURS (1u << 26) 348 #define VME2_BOARD_CONTROL_PURS (1u << 27) 349 #define VME2_BOARD_CONTROL_BRFLI (1u << 28) 350 #define VME2_BOARD_CONTROL_SFFL (1u << 29) 351 #define VME2_BOARD_CONTROL_SCON (1u << 30) 352 353 /* 354 * Watchdog Timer Control register 355 */ 356 #define VME2LCSR_WATCHDOG_TIMER_CONTROL 0x60 357 #define VME2_WATCHDOG_TCONTROL_WDEN (1u << 16) 358 #define VME2_WATCHDOG_TCONTTRL_WDRSE (1u << 17) 359 #define VME2_WATCHDOG_TCONTTRL_WDSL (1u << 18) 360 #define VME2_WATCHDOG_TCONTTRL_WDBFE (1u << 19) 361 #define VME2_WATCHDOG_TCONTTRL_WDTO (1u << 20) 362 #define VME2_WATCHDOG_TCONTTRL_WDCC (1u << 21) 363 #define VME2_WATCHDOG_TCONTTRL_WDCS (1u << 22) 364 #define VME2_WATCHDOG_TCONTTRL_SRST (1u << 23) 365 366 /* 367 * Tick Timer Control registers 368 */ 369 #define VME2LCSR_TIMER_CONTROL 0x60 370 #define VME2_TIMER_CONTROL_EN(x) (1u << (0 + ((x) * 8))) 371 #define VME2_TIMER_CONTROL_COC(x) (1u << (1 + ((x) * 8))) 372 #define VME2_TIMER_CONTROL_COF(x) (1u << (2 + ((x) * 8))) 373 #define VME2_TIMER_CONTROL_OVF_SHIFT(x) (4 + ((x) * 8)) 374 #define VME2_TIMER_CONTROL_OVF_MASK(x) (0x000000f0u << (4 + ((x) * 8))) 375 376 /* 377 * Prescaler Counter register 378 */ 379 #define VME2LCSR_PRESCALER_COUNTER 0x64 380 381 /* 382 * Local Bus Interrupter Status/Enable/Clear registers 383 */ 384 #define VME2LCSR_LOCAL_INTERRUPT_STATUS 0x68 385 #define VME2LCSR_LOCAL_INTERRUPT_ENABLE 0x6c 386 #define VME2LCSR_LOCAL_INTERRUPT_CLEAR 0x74 387 #define VME2_LOCAL_INTERRUPT(x) (1u << (x)) 388 #define VME2_LOCAL_INTERRUPT_VME(x) (1u << ((x) - 1)) 389 #define VME2_LOCAL_INTERRUPT_SWINT(x) (1u << ((x) + 8)) 390 #define VME2_LOCAL_INTERRUPT_LM(x) (1u << ((x) + 16)) 391 #define VME2_LOCAL_INTERRUPT_SIG(x) (1u << ((x) + 18)) 392 #define VME2_LOCAL_INTERRUPT_DMAC (1u << 22) 393 #define VME2_LOCAL_INTERRUPT_VIA (1u << 23) 394 #define VME2_LOCAL_INTERRUPT_TIC(x) (1u << ((x) + 24)) 395 #define VME2_LOCAL_INTERRUPT_VI1E (1u << 26) 396 #define VME2_LOCAL_INTERRUPT_PE (1u << 27) 397 #define VME2_LOCAL_INTERRUPT_MWP (1u << 28) 398 #define VME2_LOCAL_INTERRUPT_SYSF (1u << 29) 399 #define VME2_LOCAL_INTERRUPT_ABORT (1u << 30) 400 #define VME2_LOCAL_INTERRUPT_ACFAIL (1u << 31) 401 #define VME2_LOCAL_INTERRUPT_CLEAR_ALL (0xffffff00u) 402 403 /* 404 * Software Interrupt Set register 405 */ 406 #define VME2LCSR_SOFTINT_SET 0x70 407 #define VME2_SOFTINT_SET(x) (1u << ((x) + 8)) 408 409 /* 410 * Interrupt Level registers 411 */ 412 #define VME2LCSR_INTERRUPT_LEVEL_BASE 0x78 413 #define VME2_NUM_IL_REGS 4 414 #define VME2_ILOFFSET_FROM_VECTOR(v) (((((VME2_NUM_IL_REGS*8)-1)-(v))/8)<<2) 415 #define VME2_ILSHIFT_FROM_VECTOR(v) (((v) & 7) * 4) 416 #define VME2_INTERRUPT_LEVEL_MASK (0x0fu) 417 418 /* 419 * Vector Base register 420 */ 421 #define VME2LCSR_VECTOR_BASE 0x88 422 #define VME2_VECTOR_BASE_MASK (0xff000000u) 423 #define VME2_VECTOR_BASE_REG_VALUE (0x76000000u) 424 #define VME2_VECTOR_BASE (0x60u) 425 #define VME2_VECTOR_LOCAL_OFFSET (0x08u) 426 #define VME2_VECTOR_LOCAL_MIN (VME2_VECTOR_BASE + 0x08u) 427 #define VME2_VECTOR_LOCAL_MAX (VME2_VECTOR_BASE + 0x1fu) 428 #define VME2_VEC_SOFT0 (VME2_VECTOR_BASE + 0x08u) 429 #define VME2_VEC_SOFT1 (VME2_VECTOR_BASE + 0x09u) 430 #define VME2_VEC_SOFT2 (VME2_VECTOR_BASE + 0x0au) 431 #define VME2_VEC_SOFT3 (VME2_VECTOR_BASE + 0x0bu) 432 #define VME2_VEC_SOFT4 (VME2_VECTOR_BASE + 0x0cu) 433 #define VME2_VEC_SOFT5 (VME2_VECTOR_BASE + 0x0du) 434 #define VME2_VEC_SOFT6 (VME2_VECTOR_BASE + 0x0eu) 435 #define VME2_VEC_SOFT7 (VME2_VECTOR_BASE + 0x0fu) 436 #define VME2_VEC_GCSRLM0 (VME2_VECTOR_BASE + 0x10u) 437 #define VME2_VEC_GCSRLM1 (VME2_VECTOR_BASE + 0x11u) 438 #define VME2_VEC_GCSRSIG0 (VME2_VECTOR_BASE + 0x12u) 439 #define VME2_VEC_GCSRSIG1 (VME2_VECTOR_BASE + 0x13u) 440 #define VME2_VEC_GCSRSIG2 (VME2_VECTOR_BASE + 0x14u) 441 #define VME2_VEC_GCSRSIG3 (VME2_VECTOR_BASE + 0x15u) 442 #define VME2_VEC_DMAC (VME2_VECTOR_BASE + 0x16u) 443 #define VME2_VEC_VIA (VME2_VECTOR_BASE + 0x17u) 444 #define VME2_VEC_TT1 (VME2_VECTOR_BASE + 0x18u) 445 #define VME2_VEC_TT2 (VME2_VECTOR_BASE + 0x19u) 446 #define VME2_VEC_IRQ1 (VME2_VECTOR_BASE + 0x1au) 447 #define VME2_VEC_PARITY_ERROR (VME2_VECTOR_BASE + 0x1bu) 448 #define VME2_VEC_MWP_ERROR (VME2_VECTOR_BASE + 0x1cu) 449 #define VME2_VEC_SYSFAIL (VME2_VECTOR_BASE + 0x1du) 450 #define VME2_VEC_ABORT (VME2_VECTOR_BASE + 0x1eu) 451 #define VME2_VEC_ACFAIL (VME2_VECTOR_BASE + 0x1fu) 452 453 /* 454 * I/O Control register #1 455 */ 456 #define VME2LCSR_GPIO_DIRECTION 0x88 457 #define VME2_GPIO_DIRECTION_OUT(x) (1u << ((x) + 16)) 458 459 /* 460 * Misc. Status register 461 */ 462 #define VME2LCSR_MISC_STATUS 0x88 463 #define VME2_MISC_STATUS_ABRTL (1u << 20) 464 #define VME2_MISC_STATUS_ACFL (1u << 21) 465 #define VME2_MISC_STATUS_SYSFL (1u << 22) 466 #define VME2_MISC_STATUS_MIEN (1u << 23) 467 468 /* 469 * GPIO Status register 470 */ 471 #define VME2LCSR_GPIO_STATUS 0x88 472 #define VME2_GPIO_STATUS(x) (1u << ((x) + 8)) 473 474 /* 475 * GPIO Control register #2 476 */ 477 #define VME2LCSR_GPIO_CONTROL 0x88 478 #define VME2_GPIO_CONTROL_SET(x) (1u << ((x) + 12)) 479 480 /* 481 * General purpose input registers 482 */ 483 #define VME2LCSR_GP_INPUTS 0x88 484 #define VME2_GP_INPUT(x) (1u << (x)) 485 486 /* 487 * Miscellaneous Control register 488 */ 489 #define VME2LCSR_MISC_CONTROL 0x8c 490 #define VME2_MISC_CONTROL_DISBGN (1u << 0) 491 #define VME2_MISC_CONTROL_ENINT (1u << 1) 492 #define VME2_MISC_CONTROL_DISBSYT (1u << 2) 493 #define VME2_MISC_CONTROL_NOELBBSY (1u << 3) 494 #define VME2_MISC_CONTROL_DISMST (1u << 4) 495 #define VME2_MISC_CONTROL_DISSRAM (1u << 5) 496 #define VME2_MISC_CONTROL_REVEROM (1u << 6) 497 #define VME2_MISC_CONTROL_MPIRQEN (1u << 7) 498 499 #define VME2LCSR_SIZE 0x90 500 501 502 #define vme2_lcsr_read(s,r) \ 503 bus_space_read_4((s)->sc_mvmebus.sc_bust, (s)->sc_lcrh, (r)) 504 #define vme2_lcsr_write(s,r,v) \ 505 bus_space_write_4((s)->sc_mvmebus.sc_bust, (s)->sc_lcrh, (r), (v)) 506 507 508 /* 509 * Locations of the three fixed VMEbus I/O ranges 510 */ 511 #define VME2_IO0_LOCAL_START (0xffff0000u) 512 #define VME2_IO0_MASK (0x0000ffffu) 513 #define VME2_IO0_VME_START (0x00000000u) 514 #define VME2_IO0_VME_END (0x0000ffffu) 515 516 #define VME2_IO1_LOCAL_START (0xf0000000u) 517 #define VME2_IO1_MASK (0x00ffffffu) 518 #define VME2_IO1_VME_START (0x00000000u) 519 #define VME2_IO1_VME_END (0x00ffffffu) 520 521 #define VME2_IO2_LOCAL_START (0x00000000u) 522 #define VME2_IO2_MASK (0xffffffffu) 523 #define VME2_IO2_VME_START (0xf1000000u) /* Maybe starts@ 0x0? */ 524 #define VME2_IO2_VME_END (0xff7fffffu) 525 526 #endif /* _MVME_VME_TWOREG_H */ 527