1 /* $NetBSD: aac_pci.c,v 1.31 2010/05/07 13:59:51 is Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 2000 Michael Smith 34 * Copyright (c) 2000 BSDi 35 * Copyright (c) 2000 Niklas Hallqvist 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 48 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 49 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 50 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 51 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 52 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 53 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 55 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 56 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 57 * SUCH DAMAGE. 58 * 59 * from FreeBSD: aac_pci.c,v 1.1 2000/09/13 03:20:34 msmith Exp 60 * via OpenBSD: aac_pci.c,v 1.7 2002/03/14 01:26:58 millert Exp 61 */ 62 63 /* 64 * PCI front-end for the `aac' driver. 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: aac_pci.c,v 1.31 2010/05/07 13:59:51 is Exp $"); 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/device.h> 73 #include <sys/kernel.h> 74 #include <sys/malloc.h> 75 #include <sys/queue.h> 76 77 #include <sys/bus.h> 78 #include <machine/endian.h> 79 #include <sys/intr.h> 80 81 #include <dev/pci/pcidevs.h> 82 #include <dev/pci/pcireg.h> 83 #include <dev/pci/pcivar.h> 84 85 #include <dev/ic/aacreg.h> 86 #include <dev/ic/aacvar.h> 87 88 struct aac_pci_softc { 89 struct aac_softc sc_aac; 90 pci_chipset_tag_t sc_pc; 91 pci_intr_handle_t sc_ih; 92 }; 93 94 /* i960Rx interface */ 95 static int aac_rx_get_fwstatus(struct aac_softc *); 96 static void aac_rx_qnotify(struct aac_softc *, int); 97 static int aac_rx_get_istatus(struct aac_softc *); 98 static void aac_rx_clear_istatus(struct aac_softc *, int); 99 static void aac_rx_set_mailbox(struct aac_softc *, u_int32_t, u_int32_t, 100 u_int32_t, u_int32_t, u_int32_t); 101 static uint32_t aac_rx_get_mailbox(struct aac_softc *, int); 102 static void aac_rx_set_interrupts(struct aac_softc *, int); 103 static int aac_rx_send_command(struct aac_softc *, struct aac_ccb *); 104 static int aac_rx_get_outb_queue(struct aac_softc *); 105 static void aac_rx_set_outb_queue(struct aac_softc *, int); 106 107 /* StrongARM interface */ 108 static int aac_sa_get_fwstatus(struct aac_softc *); 109 static void aac_sa_qnotify(struct aac_softc *, int); 110 static int aac_sa_get_istatus(struct aac_softc *); 111 static void aac_sa_clear_istatus(struct aac_softc *, int); 112 static void aac_sa_set_mailbox(struct aac_softc *, u_int32_t, u_int32_t, 113 u_int32_t, u_int32_t, u_int32_t); 114 static uint32_t aac_sa_get_mailbox(struct aac_softc *, int); 115 static void aac_sa_set_interrupts(struct aac_softc *, int); 116 117 /* Rocket/MIPS interface */ 118 static int aac_rkt_get_fwstatus(struct aac_softc *); 119 static void aac_rkt_qnotify(struct aac_softc *, int); 120 static int aac_rkt_get_istatus(struct aac_softc *); 121 static void aac_rkt_clear_istatus(struct aac_softc *, int); 122 static void aac_rkt_set_mailbox(struct aac_softc *, u_int32_t, u_int32_t, 123 u_int32_t, u_int32_t, u_int32_t); 124 static uint32_t aac_rkt_get_mailbox(struct aac_softc *, int); 125 static void aac_rkt_set_interrupts(struct aac_softc *, int); 126 static int aac_rkt_send_command(struct aac_softc *, struct aac_ccb *); 127 static int aac_rkt_get_outb_queue(struct aac_softc *); 128 static void aac_rkt_set_outb_queue(struct aac_softc *, int); 129 130 static const struct aac_interface aac_rx_interface = { 131 aac_rx_get_fwstatus, 132 aac_rx_qnotify, 133 aac_rx_get_istatus, 134 aac_rx_clear_istatus, 135 aac_rx_set_mailbox, 136 aac_rx_get_mailbox, 137 aac_rx_set_interrupts, 138 aac_rx_send_command, 139 aac_rx_get_outb_queue, 140 aac_rx_set_outb_queue 141 }; 142 143 static const struct aac_interface aac_sa_interface = { 144 aac_sa_get_fwstatus, 145 aac_sa_qnotify, 146 aac_sa_get_istatus, 147 aac_sa_clear_istatus, 148 aac_sa_set_mailbox, 149 aac_sa_get_mailbox, 150 aac_sa_set_interrupts, 151 NULL, NULL, NULL 152 }; 153 154 static const struct aac_interface aac_rkt_interface = { 155 aac_rkt_get_fwstatus, 156 aac_rkt_qnotify, 157 aac_rkt_get_istatus, 158 aac_rkt_clear_istatus, 159 aac_rkt_set_mailbox, 160 aac_rkt_get_mailbox, 161 aac_rkt_set_interrupts, 162 aac_rkt_send_command, 163 aac_rkt_get_outb_queue, 164 aac_rkt_set_outb_queue 165 }; 166 167 static struct aac_ident { 168 u_short vendor; 169 u_short device; 170 u_short subvendor; 171 u_short subdevice; 172 u_short hwif; 173 u_short quirks; 174 const char *prodstr; 175 } const aac_ident[] = { 176 { 177 PCI_VENDOR_DELL, 178 PCI_PRODUCT_DELL_PERC_2SI, 179 PCI_VENDOR_DELL, 180 PCI_PRODUCT_DELL_PERC_2SI, 181 AAC_HWIF_I960RX, 182 0, 183 "Dell PERC 2/Si" 184 }, 185 { 186 PCI_VENDOR_DELL, 187 PCI_PRODUCT_DELL_PERC_3DI, 188 PCI_VENDOR_DELL, 189 PCI_PRODUCT_DELL_PERC_3DI, 190 AAC_HWIF_I960RX, 191 0, 192 "Dell PERC 3/Di" 193 }, 194 { 195 PCI_VENDOR_DELL, 196 PCI_PRODUCT_DELL_PERC_3DI, 197 PCI_VENDOR_DELL, 198 PCI_PRODUCT_DELL_PERC_3DI_SUB2, 199 AAC_HWIF_I960RX, 200 0, 201 "Dell PERC 3/Di" 202 }, 203 { 204 PCI_VENDOR_DELL, 205 PCI_PRODUCT_DELL_PERC_3DI, 206 PCI_VENDOR_DELL, 207 PCI_PRODUCT_DELL_PERC_3DI_SUB3, 208 AAC_HWIF_I960RX, 209 0, 210 "Dell PERC 3/Di" 211 }, 212 { 213 PCI_VENDOR_DELL, 214 PCI_PRODUCT_DELL_PERC_3DI_2, 215 PCI_VENDOR_DELL, 216 PCI_PRODUCT_DELL_PERC_3DI_2_SUB, 217 AAC_HWIF_I960RX, 218 0, 219 "Dell PERC 3/Di" 220 }, 221 { 222 PCI_VENDOR_DELL, 223 PCI_PRODUCT_DELL_PERC_3DI_3, 224 PCI_VENDOR_DELL, 225 PCI_PRODUCT_DELL_PERC_3DI_3_SUB, 226 AAC_HWIF_I960RX, 227 0, 228 "Dell PERC 3/Di" 229 }, 230 { 231 PCI_VENDOR_DELL, 232 PCI_PRODUCT_DELL_PERC_3DI_3, 233 PCI_VENDOR_DELL, 234 PCI_PRODUCT_DELL_PERC_3DI_3_SUB2, 235 AAC_HWIF_I960RX, 236 0, 237 "Dell PERC 3/Di" 238 }, 239 { 240 PCI_VENDOR_DELL, 241 PCI_PRODUCT_DELL_PERC_3DI_3, 242 PCI_VENDOR_DELL, 243 PCI_PRODUCT_DELL_PERC_3DI_3_SUB3, 244 AAC_HWIF_I960RX, 245 0, 246 "Dell PERC 3/Di" 247 }, 248 { 249 PCI_VENDOR_DELL, 250 PCI_PRODUCT_DELL_PERC_3SI, 251 PCI_VENDOR_DELL, 252 PCI_PRODUCT_DELL_PERC_3SI, 253 AAC_HWIF_I960RX, 254 0, 255 "Dell PERC 3/Si" 256 }, 257 { 258 PCI_VENDOR_DELL, 259 PCI_PRODUCT_DELL_PERC_3SI_2, 260 PCI_VENDOR_DELL, 261 PCI_PRODUCT_DELL_PERC_3SI_2_SUB, 262 AAC_HWIF_I960RX, 263 0, 264 "Dell PERC 3/Si" 265 }, 266 { 267 PCI_VENDOR_ADP2, 268 PCI_PRODUCT_ADP2_ASR2200S, 269 PCI_VENDOR_DELL, 270 PCI_PRODUCT_DELL_CERC_1_5, 271 AAC_HWIF_I960RX, 272 AAC_QUIRK_NO4GB, 273 "Dell CERC SATA RAID 1.5/6ch" 274 }, 275 { 276 PCI_VENDOR_ADP2, 277 PCI_PRODUCT_ADP2_AAC2622, 278 PCI_VENDOR_ADP2, 279 PCI_PRODUCT_ADP2_AAC2622, 280 AAC_HWIF_I960RX, 281 0, 282 "Adaptec ADP-2622" 283 }, 284 { 285 PCI_VENDOR_ADP2, 286 PCI_PRODUCT_ADP2_ASR2200S, 287 PCI_VENDOR_ADP2, 288 PCI_PRODUCT_ADP2_ASR2200S_SUB2M, 289 AAC_HWIF_I960RX, 290 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 291 "Adaptec ASR-2200S" 292 }, 293 { 294 PCI_VENDOR_ADP2, 295 PCI_PRODUCT_ADP2_ASR2200S, 296 PCI_VENDOR_DELL, 297 PCI_PRODUCT_ADP2_ASR2200S_SUB2M, 298 AAC_HWIF_I960RX, 299 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 300 "Dell PERC 320/DC" 301 }, 302 { 303 PCI_VENDOR_ADP2, 304 PCI_PRODUCT_ADP2_ASR2200S, 305 PCI_VENDOR_ADP2, 306 PCI_PRODUCT_ADP2_ASR2200S, 307 AAC_HWIF_I960RX, 308 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 309 "Adaptec ASR-2200S" 310 }, 311 { 312 PCI_VENDOR_ADP2, 313 PCI_PRODUCT_ADP2_ASR2200S, 314 PCI_VENDOR_ADP2, 315 PCI_PRODUCT_ADP2_AAR2810SA, 316 AAC_HWIF_I960RX, 317 AAC_QUIRK_NO4GB, 318 "Adaptec AAR-2810SA" 319 }, 320 { 321 PCI_VENDOR_ADP2, 322 PCI_PRODUCT_ADP2_ASR2200S, 323 PCI_VENDOR_ADP2, 324 PCI_PRODUCT_ADP2_ASR2120S, 325 AAC_HWIF_I960RX, 326 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 327 "Adaptec ASR-2120S" 328 }, 329 { 330 PCI_VENDOR_ADP2, 331 PCI_PRODUCT_ADP2_ASR2200S, 332 PCI_VENDOR_ADP2, 333 PCI_PRODUCT_ADP2_ASR2410SA, 334 AAC_HWIF_I960RX, 335 AAC_QUIRK_NO4GB, 336 "Adaptec ASR-2410SA" 337 }, 338 { 339 PCI_VENDOR_ADP2, 340 PCI_PRODUCT_ADP2_ASR2200S, 341 PCI_VENDOR_HP, 342 PCI_PRODUCT_ADP2_HP_M110_G2, 343 AAC_HWIF_I960RX, 344 AAC_QUIRK_NO4GB, 345 "HP ML110 G2 (Adaptec ASR-2610SA)" 346 }, 347 { 348 PCI_VENDOR_ADP2, 349 PCI_PRODUCT_ADP2_ASR2120S, 350 PCI_VENDOR_IBM, 351 PCI_PRODUCT_IBM_SERVERAID8K, 352 AAC_HWIF_RKT, 353 0, 354 "IBM ServeRAID 8k" 355 }, 356 { 357 PCI_VENDOR_DEC, 358 PCI_PRODUCT_DEC_21554, 359 PCI_VENDOR_ADP2, 360 PCI_PRODUCT_ADP2_AAC364, 361 AAC_HWIF_STRONGARM, 362 0, 363 "Adaptec AAC-364" 364 }, 365 { 366 PCI_VENDOR_DEC, 367 PCI_PRODUCT_DEC_21554, 368 PCI_VENDOR_ADP2, 369 PCI_PRODUCT_ADP2_ASR5400S, 370 AAC_HWIF_STRONGARM, 371 AAC_QUIRK_BROKEN_MMAP, 372 "Adaptec ASR-5400S" 373 }, 374 { 375 PCI_VENDOR_DEC, 376 PCI_PRODUCT_DEC_21554, 377 PCI_VENDOR_ADP2, 378 PCI_PRODUCT_ADP2_PERC_2QC, 379 AAC_HWIF_STRONGARM, 380 AAC_QUIRK_PERC2QC, 381 "Dell PERC 2/QC" 382 }, 383 { 384 PCI_VENDOR_DEC, 385 PCI_PRODUCT_DEC_21554, 386 PCI_VENDOR_ADP2, 387 PCI_PRODUCT_ADP2_PERC_3QC, 388 AAC_HWIF_STRONGARM, 389 0, 390 "Dell PERC 3/QC" 391 }, 392 { 393 PCI_VENDOR_DEC, 394 PCI_PRODUCT_DEC_21554, 395 PCI_VENDOR_HP, 396 PCI_PRODUCT_HP_NETRAID_4M, 397 AAC_HWIF_STRONGARM, 398 0, 399 "HP NetRAID-4M" 400 }, 401 { 0x9005, 402 0x0285, 403 0x108e, 404 0x286, 405 AAC_HWIF_I960RX, 406 0, 407 "SG-XPCIESAS-R-IN" 408 }, 409 }; 410 411 static const struct aac_ident * 412 aac_find_ident(struct pci_attach_args *pa) 413 { 414 const struct aac_ident *m, *mm; 415 u_int32_t subsysid; 416 417 m = aac_ident; 418 mm = aac_ident + (sizeof(aac_ident) / sizeof(aac_ident[0])); 419 420 while (m < mm) { 421 if (m->vendor == PCI_VENDOR(pa->pa_id) && 422 m->device == PCI_PRODUCT(pa->pa_id)) { 423 subsysid = pci_conf_read(pa->pa_pc, pa->pa_tag, 424 PCI_SUBSYS_ID_REG); 425 if (m->subvendor == PCI_VENDOR(subsysid) && 426 m->subdevice == PCI_PRODUCT(subsysid)) 427 return (m); 428 } 429 m++; 430 } 431 432 return (NULL); 433 } 434 435 static int 436 aac_pci_intr_set(struct aac_softc *sc, int (*hand)(void*), void *arg) 437 { 438 struct aac_pci_softc *pcisc; 439 440 pcisc = (struct aac_pci_softc *) sc; 441 442 pci_intr_disestablish(pcisc->sc_pc, sc->sc_ih); 443 sc->sc_ih = pci_intr_establish(pcisc->sc_pc, pcisc->sc_ih, 444 IPL_BIO, hand, arg); 445 if (sc->sc_ih == NULL) { 446 return ENXIO; 447 } 448 return 0; 449 } 450 451 static int 452 aac_pci_match(device_t parent, cfdata_t match, void *aux) 453 { 454 struct pci_attach_args *pa; 455 456 pa = aux; 457 458 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 459 return (0); 460 461 return (aac_find_ident(pa) != NULL); 462 } 463 464 static void 465 aac_pci_attach(device_t parent, device_t self, void *aux) 466 { 467 struct pci_attach_args *pa; 468 pci_chipset_tag_t pc; 469 struct aac_pci_softc *pcisc; 470 struct aac_softc *sc; 471 u_int16_t command; 472 bus_addr_t membase; 473 bus_size_t memsize; 474 const char *intrstr; 475 int state; 476 const struct aac_ident *m; 477 478 pa = aux; 479 pc = pa->pa_pc; 480 pcisc = device_private(self); 481 pcisc->sc_pc = pc; 482 sc = &pcisc->sc_aac; 483 state = 0; 484 485 aprint_naive(": RAID controller\n"); 486 aprint_normal(": "); 487 488 /* 489 * Verify that the adapter is correctly set up in PCI space. 490 */ 491 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 492 command |= PCI_COMMAND_MASTER_ENABLE; 493 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 494 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 495 AAC_DPRINTF(AAC_D_MISC, ("pci command status reg 0x08x ")); 496 497 if ((command & PCI_COMMAND_MASTER_ENABLE) == 0) { 498 aprint_error("can't enable bus-master feature\n"); 499 goto bail_out; 500 } 501 502 if ((command & PCI_COMMAND_MEM_ENABLE) == 0) { 503 aprint_error("memory window not available\n"); 504 goto bail_out; 505 } 506 507 /* 508 * Map control/status registers. 509 */ 510 if (pci_mapreg_map(pa, PCI_MAPREG_START, 511 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_memt, 512 &sc->sc_memh, &membase, &memsize)) { 513 aprint_error("can't find mem space\n"); 514 goto bail_out; 515 } 516 state++; 517 518 if (pci_intr_map(pa, &pcisc->sc_ih)) { 519 aprint_error("couldn't map interrupt\n"); 520 goto bail_out; 521 } 522 intrstr = pci_intr_string(pc, pcisc->sc_ih); 523 sc->sc_ih = pci_intr_establish(pc, pcisc->sc_ih, IPL_BIO, aac_intr, sc); 524 if (sc->sc_ih == NULL) { 525 aprint_error("couldn't establish interrupt"); 526 if (intrstr != NULL) 527 aprint_error(" at %s", intrstr); 528 aprint_error("\n"); 529 goto bail_out; 530 } 531 state++; 532 533 sc->sc_dmat = pa->pa_dmat; 534 535 m = aac_find_ident(pa); 536 aprint_normal("%s\n", m->prodstr); 537 if (intrstr != NULL) 538 aprint_normal_dev(&sc->sc_dv, "interrupting at %s\n", 539 intrstr); 540 541 sc->sc_hwif = m->hwif; 542 sc->sc_quirks = m->quirks; 543 switch (sc->sc_hwif) { 544 case AAC_HWIF_I960RX: 545 AAC_DPRINTF(AAC_D_MISC, 546 ("set hardware up for i960Rx")); 547 sc->sc_if = aac_rx_interface; 548 break; 549 550 case AAC_HWIF_STRONGARM: 551 AAC_DPRINTF(AAC_D_MISC, 552 ("set hardware up for StrongARM")); 553 sc->sc_if = aac_sa_interface; 554 break; 555 556 case AAC_HWIF_RKT: 557 AAC_DPRINTF(AAC_D_MISC, 558 ("set hardware up for MIPS/Rocket")); 559 sc->sc_if = aac_rkt_interface; 560 break; 561 } 562 sc->sc_regsize = memsize; 563 sc->sc_intr_set = aac_pci_intr_set; 564 565 if (!aac_attach(sc)) 566 return; 567 568 bail_out: 569 if (state > 1) 570 pci_intr_disestablish(pc, sc->sc_ih); 571 if (state > 0) 572 bus_space_unmap(sc->sc_memt, sc->sc_memh, memsize); 573 } 574 575 CFATTACH_DECL(aac_pci, sizeof(struct aac_pci_softc), 576 aac_pci_match, aac_pci_attach, NULL, NULL); 577 578 /* 579 * Read the current firmware status word. 580 */ 581 static int 582 aac_sa_get_fwstatus(struct aac_softc *sc) 583 { 584 585 return (AAC_GETREG4(sc, AAC_SA_FWSTATUS)); 586 } 587 588 static int 589 aac_rx_get_fwstatus(struct aac_softc *sc) 590 { 591 592 return (AAC_GETREG4(sc, AAC_RX_FWSTATUS)); 593 } 594 595 static int 596 aac_rkt_get_fwstatus(struct aac_softc *sc) 597 { 598 599 return (AAC_GETREG4(sc, AAC_RKT_FWSTATUS)); 600 } 601 602 /* 603 * Notify the controller of a change in a given queue 604 */ 605 606 static void 607 aac_sa_qnotify(struct aac_softc *sc, int qbit) 608 { 609 610 AAC_SETREG2(sc, AAC_SA_DOORBELL1_SET, qbit); 611 } 612 613 static void 614 aac_rx_qnotify(struct aac_softc *sc, int qbit) 615 { 616 617 AAC_SETREG4(sc, AAC_RX_IDBR, qbit); 618 } 619 620 static void 621 aac_rkt_qnotify(struct aac_softc *sc, int qbit) 622 { 623 624 AAC_SETREG4(sc, AAC_RKT_IDBR, qbit); 625 } 626 627 /* 628 * Get the interrupt reason bits 629 */ 630 static int 631 aac_sa_get_istatus(struct aac_softc *sc) 632 { 633 634 return (AAC_GETREG2(sc, AAC_SA_DOORBELL0)); 635 } 636 637 static int 638 aac_rx_get_istatus(struct aac_softc *sc) 639 { 640 641 return (AAC_GETREG4(sc, AAC_RX_ODBR)); 642 } 643 644 static int 645 aac_rkt_get_istatus(struct aac_softc *sc) 646 { 647 648 return (AAC_GETREG4(sc, AAC_RKT_ODBR)); 649 } 650 651 /* 652 * Clear some interrupt reason bits 653 */ 654 static void 655 aac_sa_clear_istatus(struct aac_softc *sc, int mask) 656 { 657 658 AAC_SETREG2(sc, AAC_SA_DOORBELL0_CLEAR, mask); 659 } 660 661 static void 662 aac_rx_clear_istatus(struct aac_softc *sc, int mask) 663 { 664 665 AAC_SETREG4(sc, AAC_RX_ODBR, mask); 666 } 667 668 static void 669 aac_rkt_clear_istatus(struct aac_softc *sc, int mask) 670 { 671 672 AAC_SETREG4(sc, AAC_RKT_ODBR, mask); 673 } 674 675 /* 676 * Populate the mailbox and set the command word 677 */ 678 static void 679 aac_sa_set_mailbox(struct aac_softc *sc, u_int32_t command, 680 u_int32_t arg0, u_int32_t arg1, u_int32_t arg2, 681 u_int32_t arg3) 682 { 683 684 AAC_SETREG4(sc, AAC_SA_MAILBOX, command); 685 AAC_SETREG4(sc, AAC_SA_MAILBOX + 4, arg0); 686 AAC_SETREG4(sc, AAC_SA_MAILBOX + 8, arg1); 687 AAC_SETREG4(sc, AAC_SA_MAILBOX + 12, arg2); 688 AAC_SETREG4(sc, AAC_SA_MAILBOX + 16, arg3); 689 } 690 691 static void 692 aac_rx_set_mailbox(struct aac_softc *sc, u_int32_t command, 693 u_int32_t arg0, u_int32_t arg1, u_int32_t arg2, 694 u_int32_t arg3) 695 { 696 697 AAC_SETREG4(sc, AAC_RX_MAILBOX, command); 698 AAC_SETREG4(sc, AAC_RX_MAILBOX + 4, arg0); 699 AAC_SETREG4(sc, AAC_RX_MAILBOX + 8, arg1); 700 AAC_SETREG4(sc, AAC_RX_MAILBOX + 12, arg2); 701 AAC_SETREG4(sc, AAC_RX_MAILBOX + 16, arg3); 702 } 703 704 static void 705 aac_rkt_set_mailbox(struct aac_softc *sc, u_int32_t command, 706 u_int32_t arg0, u_int32_t arg1, u_int32_t arg2, 707 u_int32_t arg3) 708 { 709 710 AAC_SETREG4(sc, AAC_RKT_MAILBOX, command); 711 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 4, arg0); 712 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 8, arg1); 713 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 12, arg2); 714 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 16, arg3); 715 } 716 717 /* 718 * Fetch the specified mailbox 719 */ 720 static uint32_t 721 aac_sa_get_mailbox(struct aac_softc *sc, int mb) 722 { 723 724 return (AAC_GETREG4(sc, AAC_SA_MAILBOX + (mb * 4))); 725 } 726 727 static uint32_t 728 aac_rx_get_mailbox(struct aac_softc *sc, int mb) 729 { 730 731 return (AAC_GETREG4(sc, AAC_RX_MAILBOX + (mb * 4))); 732 } 733 734 static uint32_t 735 aac_rkt_get_mailbox(struct aac_softc *sc, int mb) 736 { 737 738 return (AAC_GETREG4(sc, AAC_RKT_MAILBOX + (mb * 4))); 739 } 740 741 /* 742 * Set/clear interrupt masks 743 */ 744 static void 745 aac_sa_set_interrupts(struct aac_softc *sc, int enable) 746 { 747 748 if (enable) 749 AAC_SETREG2((sc), AAC_SA_MASK0_CLEAR, AAC_DB_INTERRUPTS); 750 else 751 AAC_SETREG2((sc), AAC_SA_MASK0_SET, ~0); 752 } 753 754 static void 755 aac_rx_set_interrupts(struct aac_softc *sc, int enable) 756 { 757 758 if (enable) { 759 if (sc->sc_quirks & AAC_QUIRK_NEW_COMM) 760 AAC_SETREG4(sc, AAC_RX_OIMR, ~AAC_DB_INT_NEW_COMM); 761 else 762 AAC_SETREG4(sc, AAC_RX_OIMR, ~AAC_DB_INTERRUPTS); 763 } else { 764 AAC_SETREG4(sc, AAC_RX_OIMR, ~0); 765 } 766 } 767 768 static void 769 aac_rkt_set_interrupts(struct aac_softc *sc, int enable) 770 { 771 772 if (enable) { 773 if (sc->sc_quirks & AAC_QUIRK_NEW_COMM) 774 AAC_SETREG4(sc, AAC_RKT_OIMR, ~AAC_DB_INT_NEW_COMM); 775 else 776 AAC_SETREG4(sc, AAC_RKT_OIMR, ~AAC_DB_INTERRUPTS); 777 } else { 778 AAC_SETREG4(sc, AAC_RKT_OIMR, ~0); 779 } 780 } 781 782 /* 783 * New comm. interface: Send command functions 784 */ 785 static int 786 aac_rx_send_command(struct aac_softc *sc, struct aac_ccb *ac) 787 { 788 u_int32_t index, device; 789 790 index = AAC_GETREG4(sc, AAC_RX_IQUE); 791 if (index == 0xffffffffL) 792 index = AAC_GETREG4(sc, AAC_RX_IQUE); 793 if (index == 0xffffffffL) 794 return index; 795 #ifdef notyet 796 aac_enqueue_busy(ac); 797 #endif 798 device = index; 799 AAC_SETREG4(sc, device, 800 htole32((u_int32_t)(ac->ac_fibphys & 0xffffffffUL))); 801 device += 4; 802 if (sizeof(bus_addr_t) > 4) { 803 AAC_SETREG4(sc, device, 804 htole32((u_int32_t)((u_int64_t)ac->ac_fibphys >> 32))); 805 } else { 806 AAC_SETREG4(sc, device, 0); 807 } 808 device += 4; 809 AAC_SETREG4(sc, device, ac->ac_fib->Header.Size); 810 AAC_SETREG4(sc, AAC_RX_IQUE, index); 811 return 0; 812 } 813 814 static int 815 aac_rkt_send_command(struct aac_softc *sc, struct aac_ccb *ac) 816 { 817 u_int32_t index, device; 818 819 index = AAC_GETREG4(sc, AAC_RKT_IQUE); 820 if (index == 0xffffffffL) 821 index = AAC_GETREG4(sc, AAC_RKT_IQUE); 822 if (index == 0xffffffffL) 823 return index; 824 #ifdef notyet 825 aac_enqueue_busy(ac); 826 #endif 827 device = index; 828 AAC_SETREG4(sc, device, 829 htole32((u_int32_t)(ac->ac_fibphys & 0xffffffffUL))); 830 device += 4; 831 if (sizeof(bus_addr_t) > 4) { 832 AAC_SETREG4(sc, device, 833 htole32((u_int32_t)((u_int64_t)ac->ac_fibphys >> 32))); 834 } else { 835 AAC_SETREG4(sc, device, 0); 836 } 837 device += 4; 838 AAC_SETREG4(sc, device, ac->ac_fib->Header.Size); 839 AAC_SETREG4(sc, AAC_RKT_IQUE, index); 840 return 0; 841 } 842 843 /* 844 * New comm. interface: get, set outbound queue index 845 */ 846 static int 847 aac_rx_get_outb_queue(struct aac_softc *sc) 848 { 849 850 return AAC_GETREG4(sc, AAC_RX_OQUE); 851 } 852 853 static int 854 aac_rkt_get_outb_queue(struct aac_softc *sc) 855 { 856 857 return AAC_GETREG4(sc, AAC_RKT_OQUE); 858 } 859 860 static void 861 aac_rx_set_outb_queue(struct aac_softc *sc, int index) 862 { 863 864 AAC_SETREG4(sc, AAC_RX_OQUE, index); 865 } 866 867 static void 868 aac_rkt_set_outb_queue(struct aac_softc *sc, int index) 869 { 870 871 AAC_SETREG4(sc, AAC_RKT_OQUE, index); 872 } 873