1 /* $NetBSD: amrreg.h,v 1.1 2002/01/30 14:35:45 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999,2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: amrreg.h,v 1.2 2000/08/30 07:52:40 msmith Exp 66 */ 67 68 #ifndef _PCI_AMRREG_H_ 69 #define _PCI_AMRREG_H_ 70 71 #ifdef AMR_CRASH_ME 72 #define AMR_MAX_CMDS 255 /* ident = 0 not allowed */ 73 #else 74 #define AMR_MAX_CMDS 120 75 #endif 76 #define AMR_MAXLD 40 77 78 #define AMR_MAX_CMDS_PU 63 79 80 #define AMR_MAX_SEGS 17 81 #define AMR_MAX_XFER (PAGE_SIZE * (AMR_MAX_SEGS - 1)) 82 83 #define AMR_MAX_CHANNEL 3 84 #define AMR_MAX_TARGET 15 85 #define AMR_MAX_LUN 7 86 87 #define AMR_MAX_CDB_LEN 0x0a 88 #define AMR_MAX_REQ_SENSE_LEN 0x20 89 90 #define AMR_SECTOR_SIZE 512 91 92 /* Mailbox commands.*/ 93 #define AMR_CMD_LREAD 0x01 94 #define AMR_CMD_LWRITE 0x02 95 #define AMR_CMD_PASS 0x03 96 #define AMR_CMD_EXT_ENQUIRY 0x04 97 #define AMR_CMD_ENQUIRY 0x05 98 #define AMR_CMD_FLUSH 0x0a 99 #define AMR_CMD_EXT_ENQUIRY2 0x0c 100 #define AMR_CMD_GET_MACHINEID 0x36 101 #define AMR_CMD_GET_INITIATOR 0x7d /* returns one byte */ 102 #define AMR_CMD_CONFIG 0xa1 103 #define AMR_CONFIG_PRODUCT_INFO 0x0e 104 #define AMR_CONFIG_ENQ3 0x0f 105 #define AMR_CONFIG_ENQ3_SOLICITED_NOTIFY 0x01 106 #define AMR_CONFIG_ENQ3_SOLICITED_FULL 0x02 107 #define AMR_CONFIG_ENQ3_UNSOLICITED 0x03 108 109 /* Command completion status. */ 110 #define AMR_STATUS_SUCCESS 0x00 111 #define AMR_STATUS_ABORTED 0x02 112 #define AMR_STATUS_FAILED 0x80 113 114 /* Physical/logical drive states. */ 115 #define AMR_DRV_CURSTATE(x) ((x) & 0x0f) 116 #define AMR_DRV_PREVSTATE(x) (((x) >> 4) & 0x0f) 117 #define AMR_DRV_OFFLINE 0x00 118 #define AMR_DRV_DEGRADED 0x01 119 #define AMR_DRV_OPTIMAL 0x02 120 #define AMR_DRV_ONLINE 0x03 121 #define AMR_DRV_FAILED 0x04 122 #define AMR_DRV_REBUILD 0x05 123 #define AMR_DRV_HOTSPARE 0x06 124 125 /* Logical drive properties. */ 126 #define AMR_DRV_RAID_MASK 0x0f /* RAID level 0, 1, 3, 5, etc. */ 127 #define AMR_DRV_WRITEBACK 0x10 /* write-back enabled */ 128 #define AMR_DRV_READHEAD 0x20 /* readhead policy enabled */ 129 #define AMR_DRV_ADAPTIVE 0x40 /* adaptive I/O policy enabled */ 130 131 /* Battery status. */ 132 #define AMR_BATT_MODULE_MISSING 0x01 133 #define AMR_BATT_LOW_VOLTAGE 0x02 134 #define AMR_BATT_TEMP_HIGH 0x04 135 #define AMR_BATT_PACK_MISSING 0x08 136 #define AMR_BATT_CHARGE_MASK 0x30 137 #define AMR_BATT_CHARGE_DONE 0x00 138 #define AMR_BATT_CHARGE_INPROG 0x10 139 #define AMR_BATT_CHARGE_FAIL 0x20 140 #define AMR_BATT_CYCLES_EXCEEDED 0x40 141 142 /* 143 * 8LD firmware interface. 144 */ 145 146 /* Array constraints. */ 147 #define AMR_8LD_MAXDRIVES 8 148 #define AMR_8LD_MAXCHAN 5 149 #define AMR_8LD_MAXTARG 15 150 #define AMR_8LD_MAXPHYSDRIVES (AMR_8LD_MAXCHAN * AMR_8LD_MAXTARG) 151 152 /* Adapter information. */ 153 struct amr_adapter_info { 154 u_int8_t aa_maxio; 155 u_int8_t aa_rebuild_rate; 156 u_int8_t aa_maxtargchan; 157 u_int8_t aa_channels; 158 u_int8_t aa_firmware[4]; 159 u_int16_t aa_flashage; 160 u_int8_t aa_chipsetvalue; 161 u_int8_t aa_memorysize; 162 u_int8_t aa_cacheflush; 163 u_int8_t aa_bios[4]; 164 u_int8_t aa_boardtype; 165 u_int8_t aa_scsisensealert; 166 u_int8_t aa_writeconfigcount; 167 u_int8_t aa_driveinsertioncount; 168 u_int8_t aa_inserteddrive; 169 u_int8_t aa_batterystatus; 170 u_int8_t aa_res1; 171 } __attribute__ ((__packed__)); 172 173 /* Logical drive information. */ 174 struct amr_logdrive_info { 175 u_int8_t al_numdrives; 176 u_int8_t al_res1[3]; 177 u_int32_t al_size[AMR_8LD_MAXDRIVES]; 178 u_int8_t al_properties[AMR_8LD_MAXDRIVES]; 179 u_int8_t al_state[AMR_8LD_MAXDRIVES]; 180 } __attribute__ ((__packed__)); 181 182 /* Physical drive information. */ 183 struct amr_physdrive_info { 184 /* Low nybble is current state, high nybble is previous state. */ 185 u_int8_t ap_state[AMR_8LD_MAXPHYSDRIVES]; 186 u_int8_t ap_predictivefailure; 187 } __attribute__ ((__packed__)); 188 189 /* 190 * Enquiry response structure for AMR_CMD_ENQUIRY (e), AMR_CMD_EXT_ENQUIRY (x) 191 * and AMR_CMD_EXT_ENQUIRY2 (2). 192 */ 193 struct amr_enquiry { 194 struct amr_adapter_info ae_adapter; /* e x 2 */ 195 struct amr_logdrive_info ae_ldrv; /* e x 2 */ 196 struct amr_physdrive_info ae_pdrv; /* e x 2 */ 197 u_int8_t ae_formatting[AMR_8LD_MAXDRIVES]; /* x 2 */ 198 u_int8_t res1[AMR_8LD_MAXDRIVES]; /* x 2 */ 199 u_int32_t ae_extlen; /* 2 */ 200 u_int16_t ae_subsystem; /* 2 */ 201 u_int16_t ae_subvendor; /* 2 */ 202 u_int32_t ae_signature; /* 2 */ 203 #define AMR_SIG_431 0xfffe0001 204 #define AMR_SIG_438 0xfffd0002 205 #define AMR_SIG_762 0xfffc0003 206 #define AMR_SIG_T5 0xfffb0004 207 #define AMR_SIG_466 0xfffa0005 208 #define AMR_SIG_467 0xfff90006 209 #define AMR_SIG_T7 0xfff80007 210 #define AMR_SIG_490 0xfff70008 211 u_int8_t res2[844]; /* 2 */ 212 } __attribute__ ((__packed__)); 213 214 /* 215 * 40LD firmware interface. 216 */ 217 218 /* Array constraints. */ 219 #define AMR_40LD_MAXDRIVES 40 220 #define AMR_40LD_MAXCHAN 16 221 #define AMR_40LD_MAXTARG 16 222 #define AMR_40LD_MAXPHYSDRIVES 256 223 224 /* Product information structure. */ 225 struct amr_prodinfo { 226 u_int32_t ap_size; /* current size in bytes (not including resvd) */ 227 u_int32_t ap_configsig; /* default is 0x00282008, indicating 0x28 maximum 228 * logical drives, 0x20 maximum stripes and 0x08 229 * maximum spans */ 230 u_int8_t ap_firmware[16]; /* printable identifiers */ 231 u_int8_t ap_bios[16]; 232 u_int8_t ap_product[80]; 233 u_int8_t ap_maxio; /* maximum number of concurrent commands supported */ 234 u_int8_t ap_nschan; /* number of SCSI channels present */ 235 u_int8_t ap_fcloops; /* number of fibre loops present */ 236 u_int8_t ap_memtype; /* memory type */ 237 u_int32_t ap_signature; 238 u_int16_t ap_memsize; /* onboard memory in MB */ 239 u_int16_t ap_subsystem; /* subsystem identifier */ 240 u_int16_t ap_subvendor; /* subsystem vendor ID */ 241 u_int8_t ap_numnotifyctr; /* number of notify counters */ 242 } __attribute__ ((__packed__)); 243 244 /* Notify structure. */ 245 struct amr_notify { 246 u_int32_t an_globalcounter; /* change counter */ 247 248 u_int8_t an_paramcounter; /* parameter change counter */ 249 u_int8_t an_paramid; 250 #define AMR_PARAM_REBUILD_RATE 0x01 /* value = new rebuild rate */ 251 #define AMR_PARAM_FLUSH_INTERVAL 0x02 /* value = new flush interval */ 252 #define AMR_PARAM_SENSE_ALERT 0x03 /* value = last physical drive with check condition set */ 253 #define AMR_PARAM_DRIVE_INSERTED 0x04 /* value = last physical drive inserted */ 254 #define AMR_PARAM_BATTERY_STATUS 0x05 /* value = battery status */ 255 u_int16_t an_paramval; 256 257 u_int8_t an_writeconfigcounter; /* write config occurred */ 258 u_int8_t res1[3]; 259 260 u_int8_t an_ldrvopcounter; /* logical drive operation started/completed */ 261 u_int8_t an_ldrvopid; 262 u_int8_t an_ldrvopcmd; 263 #define AMR_LDRVOP_CHECK 0x01 264 #define AMR_LDRVOP_INIT 0x02 265 #define AMR_LDRVOP_REBUILD 0x03 266 u_int8_t an_ldrvopstatus; 267 #define AMR_LDRVOP_SUCCESS 0x00 268 #define AMR_LDRVOP_FAILED 0x01 269 #define AMR_LDRVOP_ABORTED 0x02 270 #define AMR_LDRVOP_CORRECTED 0x03 271 #define AMR_LDRVOP_STARTED 0x04 272 273 u_int8_t an_ldrvstatecounter; /* logical drive state change occurred */ 274 u_int8_t an_ldrvstateid; 275 u_int8_t an_ldrvstatenew; 276 u_int8_t an_ldrvstateold; 277 278 u_int8_t an_pdrvstatecounter; /* physical drive state change occurred */ 279 u_int8_t an_pdrvstateid; 280 u_int8_t an_pdrvstatenew; 281 u_int8_t an_pdrvstateold; 282 283 u_int8_t an_pdrvfmtcounter; 284 u_int8_t an_pdrvfmtid; 285 u_int8_t an_pdrvfmtval; 286 #define AMR_FORMAT_START 0x01 287 #define AMR_FORMAT_COMPLETE 0x02 288 u_int8_t res2; 289 290 u_int8_t an_targxfercounter; /* scsi xfer rate change */ 291 u_int8_t an_targxferid; 292 u_int8_t an_targxferval; 293 u_int8_t res3; 294 295 u_int8_t an_fcloopidcounter; /* FC/AL loop ID changed */ 296 u_int8_t an_fcloopidpdrvid; 297 u_int8_t an_fcloopid0; 298 u_int8_t an_fcloopid1; 299 300 u_int8_t an_fcloopstatecounter; /* FC/AL loop status changed */ 301 u_int8_t an_fcloopstate0; 302 u_int8_t an_fcloopstate1; 303 u_int8_t res4; 304 } __attribute__ ((__packed__)); 305 306 /* Enquiry3 structure. */ 307 struct amr_enquiry3 { 308 u_int32_t ae_datasize; /* valid data size in this structure */ 309 union { /* event notify structure */ 310 struct amr_notify n; 311 u_int8_t pad[0x80]; 312 } ae_notify; 313 u_int8_t ae_rebuildrate; /* current rebuild rate in % */ 314 u_int8_t ae_cacheflush; /* flush interval in seconds */ 315 u_int8_t ae_sensealert; 316 u_int8_t ae_driveinsertcount; /* count of inserted drives */ 317 u_int8_t ae_batterystatus; 318 u_int8_t ae_numldrives; 319 u_int8_t ae_reconstate[AMR_40LD_MAXDRIVES / 8]; /* reconstruction state */ 320 u_int16_t ae_opstatus[AMR_40LD_MAXDRIVES / 8]; /* operation status per drive */ 321 u_int32_t ae_drivesize[AMR_40LD_MAXDRIVES]; /* logical drive size */ 322 u_int8_t ae_driveprop[AMR_40LD_MAXDRIVES]; /* logical drive properties */ 323 u_int8_t ae_drivestate[AMR_40LD_MAXDRIVES]; /* physical drive state */ 324 u_int16_t ae_driveformat[AMR_40LD_MAXPHYSDRIVES]; 325 u_int8_t ae_targxfer[80]; /* physical drive transfer rates */ 326 327 u_int8_t res1[263]; /* pad to 1024 bytes */ 328 } __attribute__ ((__packed__)); 329 330 /* 331 * Mailbox and command structures. 332 */ 333 334 #define AMR_MBOX_CMDSIZE 0x10 /* portion worth copying for controller */ 335 336 struct amr_mailbox { 337 u_int8_t mb_command; 338 u_int8_t mb_ident; 339 u_int16_t mb_blkcount; 340 u_int32_t mb_lba; 341 u_int32_t mb_physaddr; 342 u_int8_t mb_drive; 343 u_int8_t mb_nsgelem; 344 u_int8_t res1; 345 u_int8_t mb_busy; 346 u_int8_t mb_nstatus; 347 u_int8_t mb_status; 348 u_int8_t mb_completed[46]; 349 u_int8_t mb_poll; 350 u_int8_t mb_ack; 351 u_int8_t res2[62]; /* Pad to 128 bytes. */ 352 } __attribute__ ((__packed__)); 353 354 struct amr_mailbox64 { 355 u_int32_t mb64_segment; /* for 64-bit controllers */ 356 struct amr_mailbox mb; 357 } __attribute__ ((__packed__)); 358 359 struct amr_mailbox_ioctl { 360 u_int8_t mb_command; 361 u_int8_t mb_ident; 362 u_int8_t mb_channel; 363 u_int8_t mb_param; 364 u_int8_t mb_pad[4]; 365 u_int32_t mb_physaddr; 366 u_int8_t mb_drive; 367 u_int8_t mb_nsgelem; 368 u_int8_t res1; 369 u_int8_t mb_busy; 370 u_int8_t mb_nstatus; 371 u_int8_t mb_completed[46]; 372 u_int8_t mb_poll; 373 u_int8_t mb_ack; 374 u_int8_t res4[16]; 375 } __attribute__ ((__packed__)); 376 377 struct amr_sgentry { 378 u_int32_t sge_addr; 379 u_int32_t sge_count; 380 } __attribute__ ((__packed__)); 381 382 struct amr_passthrough { 383 u_int8_t ap_timeout:3; 384 u_int8_t ap_ars:1; 385 u_int8_t ap_dummy:3; 386 u_int8_t ap_islogical:1; 387 u_int8_t ap_logical_drive_no; 388 u_int8_t ap_channel; 389 u_int8_t ap_scsi_id; 390 u_int8_t ap_queue_tag; 391 u_int8_t ap_queue_action; 392 u_int8_t ap_cdb[AMR_MAX_CDB_LEN]; 393 u_int8_t ap_cdb_length; 394 u_int8_t ap_request_sense_length; 395 u_int8_t ap_request_sense_area[AMR_MAX_REQ_SENSE_LEN]; 396 u_int8_t ap_no_sg_elements; 397 u_int8_t ap_scsi_status; 398 u_int32_t ap_data_transfer_address; 399 u_int32_t ap_data_transfer_length; 400 } __attribute__ ((__packed__)); 401 402 /* 403 * "Quartz" i960 PCI bridge interface. 404 */ 405 406 #define AMR_QUARTZ_SIG_REG 0xa0 407 #define AMR_QUARTZ_SIG0 0xcccc 408 #define AMR_QUARTZ_SIG1 0x3344 409 410 /* Doorbell registers. */ 411 #define AMR_QREG_IDB 0x20 412 #define AMR_QREG_ODB 0x2c 413 414 #define AMR_QIDB_SUBMIT 0x00000001 /* mailbox ready for work */ 415 #define AMR_QIDB_ACK 0x00000002 /* mailbox done */ 416 #define AMR_QODB_READY 0x10001234 /* work ready to be processed */ 417 418 /* 419 * Old-style ("standard") ASIC bridge interface. 420 */ 421 422 /* I/O registers. */ 423 #define AMR_SREG_CMD 0x10 /* Command/ack register (w) */ 424 #define AMR_SREG_MBOX_BUSY 0x10 /* Mailbox status (r) */ 425 #define AMR_SREG_TOGL 0x11 /* Interrupt enable */ 426 #define AMR_SREG_MBOX 0x14 /* Mailbox physical address */ 427 #define AMR_SREG_MBOX_ENABLE 0x18 /* Atomic mailbox address enable */ 428 #define AMR_SREG_INTR 0x1a /* Interrupt status */ 429 430 /* I/O magic numbers. */ 431 #define AMR_SCMD_POST 0x10 /* in SCMD to initiate action on mailbox */ 432 #define AMR_SCMD_ACKINTR 0x08 /* in SCMD to ack mailbox retrieved */ 433 #define AMR_STOGL_ENABLE 0xc0 /* in STOGL */ 434 #define AMR_SINTR_VALID 0x40 /* in SINTR */ 435 #define AMR_SMBOX_BUSY_FLAG 0x10 /* in SMBOX_BUSY */ 436 #define AMR_SMBOX_ENABLE_ADDR 0x00 /* in SMBOX_ENABLE */ 437 438 #endif /* !_PCI_AMRREG_H_ */ 439