xref: /netbsd/sys/dev/pci/bktr/bktr_reg.h (revision 5f819ca3)
10cdd0c66Swiz /* $SourceForge: bktr_reg.h,v 1.3 2003/03/11 23:11:27 thomasklausner Exp $ */
28b27ce1aSwiz 
3*5f819ca3Schs /*	$NetBSD: bktr_reg.h,v 1.22 2012/10/27 17:18:36 chs Exp $	*/
48b27ce1aSwiz /*
50cdd0c66Swiz  * $FreeBSD: src/sys/dev/bktr/bktr_reg.h,v 1.42 2000/10/31 13:09:56 roger Exp$
68b27ce1aSwiz  *
78b27ce1aSwiz  * Copyright (c) 1999 Roger Hardiman
88b27ce1aSwiz  * Copyright (c) 1998 Amancio Hasty
98b27ce1aSwiz  * Copyright (c) 1995 Mark Tinguely and Jim Lowe
108b27ce1aSwiz  * All rights reserved.
118b27ce1aSwiz  *
128b27ce1aSwiz  * Redistribution and use in source and binary forms, with or without
138b27ce1aSwiz  * modification, are permitted provided that the following conditions
148b27ce1aSwiz  * are met:
158b27ce1aSwiz  * 1. Redistributions of source code must retain the above copyright
168b27ce1aSwiz  *    notice, this list of conditions and the following disclaimer.
178b27ce1aSwiz  * 2. Redistributions in binary form must reproduce the above copyright
188b27ce1aSwiz  *    notice, this list of conditions and the following disclaimer in the
198b27ce1aSwiz  *    documentation and/or other materials provided with the distribution.
208b27ce1aSwiz  * 3. All advertising materials mentioning features or use of this software
218b27ce1aSwiz  *    must display the following acknowledgement:
228b27ce1aSwiz  *	This product includes software developed by Mark Tinguely and Jim Lowe
238b27ce1aSwiz  * 4. The name of the author may not be used to endorse or promote products
248b27ce1aSwiz  *    derived from this software without specific prior written permission.
258b27ce1aSwiz  *
268b27ce1aSwiz  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
278b27ce1aSwiz  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
288b27ce1aSwiz  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
298b27ce1aSwiz  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
308b27ce1aSwiz  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
318b27ce1aSwiz  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
328b27ce1aSwiz  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
338b27ce1aSwiz  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
348b27ce1aSwiz  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
358b27ce1aSwiz  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
368b27ce1aSwiz  * POSSIBILITY OF SUCH DAMAGE.
378b27ce1aSwiz  *
388b27ce1aSwiz  */
398b27ce1aSwiz 
408b27ce1aSwiz 
41a591bc88Scegger #include <sys/bus.h>
42a591bc88Scegger #include <sys/device.h>			/* device_t */
438b27ce1aSwiz #include <sys/select.h>			/* struct selinfo */
445fea9616Sjdolecek #include <sys/reboot.h>			/* AB_* for bootverbose */
458b27ce1aSwiz 
46d307475cSwiz /*
47d307475cSwiz  * The kernel options for the driver now all begin with BKTR.
48d307475cSwiz  * Support the older kernel options on FreeBSD and OpenBSD.
49d307475cSwiz  *
50d307475cSwiz  */
51d307475cSwiz 
52d307475cSwiz 
538b27ce1aSwiz #ifndef PCI_LATENCY_TIMER
548b27ce1aSwiz #define	PCI_LATENCY_TIMER		0x0c	/* pci timer register */
558b27ce1aSwiz #endif
568b27ce1aSwiz 
578b27ce1aSwiz /*
588b27ce1aSwiz  * Definitions for the Brooktree 848/878 video capture to pci interface.
598b27ce1aSwiz  */
608b27ce1aSwiz 
618b27ce1aSwiz #define BROOKTREE_848                   1
628b27ce1aSwiz #define BROOKTREE_848A                  2
638b27ce1aSwiz #define BROOKTREE_849A                  3
648b27ce1aSwiz #define BROOKTREE_878                   4
658b27ce1aSwiz #define BROOKTREE_879                   5
668b27ce1aSwiz 
678b27ce1aSwiz typedef volatile u_int 	bregister_t;
688b27ce1aSwiz /*
698b27ce1aSwiz  * if other persuasion endian, then compiler will probably require that
708b27ce1aSwiz  * these next
718b27ce1aSwiz  * macros be reversed
728b27ce1aSwiz  */
738b27ce1aSwiz #define	BTBYTE(what)	bregister_t  what:8; int :24
748b27ce1aSwiz #define	BTWORD(what)	bregister_t  what:16; int: 16
758b27ce1aSwiz #define BTLONG(what)	bregister_t  what:32
768b27ce1aSwiz 
778b27ce1aSwiz struct bt848_registers {
788b27ce1aSwiz     BTBYTE (dstatus);		/* 0, 1,2,3 */
798b27ce1aSwiz #define BT848_DSTATUS_PRES		(1<<7)
808b27ce1aSwiz #define BT848_DSTATUS_HLOC		(1<<6)
818b27ce1aSwiz #define BT848_DSTATUS_FIELD		(1<<5)
828b27ce1aSwiz #define BT848_DSTATUS_NUML		(1<<4)
838b27ce1aSwiz #define BT848_DSTATUS_CSEL		(1<<3)
848b27ce1aSwiz #define BT848_DSTATUS_PLOCK		(1<<2)
858b27ce1aSwiz #define BT848_DSTATUS_LOF		(1<<1)
868b27ce1aSwiz #define BT848_DSTATUS_COF		(1<<0)
878b27ce1aSwiz     BTBYTE (iform);		/* 4, 5,6,7 */
888b27ce1aSwiz #define BT848_IFORM_MUXSEL		(0x3<<5)
898b27ce1aSwiz # define BT848_IFORM_M_MUX1		(0x03<<5)
908b27ce1aSwiz # define BT848_IFORM_M_MUX0		(0x02<<5)
918b27ce1aSwiz # define BT848_IFORM_M_MUX2		(0x01<<5)
928b27ce1aSwiz # define BT848_IFORM_M_MUX3		(0x0)
938b27ce1aSwiz # define BT848_IFORM_M_RSVD		(0x00<<5)
948b27ce1aSwiz #define BT848_IFORM_XTSEL		(0x3<<3)
958b27ce1aSwiz # define BT848_IFORM_X_AUTO		(0x03<<3)
968b27ce1aSwiz # define BT848_IFORM_X_XT1		(0x02<<3)
978b27ce1aSwiz # define BT848_IFORM_X_XT0		(0x01<<3)
988b27ce1aSwiz # define BT848_IFORM_X_RSVD		(0x00<<3)
998b27ce1aSwiz     BTBYTE (tdec);		/* 8, 9,a,b */
1008b27ce1aSwiz     BTBYTE (e_crop);		/* c, d,e,f */
1018b27ce1aSwiz     BTBYTE (e_vdelay_lo);	/* 10, 11,12,13 */
1028b27ce1aSwiz     BTBYTE (e_vactive_lo);	/* 14, 15,16,17 */
1038b27ce1aSwiz     BTBYTE (e_delay_lo);	/* 18, 19,1a,1b */
1048b27ce1aSwiz     BTBYTE (e_hactive_lo);	/* 1c, 1d,1e,1f */
1058b27ce1aSwiz     BTBYTE (e_hscale_hi);	/* 20, 21,22,23 */
1068b27ce1aSwiz     BTBYTE (e_hscale_lo);	/* 24, 25,26,27 */
1078b27ce1aSwiz     BTBYTE (bright);		/* 28, 29,2a,2b */
1088b27ce1aSwiz     BTBYTE (e_control);		/* 2c, 2d,2e,2f */
1098b27ce1aSwiz #define BT848_E_CONTROL_LNOTCH		(1<<7)
1108b27ce1aSwiz #define BT848_E_CONTROL_COMP		(1<<6)
1118b27ce1aSwiz #define BT848_E_CONTROL_LDEC		(1<<5)
1128b27ce1aSwiz #define BT848_E_CONTROL_CBSENSE		(1<<4)
1138b27ce1aSwiz #define BT848_E_CONTROL_RSVD		(1<<3)
1148b27ce1aSwiz #define BT848_E_CONTROL_CON_MSB		(1<<2)
1158b27ce1aSwiz #define BT848_E_CONTROL_SAT_U_MSB	(1<<1)
1168b27ce1aSwiz #define BT848_E_CONTROL_SAT_V_MSB	(1<<0)
1178b27ce1aSwiz     BTBYTE (contrast_lo);	/* 30, 31,32,33 */
1188b27ce1aSwiz     BTBYTE (sat_u_lo);		/* 34, 35,36,37 */
1198b27ce1aSwiz     BTBYTE (sat_v_lo);		/* 38, 39,3a,3b */
1208b27ce1aSwiz     BTBYTE (hue);		/* 3c, 3d,3e,3f */
1218b27ce1aSwiz     BTBYTE (e_scloop);		/* 40, 41,42,43 */
1228b27ce1aSwiz #define BT848_E_SCLOOP_RSVD1		(1<<7)
1238b27ce1aSwiz #define BT848_E_SCLOOP_CAGC		(1<<6)
1248b27ce1aSwiz #define BT848_E_SCLOOP_CKILL		(1<<5)
1258b27ce1aSwiz #define BT848_E_SCLOOP_HFILT		(0x3<<3)
1268b27ce1aSwiz # define BT848_E_SCLOOP_HFILT_ICON	(0x3<<3)
1278b27ce1aSwiz # define BT848_E_SCLOOP_HFILT_QCIF	(0x2<<3)
1288b27ce1aSwiz # define BT848_E_SCLOOP_HFILT_CIF	(0x1<<3)
1298b27ce1aSwiz # define BT848_E_SCLOOP_HFILT_AUTO	(0x0<<3)
1308b27ce1aSwiz #define BT848_E_SCLOOP_RSVD0		(0x7<<0)
1318b27ce1aSwiz     int		:32;		/* 44, 45,46,47 */
1328b27ce1aSwiz     BTBYTE (oform);		/* 48, 49,4a,4b */
1338b27ce1aSwiz     BTBYTE (e_vscale_hi);	/* 4c, 4d,4e,4f */
1348b27ce1aSwiz     BTBYTE (e_vscale_lo);	/* 50, 51,52,53 */
1358b27ce1aSwiz     BTBYTE (test);		/* 54, 55,56,57 */
1368b27ce1aSwiz     int		:32;		/* 58, 59,5a,5b */
1378b27ce1aSwiz     int		:32;		/* 5c, 5d,5e,5f */
1388b27ce1aSwiz     BTLONG (adelay);		/* 60, 61,62,63 */
1398b27ce1aSwiz     BTBYTE (bdelay);		/* 64, 65,66,67 */
1408b27ce1aSwiz     BTBYTE (adc);		/* 68, 69,6a,6b */
1418b27ce1aSwiz #define BT848_ADC_RESERVED		(0x80)	/* required pattern */
1428b27ce1aSwiz #define BT848_ADC_SYNC_T		(1<<5)
1438b27ce1aSwiz #define BT848_ADC_AGC_EN		(1<<4)
1448b27ce1aSwiz #define BT848_ADC_CLK_SLEEP		(1<<3)
1458b27ce1aSwiz #define BT848_ADC_Y_SLEEP		(1<<2)
1468b27ce1aSwiz #define BT848_ADC_C_SLEEP		(1<<1)
1478b27ce1aSwiz #define BT848_ADC_CRUSH			(1<<0)
1488b27ce1aSwiz     BTBYTE (e_vtc);		/* 6c, 6d,6e,6f */
1498b27ce1aSwiz     int		:32;		/* 70, 71,72,73 */
1508b27ce1aSwiz     int 	:32;		/* 74, 75,76,77 */
1518b27ce1aSwiz     int		:32;		/* 78, 79,7a,7b */
1528b27ce1aSwiz     BTLONG (sreset);		/* 7c, 7d,7e,7f */
1538b27ce1aSwiz     u_char 	filler1[0x84-0x80];
1548b27ce1aSwiz     BTBYTE (tgctrl);		/* 84, 85,86,87 */
1558b27ce1aSwiz #define BT848_TGCTRL_TGCKI		(3<<3)
1568b27ce1aSwiz #define BT848_TGCTRL_TGCKI_XTAL		(0<<3)
1578b27ce1aSwiz #define BT848_TGCTRL_TGCKI_PLL		(1<<3)
1588b27ce1aSwiz #define BT848_TGCTRL_TGCKI_GPCLK	(2<<3)
1598b27ce1aSwiz #define BT848_TGCTRL_TGCKI_GPCLK_I	(3<<3)
1608b27ce1aSwiz     u_char 	filler[0x8c-0x88];
1618b27ce1aSwiz     BTBYTE (o_crop);		/* 8c, 8d,8e,8f */
1628b27ce1aSwiz     BTBYTE (o_vdelay_lo);	/* 90, 91,92,93 */
1638b27ce1aSwiz     BTBYTE (o_vactive_lo);	/* 94, 95,96,97 */
1648b27ce1aSwiz     BTBYTE (o_delay_lo);	/* 98, 99,9a,9b */
1658b27ce1aSwiz     BTBYTE (o_hactive_lo);	/* 9c, 9d,9e,9f */
1668b27ce1aSwiz     BTBYTE (o_hscale_hi);	/* a0, a1,a2,a3 */
1678b27ce1aSwiz     BTBYTE (o_hscale_lo);	/* a4, a5,a6,a7 */
1688b27ce1aSwiz     int		:32;		/* a8, a9,aa,ab */
1698b27ce1aSwiz     BTBYTE (o_control);		/* ac, ad,ae,af */
1708b27ce1aSwiz #define BT848_O_CONTROL_LNOTCH		(1<<7)
1718b27ce1aSwiz #define BT848_O_CONTROL_COMP		(1<<6)
1728b27ce1aSwiz #define BT848_O_CONTROL_LDEC		(1<<5)
1738b27ce1aSwiz #define BT848_O_CONTROL_CBSENSE		(1<<4)
1748b27ce1aSwiz #define BT848_O_CONTROL_RSVD		(1<<3)
1758b27ce1aSwiz #define BT848_O_CONTROL_CON_MSB		(1<<2)
1768b27ce1aSwiz #define BT848_O_CONTROL_SAT_U_MSB	(1<<1)
1778b27ce1aSwiz #define BT848_O_CONTROL_SAT_V_MSB	(1<<0)
1788b27ce1aSwiz     u_char	fillter4[16];
1798b27ce1aSwiz     BTBYTE (o_scloop);		/* c0, c1,c2,c3 */
1808b27ce1aSwiz #define BT848_O_SCLOOP_RSVD1		(1<<7)
1818b27ce1aSwiz #define BT848_O_SCLOOP_CAGC		(1<<6)
1828b27ce1aSwiz #define BT848_O_SCLOOP_CKILL		(1<<5)
1838b27ce1aSwiz #define BT848_O_SCLOOP_HFILT		(0x3<<3)
1848b27ce1aSwiz #define BT848_O_SCLOOP_HFILT_ICON	(0x3<<3)
1858b27ce1aSwiz #define BT848_O_SCLOOP_HFILT_QCIF	(0x2<<3)
1868b27ce1aSwiz #define BT848_O_SCLOOP_HFILT_CIF	(0x1<<3)
1878b27ce1aSwiz #define BT848_O_SCLOOP_HFILT_AUTO	(0x0<<3)
1888b27ce1aSwiz #define BT848_O_SCLOOP_RSVD0		(0x7<<0)
1898b27ce1aSwiz     int		:32;		/* c4, c5,c6,c7 */
1908b27ce1aSwiz     int		:32;		/* c8, c9,ca,cb */
1918b27ce1aSwiz     BTBYTE (o_vscale_hi);	/* cc, cd,ce,cf */
1928b27ce1aSwiz     BTBYTE (o_vscale_lo);	/* d0, d1,d2,d3 */
1938b27ce1aSwiz     BTBYTE (color_fmt);		/* d4, d5,d6,d7 */
1948b27ce1aSwiz     bregister_t color_ctl_swap		:4; /* d8 */
1958b27ce1aSwiz #define BT848_COLOR_CTL_WSWAP_ODD	(1<<3)
1968b27ce1aSwiz #define BT848_COLOR_CTL_WSWAP_EVEN	(1<<2)
1978b27ce1aSwiz #define BT848_COLOR_CTL_BSWAP_ODD	(1<<1)
1988b27ce1aSwiz #define BT848_COLOR_CTL_BSWAP_EVEN	(1<<0)
1998b27ce1aSwiz     bregister_t color_ctl_gamma		:1;
2008b27ce1aSwiz     bregister_t color_ctl_rgb_ded	:1;
2018b27ce1aSwiz     bregister_t color_ctl_color_bars	:1;
2028b27ce1aSwiz     bregister_t color_ctl_ext_frmrate	:1;
2038b27ce1aSwiz #define BT848_COLOR_CTL_GAMMA		(1<<4)
2048b27ce1aSwiz #define BT848_COLOR_CTL_RGB_DED		(1<<5)
2058b27ce1aSwiz #define BT848_COLOR_CTL_COLOR_BARS	(1<<6)
2068b27ce1aSwiz #define BT848_COLOR_CTL_EXT_FRMRATE     (1<<7)
2078b27ce1aSwiz     int		:24;		/* d9,da,db */
2088b27ce1aSwiz     BTBYTE (cap_ctl);		/* dc, dd,de,df */
2098b27ce1aSwiz #define BT848_CAP_CTL_DITH_FRAME	(1<<4)
2108b27ce1aSwiz #define BT848_CAP_CTL_VBI_ODD		(1<<3)
2118b27ce1aSwiz #define BT848_CAP_CTL_VBI_EVEN		(1<<2)
2128b27ce1aSwiz #define BT848_CAP_CTL_ODD		(1<<1)
2138b27ce1aSwiz #define BT848_CAP_CTL_EVEN		(1<<0)
2148b27ce1aSwiz     BTBYTE (vbi_pack_size);	/* e0, e1,e2,e3 */
2158b27ce1aSwiz     BTBYTE (vbi_pack_del);	/* e4, e5,e6,e7 */
2168b27ce1aSwiz     int		:32;		/* e8, e9,ea,eb */
2178b27ce1aSwiz     BTBYTE (o_vtc);		/* ec, ed,ee,ef */
2188b27ce1aSwiz     BTBYTE (pll_f_lo);		/* f0, f1,f2,f3 */
2198b27ce1aSwiz     BTBYTE (pll_f_hi);		/* f4, f5,f6,f7 */
2208b27ce1aSwiz     BTBYTE (pll_f_xci);		/* f8, f9,fa,fb */
2218b27ce1aSwiz #define BT848_PLL_F_C			(1<<6)
2228b27ce1aSwiz #define BT848_PLL_F_X			(1<<7)
2238b27ce1aSwiz     u_char	filler2[0x100-0xfc];
2248b27ce1aSwiz     BTLONG (int_stat);		/* 100, 101,102,103 */
2258b27ce1aSwiz     BTLONG (int_mask);		/* 104, 105,106,107 */
2268b27ce1aSwiz #define BT848_INT_RISCS			(0xf<<28)
2278b27ce1aSwiz #define BT848_INT_RISC_EN		(1<<27)
2288b27ce1aSwiz #define BT848_INT_RACK			(1<<25)
2298b27ce1aSwiz #define BT848_INT_FIELD			(1<<24)
2308b27ce1aSwiz #define BT848_INT_MYSTERYBIT		(1<<23)
2318b27ce1aSwiz #define BT848_INT_SCERR			(1<<19)
2328b27ce1aSwiz #define BT848_INT_OCERR			(1<<18)
2338b27ce1aSwiz #define BT848_INT_PABORT		(1<<17)
2348b27ce1aSwiz #define BT848_INT_RIPERR		(1<<16)
2358b27ce1aSwiz #define BT848_INT_PPERR			(1<<15)
2368b27ce1aSwiz #define BT848_INT_FDSR			(1<<14)
2378b27ce1aSwiz #define BT848_INT_FTRGT			(1<<13)
2388b27ce1aSwiz #define BT848_INT_FBUS			(1<<12)
2398b27ce1aSwiz #define BT848_INT_RISCI			(1<<11)
2408b27ce1aSwiz #define BT848_INT_GPINT			(1<<9)
2418b27ce1aSwiz #define BT848_INT_I2CDONE		(1<<8)
2428b27ce1aSwiz #define BT848_INT_RSV1			(1<<7)
2438b27ce1aSwiz #define BT848_INT_RSV0			(1<<6)
2448b27ce1aSwiz #define BT848_INT_VPRES			(1<<5)
2458b27ce1aSwiz #define BT848_INT_HLOCK			(1<<4)
2468b27ce1aSwiz #define BT848_INT_OFLOW			(1<<3)
2478b27ce1aSwiz #define BT848_INT_HSYNC			(1<<2)
2488b27ce1aSwiz #define BT848_INT_VSYNC			(1<<1)
2498b27ce1aSwiz #define BT848_INT_FMTCHG		(1<<0)
2508b27ce1aSwiz     int		:32;		/* 108, 109,10a,10b */
2518b27ce1aSwiz     BTWORD (gpio_dma_ctl);	/* 10c, 10d,10e,10f */
2528b27ce1aSwiz #define BT848_DMA_CTL_PL23TP4		(0<<6)	/* planar1 trigger 4 */
2538b27ce1aSwiz #define BT848_DMA_CTL_PL23TP8		(1<<6)	/* planar1 trigger 8 */
2548b27ce1aSwiz #define BT848_DMA_CTL_PL23TP16		(2<<6)	/* planar1 trigger 16 */
2558b27ce1aSwiz #define BT848_DMA_CTL_PL23TP32		(3<<6)	/* planar1 trigger 32 */
2568b27ce1aSwiz #define BT848_DMA_CTL_PL1TP4		(0<<4)	/* planar1 trigger 4 */
2578b27ce1aSwiz #define BT848_DMA_CTL_PL1TP8		(1<<4)	/* planar1 trigger 8 */
2588b27ce1aSwiz #define BT848_DMA_CTL_PL1TP16		(2<<4)	/* planar1 trigger 16 */
2598b27ce1aSwiz #define BT848_DMA_CTL_PL1TP32		(3<<4)	/* planar1 trigger 32 */
2608b27ce1aSwiz #define BT848_DMA_CTL_PKTP4		(0<<2)	/* packed trigger 4 */
2618b27ce1aSwiz #define BT848_DMA_CTL_PKTP8		(1<<2)	/* packed trigger 8 */
2628b27ce1aSwiz #define BT848_DMA_CTL_PKTP16		(2<<2)	/* packed trigger 16 */
2638b27ce1aSwiz #define BT848_DMA_CTL_PKTP32		(3<<2)	/* packed trigger 32 */
2648b27ce1aSwiz #define BT848_DMA_CTL_RISC_EN		(1<<1)
2658b27ce1aSwiz #define BT848_DMA_CTL_FIFO_EN		(1<<0)
2668b27ce1aSwiz     BTLONG (i2c_data_ctl);	/* 110, 111,112,113 */
2678b27ce1aSwiz #define BT848_DATA_CTL_I2CDIV		(0xf<<4)
2688b27ce1aSwiz #define BT848_DATA_CTL_I2CSYNC		(1<<3)
2698b27ce1aSwiz #define BT848_DATA_CTL_I2CW3B		(1<<2)
2708b27ce1aSwiz #define BT848_DATA_CTL_I2CSCL		(1<<1)
2718b27ce1aSwiz #define BT848_DATA_CTL_I2CSDA		(1<<0)
2728b27ce1aSwiz     BTLONG (risc_strt_add);	/* 114, 115,116,117 */
2738b27ce1aSwiz     BTLONG (gpio_out_en);	/* 118, 119,11a,11b */	/* really 24 bits */
2748b27ce1aSwiz     BTLONG (gpio_reg_inp);	/* 11c, 11d,11e,11f */	/* really 24 bits */
2758b27ce1aSwiz     BTLONG (risc_count);	/* 120, 121,122,123 */
2768b27ce1aSwiz     u_char	filler3[0x200-0x124];
2778b27ce1aSwiz     BTLONG (gpio_data);		/* 200, 201,202,203 */	/* really 24 bits */
2788b27ce1aSwiz };
2798b27ce1aSwiz 
2808b27ce1aSwiz 
2818b27ce1aSwiz #define BKTR_DSTATUS			0x000
2828b27ce1aSwiz #define BKTR_IFORM			0x004
2838b27ce1aSwiz #define BKTR_TDEC			0x008
2848b27ce1aSwiz #define BKTR_E_CROP			0x00C
2858b27ce1aSwiz #define BKTR_O_CROP			0x08C
2868b27ce1aSwiz #define BKTR_E_VDELAY_LO		0x010
2878b27ce1aSwiz #define BKTR_O_VDELAY_LO		0x090
2888b27ce1aSwiz #define BKTR_E_VACTIVE_LO		0x014
2898b27ce1aSwiz #define BKTR_O_VACTIVE_LO		0x094
2908b27ce1aSwiz #define BKTR_E_DELAY_LO			0x018
2918b27ce1aSwiz #define BKTR_O_DELAY_LO			0x098
2928b27ce1aSwiz #define BKTR_E_HACTIVE_LO		0x01C
2938b27ce1aSwiz #define BKTR_O_HACTIVE_LO		0x09C
2948b27ce1aSwiz #define BKTR_E_HSCALE_HI		0x020
2958b27ce1aSwiz #define BKTR_O_HSCALE_HI		0x0A0
2968b27ce1aSwiz #define BKTR_E_HSCALE_LO		0x024
2978b27ce1aSwiz #define BKTR_O_HSCALE_LO		0x0A4
2988b27ce1aSwiz #define BKTR_BRIGHT			0x028
2998b27ce1aSwiz #define BKTR_E_CONTROL			0x02C
3008b27ce1aSwiz #define BKTR_O_CONTROL			0x0AC
3018b27ce1aSwiz #define BKTR_CONTRAST_LO		0x030
3028b27ce1aSwiz #define BKTR_SAT_U_LO			0x034
3038b27ce1aSwiz #define BKTR_SAT_V_LO			0x038
3048b27ce1aSwiz #define BKTR_HUE			0x03C
3058b27ce1aSwiz #define BKTR_E_SCLOOP			0x040
3068b27ce1aSwiz #define BKTR_O_SCLOOP			0x0C0
3078b27ce1aSwiz #define BKTR_OFORM			0x048
3088b27ce1aSwiz #define BKTR_E_VSCALE_HI		0x04C
3098b27ce1aSwiz #define BKTR_O_VSCALE_HI		0x0CC
3108b27ce1aSwiz #define BKTR_E_VSCALE_LO		0x050
3118b27ce1aSwiz #define BKTR_O_VSCALE_LO		0x0D0
3128b27ce1aSwiz #define BKTR_TEST			0x054
3138b27ce1aSwiz #define BKTR_ADELAY			0x060
3148b27ce1aSwiz #define BKTR_BDELAY			0x064
3158b27ce1aSwiz #define BKTR_ADC			0x068
3168b27ce1aSwiz #define BKTR_E_VTC			0x06C
3178b27ce1aSwiz #define BKTR_O_VTC			0x0EC
3188b27ce1aSwiz #define BKTR_SRESET			0x07C
3198b27ce1aSwiz #define BKTR_COLOR_FMT			0x0D4
3208b27ce1aSwiz #define BKTR_COLOR_CTL			0x0D8
3218b27ce1aSwiz #define BKTR_CAP_CTL			0x0DC
3228b27ce1aSwiz #define BKTR_VBI_PACK_SIZE		0x0E0
3238b27ce1aSwiz #define BKTR_VBI_PACK_DEL		0x0E4
3248b27ce1aSwiz #define BKTR_INT_STAT			0x100
3258b27ce1aSwiz #define BKTR_INT_MASK			0x104
3268b27ce1aSwiz #define BKTR_RISC_COUNT			0x120
3278b27ce1aSwiz #define BKTR_RISC_STRT_ADD		0x114
3288b27ce1aSwiz #define BKTR_GPIO_DMA_CTL		0x10C
3298b27ce1aSwiz #define BKTR_GPIO_OUT_EN		0x118
3308b27ce1aSwiz #define BKTR_GPIO_REG_INP		0x11C
3318b27ce1aSwiz #define BKTR_GPIO_DATA			0x200
3328b27ce1aSwiz #define BKTR_I2C_DATA_CTL		0x110
3338b27ce1aSwiz #define BKTR_TGCTRL			0x084
3348b27ce1aSwiz #define BKTR_PLL_F_LO			0x0F0
3358b27ce1aSwiz #define BKTR_PLL_F_HI			0x0F4
3368b27ce1aSwiz #define BKTR_PLL_F_XCI			0x0F8
3378b27ce1aSwiz 
3388b27ce1aSwiz /*
3398b27ce1aSwiz  * device support for onboard tv tuners
3408b27ce1aSwiz  */
3418b27ce1aSwiz 
3428b27ce1aSwiz /* description of the LOGICAL tuner */
3438b27ce1aSwiz struct TVTUNER {
3448b27ce1aSwiz 	int		frequency;
3458b27ce1aSwiz 	u_char		chnlset;
3468b27ce1aSwiz 	u_char		channel;
3478b27ce1aSwiz 	u_char		band;
3488b27ce1aSwiz 	u_char		afc;
3498b27ce1aSwiz  	u_char		radio_mode;	/* current mode of the radio mode */
3508b27ce1aSwiz };
3518b27ce1aSwiz 
3528b27ce1aSwiz /* description of the PHYSICAL tuner */
3538b27ce1aSwiz struct TUNER {
35426f4234eSchristos 	const char*	name;
3558b27ce1aSwiz 	u_char		type;
3568b27ce1aSwiz 	u_char		pllControl[4];
3571c357819Smjl 	u_int		bandLimits[2];
3588b27ce1aSwiz 	u_char		bandAddrs[4];        /* 3 first for the 3 TV
3598b27ce1aSwiz 					       ** bands. Last for radio
3608b27ce1aSwiz 					       ** band (0x00=NoRadio).
3618b27ce1aSwiz 					       */
3628b27ce1aSwiz 
3638b27ce1aSwiz };
3648b27ce1aSwiz 
3658b27ce1aSwiz /* description of the card */
3668b27ce1aSwiz #define EEPROMBLOCKSIZE		32
3678b27ce1aSwiz struct CARDTYPE {
3688b27ce1aSwiz 	unsigned int		card_id;	/* card id (from #define's) */
36926f4234eSchristos 	const char*		name;
3708b27ce1aSwiz 	const struct TUNER*	tuner;		/* Tuner details */
3718b27ce1aSwiz 	u_char			tuner_pllAddr;	/* Tuner i2c address */
3728b27ce1aSwiz 	u_char			dbx;		/* Has DBX chip? */
3738b27ce1aSwiz 	u_char			msp3400c;	/* Has msp3400c chip? */
3748b27ce1aSwiz 	u_char			dpl3518a;	/* Has dpl3518a chip? */
3758b27ce1aSwiz 	u_char			eepromAddr;
3768b27ce1aSwiz 	u_char			eepromSize;	/* bytes / EEPROMBLOCKSIZE */
3778b27ce1aSwiz 	u_int			audiomuxs[5];	/* tuner, ext (line-in) */
3788b27ce1aSwiz 						/* int/unused (radio) */
3798b27ce1aSwiz 						/* mute, present */
3808b27ce1aSwiz 	u_int			gpio_mux_bits;	/* GPIO mask for audio mux */
3818b27ce1aSwiz };
3828b27ce1aSwiz 
3838b27ce1aSwiz struct format_params {
3848b27ce1aSwiz   /* Total lines, lines before image, image lines */
3858b27ce1aSwiz   int vtotal, vdelay, vactive;
3868b27ce1aSwiz   /* Total unscaled horizontal pixels, pixels before image, image pixels */
3878b27ce1aSwiz   int htotal, hdelay, hactive;
3888b27ce1aSwiz   /* Scaled horizontal image pixels, Total Scaled horizontal pixels */
3898b27ce1aSwiz   int  scaled_hactive, scaled_htotal;
3908b27ce1aSwiz   /* frame rate . for ntsc is 30 frames per second */
3918b27ce1aSwiz   int frame_rate;
3928b27ce1aSwiz   /* A-delay and B-delay */
3938b27ce1aSwiz   u_char adelay, bdelay;
3948b27ce1aSwiz   /* Iform XTSEL value */
3958b27ce1aSwiz   int iform_xtsel;
3968b27ce1aSwiz   /* VBI number of lines per field, and number of samples per line */
3978b27ce1aSwiz   int vbi_num_lines, vbi_num_samples;
3988b27ce1aSwiz };
3998b27ce1aSwiz 
40013460826Swiz #if defined(BKTR_USE_FREEBSD_SMBUS)
4018b27ce1aSwiz struct bktr_i2c_softc {
4028b27ce1aSwiz 	device_t iicbus;
4038b27ce1aSwiz 	device_t smbus;
4048b27ce1aSwiz };
4058b27ce1aSwiz #endif
4068b27ce1aSwiz 
4078b27ce1aSwiz 
4088b27ce1aSwiz /* Bt848/878 register access
4098b27ce1aSwiz  * The registers can either be access via a memory mapped structure
4108b27ce1aSwiz  * or accessed via bus_space.
411f8a4b3b1Smjl  * bus_space access allows cross platform support, where as the
4128b27ce1aSwiz  * memory mapped structure method only works on 32 bit processors
4138b27ce1aSwiz  * with the right type of endianness.
4148b27ce1aSwiz  */
415f8a4b3b1Smjl struct bktr_softc;
416f8a4b3b1Smjl 
417f8a4b3b1Smjl u_int8_t bktr_INB(struct bktr_softc *, int);
418f8a4b3b1Smjl u_int16_t bktr_INW(struct bktr_softc *, int);
419f8a4b3b1Smjl u_int32_t bktr_INL(struct bktr_softc *, int);
420f8a4b3b1Smjl void bktr_OUTB(struct bktr_softc *, int, u_int8_t);
421f8a4b3b1Smjl void bktr_OUTW(struct bktr_softc *, int, u_int16_t);
422f8a4b3b1Smjl void bktr_OUTL(struct bktr_softc *, int, u_int32_t);
423f8a4b3b1Smjl 
424f8a4b3b1Smjl #define INB(bktr,offset)	bktr_INB(bktr,offset)
425f8a4b3b1Smjl #define INW(bktr,offset)	bktr_INW(bktr,offset)
426f8a4b3b1Smjl #define INL(bktr,offset)	bktr_INL(bktr,offset)
427f8a4b3b1Smjl #define OUTB(bktr,offset,value)	bktr_OUTB(bktr,offset,value)
428f8a4b3b1Smjl #define OUTW(bktr,offset,value)	bktr_OUTW(bktr,offset,value)
429f8a4b3b1Smjl #define OUTL(bktr,offset,value)	bktr_OUTL(bktr,offset,value)
430f8a4b3b1Smjl 
4318b27ce1aSwiz typedef struct bktr_clip bktr_clip_t;
4328b27ce1aSwiz 
4338b27ce1aSwiz /*
4348b27ce1aSwiz  * BrookTree 848  info structure, one per bt848 card installed.
4358b27ce1aSwiz  */
4368b27ce1aSwiz struct bktr_softc {
4378b27ce1aSwiz 
4388b27ce1aSwiz 
439*5f819ca3Schs     device_t bktr_dev;     /* base device */
4408b27ce1aSwiz     bus_dma_tag_t	dmat;   /* DMA tag */
4418b27ce1aSwiz     bus_space_tag_t	memt;
4428b27ce1aSwiz     bus_space_handle_t	memh;
4438b27ce1aSwiz     bus_size_t		obmemsz;        /* size of en card (bytes) */
4448b27ce1aSwiz     void		*ih;
4458b27ce1aSwiz     bus_dmamap_t	dm_prog;
4468b27ce1aSwiz     bus_dmamap_t	dm_oprog;
4478b27ce1aSwiz     bus_dmamap_t	dm_mem;
4488b27ce1aSwiz     bus_dmamap_t	dm_vbidata;
4498b27ce1aSwiz     bus_dmamap_t	dm_vbibuffer;
4508b27ce1aSwiz 
4518b27ce1aSwiz 
4528b27ce1aSwiz 
4538b27ce1aSwiz 
45413460826Swiz     /* The following definitions are for the contiguous memory */
45513460826Swiz     vaddr_t bigbuf;          /* buffer that holds the captured image */
45613460826Swiz     vaddr_t vbidata;         /* RISC program puts VBI data from the current frame here */
45713460826Swiz     vaddr_t vbibuffer;       /* Circular buffer holding VBI data for the user */
45813460826Swiz     vaddr_t dma_prog;        /* RISC prog for single and/or even field capture*/
45913460826Swiz     vaddr_t odd_dma_prog;    /* RISC program for Odd field capture */
46013460826Swiz 
46113460826Swiz 
46213460826Swiz     /* the following definitions are common over all platforms */
46313460826Swiz     int		alloc_pages;	/* number of pages in bigbuf */
4648b27ce1aSwiz     int         vbiinsert;      /* Position for next write into circular buffer */
4658b27ce1aSwiz     int         vbistart;       /* Position of last read from circular buffer */
4668b27ce1aSwiz     int         vbisize;        /* Number of bytes in the circular buffer */
467f4e9b243Sjmcneill     u_int	vbi_sequence_number;	/* sequence number for VBI */
4688b27ce1aSwiz     int		vbi_read_blocked;	/* user process blocked on read() from /dev/vbi */
4698b27ce1aSwiz     struct selinfo vbi_select;	/* Data used by select() on /dev/vbi */
4708b27ce1aSwiz 
4718b27ce1aSwiz 
4728b27ce1aSwiz     struct proc	*proc;		/* process to receive raised signal */
4738b27ce1aSwiz     int		signal;		/* signal to send to process */
4748b27ce1aSwiz     int		clr_on_start;	/* clear cap buf on capture start? */
4758b27ce1aSwiz #define	METEOR_SIG_MODE_MASK	0xffff0000
4768b27ce1aSwiz #define	METEOR_SIG_FIELD_MODE	0x00010000
4778b27ce1aSwiz #define	METEOR_SIG_FRAME_MODE	0x00000000
4788b27ce1aSwiz     char         dma_prog_loaded;
4798b27ce1aSwiz     struct meteor_mem *mem;	/* used to control sync. multi-frame output */
480f4e9b243Sjmcneill     u_int	synch_wait;	/* wait for free buffer before continuing */
4818b27ce1aSwiz     short	current;	/* frame number in buffer (1-frames) */
4828b27ce1aSwiz     short	rows;		/* number of rows in a frame */
4838b27ce1aSwiz     short	cols;		/* number of columns in a frame */
4848b27ce1aSwiz     int		capture_area_x_offset; /* Usually the full 640x480(NTSC) image is */
4858b27ce1aSwiz     int		capture_area_y_offset; /* captured. The capture area allows for */
4868b27ce1aSwiz     int		capture_area_x_size;   /* example 320x200 pixels from the centre */
4878b27ce1aSwiz     int		capture_area_y_size;   /* of the video image to be captured. */
4888b27ce1aSwiz     char	capture_area_enabled;  /* When TRUE use user's capture area. */
4898b27ce1aSwiz     int		pixfmt;         /* active pixel format (idx into fmt tbl) */
4908b27ce1aSwiz     int		pixfmt_compat;  /* Y/N - in meteor pix fmt compat mode */
491f4e9b243Sjmcneill     u_int	format;		/* frame format rgb, yuv, etc.. */
4928b27ce1aSwiz     short	frames;		/* number of frames allocated */
4938b27ce1aSwiz     int		frame_size;	/* number of bytes in a frame */
494f4e9b243Sjmcneill     u_int	fifo_errors;	/* number of fifo capture errors since open */
495f4e9b243Sjmcneill     u_int	dma_errors;	/* number of DMA capture errors since open */
496f4e9b243Sjmcneill     u_int	frames_captured;/* number of frames captured since open */
497f4e9b243Sjmcneill     u_int	even_fields_captured; /* number of even fields captured */
498f4e9b243Sjmcneill     u_int	odd_fields_captured; /* number of odd fields captured */
499f4e9b243Sjmcneill     u_int	range_enable;	/* enable range checking ?? */
5008b27ce1aSwiz     u_short     capcontrol;     /* reg 0xdc capture control */
5018b27ce1aSwiz     u_short     bktr_cap_ctl;
5028b27ce1aSwiz     volatile u_int	flags;
5039fa0b176Swiz #define	METEOR_INITIALIZED	0x00000001
5048b27ce1aSwiz #define	METEOR_OPEN		0x00000002
5058b27ce1aSwiz #define	METEOR_MMAP		0x00000004
5068b27ce1aSwiz #define	METEOR_INTR		0x00000008
5078b27ce1aSwiz #define	METEOR_READ		0x00000010	/* XXX never gets referenced */
5088b27ce1aSwiz #define	METEOR_SINGLE		0x00000020	/* get single frame */
5098b27ce1aSwiz #define	METEOR_CONTIN		0x00000040	/* continuously get frames */
5108b27ce1aSwiz #define	METEOR_SYNCAP		0x00000080	/* synchronously get frames */
5118b27ce1aSwiz #define	METEOR_CAP_MASK		0x000000f0
5128b27ce1aSwiz #define	METEOR_NTSC		0x00000100
5138b27ce1aSwiz #define	METEOR_PAL		0x00000200
5148b27ce1aSwiz #define	METEOR_SECAM		0x00000400
5158b27ce1aSwiz #define	BROOKTREE_NTSC		0x00000100	/* used in video open() and */
5168b27ce1aSwiz #define	BROOKTREE_PAL		0x00000200	/* in the kernel config */
5178b27ce1aSwiz #define	BROOKTREE_SECAM		0x00000400	/* file */
5188b27ce1aSwiz #define	METEOR_AUTOMODE		0x00000800
5198b27ce1aSwiz #define	METEOR_FORM_MASK	0x00000f00
5208b27ce1aSwiz #define	METEOR_DEV0		0x00001000
5218b27ce1aSwiz #define	METEOR_DEV1		0x00002000
5228b27ce1aSwiz #define	METEOR_DEV2		0x00004000
5238b27ce1aSwiz #define	METEOR_DEV3		0x00008000
5248b27ce1aSwiz #define METEOR_DEV_SVIDEO	0x00006000
5258b27ce1aSwiz #define METEOR_DEV_RGB		0x0000a000
5268b27ce1aSwiz #define	METEOR_DEV_MASK		0x0000f000
5278b27ce1aSwiz #define	METEOR_RGB16		0x00010000
5288b27ce1aSwiz #define	METEOR_RGB24		0x00020000
5298b27ce1aSwiz #define	METEOR_YUV_PACKED	0x00040000
5308b27ce1aSwiz #define	METEOR_YUV_PLANAR	0x00080000
5318b27ce1aSwiz #define	METEOR_WANT_EVEN	0x00100000	/* want even frame */
5328b27ce1aSwiz #define	METEOR_WANT_ODD		0x00200000	/* want odd frame */
5338b27ce1aSwiz #define	METEOR_WANT_MASK	0x00300000
5348b27ce1aSwiz #define METEOR_ONLY_EVEN_FIELDS	0x01000000
5358b27ce1aSwiz #define METEOR_ONLY_ODD_FIELDS	0x02000000
5368b27ce1aSwiz #define METEOR_ONLY_FIELDS_MASK 0x03000000
5378b27ce1aSwiz #define METEOR_YUV_422		0x04000000
5388b27ce1aSwiz #define	METEOR_OUTPUT_FMT_MASK	0x040f0000
5398b27ce1aSwiz #define	METEOR_WANT_TS		0x08000000	/* time-stamp a frame */
5408b27ce1aSwiz #define METEOR_RGB		0x20000000	/* meteor rgb unit */
5418b27ce1aSwiz     u_char	tflags;				/* Tuner flags (/dev/tuner) */
5429fa0b176Swiz #define	TUNER_INITIALIZED	0x00000001
5438b27ce1aSwiz #define	TUNER_OPEN		0x00000002
5448b27ce1aSwiz     u_char      vbiflags;			/* VBI flags (/dev/vbi) */
5459fa0b176Swiz #define VBI_INITIALIZED         0x00000001
5468b27ce1aSwiz #define VBI_OPEN                0x00000002
5478b27ce1aSwiz #define VBI_CAPTURE             0x00000004
5488b27ce1aSwiz     u_short	fps;		/* frames per second */
5498b27ce1aSwiz     struct meteor_video video;
5508b27ce1aSwiz     struct TVTUNER	tuner;
5518b27ce1aSwiz     struct CARDTYPE	card;
5528b27ce1aSwiz     u_char		audio_mux_select;	/* current mode of the audio */
5538b27ce1aSwiz     u_char		audio_mute_state;	/* mute state of the audio */
5548b27ce1aSwiz     u_char		format_params;
555f4e9b243Sjmcneill     u_int              current_sol;
556f4e9b243Sjmcneill     u_int              current_col;
5578b27ce1aSwiz     int                 clip_start;
5588b27ce1aSwiz     int                 line_length;
5598b27ce1aSwiz     int                 last_y;
5608b27ce1aSwiz     int                 y;
5618b27ce1aSwiz     int                 y2;
5628b27ce1aSwiz     int                 yclip;
5638b27ce1aSwiz     int                 yclip2;
5648b27ce1aSwiz     int                 max_clip_node;
5658b27ce1aSwiz     bktr_clip_t		clip_list[100];
5668b27ce1aSwiz     int                 reverse_mute;		/* Swap the GPIO values for Mute and TV Audio */
5678b27ce1aSwiz     int                 bt848_tuner;
5688b27ce1aSwiz     int                 bt848_card;
569f4e9b243Sjmcneill     u_int              id;
5708b27ce1aSwiz #define BT848_USE_XTALS 0
5718b27ce1aSwiz #define BT848_USE_PLL   1
5728b27ce1aSwiz     int			xtal_pll_mode;	/* Use XTAL or PLL mode for PAL/SECAM */
5738b27ce1aSwiz     int			remote_control;      /* remote control detected */
5748b27ce1aSwiz     int			remote_control_addr;   /* remote control i2c address */
5758b27ce1aSwiz     char		msp_version_string[9]; /* MSP version string 34xxx-xx */
5768b27ce1aSwiz     int			msp_addr;	       /* MSP i2c address */
5778b27ce1aSwiz     char		dpl_version_string[9]; /* DPL version string 35xxx-xx */
5788b27ce1aSwiz     int			dpl_addr;	       /* DPL i2c address */
5798b27ce1aSwiz     int                 slow_msp_audio;	       /* 0 = use fast MSP3410/3415 programming sequence */
5808b27ce1aSwiz 					       /* 1 = use slow MSP3410/3415 programming sequence */
5812ad3fd95Swiz 					       /* 2 = use Tuner's Mono audio output via the MSP chip */
5822ad3fd95Swiz     int                 msp_use_mono_source;   /* use Tuner's Mono audio output via the MSP chip */
5832ad3fd95Swiz     int                 audio_mux_present;     /* 1 = has audio mux on GPIO lines, 0 = no audio mux */
5842ad3fd95Swiz     int                 msp_source_selected;   /* 0 = TV source, 1 = Line In source, 2 = FM Radio Source */
5856d70f903Sad     void		*sih;
5868b27ce1aSwiz 
5878b27ce1aSwiz };
5888b27ce1aSwiz 
5898b27ce1aSwiz typedef struct bktr_softc bktr_reg_t;
5908b27ce1aSwiz typedef struct bktr_softc* bktr_ptr_t;
5918b27ce1aSwiz 
5928b27ce1aSwiz #define Bt848_MAX_SIGN 16
5938b27ce1aSwiz 
5948b27ce1aSwiz struct bt848_card_sig {
5958b27ce1aSwiz   int card;
5968b27ce1aSwiz   int tuner;
5978b27ce1aSwiz   u_char signature[Bt848_MAX_SIGN];
5988b27ce1aSwiz };
5998b27ce1aSwiz 
6008b27ce1aSwiz 
6018b27ce1aSwiz /***********************************************************/
6028b27ce1aSwiz /* ioctl_cmd_t int on old versions, u_long on new versions */
6038b27ce1aSwiz /***********************************************************/
6048b27ce1aSwiz 
6058b27ce1aSwiz 
6068b27ce1aSwiz 
6078b27ce1aSwiz typedef u_long ioctl_cmd_t;
6088b27ce1aSwiz 
6098b27ce1aSwiz 
610