1 /* $NetBSD: cs4280.c,v 1.60 2010/05/25 08:37:10 pgoyette Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.60 2010/05/25 08:37:10 pgoyette Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 68 #include <dev/pci/pcidevs.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/cs4280reg.h> 71 #include <dev/pci/cs4280_image.h> 72 #include <dev/pci/cs428xreg.h> 73 74 #include <sys/audioio.h> 75 #include <dev/audio_if.h> 76 #include <dev/midi_if.h> 77 #include <dev/mulaw.h> 78 #include <dev/auconv.h> 79 80 #include <dev/ic/ac97reg.h> 81 #include <dev/ic/ac97var.h> 82 83 #include <dev/pci/cs428x.h> 84 85 #include <sys/bus.h> 86 #include <sys/bswap.h> 87 88 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 89 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 90 91 /* IF functions for audio driver */ 92 static int cs4280_match(device_t, cfdata_t, void *); 93 static void cs4280_attach(device_t, device_t, void *); 94 static int cs4280_intr(void *); 95 static int cs4280_query_encoding(void *, struct audio_encoding *); 96 static int cs4280_set_params(void *, int, int, audio_params_t *, 97 audio_params_t *, stream_filter_list_t *, 98 stream_filter_list_t *); 99 static int cs4280_halt_output(void *); 100 static int cs4280_halt_input(void *); 101 static int cs4280_getdev(void *, struct audio_device *); 102 static int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 103 void *, const audio_params_t *); 104 static int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 105 void *, const audio_params_t *); 106 static int cs4280_read_codec(void *, u_int8_t, u_int16_t *); 107 static int cs4280_write_codec(void *, u_int8_t, u_int16_t); 108 #if 0 109 static int cs4280_reset_codec(void *); 110 #endif 111 static enum ac97_host_flags cs4280_flags_codec(void *); 112 113 static bool cs4280_resume(device_t, const pmf_qual_t *); 114 static bool cs4280_suspend(device_t, const pmf_qual_t *); 115 116 /* Internal functions */ 117 static const struct cs4280_card_t * cs4280_identify_card(struct pci_attach_args *); 118 static int cs4280_piix4_match(struct pci_attach_args *); 119 static void cs4280_clkrun_hack(struct cs428x_softc *, int); 120 static void cs4280_clkrun_hack_init(struct cs428x_softc *); 121 static void cs4280_set_adc_rate(struct cs428x_softc *, int ); 122 static void cs4280_set_dac_rate(struct cs428x_softc *, int ); 123 static int cs4280_download(struct cs428x_softc *, const uint32_t *, uint32_t, 124 uint32_t); 125 static int cs4280_download_image(struct cs428x_softc *); 126 static void cs4280_reset(void *); 127 static int cs4280_init(struct cs428x_softc *, int); 128 static void cs4280_clear_fifos(struct cs428x_softc *); 129 130 #if CS4280_DEBUG > 10 131 /* Thease two function is only for checking image loading is succeeded or not. */ 132 static int cs4280_check_images(struct cs428x_softc *); 133 static int cs4280_checkimage(struct cs428x_softc *, uint32_t *, uint32_t, 134 uint32_t); 135 #endif 136 137 /* Special cards */ 138 struct cs4280_card_t 139 { 140 pcireg_t id; 141 enum cs428x_flags flags; 142 }; 143 144 #define _card(vend, prod, flags) \ 145 {PCI_ID_CODE(vend, prod), flags} 146 147 static const struct cs4280_card_t cs4280_cards[] = { 148 #if 0 /* untested, from ALSA driver */ 149 _card(PCI_VENDOR_MITAC, PCI_PRODUCT_MITAC_MI6020, 150 CS428X_FLAG_INVAC97EAMP), 151 #endif 152 _card(PCI_VENDOR_TURTLE_BEACH, PCI_PRODUCT_TURTLE_BEACH_SANTA_CRUZ, 153 CS428X_FLAG_INVAC97EAMP), 154 _card(PCI_VENDOR_IBM, PCI_PRODUCT_IBM_TPAUDIO, 155 CS428X_FLAG_CLKRUNHACK) 156 }; 157 158 #undef _card 159 160 #define CS4280_CARDS_SIZE (sizeof(cs4280_cards)/sizeof(cs4280_cards[0])) 161 162 static const struct audio_hw_if cs4280_hw_if = { 163 NULL, /* open */ 164 NULL, /* close */ 165 NULL, 166 cs4280_query_encoding, 167 cs4280_set_params, 168 cs428x_round_blocksize, 169 NULL, 170 NULL, 171 NULL, 172 NULL, 173 NULL, 174 cs4280_halt_output, 175 cs4280_halt_input, 176 NULL, 177 cs4280_getdev, 178 NULL, 179 cs428x_mixer_set_port, 180 cs428x_mixer_get_port, 181 cs428x_query_devinfo, 182 cs428x_malloc, 183 cs428x_free, 184 cs428x_round_buffersize, 185 cs428x_mappage, 186 cs428x_get_props, 187 cs4280_trigger_output, 188 cs4280_trigger_input, 189 NULL, 190 NULL, 191 }; 192 193 #if NMIDI > 0 194 /* Midi Interface */ 195 static int cs4280_midi_open(void *, int, void (*)(void *, int), 196 void (*)(void *), void *); 197 static void cs4280_midi_close(void*); 198 static int cs4280_midi_output(void *, int); 199 static void cs4280_midi_getinfo(void *, struct midi_info *); 200 201 static const struct midi_hw_if cs4280_midi_hw_if = { 202 cs4280_midi_open, 203 cs4280_midi_close, 204 cs4280_midi_output, 205 cs4280_midi_getinfo, 206 0, 207 }; 208 #endif 209 210 CFATTACH_DECL(clcs, sizeof(struct cs428x_softc), 211 cs4280_match, cs4280_attach, NULL, NULL); 212 213 static struct audio_device cs4280_device = { 214 "CS4280", 215 "", 216 "cs4280" 217 }; 218 219 220 static int 221 cs4280_match(device_t parent, cfdata_t match, void *aux) 222 { 223 struct pci_attach_args *pa; 224 225 pa = (struct pci_attach_args *)aux; 226 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 227 return 0; 228 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 229 #if 0 /* I can't confirm */ 230 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 231 #endif 232 ) 233 return 1; 234 return 0; 235 } 236 237 static void 238 cs4280_attach(device_t parent, device_t self, void *aux) 239 { 240 struct cs428x_softc *sc; 241 struct pci_attach_args *pa; 242 pci_chipset_tag_t pc; 243 const struct cs4280_card_t *cs_card; 244 char const *intrstr; 245 const char *vendor, *product; 246 pcireg_t reg; 247 char devinfo[256]; 248 uint32_t mem; 249 int error; 250 251 sc = device_private(self); 252 pa = (struct pci_attach_args *)aux; 253 pc = pa->pa_pc; 254 aprint_naive(": Audio controller\n"); 255 256 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 257 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 258 PCI_REVISION(pa->pa_class)); 259 260 cs_card = cs4280_identify_card(pa); 261 if (cs_card != NULL) { 262 vendor = pci_findvendor(cs_card->id); 263 product = pci_findproduct(cs_card->id); 264 if (vendor == NULL) 265 aprint_normal_dev(&sc->sc_dev, 266 "vendor 0x%04x product 0x%04x\n", 267 PCI_VENDOR(cs_card->id), 268 PCI_PRODUCT(cs_card->id)); 269 else if (product == NULL) 270 aprint_normal_dev(&sc->sc_dev, "%s product 0x%04x\n", 271 vendor, PCI_PRODUCT(cs_card->id)); 272 else 273 aprint_normal_dev(&sc->sc_dev, "%s %s\n", 274 vendor, product); 275 sc->sc_flags = cs_card->flags; 276 } else { 277 sc->sc_flags = CS428X_FLAG_NONE; 278 } 279 280 sc->sc_pc = pa->pa_pc; 281 sc->sc_pt = pa->pa_tag; 282 283 /* Map I/O register */ 284 if (pci_mapreg_map(pa, PCI_BA0, 285 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 286 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 287 aprint_error_dev(&sc->sc_dev, "can't map BA0 space\n"); 288 return; 289 } 290 if (pci_mapreg_map(pa, PCI_BA1, 291 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 292 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 293 aprint_error_dev(&sc->sc_dev, "can't map BA1 space\n"); 294 return; 295 } 296 297 sc->sc_dmatag = pa->pa_dmat; 298 299 /* power up chip */ 300 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 301 pci_activate_null)) && error != EOPNOTSUPP) { 302 aprint_error_dev(&sc->sc_dev, "cannot activate %d\n", error); 303 return; 304 } 305 306 /* Enable the device (set bus master flag) */ 307 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 308 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 309 reg | PCI_COMMAND_MASTER_ENABLE); 310 311 /* LATENCY_TIMER setting */ 312 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 313 if ( PCI_LATTIMER(mem) < 32 ) { 314 mem &= 0xffff00ff; 315 mem |= 0x00002000; 316 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 317 } 318 319 /* CLKRUN hack initialization */ 320 cs4280_clkrun_hack_init(sc); 321 322 /* Map and establish the interrupt. */ 323 if (pci_intr_map(pa, &sc->intrh)) { 324 aprint_error_dev(&sc->sc_dev, "couldn't map interrupt\n"); 325 return; 326 } 327 intrstr = pci_intr_string(pc, sc->intrh); 328 329 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO, 330 cs4280_intr, sc); 331 if (sc->sc_ih == NULL) { 332 aprint_error_dev(&sc->sc_dev, "couldn't establish interrupt"); 333 if (intrstr != NULL) 334 aprint_error(" at %s", intrstr); 335 aprint_error("\n"); 336 return; 337 } 338 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 339 340 /* Initialization */ 341 if(cs4280_init(sc, 1) != 0) 342 return; 343 344 sc->type = TYPE_CS4280; 345 sc->halt_input = cs4280_halt_input; 346 sc->halt_output = cs4280_halt_output; 347 348 /* setup buffer related parameters */ 349 sc->dma_size = CS4280_DCHUNK; 350 sc->dma_align = CS4280_DALIGN; 351 sc->hw_blocksize = CS4280_ICHUNK; 352 353 /* AC 97 attachment */ 354 sc->host_if.arg = sc; 355 sc->host_if.attach = cs428x_attach_codec; 356 sc->host_if.read = cs4280_read_codec; 357 sc->host_if.write = cs4280_write_codec; 358 #if 0 359 sc->host_if.reset = cs4280_reset_codec; 360 #else 361 sc->host_if.reset = NULL; 362 #endif 363 sc->host_if.flags = cs4280_flags_codec; 364 if (ac97_attach(&sc->host_if, self) != 0) { 365 aprint_error_dev(&sc->sc_dev, "ac97_attach failed\n"); 366 return; 367 } 368 369 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 370 371 #if NMIDI > 0 372 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 373 #endif 374 375 if (!pmf_device_register(self, cs4280_suspend, cs4280_resume)) 376 aprint_error_dev(self, "couldn't establish power handler\n"); 377 } 378 379 /* Interrupt handling function */ 380 static int 381 cs4280_intr(void *p) 382 { 383 /* 384 * XXX 385 * 386 * Since CS4280 has only 4kB DMA buffer and 387 * interrupt occurs every 2kB block, I create dummy buffer 388 * which returns to audio driver and actual DMA buffer 389 * using in DMA transfer. 390 * 391 * 392 * ring buffer in audio.c is pointed by BUFADDR 393 * <------ ring buffer size == 64kB ------> 394 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 395 * |= = = =|= = = =|= = = =|= = = =|= = = =| 396 * | | | | | | <- call audio_intp every 397 * sc->sc_[pr]_count time. 398 * 399 * actual DMA buffer is pointed by KERNADDR 400 * <-> DMA buffer size = 4kB 401 * |= =| 402 * 403 * 404 */ 405 struct cs428x_softc *sc; 406 uint32_t intr, mem; 407 char * empty_dma; 408 int handled; 409 410 sc = p; 411 handled = 0; 412 /* grab interrupt register then clear it */ 413 intr = BA0READ4(sc, CS4280_HISR); 414 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 415 416 /* not for us ? */ 417 if ((intr & HISR_INTENA) == 0) 418 return 0; 419 420 /* Playback Interrupt */ 421 if (intr & HISR_PINT) { 422 handled = 1; 423 mem = BA1READ4(sc, CS4280_PFIE); 424 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 425 if (sc->sc_prun) { 426 if ((sc->sc_pi%sc->sc_pcount) == 0) 427 sc->sc_pintr(sc->sc_parg); 428 /* copy buffer */ 429 ++sc->sc_pi; 430 empty_dma = sc->sc_pdma->addr; 431 if (sc->sc_pi&1) 432 empty_dma += sc->hw_blocksize; 433 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 434 sc->sc_pn += sc->hw_blocksize; 435 if (sc->sc_pn >= sc->sc_pe) 436 sc->sc_pn = sc->sc_ps; 437 } else { 438 aprint_error_dev(&sc->sc_dev, "unexpected play intr\n"); 439 } 440 BA1WRITE4(sc, CS4280_PFIE, mem); 441 } 442 /* Capture Interrupt */ 443 if (intr & HISR_CINT) { 444 int i; 445 int16_t rdata; 446 447 handled = 1; 448 mem = BA1READ4(sc, CS4280_CIE); 449 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 450 451 if (sc->sc_rrun) { 452 ++sc->sc_ri; 453 empty_dma = sc->sc_rdma->addr; 454 if ((sc->sc_ri&1) == 0) 455 empty_dma += sc->hw_blocksize; 456 457 /* 458 * XXX 459 * I think this audio data conversion should be 460 * happend in upper layer, but I put this here 461 * since there is no conversion function available. 462 */ 463 switch(sc->sc_rparam) { 464 case CF_16BIT_STEREO: 465 /* just copy it */ 466 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 467 sc->sc_rn += sc->hw_blocksize; 468 break; 469 case CF_16BIT_MONO: 470 for (i = 0; i < 512; i++) { 471 rdata = *((int16_t *)empty_dma)>>1; 472 empty_dma += 2; 473 rdata += *((int16_t *)empty_dma)>>1; 474 empty_dma += 2; 475 *((int16_t *)sc->sc_rn) = rdata; 476 sc->sc_rn += 2; 477 } 478 break; 479 case CF_8BIT_STEREO: 480 for (i = 0; i < 512; i++) { 481 rdata = *((int16_t*)empty_dma); 482 empty_dma += 2; 483 *sc->sc_rn++ = rdata >> 8; 484 rdata = *((int16_t*)empty_dma); 485 empty_dma += 2; 486 *sc->sc_rn++ = rdata >> 8; 487 } 488 break; 489 case CF_8BIT_MONO: 490 for (i = 0; i < 512; i++) { 491 rdata = *((int16_t*)empty_dma) >>1; 492 empty_dma += 2; 493 rdata += *((int16_t*)empty_dma) >>1; 494 empty_dma += 2; 495 *sc->sc_rn++ = rdata >>8; 496 } 497 break; 498 default: 499 /* Should not reach here */ 500 aprint_error_dev(&sc->sc_dev, 501 "unknown sc->sc_rparam: %d\n", 502 sc->sc_rparam); 503 } 504 if (sc->sc_rn >= sc->sc_re) 505 sc->sc_rn = sc->sc_rs; 506 } 507 BA1WRITE4(sc, CS4280_CIE, mem); 508 509 if (sc->sc_rrun) { 510 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 511 sc->sc_rintr(sc->sc_rarg); 512 } else { 513 aprint_error_dev(&sc->sc_dev, 514 "unexpected record intr\n"); 515 } 516 } 517 518 #if NMIDI > 0 519 /* Midi port Interrupt */ 520 if (intr & HISR_MIDI) { 521 int data; 522 523 handled = 1; 524 DPRINTF(("i: %d: ", 525 BA0READ4(sc, CS4280_MIDSR))); 526 /* Read the received data */ 527 while ((sc->sc_iintr != NULL) && 528 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 529 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 530 DPRINTF(("r:%x\n",data)); 531 sc->sc_iintr(sc->sc_arg, data); 532 } 533 534 /* Write the data */ 535 #if 1 536 /* XXX: 537 * It seems "Transmit Buffer Full" never activate until EOI 538 * is deliverd. Shall I throw EOI top of this routine ? 539 */ 540 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 541 DPRINTF(("w: ")); 542 if (sc->sc_ointr != NULL) 543 sc->sc_ointr(sc->sc_arg); 544 } 545 #else 546 while ((sc->sc_ointr != NULL) && 547 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 548 DPRINTF(("w: ")); 549 sc->sc_ointr(sc->sc_arg); 550 } 551 #endif 552 DPRINTF(("\n")); 553 } 554 #endif 555 556 return handled; 557 } 558 559 static int 560 cs4280_query_encoding(void *addr, struct audio_encoding *fp) 561 { 562 switch (fp->index) { 563 case 0: 564 strcpy(fp->name, AudioEulinear); 565 fp->encoding = AUDIO_ENCODING_ULINEAR; 566 fp->precision = 8; 567 fp->flags = 0; 568 break; 569 case 1: 570 strcpy(fp->name, AudioEmulaw); 571 fp->encoding = AUDIO_ENCODING_ULAW; 572 fp->precision = 8; 573 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 574 break; 575 case 2: 576 strcpy(fp->name, AudioEalaw); 577 fp->encoding = AUDIO_ENCODING_ALAW; 578 fp->precision = 8; 579 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 580 break; 581 case 3: 582 strcpy(fp->name, AudioEslinear); 583 fp->encoding = AUDIO_ENCODING_SLINEAR; 584 fp->precision = 8; 585 fp->flags = 0; 586 break; 587 case 4: 588 strcpy(fp->name, AudioEslinear_le); 589 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 590 fp->precision = 16; 591 fp->flags = 0; 592 break; 593 case 5: 594 strcpy(fp->name, AudioEulinear_le); 595 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 596 fp->precision = 16; 597 fp->flags = 0; 598 break; 599 case 6: 600 strcpy(fp->name, AudioEslinear_be); 601 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 602 fp->precision = 16; 603 fp->flags = 0; 604 break; 605 case 7: 606 strcpy(fp->name, AudioEulinear_be); 607 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 608 fp->precision = 16; 609 fp->flags = 0; 610 break; 611 default: 612 return EINVAL; 613 } 614 return 0; 615 } 616 617 static int 618 cs4280_set_params(void *addr, int setmode, int usemode, 619 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 620 stream_filter_list_t *rfil) 621 { 622 audio_params_t hw; 623 struct cs428x_softc *sc; 624 struct audio_params *p; 625 stream_filter_list_t *fil; 626 int mode; 627 628 sc = addr; 629 for (mode = AUMODE_RECORD; mode != -1; 630 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 631 if ((setmode & mode) == 0) 632 continue; 633 634 p = mode == AUMODE_PLAY ? play : rec; 635 636 if (p == play) { 637 DPRINTFN(5,("play: sample=%d precision=%d channels=%d\n", 638 p->sample_rate, p->precision, p->channels)); 639 /* play back data format may be 8- or 16-bit and 640 * either stereo or mono. 641 * playback rate may range from 8000Hz to 48000Hz 642 */ 643 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 644 (p->precision != 8 && p->precision != 16) || 645 (p->channels != 1 && p->channels != 2) ) { 646 return EINVAL; 647 } 648 } else { 649 DPRINTFN(5,("rec: sample=%d precision=%d channels=%d\n", 650 p->sample_rate, p->precision, p->channels)); 651 /* capture data format must be 16bit stereo 652 * and sample rate range from 11025Hz to 48000Hz. 653 * 654 * XXX: it looks like to work with 8000Hz, 655 * although data sheets say lower limit is 656 * 11025 Hz. 657 */ 658 659 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 660 (p->precision != 8 && p->precision != 16) || 661 (p->channels != 1 && p->channels != 2) ) { 662 return EINVAL; 663 } 664 } 665 fil = mode == AUMODE_PLAY ? pfil : rfil; 666 hw = *p; 667 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 668 669 /* capturing data is slinear */ 670 switch (p->encoding) { 671 case AUDIO_ENCODING_SLINEAR_BE: 672 if (mode == AUMODE_RECORD && p->precision == 16) { 673 fil->append(fil, swap_bytes, &hw); 674 } 675 break; 676 case AUDIO_ENCODING_SLINEAR_LE: 677 break; 678 case AUDIO_ENCODING_ULINEAR_BE: 679 if (mode == AUMODE_RECORD) { 680 fil->append(fil, p->precision == 16 681 ? swap_bytes_change_sign16 682 : change_sign8, &hw); 683 } 684 break; 685 case AUDIO_ENCODING_ULINEAR_LE: 686 if (mode == AUMODE_RECORD) { 687 fil->append(fil, p->precision == 16 688 ? change_sign16 : change_sign8, 689 &hw); 690 } 691 break; 692 case AUDIO_ENCODING_ULAW: 693 if (mode == AUMODE_PLAY) { 694 hw.precision = 16; 695 hw.validbits = 16; 696 fil->append(fil, mulaw_to_linear16, &hw); 697 } else { 698 fil->append(fil, linear8_to_mulaw, &hw); 699 } 700 break; 701 case AUDIO_ENCODING_ALAW: 702 if (mode == AUMODE_PLAY) { 703 hw.precision = 16; 704 hw.validbits = 16; 705 fil->append(fil, alaw_to_linear16, &hw); 706 } else { 707 fil->append(fil, linear8_to_alaw, &hw); 708 } 709 break; 710 default: 711 return EINVAL; 712 } 713 } 714 715 /* set sample rate */ 716 cs4280_set_dac_rate(sc, play->sample_rate); 717 cs4280_set_adc_rate(sc, rec->sample_rate); 718 return 0; 719 } 720 721 static int 722 cs4280_halt_output(void *addr) 723 { 724 struct cs428x_softc *sc; 725 uint32_t mem; 726 727 sc = addr; 728 mem = BA1READ4(sc, CS4280_PCTL); 729 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 730 sc->sc_prun = 0; 731 cs4280_clkrun_hack(sc, -1); 732 733 return 0; 734 } 735 736 static int 737 cs4280_halt_input(void *addr) 738 { 739 struct cs428x_softc *sc; 740 uint32_t mem; 741 742 sc = addr; 743 mem = BA1READ4(sc, CS4280_CCTL); 744 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 745 sc->sc_rrun = 0; 746 cs4280_clkrun_hack(sc, -1); 747 748 return 0; 749 } 750 751 static int 752 cs4280_getdev(void *addr, struct audio_device *retp) 753 { 754 755 *retp = cs4280_device; 756 return 0; 757 } 758 759 static int 760 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 761 void (*intr)(void *), void *arg, 762 const audio_params_t *param) 763 { 764 struct cs428x_softc *sc; 765 uint32_t pfie, pctl, pdtc; 766 struct cs428x_dma *p; 767 768 sc = addr; 769 #ifdef DIAGNOSTIC 770 if (sc->sc_prun) 771 printf("cs4280_trigger_output: already running\n"); 772 #endif 773 sc->sc_prun = 1; 774 cs4280_clkrun_hack(sc, 1); 775 776 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 777 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 778 sc->sc_pintr = intr; 779 sc->sc_parg = arg; 780 781 /* stop playback DMA */ 782 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 783 784 /* setup PDTC */ 785 pdtc = BA1READ4(sc, CS4280_PDTC); 786 pdtc &= ~PDTC_MASK; 787 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 788 BA1WRITE4(sc, CS4280_PDTC, pdtc); 789 790 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 791 param->precision, param->channels, param->encoding)); 792 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 793 continue; 794 if (p == NULL) { 795 printf("cs4280_trigger_output: bad addr %p\n", start); 796 return EINVAL; 797 } 798 if (DMAADDR(p) % sc->dma_align != 0 ) { 799 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 800 "4kB align\n", (ulong)DMAADDR(p)); 801 return EINVAL; 802 } 803 804 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 805 sc->sc_ps = (char *)start; 806 sc->sc_pe = (char *)end; 807 sc->sc_pdma = p; 808 sc->sc_pbuf = KERNADDR(p); 809 sc->sc_pi = 0; 810 sc->sc_pn = sc->sc_ps; 811 if (blksize >= sc->dma_size) { 812 sc->sc_pn = sc->sc_ps + sc->dma_size; 813 memcpy(sc->sc_pbuf, start, sc->dma_size); 814 ++sc->sc_pi; 815 } else { 816 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 817 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 818 } 819 820 /* initiate playback DMA */ 821 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 822 823 /* set PFIE */ 824 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 825 826 if (param->precision == 8) 827 pfie |= PFIE_8BIT; 828 if (param->channels == 1) 829 pfie |= PFIE_MONO; 830 831 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 832 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 833 pfie |= PFIE_SWAPPED; 834 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 835 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 836 pfie |= PFIE_UNSIGNED; 837 838 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 839 840 sc->sc_prate = param->sample_rate; 841 cs4280_set_dac_rate(sc, param->sample_rate); 842 843 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 844 pctl |= sc->pctl; 845 BA1WRITE4(sc, CS4280_PCTL, pctl); 846 return 0; 847 } 848 849 static int 850 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 851 void (*intr)(void *), void *arg, 852 const audio_params_t *param) 853 { 854 struct cs428x_softc *sc; 855 uint32_t cctl, cie; 856 struct cs428x_dma *p; 857 858 sc = addr; 859 #ifdef DIAGNOSTIC 860 if (sc->sc_rrun) 861 printf("cs4280_trigger_input: already running\n"); 862 #endif 863 sc->sc_rrun = 1; 864 cs4280_clkrun_hack(sc, 1); 865 866 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 867 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 868 sc->sc_rintr = intr; 869 sc->sc_rarg = arg; 870 871 /* stop capture DMA */ 872 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 873 874 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 875 continue; 876 if (p == NULL) { 877 printf("cs4280_trigger_input: bad addr %p\n", start); 878 return EINVAL; 879 } 880 if (DMAADDR(p) % sc->dma_align != 0) { 881 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 882 "4kB align\n", (ulong)DMAADDR(p)); 883 return EINVAL; 884 } 885 886 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 887 sc->sc_rs = (char *)start; 888 sc->sc_re = (char *)end; 889 sc->sc_rdma = p; 890 sc->sc_rbuf = KERNADDR(p); 891 sc->sc_ri = 0; 892 sc->sc_rn = sc->sc_rs; 893 894 /* initiate capture DMA */ 895 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 896 897 /* setup format information for internal converter */ 898 sc->sc_rparam = 0; 899 if (param->precision == 8) { 900 sc->sc_rparam += CF_8BIT; 901 sc->sc_rcount <<= 1; 902 } 903 if (param->channels == 1) { 904 sc->sc_rparam += CF_MONO; 905 sc->sc_rcount <<= 1; 906 } 907 908 /* set CIE */ 909 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 910 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 911 912 sc->sc_rrate = param->sample_rate; 913 cs4280_set_adc_rate(sc, param->sample_rate); 914 915 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 916 cctl |= sc->cctl; 917 BA1WRITE4(sc, CS4280_CCTL, cctl); 918 return 0; 919 } 920 921 static bool 922 cs4280_suspend(device_t dv, const pmf_qual_t *qual) 923 { 924 struct cs428x_softc *sc = device_private(dv); 925 926 if (sc->sc_prun) { 927 sc->sc_suspend_state.cs4280.pctl = BA1READ4(sc, CS4280_PCTL); 928 sc->sc_suspend_state.cs4280.pfie = BA1READ4(sc, CS4280_PFIE); 929 sc->sc_suspend_state.cs4280.pba = BA1READ4(sc, CS4280_PBA); 930 sc->sc_suspend_state.cs4280.pdtc = BA1READ4(sc, CS4280_PDTC); 931 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 932 sc->sc_suspend_state.cs4280.pctl, 933 sc->sc_suspend_state.cs4280.pfie, 934 sc->sc_suspend_state.cs4280.pba, 935 sc->sc_suspend_state.cs4280.pdtc)); 936 } 937 938 /* save current capture status */ 939 if (sc->sc_rrun) { 940 sc->sc_suspend_state.cs4280.cctl = BA1READ4(sc, CS4280_CCTL); 941 sc->sc_suspend_state.cs4280.cie = BA1READ4(sc, CS4280_CIE); 942 sc->sc_suspend_state.cs4280.cba = BA1READ4(sc, CS4280_CBA); 943 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 944 sc->sc_suspend_state.cs4280.cctl, 945 sc->sc_suspend_state.cs4280.cie, 946 sc->sc_suspend_state.cs4280.cba)); 947 } 948 949 /* Stop DMA */ 950 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl & ~PCTL_MASK); 951 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 952 953 return true; 954 } 955 956 static bool 957 cs4280_resume(device_t dv, const pmf_qual_t *qual) 958 { 959 struct cs428x_softc *sc = device_private(dv); 960 961 cs4280_init(sc, 0); 962 #if 0 963 cs4280_reset_codec(sc); 964 #endif 965 /* restore ac97 registers */ 966 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 967 968 /* restore DMA related status */ 969 if(sc->sc_prun) { 970 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 971 sc->sc_suspend_state.cs4280.pctl, 972 sc->sc_suspend_state.cs4280.pfie, 973 sc->sc_suspend_state.cs4280.pba, 974 sc->sc_suspend_state.cs4280.pdtc)); 975 cs4280_set_dac_rate(sc, sc->sc_prate); 976 BA1WRITE4(sc, CS4280_PDTC, sc->sc_suspend_state.cs4280.pdtc); 977 BA1WRITE4(sc, CS4280_PBA, sc->sc_suspend_state.cs4280.pba); 978 BA1WRITE4(sc, CS4280_PFIE, sc->sc_suspend_state.cs4280.pfie); 979 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl); 980 } 981 982 if (sc->sc_rrun) { 983 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 984 sc->sc_suspend_state.cs4280.cctl, 985 sc->sc_suspend_state.cs4280.cie, 986 sc->sc_suspend_state.cs4280.cba)); 987 cs4280_set_adc_rate(sc, sc->sc_rrate); 988 BA1WRITE4(sc, CS4280_CBA, sc->sc_suspend_state.cs4280.cba); 989 BA1WRITE4(sc, CS4280_CIE, sc->sc_suspend_state.cs4280.cie); 990 BA1WRITE4(sc, CS4280_CCTL, sc->sc_suspend_state.cs4280.cctl); 991 } 992 993 return true; 994 } 995 996 static int 997 cs4280_read_codec(void *addr, u_int8_t reg, u_int16_t *result) 998 { 999 struct cs428x_softc *sc = addr; 1000 int rv; 1001 1002 cs4280_clkrun_hack(sc, 1); 1003 rv = cs428x_read_codec(addr, reg, result); 1004 cs4280_clkrun_hack(sc, -1); 1005 1006 return rv; 1007 } 1008 1009 static int 1010 cs4280_write_codec(void *addr, u_int8_t reg, u_int16_t data) 1011 { 1012 struct cs428x_softc *sc = addr; 1013 int rv; 1014 1015 cs4280_clkrun_hack(sc, 1); 1016 rv = cs428x_write_codec(addr, reg, data); 1017 cs4280_clkrun_hack(sc, -1); 1018 1019 return rv; 1020 } 1021 1022 #if 0 /* XXX buggy and not required */ 1023 /* control AC97 codec */ 1024 static int 1025 cs4280_reset_codec(void *addr) 1026 { 1027 struct cs428x_softc *sc; 1028 int n; 1029 1030 sc = addr; 1031 1032 /* Reset codec */ 1033 BA0WRITE4(sc, CS428X_ACCTL, 0); 1034 delay(100); /* delay 100us */ 1035 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1036 1037 /* 1038 * It looks like we do the following procedure, too 1039 */ 1040 1041 /* Enable AC-link sync generation */ 1042 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1043 delay(50*1000); /* XXX delay 50ms */ 1044 1045 /* Assert valid frame signal */ 1046 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1047 1048 /* Wait for valid AC97 input slot */ 1049 n = 0; 1050 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1051 (ACISV_ISV3 | ACISV_ISV4)) { 1052 delay(1000); 1053 if (++n > 1000) { 1054 printf("reset_codec: AC97 inputs slot ready timeout\n"); 1055 return ETIMEDOUT; 1056 } 1057 } 1058 1059 return 0; 1060 } 1061 #endif 1062 1063 static enum ac97_host_flags cs4280_flags_codec(void *addr) 1064 { 1065 struct cs428x_softc *sc; 1066 1067 sc = addr; 1068 if (sc->sc_flags & CS428X_FLAG_INVAC97EAMP) 1069 return AC97_HOST_INVERTED_EAMP; 1070 1071 return 0; 1072 } 1073 1074 /* Internal functions */ 1075 1076 static const struct cs4280_card_t * 1077 cs4280_identify_card(struct pci_attach_args *pa) 1078 { 1079 pcireg_t idreg; 1080 u_int16_t i; 1081 1082 idreg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1083 for (i = 0; i < CS4280_CARDS_SIZE; i++) { 1084 if (idreg == cs4280_cards[i].id) 1085 return &cs4280_cards[i]; 1086 } 1087 1088 return NULL; 1089 } 1090 1091 static int 1092 cs4280_piix4_match(struct pci_attach_args *pa) 1093 { 1094 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 1095 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_PMC) { 1096 return 1; 1097 } 1098 1099 return 0; 1100 } 1101 1102 static void 1103 cs4280_clkrun_hack(struct cs428x_softc *sc, int change) 1104 { 1105 uint16_t control, val; 1106 1107 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1108 return; 1109 1110 sc->sc_active += change; 1111 val = control = bus_space_read_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10); 1112 if (!sc->sc_active) 1113 val |= 0x2000; 1114 else 1115 val &= ~0x2000; 1116 if (val != control) 1117 bus_space_write_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10, val); 1118 } 1119 1120 static void 1121 cs4280_clkrun_hack_init(struct cs428x_softc *sc) 1122 { 1123 struct pci_attach_args smbuspa; 1124 uint16_t reg; 1125 pcireg_t port; 1126 1127 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1128 return; 1129 1130 if (pci_find_device(&smbuspa, cs4280_piix4_match)) { 1131 sc->sc_active = 0; 1132 aprint_normal_dev(&sc->sc_dev, "enabling CLKRUN hack\n"); 1133 1134 reg = pci_conf_read(smbuspa.pa_pc, smbuspa.pa_tag, 0x40); 1135 port = reg & 0xffc0; 1136 aprint_normal_dev(&sc->sc_dev, "power management port 0x%x\n", 1137 port); 1138 1139 sc->sc_pm_iot = smbuspa.pa_iot; 1140 if (bus_space_map(sc->sc_pm_iot, port, 0x20 /* XXX */, 0, 1141 &sc->sc_pm_ioh) == 0) 1142 return; 1143 } 1144 1145 /* handle error */ 1146 sc->sc_flags &= ~CS428X_FLAG_CLKRUNHACK; 1147 aprint_normal_dev(&sc->sc_dev, "disabling CLKRUN hack\n"); 1148 } 1149 1150 static void 1151 cs4280_set_adc_rate(struct cs428x_softc *sc, int rate) 1152 { 1153 /* calculate capture rate: 1154 * 1155 * capture_coefficient_increment = -round(rate*128*65536/48000; 1156 * capture_phase_increment = floor(48000*65536*1024/rate); 1157 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 1158 * cy = floor(cx/200); 1159 * capture_sample_rate_correction = cx - 200*cy; 1160 * capture_delay = ceil(24*48000/rate); 1161 * capture_num_triplets = floor(65536*rate/24000); 1162 * capture_group_length = 24000/GCD(rate, 24000); 1163 * where GCD means "Greatest Common Divisor". 1164 * 1165 * capture_coefficient_increment, capture_phase_increment and 1166 * capture_num_triplets are 32-bit signed quantities. 1167 * capture_sample_rate_correction and capture_group_length are 1168 * 16-bit signed quantities. 1169 * capture_delay is a 14-bit unsigned quantity. 1170 */ 1171 uint32_t cci, cpi, cnt, cx, cy, tmp1; 1172 uint16_t csrc, cgl, cdlay; 1173 1174 /* XXX 1175 * Even though, embedded_audio_spec says capture rate range 11025 to 1176 * 48000, dhwiface.cpp says, 1177 * 1178 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1179 * Return an error if an attempt is made to stray outside that limit." 1180 * 1181 * so assume range as 48000/9 to 48000 1182 */ 1183 1184 if (rate < 8000) 1185 rate = 8000; 1186 if (rate > 48000) 1187 rate = 48000; 1188 1189 cx = rate << 16; 1190 cci = cx / 48000; 1191 cx -= cci * 48000; 1192 cx <<= 7; 1193 cci <<= 7; 1194 cci += cx / 48000; 1195 cci = - cci; 1196 1197 cx = 48000 << 16; 1198 cpi = cx / rate; 1199 cx -= cpi * rate; 1200 cx <<= 10; 1201 cpi <<= 10; 1202 cy = cx / rate; 1203 cpi += cy; 1204 cx -= cy * rate; 1205 1206 cy = cx / 200; 1207 csrc = cx - 200*cy; 1208 1209 cdlay = ((48000 * 24) + rate - 1) / rate; 1210 #if 0 1211 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1212 #endif 1213 1214 cnt = rate << 16; 1215 cnt /= 24000; 1216 1217 cgl = 1; 1218 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1219 if (((rate / tmp1) * tmp1) != rate) 1220 cgl *= 2; 1221 } 1222 if (((rate / 3) * 3) != rate) 1223 cgl *= 3; 1224 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1225 if (((rate / tmp1) * tmp1) != rate) 1226 cgl *= 5; 1227 } 1228 #if 0 1229 /* XXX what manual says */ 1230 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1231 tmp1 |= csrc<<16; 1232 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1233 #else 1234 /* suggested by cs461x.c (ALSA driver) */ 1235 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1236 #endif 1237 1238 #if 0 1239 /* I am confused. The sample rate calculation section says 1240 * cci *is* 32-bit signed quantity but in the parameter description 1241 * section, CCI only assigned 16bit. 1242 * I believe size of the variable. 1243 */ 1244 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1245 tmp1 |= cci<<16; 1246 BA1WRITE4(sc, CS4280_CCI, tmp1); 1247 #else 1248 BA1WRITE4(sc, CS4280_CCI, cci); 1249 #endif 1250 1251 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1252 tmp1 |= cdlay <<18; 1253 BA1WRITE4(sc, CS4280_CD, tmp1); 1254 1255 BA1WRITE4(sc, CS4280_CPI, cpi); 1256 1257 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1258 tmp1 |= cgl; 1259 BA1WRITE4(sc, CS4280_CGL, tmp1); 1260 1261 BA1WRITE4(sc, CS4280_CNT, cnt); 1262 1263 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1264 tmp1 |= cgl; 1265 BA1WRITE4(sc, CS4280_CGC, tmp1); 1266 } 1267 1268 static void 1269 cs4280_set_dac_rate(struct cs428x_softc *sc, int rate) 1270 { 1271 /* 1272 * playback rate may range from 8000Hz to 48000Hz 1273 * 1274 * play_phase_increment = floor(rate*65536*1024/48000) 1275 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1276 * py=floor(px/200) 1277 * play_sample_rate_correction = px - 200*py 1278 * 1279 * play_phase_increment is a 32bit signed quantity. 1280 * play_sample_rate_correction is a 16bit signed quantity. 1281 */ 1282 int32_t ppi; 1283 int16_t psrc; 1284 uint32_t px, py; 1285 1286 if (rate < 8000) 1287 rate = 8000; 1288 if (rate > 48000) 1289 rate = 48000; 1290 px = rate << 16; 1291 ppi = px/48000; 1292 px -= ppi*48000; 1293 ppi <<= 10; 1294 px <<= 10; 1295 py = px / 48000; 1296 ppi += py; 1297 px -= py*48000; 1298 py = px/200; 1299 px -= py*200; 1300 psrc = px; 1301 #if 0 1302 /* what manual says */ 1303 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1304 BA1WRITE4(sc, CS4280_PSRC, 1305 ( ((psrc<<16) & PSRC_MASK) | px )); 1306 #else 1307 /* suggested by cs461x.c (ALSA driver) */ 1308 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1309 #endif 1310 BA1WRITE4(sc, CS4280_PPI, ppi); 1311 } 1312 1313 /* Download Processor Code and Data image */ 1314 static int 1315 cs4280_download(struct cs428x_softc *sc, const uint32_t *src, 1316 uint32_t offset, uint32_t len) 1317 { 1318 uint32_t ctr; 1319 #if CS4280_DEBUG > 10 1320 uint32_t con, data; 1321 uint8_t c0, c1, c2, c3; 1322 #endif 1323 if ((offset & 3) || (len & 3)) 1324 return -1; 1325 1326 len /= sizeof(uint32_t); 1327 for (ctr = 0; ctr < len; ctr++) { 1328 /* XXX: 1329 * I cannot confirm this is the right thing or not 1330 * on BIG-ENDIAN machines. 1331 */ 1332 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1333 #if CS4280_DEBUG > 10 1334 data = htole32(*(src+ctr)); 1335 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1336 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1337 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1338 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1339 con = (c3 << 24) | (c2 << 16) | (c1 << 8) | c0; 1340 if (data != con ) { 1341 printf("0x%06x: write=0x%08x read=0x%08x\n", 1342 offset+ctr*4, data, con); 1343 return -1; 1344 } 1345 #endif 1346 } 1347 return 0; 1348 } 1349 1350 static int 1351 cs4280_download_image(struct cs428x_softc *sc) 1352 { 1353 int idx, err; 1354 uint32_t offset = 0; 1355 1356 err = 0; 1357 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1358 err = cs4280_download(sc, &BA1Struct.map[offset], 1359 BA1Struct.memory[idx].offset, 1360 BA1Struct.memory[idx].size); 1361 if (err != 0) { 1362 aprint_error_dev(&sc->sc_dev, 1363 "load_image failed at %d\n", idx); 1364 return -1; 1365 } 1366 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1367 } 1368 return err; 1369 } 1370 1371 /* Processor Soft Reset */ 1372 static void 1373 cs4280_reset(void *sc_) 1374 { 1375 struct cs428x_softc *sc; 1376 1377 sc = sc_; 1378 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1379 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1380 delay(100); 1381 /* Clear RSTSP bit in SPCR */ 1382 BA1WRITE4(sc, CS4280_SPCR, 0); 1383 /* enable DMA reqest */ 1384 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1385 } 1386 1387 static int 1388 cs4280_init(struct cs428x_softc *sc, int init) 1389 { 1390 int n; 1391 uint32_t mem; 1392 int rv; 1393 1394 rv = 1; 1395 cs4280_clkrun_hack(sc, 1); 1396 1397 /* Start PLL out in known state */ 1398 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1399 /* Start serial ports out in known state */ 1400 BA0WRITE4(sc, CS4280_SERMC1, 0); 1401 1402 /* Specify type of CODEC */ 1403 /* XXX should not be here */ 1404 #define SERACC_CODEC_TYPE_1_03 1405 #ifdef SERACC_CODEC_TYPE_1_03 1406 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1407 #else 1408 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1409 #endif 1410 1411 /* Reset codec */ 1412 BA0WRITE4(sc, CS428X_ACCTL, 0); 1413 delay(100); /* delay 100us */ 1414 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1415 1416 /* Enable AC-link sync generation */ 1417 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1418 delay(50*1000); /* delay 50ms */ 1419 1420 /* Set the serial port timing configuration */ 1421 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1422 1423 /* Setup clock control */ 1424 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1425 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1426 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1427 1428 /* Power up the PLL */ 1429 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1430 delay(50*1000); /* delay 50ms */ 1431 1432 /* Turn on clock */ 1433 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1434 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1435 1436 /* Set the serial port FIFO pointer to the 1437 * first sample in FIFO. (not documented) */ 1438 cs4280_clear_fifos(sc); 1439 1440 #if 0 1441 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1442 BA0WRITE4(sc, CS4280_SERBSP, 0); 1443 #endif 1444 1445 /* Configure the serial port */ 1446 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1447 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1448 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1449 1450 /* Wait for CODEC ready */ 1451 n = 0; 1452 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1453 delay(125); 1454 if (++n > 1000) { 1455 aprint_error_dev(&sc->sc_dev, "codec ready timeout\n"); 1456 goto exit; 1457 } 1458 } 1459 1460 /* Assert valid frame signal */ 1461 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1462 1463 /* Wait for valid AC97 input slot */ 1464 n = 0; 1465 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1466 (ACISV_ISV3 | ACISV_ISV4)) { 1467 delay(1000); 1468 if (++n > 1000) { 1469 printf("AC97 inputs slot ready timeout\n"); 1470 goto exit; 1471 } 1472 } 1473 1474 /* Set AC97 output slot valid signals */ 1475 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1476 1477 /* reset the processor */ 1478 cs4280_reset(sc); 1479 1480 /* Download the image to the processor */ 1481 if (cs4280_download_image(sc) != 0) { 1482 aprint_error_dev(&sc->sc_dev, "image download error\n"); 1483 goto exit; 1484 } 1485 1486 /* Save playback parameter and then write zero. 1487 * this ensures that DMA doesn't immediately occur upon 1488 * starting the processor core 1489 */ 1490 mem = BA1READ4(sc, CS4280_PCTL); 1491 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1492 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1493 if (init != 0) 1494 sc->sc_prun = 0; 1495 1496 /* Save capture parameter and then write zero. 1497 * this ensures that DMA doesn't immediately occur upon 1498 * starting the processor core 1499 */ 1500 mem = BA1READ4(sc, CS4280_CCTL); 1501 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1502 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1503 if (init != 0) 1504 sc->sc_rrun = 0; 1505 1506 /* Processor Startup Procedure */ 1507 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1508 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1509 1510 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1511 n = 0; 1512 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1513 delay(10); 1514 if (++n > 1000) { 1515 printf("SPCR 1->0 transition timeout\n"); 1516 goto exit; 1517 } 1518 } 1519 1520 n = 0; 1521 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1522 delay(10); 1523 if (++n > 1000) { 1524 printf("SPCS 0->1 transition timeout\n"); 1525 goto exit; 1526 } 1527 } 1528 /* Processor is now running !!! */ 1529 1530 /* Setup volume */ 1531 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1532 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1533 1534 /* Interrupt enable */ 1535 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1536 1537 /* playback interrupt enable */ 1538 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1539 mem |= PFIE_PI_ENABLE; 1540 BA1WRITE4(sc, CS4280_PFIE, mem); 1541 /* capture interrupt enable */ 1542 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1543 mem |= CIE_CI_ENABLE; 1544 BA1WRITE4(sc, CS4280_CIE, mem); 1545 1546 #if NMIDI > 0 1547 /* Reset midi port */ 1548 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1549 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1550 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1551 /* midi interrupt enable */ 1552 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1553 BA0WRITE4(sc, CS4280_MIDCR, mem); 1554 #endif 1555 1556 rv = 0; 1557 1558 exit: 1559 cs4280_clkrun_hack(sc, -1); 1560 return rv; 1561 } 1562 1563 static void 1564 cs4280_clear_fifos(struct cs428x_softc *sc) 1565 { 1566 int pd, cnt, n; 1567 uint32_t mem; 1568 1569 pd = 0; 1570 /* 1571 * If device power down, power up the device and keep power down 1572 * state. 1573 */ 1574 mem = BA0READ4(sc, CS4280_CLKCR1); 1575 if (!(mem & CLKCR1_SWCE)) { 1576 printf("cs4280_clear_fifo: power down found.\n"); 1577 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1578 pd = 1; 1579 } 1580 BA0WRITE4(sc, CS4280_SERBWP, 0); 1581 for (cnt = 0; cnt < 256; cnt++) { 1582 n = 0; 1583 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1584 delay(1000); 1585 if (++n > 1000) { 1586 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1587 break; 1588 } 1589 } 1590 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1591 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1592 } 1593 if (pd) 1594 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1595 } 1596 1597 #if NMIDI > 0 1598 static int 1599 cs4280_midi_open(void *addr, int flags, void (*iintr)(void *, int), 1600 void (*ointr)(void *), void *arg) 1601 { 1602 struct cs428x_softc *sc; 1603 uint32_t mem; 1604 1605 DPRINTF(("midi_open\n")); 1606 sc = addr; 1607 sc->sc_iintr = iintr; 1608 sc->sc_ointr = ointr; 1609 sc->sc_arg = arg; 1610 1611 /* midi interrupt enable */ 1612 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1613 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1614 BA0WRITE4(sc, CS4280_MIDCR, mem); 1615 #ifdef CS4280_DEBUG 1616 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1617 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1618 return(EINVAL); 1619 } 1620 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1621 #endif 1622 return 0; 1623 } 1624 1625 static void 1626 cs4280_midi_close(void *addr) 1627 { 1628 struct cs428x_softc *sc; 1629 uint32_t mem; 1630 1631 DPRINTF(("midi_close\n")); 1632 sc = addr; 1633 tsleep(sc, PWAIT, "cs0clm", hz/10); /* give uart a chance to drain */ 1634 mem = BA0READ4(sc, CS4280_MIDCR); 1635 mem &= ~MIDCR_MASK; 1636 BA0WRITE4(sc, CS4280_MIDCR, mem); 1637 1638 sc->sc_iintr = 0; 1639 sc->sc_ointr = 0; 1640 } 1641 1642 static int 1643 cs4280_midi_output(void *addr, int d) 1644 { 1645 struct cs428x_softc *sc; 1646 uint32_t mem; 1647 int x; 1648 1649 sc = addr; 1650 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1651 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1652 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1653 mem |= d & MIDWP_MASK; 1654 DPRINTFN(5,("midi_output d=0x%08x",d)); 1655 BA0WRITE4(sc, CS4280_MIDWP, mem); 1656 #ifdef DIAGNOSTIC 1657 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1658 DPRINTF(("Bad write data: %d %d", 1659 mem, BA0READ4(sc, CS4280_MIDWP))); 1660 return EIO; 1661 } 1662 #endif 1663 return 0; 1664 } 1665 delay(MIDI_BUSY_DELAY); 1666 } 1667 return EIO; 1668 } 1669 1670 static void 1671 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1672 { 1673 1674 mi->name = "CS4280 MIDI UART"; 1675 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1676 } 1677 1678 #endif /* NMIDI */ 1679 1680 /* DEBUG functions */ 1681 #if CS4280_DEBUG > 10 1682 static int 1683 cs4280_checkimage(struct cs428x_softc *sc, uint32_t *src, 1684 uint32_t offset, uint32_t len) 1685 { 1686 uint32_t ctr, data; 1687 int err; 1688 1689 if ((offset & 3) || (len & 3)) 1690 return -1; 1691 1692 err = 0; 1693 len /= sizeof(uint32_t); 1694 for (ctr = 0; ctr < len; ctr++) { 1695 /* I cannot confirm this is the right thing 1696 * on BIG-ENDIAN machines 1697 */ 1698 data = BA1READ4(sc, offset+ctr*4); 1699 if (data != htole32(*(src+ctr))) { 1700 printf("0x%06x: 0x%08x(0x%08x)\n", 1701 offset+ctr*4, data, *(src+ctr)); 1702 *(src+ctr) = data; 1703 ++err; 1704 } 1705 } 1706 return err; 1707 } 1708 1709 static int 1710 cs4280_check_images(struct cs428x_softc *sc) 1711 { 1712 int idx, err; 1713 uint32_t offset; 1714 1715 offset = 0; 1716 err = 0; 1717 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx)*/ 1718 for (idx = 0; idx < 1; ++idx) { 1719 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1720 BA1Struct.memory[idx].offset, 1721 BA1Struct.memory[idx].size); 1722 if (err != 0) { 1723 aprint_error_dev(&sc->sc_dev, 1724 "check_image failed at %d\n", idx); 1725 } 1726 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1727 } 1728 return err; 1729 } 1730 1731 #endif /* CS4280_DEBUG */ 1732