1 /************************************************************************** 2 3 Copyright (c) 2007, Chelsio Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 POSSIBILITY OF SUCH DAMAGE. 27 28 ***************************************************************************/ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: cxgb_main.c,v 1.8 2020/02/04 05:44:14 thorpej Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/conf.h> 37 #include <sys/bus.h> 38 #include <sys/ioccom.h> 39 #include <sys/mbuf.h> 40 #include <sys/socket.h> 41 #include <sys/sockio.h> 42 #include <sys/sysctl.h> 43 #include <sys/queue.h> 44 45 #include <net/bpf.h> 46 #include <net/if.h> 47 #include <net/if_arp.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 #include <net/if_types.h> 51 52 #include <netinet/in_systm.h> 53 #include <netinet/in.h> 54 #include <netinet/ip.h> 55 #include <netinet/ip.h> 56 #include <netinet/tcp.h> 57 #include <netinet/udp.h> 58 #include <netinet/if_inarp.h> 59 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcivar.h> 62 63 #ifdef CONFIG_DEFINED 64 #include <cxgb_include.h> 65 #else 66 #include <dev/pci/cxgb/cxgb_include.h> 67 #endif 68 69 #ifdef PRIV_SUPPORTED 70 #include <sys/priv.h> 71 #endif 72 73 #include <altq/altq_conf.h> 74 75 static int cxgb_setup_msix(adapter_t *, int); 76 static void cxgb_teardown_msix(adapter_t *); 77 static int cxgb_init(struct ifnet *); 78 static void cxgb_init_locked(struct port_info *); 79 static void cxgb_stop_locked(struct port_info *); 80 static void cxgb_set_rxmode(struct port_info *); 81 static int cxgb_ioctl(struct ifnet *, unsigned long, void *); 82 static void cxgb_start(struct ifnet *); 83 static void cxgb_stop(struct ifnet *, int); 84 static void cxgb_start_proc(struct work *, void *); 85 static int cxgb_media_change(struct ifnet *); 86 static void cxgb_media_status(struct ifnet *, struct ifmediareq *); 87 static int setup_sge_qsets(adapter_t *); 88 static int cxgb_async_intr(void *); 89 static void cxgb_ext_intr_handler(struct work *, void *); 90 static void cxgb_tick_handler(struct work *, void *); 91 static void cxgb_down_locked(struct adapter *sc); 92 static void cxgb_tick(void *); 93 static void setup_rss(adapter_t *sc); 94 95 /* Attachment glue for the PCI controller end of the device. Each port of 96 * the device is attached separately, as defined later. 97 */ 98 static int cxgb_controller_match(device_t dev, cfdata_t match, void *context); 99 static void cxgb_controller_attach(device_t parent, device_t dev, void *context); 100 static int cxgb_controller_detach(device_t dev, int flags); 101 static void cxgb_free(struct adapter *); 102 static __inline void reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start, 103 unsigned int end); 104 static void touch_bars(device_t dev); 105 106 #ifdef notyet 107 static int offload_close(struct toedev *tdev); 108 #endif 109 110 111 CFATTACH_DECL_NEW(cxgbc, sizeof(struct adapter), cxgb_controller_match, cxgb_controller_attach, cxgb_controller_detach, NULL); 112 113 /* 114 * Attachment glue for the ports. Attachment is done directly to the 115 * controller device. 116 */ 117 static int cxgb_port_match(device_t dev, cfdata_t match, void *context); 118 static void cxgb_port_attach(device_t dev, device_t self, void *context); 119 static int cxgb_port_detach(device_t dev, int flags); 120 121 CFATTACH_DECL_NEW(cxgb, sizeof(struct port_device), cxgb_port_match, cxgb_port_attach, cxgb_port_detach, NULL); 122 123 #define SGE_MSIX_COUNT (SGE_QSETS + 1) 124 125 extern int collapse_mbufs; 126 #ifdef MSI_SUPPORTED 127 /* 128 * The driver uses the best interrupt scheme available on a platform in the 129 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which 130 * of these schemes the driver may consider as follows: 131 * 132 * msi = 2: choose from among all three options 133 * msi = 1 : only consider MSI and pin interrupts 134 * msi = 0: force pin interrupts 135 */ 136 static int msi_allowed = 2; 137 #endif 138 139 /* 140 * The driver uses an auto-queue algorithm by default. 141 * To disable it and force a single queue-set per port, use singleq = 1. 142 */ 143 static int singleq = 1; 144 145 enum { 146 MAX_TXQ_ENTRIES = 16384, 147 MAX_CTRL_TXQ_ENTRIES = 1024, 148 MAX_RSPQ_ENTRIES = 16384, 149 MAX_RX_BUFFERS = 16384, 150 MAX_RX_JUMBO_BUFFERS = 16384, 151 MIN_TXQ_ENTRIES = 4, 152 MIN_CTRL_TXQ_ENTRIES = 4, 153 MIN_RSPQ_ENTRIES = 32, 154 MIN_FL_ENTRIES = 32, 155 MIN_FL_JUMBO_ENTRIES = 32 156 }; 157 158 struct filter_info { 159 u32 sip; 160 u32 sip_mask; 161 u32 dip; 162 u16 sport; 163 u16 dport; 164 u32 vlan:12; 165 u32 vlan_prio:3; 166 u32 mac_hit:1; 167 u32 mac_idx:4; 168 u32 mac_vld:1; 169 u32 pkt_type:2; 170 u32 report_filter_id:1; 171 u32 pass:1; 172 u32 rss:1; 173 u32 qset:3; 174 u32 locked:1; 175 u32 valid:1; 176 }; 177 178 enum { FILTER_NO_VLAN_PRI = 7 }; 179 180 #define PORT_MASK ((1 << MAX_NPORTS) - 1) 181 182 /* Table for probing the cards. The desc field isn't actually used */ 183 struct cxgb_ident { 184 uint16_t vendor; 185 uint16_t device; 186 int index; 187 const char *desc; 188 } cxgb_identifiers[] = { 189 {PCI_VENDOR_ID_CHELSIO, 0x0020, 0, "PE9000"}, 190 {PCI_VENDOR_ID_CHELSIO, 0x0021, 1, "T302E"}, 191 {PCI_VENDOR_ID_CHELSIO, 0x0022, 2, "T310E"}, 192 {PCI_VENDOR_ID_CHELSIO, 0x0023, 3, "T320X"}, 193 {PCI_VENDOR_ID_CHELSIO, 0x0024, 1, "T302X"}, 194 {PCI_VENDOR_ID_CHELSIO, 0x0025, 3, "T320E"}, 195 {PCI_VENDOR_ID_CHELSIO, 0x0026, 2, "T310X"}, 196 {PCI_VENDOR_ID_CHELSIO, 0x0030, 2, "T3B10"}, 197 {PCI_VENDOR_ID_CHELSIO, 0x0031, 3, "T3B20"}, 198 {PCI_VENDOR_ID_CHELSIO, 0x0032, 1, "T3B02"}, 199 {PCI_VENDOR_ID_CHELSIO, 0x0033, 4, "T3B04"}, 200 {0, 0, 0, NULL} 201 }; 202 203 204 static inline char 205 t3rev2char(struct adapter *adapter) 206 { 207 char rev = 'z'; 208 209 switch(adapter->params.rev) { 210 case T3_REV_A: 211 rev = 'a'; 212 break; 213 case T3_REV_B: 214 case T3_REV_B2: 215 rev = 'b'; 216 break; 217 case T3_REV_C: 218 rev = 'c'; 219 break; 220 } 221 return rev; 222 } 223 224 static struct cxgb_ident *cxgb_get_ident(struct pci_attach_args *pa) 225 { 226 struct cxgb_ident *id; 227 int vendorid, deviceid; 228 229 vendorid = PCI_VENDOR(pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ID_REG)); 230 deviceid = PCI_PRODUCT(pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ID_REG)); 231 232 for (id = cxgb_identifiers; id->desc != NULL; id++) { 233 if ((id->vendor == vendorid) && 234 (id->device == deviceid)) { 235 return (id); 236 } 237 } 238 return (NULL); 239 } 240 241 static const struct adapter_info *cxgb_get_adapter_info(struct pci_attach_args *pa) 242 { 243 struct cxgb_ident *id; 244 const struct adapter_info *ai; 245 246 id = cxgb_get_ident(pa); 247 if (id == NULL) 248 return (NULL); 249 250 ai = t3_get_adapter_info(id->index); 251 return (ai); 252 } 253 254 static int cxgb_controller_match(device_t dev, cfdata_t match, void *context) 255 { 256 struct pci_attach_args *pa = context; 257 const struct adapter_info *ai; 258 259 ai = cxgb_get_adapter_info(pa); 260 if (ai == NULL) 261 return (0); 262 263 return (100); // we ARE the best driver for this card!! 264 } 265 266 #define FW_FNAME "t3fw%d%d%d" 267 #define TPEEPROM_NAME "t3%ctpe%d%d%d" 268 #define TPSRAM_NAME "t3%cps%d%d%d" 269 270 int cxgb_cfprint(void *aux, const char *info); 271 int cxgb_cfprint(void *aux, const char *info) 272 { 273 if (info) 274 { 275 printf("cxgb_cfprint(%p, \"%s\")\n", aux, info); 276 INT3; 277 } 278 279 return (QUIET); 280 } 281 282 void cxgb_make_task(void *context) 283 { 284 struct cxgb_task *w = (struct cxgb_task *)context; 285 286 // we can only use workqueue_create() once the system is up and running 287 workqueue_create(&w->wq, w->name, w->func, w->context, PRIBIO, IPL_NET, 0); 288 // printf("======>> create workqueue for %s %p\n", w->name, w->wq); 289 } 290 291 static void 292 cxgb_controller_attach(device_t parent, device_t dev, void *context) 293 { 294 device_t child; 295 const struct adapter_info *ai; 296 struct adapter *sc; 297 struct pci_attach_args *pa = context; 298 struct cxgb_attach_args cxgb_args; 299 int locs[2]; 300 int i, error = 0; 301 uint32_t vers; 302 int port_qsets = 1; 303 int reg; 304 #ifdef MSI_SUPPORTED 305 int msi_needed; 306 #endif 307 308 sc = device_private(dev); 309 sc->dev = dev; 310 memcpy(&sc->pa, pa, sizeof(struct pci_attach_args)); 311 sc->msi_count = 0; 312 ai = cxgb_get_adapter_info(pa); 313 314 /* 315 * XXX not really related but a recent addition 316 */ 317 #ifdef MSI_SUPPORTED 318 /* find the PCIe link width and set max read request to 4KB*/ 319 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 320 uint16_t lnk, pectl; 321 lnk = pci_read_config(dev, reg + 0x12, 2); 322 sc->link_width = (lnk >> 4) & 0x3f; 323 324 pectl = pci_read_config(dev, reg + 0x8, 2); 325 pectl = (pectl & ~0x7000) | (5 << 12); 326 pci_write_config(dev, reg + 0x8, pectl, 2); 327 } 328 329 if (sc->link_width != 0 && sc->link_width <= 4 && 330 (ai->nports0 + ai->nports1) <= 2) { 331 device_printf(sc->dev, 332 "PCIe x%d Link, expect reduced performance\n", 333 sc->link_width); 334 } 335 #endif 336 337 touch_bars(dev); 338 339 pci_enable_busmaster(dev); 340 341 /* 342 * Allocate the registers and make them available to the driver. 343 * The registers that we care about for NIC mode are in BAR 0 344 */ 345 sc->regs_rid = PCI_MAPREG_START; 346 t3_os_pci_read_config_4(sc, PCI_MAPREG_START, ®); 347 348 // call bus_space_map 349 sc->bar0 = reg&0xFFFFF000; 350 bus_space_map(sc->pa.pa_memt, sc->bar0, 4096, 0, &sc->bar0_handle); 351 352 MTX_INIT(&sc->sge.reg_lock, sc->reglockbuf, NULL, MTX_DEF); 353 MTX_INIT(&sc->mdio_lock, sc->mdiolockbuf, NULL, MTX_DEF); 354 MTX_INIT(&sc->elmer_lock, sc->elmerlockbuf, NULL, MTX_DEF); 355 356 sc->bt = sc->pa.pa_memt; 357 sc->bh = sc->bar0_handle; 358 sc->mmio_len = 4096; 359 360 if (t3_prep_adapter(sc, ai, 1) < 0) { 361 printf("prep adapter failed\n"); 362 error = ENODEV; 363 goto out; 364 } 365 /* Allocate the BAR for doing MSI-X. If it succeeds, try to allocate 366 * enough messages for the queue sets. If that fails, try falling 367 * back to MSI. If that fails, then try falling back to the legacy 368 * interrupt pin model. 369 */ 370 #ifdef MSI_SUPPORTED 371 372 sc->msix_regs_rid = 0x20; 373 if ((msi_allowed >= 2) && 374 (sc->msix_regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 375 &sc->msix_regs_rid, RF_ACTIVE)) != NULL) { 376 377 msi_needed = sc->msi_count = SGE_MSIX_COUNT; 378 379 if (((error = pci_alloc_msix(dev, &sc->msi_count)) != 0) || 380 (sc->msi_count != msi_needed)) { 381 device_printf(dev, "msix allocation failed - msi_count = %d" 382 " msi_needed=%d will try msi err=%d\n", sc->msi_count, 383 msi_needed, error); 384 sc->msi_count = 0; 385 pci_release_msi(dev); 386 bus_release_resource(dev, SYS_RES_MEMORY, 387 sc->msix_regs_rid, sc->msix_regs_res); 388 sc->msix_regs_res = NULL; 389 } else { 390 sc->flags |= USING_MSIX; 391 sc->cxgb_intr = t3_intr_msix; 392 } 393 } 394 395 if ((msi_allowed >= 1) && (sc->msi_count == 0)) { 396 sc->msi_count = 1; 397 if (pci_alloc_msi(dev, &sc->msi_count)) { 398 device_printf(dev, "alloc msi failed - will try INTx\n"); 399 sc->msi_count = 0; 400 pci_release_msi(dev); 401 } else { 402 sc->flags |= USING_MSI; 403 sc->irq_rid = 1; 404 sc->cxgb_intr = t3_intr_msi; 405 } 406 } 407 #endif 408 if (sc->msi_count == 0) { 409 device_printf(dev, "using line interrupts\n"); 410 sc->irq_rid = 0; 411 sc->cxgb_intr = t3b_intr; 412 } 413 414 sc->ext_intr_task.name = "cxgb_ext_intr_handler"; 415 sc->ext_intr_task.func = cxgb_ext_intr_handler; 416 sc->ext_intr_task.context = sc; 417 kthread_create(PRI_NONE, 0, NULL, cxgb_make_task, &sc->ext_intr_task, NULL, "cxgb_make_task"); 418 419 sc->tick_task.name = "cxgb_tick_handler"; 420 sc->tick_task.func = cxgb_tick_handler; 421 sc->tick_task.context = sc; 422 kthread_create(PRI_NONE, 0, NULL, cxgb_make_task, &sc->tick_task, NULL, "cxgb_make_task"); 423 424 /* Create a periodic callout for checking adapter status */ 425 callout_init(&sc->cxgb_tick_ch, 0); 426 427 if (t3_check_fw_version(sc) != 0) { 428 /* 429 * Warn user that a firmware update will be attempted in init. 430 */ 431 device_printf(dev, "firmware needs to be updated to version %d.%d.%d\n", 432 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO); 433 sc->flags &= ~FW_UPTODATE; 434 } else { 435 sc->flags |= FW_UPTODATE; 436 } 437 438 if (t3_check_tpsram_version(sc) != 0) { 439 /* 440 * Warn user that a firmware update will be attempted in init. 441 */ 442 device_printf(dev, "SRAM needs to be updated to version %c-%d.%d.%d\n", 443 t3rev2char(sc), TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); 444 sc->flags &= ~TPS_UPTODATE; 445 } else { 446 sc->flags |= TPS_UPTODATE; 447 } 448 449 if ((sc->flags & USING_MSIX) && !singleq) 450 port_qsets = (SGE_QSETS/(sc)->params.nports); 451 452 /* 453 * Create a child device for each MAC. The ethernet attachment 454 * will be done in these children. 455 */ 456 for (i = 0; i < (sc)->params.nports; i++) { 457 struct port_info *pi; 458 459 pi = &sc->port[i]; 460 pi->adapter = sc; 461 pi->nqsets = port_qsets; 462 pi->first_qset = i*port_qsets; 463 pi->port_id = i; 464 pi->tx_chan = i >= ai->nports0; 465 pi->txpkt_intf = pi->tx_chan ? 2 * (i - ai->nports0) + 1 : 2 * i; 466 sc->rxpkt_map[pi->txpkt_intf] = i; 467 cxgb_args.port = i; 468 locs[0] = 1; 469 locs[1] = i; 470 printf("\n"); // for cleaner formatting in dmesg 471 child = config_found_sm_loc(dev, "cxgbc", locs, &cxgb_args, 472 cxgb_cfprint, config_stdsubmatch); 473 printf("\n"); // for cleaner formatting in dmesg 474 sc->portdev[i] = child; 475 } 476 477 /* 478 * XXX need to poll for link status 479 */ 480 sc->params.stats_update_period = 1; 481 482 /* initialize sge private state */ 483 t3_sge_init_adapter(sc); 484 485 t3_led_ready(sc); 486 487 error = t3_get_fw_version(sc, &vers); 488 if (error) 489 goto out; 490 491 snprintf(&sc->fw_version[0], sizeof(sc->fw_version), "%d.%d.%d", 492 G_FW_VERSION_MAJOR(vers), G_FW_VERSION_MINOR(vers), 493 G_FW_VERSION_MICRO(vers)); 494 out: 495 if (error) 496 { 497 cxgb_free(sc); 498 } 499 } 500 501 static int 502 cxgb_controller_detach(device_t dev, int flags) 503 { 504 struct adapter *sc; 505 506 sc = device_private(dev); 507 508 cxgb_free(sc); 509 510 return (0); 511 } 512 513 static void 514 cxgb_free(struct adapter *sc) 515 { 516 int i; 517 518 ADAPTER_LOCK(sc); 519 /* 520 * drops the lock 521 */ 522 cxgb_down_locked(sc); 523 524 #ifdef MSI_SUPPORTED 525 if (sc->flags & (USING_MSI | USING_MSIX)) { 526 device_printf(sc->dev, "releasing msi message(s)\n"); 527 pci_release_msi(sc->dev); 528 } else { 529 device_printf(sc->dev, "no msi message to release\n"); 530 } 531 if (sc->msix_regs_res != NULL) { 532 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->msix_regs_rid, 533 sc->msix_regs_res); 534 } 535 #endif 536 537 t3_sge_deinit_sw(sc); 538 /* 539 * Wait for last callout 540 */ 541 542 tsleep(&sc, 0, "cxgb unload", 3*hz); 543 544 for (i = 0; i < (sc)->params.nports; ++i) { 545 if (sc->portdev[i] != NULL) 546 { 547 INT3; 548 } 549 } 550 551 #ifdef notyet 552 if (is_offload(sc)) { 553 cxgb_adapter_unofld(sc); 554 if (isset(&sc->open_device_map, OFFLOAD_DEVMAP_BIT)) 555 offload_close(&sc->tdev); 556 } 557 #endif 558 559 t3_free_sge_resources(sc); 560 free(sc->filters, M_DEVBUF); 561 t3_sge_free(sc); 562 563 MTX_DESTROY(&sc->mdio_lock); 564 MTX_DESTROY(&sc->sge.reg_lock); 565 MTX_DESTROY(&sc->elmer_lock); 566 ADAPTER_LOCK_DEINIT(sc); 567 568 return; 569 } 570 571 /** 572 * setup_sge_qsets - configure SGE Tx/Rx/response queues 573 * @sc: the controller softc 574 * 575 * Determines how many sets of SGE queues to use and initializes them. 576 * We support multiple queue sets per port if we have MSI-X, otherwise 577 * just one queue set per port. 578 */ 579 static int 580 setup_sge_qsets(adapter_t *sc) 581 { 582 int i, j, err, irq_idx = 0, qset_idx = 0; 583 u_int ntxq = SGE_TXQ_PER_SET; 584 585 if ((err = t3_sge_alloc(sc)) != 0) { 586 device_printf(sc->dev, "t3_sge_alloc returned %d\n", err); 587 return (err); 588 } 589 590 if (sc->params.rev > 0 && !(sc->flags & USING_MSI)) 591 irq_idx = -1; 592 593 for (i = 0; i < (sc)->params.nports; i++) { 594 struct port_info *pi = &sc->port[i]; 595 596 for (j = 0; j < pi->nqsets; j++, qset_idx++) { 597 err = t3_sge_alloc_qset(sc, qset_idx, (sc)->params.nports, 598 (sc->flags & USING_MSIX) ? qset_idx + 1 : irq_idx, 599 &sc->params.sge.qset[qset_idx], ntxq, pi); 600 if (err) { 601 t3_free_sge_resources(sc); 602 device_printf(sc->dev, "t3_sge_alloc_qset failed with %d\n", 603 err); 604 return (err); 605 } 606 } 607 } 608 609 return (0); 610 } 611 612 static void 613 cxgb_teardown_msix(adapter_t *sc) 614 { 615 int i, nqsets; 616 617 for (nqsets = i = 0; i < (sc)->params.nports; i++) 618 nqsets += sc->port[i].nqsets; 619 620 for (i = 0; i < nqsets; i++) { 621 if (sc->msix_intr_tag[i] != NULL) { 622 sc->msix_intr_tag[i] = NULL; 623 } 624 if (sc->msix_irq_res[i] != NULL) { 625 sc->msix_irq_res[i] = NULL; 626 } 627 } 628 } 629 630 static int 631 cxgb_setup_msix(adapter_t *sc, int msix_count) 632 { 633 int i, j, k, nqsets, rid; 634 635 /* The first message indicates link changes and error conditions */ 636 sc->irq_rid = 1; 637 /* Allocate PCI interrupt resources. */ 638 if (pci_intr_map(&sc->pa, &sc->intr_handle)) 639 { 640 printf("cxgb_setup_msix(%d): pci_intr_map() failed\n", __LINE__); 641 return (EINVAL); 642 } 643 sc->intr_cookie = pci_intr_establish_xname(sc->pa.pa_pc, sc->intr_handle, 644 IPL_NET, cxgb_async_intr, sc, device_xname(sc->dev)); 645 if (sc->intr_cookie == NULL) 646 { 647 printf("cxgb_setup_msix(%d): pci_intr_establish() failed\n", __LINE__); 648 return (EINVAL); 649 } 650 for (i = k = 0; i < (sc)->params.nports; i++) { 651 nqsets = sc->port[i].nqsets; 652 for (j = 0; j < nqsets; j++, k++) { 653 rid = k + 2; 654 if (cxgb_debug) 655 printf("rid=%d ", rid); 656 INT3; 657 } 658 } 659 660 661 return (0); 662 } 663 664 static int cxgb_port_match(device_t dev, cfdata_t match, void *context) 665 { 666 return (100); 667 } 668 669 #define IFCAP_HWCSUM (IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_IPv4_Tx) 670 #define IFCAP_RXCSUM IFCAP_CSUM_IPv4_Rx 671 #define IFCAP_TXCSUM IFCAP_CSUM_IPv4_Tx 672 673 #ifdef TSO_SUPPORTED 674 #define CXGB_CAP (IFCAP_HWCSUM | IFCAP_TSO) 675 /* Don't enable TSO6 yet */ 676 #define CXGB_CAP_ENABLE (IFCAP_HWCSUM | IFCAP_TSO4) 677 #else 678 #define CXGB_CAP (IFCAP_HWCSUM) 679 /* Don't enable TSO6 yet */ 680 #define CXGB_CAP_ENABLE (IFCAP_HWCSUM) 681 #define IFCAP_TSO4 0x0 682 #define IFCAP_TSO6 0x0 683 #define CSUM_TSO 0x0 684 #endif 685 686 static void 687 cxgb_port_attach(device_t parent, device_t self, void *context) 688 { 689 struct port_info *p; 690 struct port_device *pd; 691 int *port_number = (int *)context; 692 char buf[32]; 693 struct ifnet *ifp; 694 int media_flags; 695 pd = device_private(self); 696 pd->dev = self; 697 pd->parent = device_private(parent); 698 pd->port_number = *port_number; 699 p = &pd->parent->port[*port_number]; 700 p->pd = pd; 701 702 PORT_LOCK_INIT(p, p->lockbuf); 703 704 /* Allocate an ifnet object and set it up */ 705 ifp = p->ifp = (void *)malloc(sizeof (struct ifnet), M_IFADDR, M_WAITOK); 706 if (ifp == NULL) { 707 device_printf(self, "Cannot allocate ifnet\n"); 708 return; 709 } 710 memset(ifp, 0, sizeof(struct ifnet)); 711 712 /* 713 * Note that there is currently no watchdog timer. 714 */ 715 snprintf(buf, sizeof(buf), "cxgb%d", p->port); 716 strcpy(ifp->if_xname, buf); 717 ifp->if_init = cxgb_init; 718 ifp->if_softc = p; 719 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 720 ifp->if_ioctl = cxgb_ioctl; 721 ifp->if_start = cxgb_start; 722 ifp->if_stop = cxgb_stop; 723 ifp->if_timer = 0; /* Disable ifnet watchdog */ 724 ifp->if_watchdog = NULL; 725 726 ifp->if_snd.ifq_maxlen = TX_ETH_Q_SIZE; 727 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_maxlen); 728 729 IFQ_SET_READY(&ifp->if_snd); 730 731 ifp->if_capabilities = ifp->if_capenable = 0; 732 ifp->if_baudrate = 10000000000; // 10 Gbps 733 /* 734 * disable TSO on 4-port - it isn't supported by the firmware yet 735 */ 736 if (p->adapter->params.nports > 2) { 737 ifp->if_capabilities &= ~(IFCAP_TSO4 | IFCAP_TSO6); 738 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TSO6); 739 } 740 741 if_attach(ifp); 742 ether_ifattach(ifp, p->hw_addr); 743 /* 744 * Only default to jumbo frames on 10GigE 745 */ 746 if (p->adapter->params.nports <= 2) 747 ifp->if_mtu = 9000; 748 ifmedia_init(&p->media, IFM_IMASK, cxgb_media_change, 749 cxgb_media_status); 750 751 if (!strcmp(p->port_type->desc, "10GBASE-CX4")) { 752 media_flags = IFM_ETHER | IFM_10G_CX4 | IFM_FDX; 753 } else if (!strcmp(p->port_type->desc, "10GBASE-SR")) { 754 media_flags = IFM_ETHER | IFM_10G_SR | IFM_FDX; 755 } else if (!strcmp(p->port_type->desc, "10GBASE-XR")) { 756 media_flags = IFM_ETHER | IFM_10G_LR | IFM_FDX; 757 } else if (!strcmp(p->port_type->desc, "10/100/1000BASE-T")) { 758 ifmedia_add(&p->media, IFM_ETHER | IFM_10_T, 0, NULL); 759 ifmedia_add(&p->media, IFM_ETHER | IFM_10_T | IFM_FDX, 760 0, NULL); 761 ifmedia_add(&p->media, IFM_ETHER | IFM_100_TX, 762 0, NULL); 763 ifmedia_add(&p->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 764 0, NULL); 765 ifmedia_add(&p->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 766 0, NULL); 767 media_flags = 0; 768 } else { 769 printf("unsupported media type %s\n", p->port_type->desc); 770 return; 771 } 772 if (media_flags) { 773 ifmedia_add(&p->media, media_flags, 0, NULL); 774 ifmedia_set(&p->media, media_flags); 775 } else { 776 ifmedia_add(&p->media, IFM_ETHER | IFM_AUTO, 0, NULL); 777 ifmedia_set(&p->media, IFM_ETHER | IFM_AUTO); 778 } 779 780 snprintf(p->taskqbuf, TASKQ_NAME_LEN, "cxgb_port_taskq%d", p->port_id); 781 p->start_task.name = "cxgb_start_proc"; 782 p->start_task.func = cxgb_start_proc; 783 p->start_task.context = ifp; 784 kthread_create(PRI_NONE, 0, NULL, cxgb_make_task, &p->start_task, NULL, "cxgb_make_task"); 785 786 t3_sge_init_port(p); 787 } 788 789 static int 790 cxgb_port_detach(device_t self, int flags) 791 { 792 struct port_info *p; 793 794 p = device_private(self); 795 796 PORT_LOCK(p); 797 if (p->ifp->if_drv_flags & IFF_DRV_RUNNING) 798 cxgb_stop_locked(p); 799 PORT_UNLOCK(p); 800 801 if (p->start_task.wq != NULL) { 802 workqueue_destroy(p->start_task.wq); 803 p->start_task.wq = NULL; 804 } 805 806 ether_ifdetach(p->ifp); 807 /* 808 * the lock may be acquired in ifdetach 809 */ 810 PORT_LOCK_DEINIT(p); 811 if_detach(p->ifp); 812 813 ifmedia_fini(&p->media); 814 815 return (0); 816 } 817 818 void 819 t3_fatal_err(struct adapter *sc) 820 { 821 u_int fw_status[4]; 822 823 if (sc->flags & FULL_INIT_DONE) { 824 t3_sge_stop(sc); 825 t3_write_reg(sc, A_XGM_TX_CTRL, 0); 826 t3_write_reg(sc, A_XGM_RX_CTRL, 0); 827 t3_write_reg(sc, XGM_REG(A_XGM_TX_CTRL, 1), 0); 828 t3_write_reg(sc, XGM_REG(A_XGM_RX_CTRL, 1), 0); 829 t3_intr_disable(sc); 830 } 831 device_printf(sc->dev,"encountered fatal error, operation suspended\n"); 832 if (!t3_cim_ctl_blk_read(sc, 0xa0, 4, fw_status)) 833 device_printf(sc->dev, "FW_ status: 0x%x, 0x%x, 0x%x, 0x%x\n", 834 fw_status[0], fw_status[1], fw_status[2], fw_status[3]); 835 } 836 837 int 838 t3_os_find_pci_capability(adapter_t *sc, int cap) 839 { 840 device_t dev; 841 uint32_t status; 842 uint32_t bhlc; 843 uint32_t temp; 844 uint8_t ptr; 845 dev = sc->dev; 846 status = pci_conf_read(sc->pa.pa_pc, sc->pa.pa_tag, PCI_COMMAND_STATUS_REG); 847 if (!(status&PCI_STATUS_CAPLIST_SUPPORT)) 848 return (0); 849 bhlc = pci_conf_read(sc->pa.pa_pc, sc->pa.pa_tag, PCI_BHLC_REG); 850 switch (PCI_HDRTYPE(bhlc)) 851 { 852 case 0: 853 case 1: 854 ptr = PCI_CAPLISTPTR_REG; 855 break; 856 case 2: 857 ptr = PCI_CARDBUS_CAPLISTPTR_REG; 858 break; 859 default: 860 return (0); 861 } 862 temp = pci_conf_read(sc->pa.pa_pc, sc->pa.pa_tag, ptr); 863 ptr = PCI_CAPLIST_PTR(temp); 864 while (ptr != 0) { 865 temp = pci_conf_read(sc->pa.pa_pc, sc->pa.pa_tag, ptr); 866 if (PCI_CAPLIST_CAP(temp) == cap) 867 return (ptr); 868 ptr = PCI_CAPLIST_NEXT(temp); 869 } 870 871 return (0); 872 } 873 874 int 875 t3_os_pci_save_state(struct adapter *sc) 876 { 877 INT3; 878 return (0); 879 } 880 881 int 882 t3_os_pci_restore_state(struct adapter *sc) 883 { 884 INT3; 885 return (0); 886 } 887 888 /** 889 * t3_os_link_changed - handle link status changes 890 * @adapter: the adapter associated with the link change 891 * @port_id: the port index whose limk status has changed 892 * @link_stat: the new status of the link 893 * @speed: the new speed setting 894 * @duplex: the new duplex setting 895 * @fc: the new flow-control setting 896 * 897 * This is the OS-dependent handler for link status changes. The OS 898 * neutral handler takes care of most of the processing for these events, 899 * then calls this handler for any OS-specific processing. 900 */ 901 void 902 t3_os_link_changed(adapter_t *adapter, int port_id, int link_status, int speed, 903 int duplex, int fc) 904 { 905 struct port_info *pi = &adapter->port[port_id]; 906 struct cmac *mac = &adapter->port[port_id].mac; 907 908 if ((pi->ifp->if_flags & IFF_UP) == 0) 909 return; 910 911 if (link_status) { 912 t3_mac_enable(mac, MAC_DIRECTION_RX); 913 if_link_state_change(pi->ifp, LINK_STATE_UP); 914 } else { 915 if_link_state_change(pi->ifp, LINK_STATE_DOWN); 916 pi->phy.ops->power_down(&pi->phy, 1); 917 t3_mac_disable(mac, MAC_DIRECTION_RX); 918 t3_link_start(&pi->phy, mac, &pi->link_config); 919 } 920 } 921 922 /* 923 * Interrupt-context handler for external (PHY) interrupts. 924 */ 925 void 926 t3_os_ext_intr_handler(adapter_t *sc) 927 { 928 if (cxgb_debug) 929 printf("t3_os_ext_intr_handler\n"); 930 /* 931 * Schedule a task to handle external interrupts as they may be slow 932 * and we use a mutex to protect MDIO registers. We disable PHY 933 * interrupts in the meantime and let the task reenable them when 934 * it's done. 935 */ 936 ADAPTER_LOCK(sc); 937 if (sc->slow_intr_mask) { 938 sc->slow_intr_mask &= ~F_T3DBG; 939 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask); 940 workqueue_enqueue(sc->ext_intr_task.wq, &sc->ext_intr_task.w, NULL); 941 } 942 ADAPTER_UNLOCK(sc); 943 } 944 945 void 946 t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[]) 947 { 948 949 /* 950 * The ifnet might not be allocated before this gets called, 951 * as this is called early on in attach by t3_prep_adapter 952 * save the address off in the port structure 953 */ 954 if (cxgb_debug) 955 printf("set_hw_addr on idx %d addr %02x:%02x:%02x:%02x:%02x:%02x\n", 956 port_idx, hw_addr[0], hw_addr[1], hw_addr[2], hw_addr[3], hw_addr[4], hw_addr[5]); 957 memcpy(adapter->port[port_idx].hw_addr, hw_addr, ETHER_ADDR_LEN); 958 } 959 960 /** 961 * link_start - enable a port 962 * @p: the port to enable 963 * 964 * Performs the MAC and PHY actions needed to enable a port. 965 */ 966 static void 967 cxgb_link_start(struct port_info *p) 968 { 969 struct ifnet *ifp; 970 struct t3_rx_mode rm; 971 struct cmac *mac = &p->mac; 972 973 ifp = p->ifp; 974 975 t3_init_rx_mode(&rm, p); 976 if (!mac->multiport) 977 t3_mac_reset(mac); 978 t3_mac_set_mtu(mac, ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 979 t3_mac_set_address(mac, 0, p->hw_addr); 980 t3_mac_set_rx_mode(mac, &rm); 981 t3_link_start(&p->phy, mac, &p->link_config); 982 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 983 } 984 985 /** 986 * setup_rss - configure Receive Side Steering (per-queue connection demux) 987 * @adap: the adapter 988 * 989 * Sets up RSS to distribute packets to multiple receive queues. We 990 * configure the RSS CPU lookup table to distribute to the number of HW 991 * receive queues, and the response queue lookup table to narrow that 992 * down to the response queues actually configured for each port. 993 * We always configure the RSS mapping for two ports since the mapping 994 * table has plenty of entries. 995 */ 996 static void 997 setup_rss(adapter_t *adap) 998 { 999 int i; 1000 u_int nq[2]; 1001 uint8_t cpus[SGE_QSETS + 1]; 1002 uint16_t rspq_map[RSS_TABLE_SIZE]; 1003 1004 for (i = 0; i < SGE_QSETS; ++i) 1005 cpus[i] = i; 1006 cpus[SGE_QSETS] = 0xff; 1007 1008 nq[0] = nq[1] = 0; 1009 for_each_port(adap, i) { 1010 const struct port_info *pi = adap2pinfo(adap, i); 1011 1012 nq[pi->tx_chan] += pi->nqsets; 1013 } 1014 nq[0] = uimax(nq[0], 1U); 1015 nq[1] = uimax(nq[1], 1U); 1016 for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) { 1017 rspq_map[i] = i % nq[0]; 1018 rspq_map[i + RSS_TABLE_SIZE / 2] = (i % nq[1]) + nq[0]; 1019 } 1020 /* Calculate the reverse RSS map table */ 1021 for (i = 0; i < RSS_TABLE_SIZE; ++i) 1022 if (adap->rrss_map[rspq_map[i]] == 0xff) 1023 adap->rrss_map[rspq_map[i]] = i; 1024 1025 t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN | 1026 F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN | F_OFDMAPEN | 1027 V_RRCPLCPUSIZE(6), cpus, rspq_map); 1028 1029 } 1030 1031 /* 1032 * Sends an mbuf to an offload queue driver 1033 * after dealing with any active network taps. 1034 */ 1035 static inline int 1036 offload_tx(struct toedev *tdev, struct mbuf *m) 1037 { 1038 int ret; 1039 1040 critical_enter(); 1041 ret = t3_offload_tx(tdev, m); 1042 critical_exit(); 1043 return (ret); 1044 } 1045 1046 static void 1047 send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo, 1048 int hi, int port) 1049 { 1050 struct mbuf *m; 1051 struct mngt_pktsched_wr *req; 1052 1053 m = m_gethdr(M_DONTWAIT, MT_DATA); 1054 if (m) { 1055 req = mtod(m, struct mngt_pktsched_wr *); 1056 req->wr_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT)); 1057 req->mngt_opcode = FW_MNGTOPCODE_PKTSCHED_SET; 1058 req->sched = sched; 1059 req->idx = qidx; 1060 req->min = lo; 1061 req->max = hi; 1062 req->binding = port; 1063 m->m_len = m->m_pkthdr.len = sizeof(*req); 1064 t3_mgmt_tx(adap, m); 1065 } 1066 } 1067 1068 static void 1069 bind_qsets(adapter_t *sc) 1070 { 1071 int i, j; 1072 1073 for (i = 0; i < (sc)->params.nports; ++i) { 1074 const struct port_info *pi = adap2pinfo(sc, i); 1075 1076 for (j = 0; j < pi->nqsets; ++j) { 1077 send_pktsched_cmd(sc, 1, pi->first_qset + j, -1, 1078 -1, pi->tx_chan); 1079 1080 } 1081 } 1082 } 1083 1084 /** 1085 * cxgb_up - enable the adapter 1086 * @adap: adapter being enabled 1087 * 1088 * Called when the first port is enabled, this function performs the 1089 * actions necessary to make an adapter operational, such as completing 1090 * the initialization of HW modules, and enabling interrupts. 1091 * 1092 */ 1093 static int 1094 cxgb_up(struct adapter *sc) 1095 { 1096 int err = 0; 1097 1098 if ((sc->flags & FULL_INIT_DONE) == 0) { 1099 1100 if ((sc->flags & FW_UPTODATE) == 0) 1101 printf("SHOULD UPGRADE FIRMWARE!\n"); 1102 if ((sc->flags & TPS_UPTODATE) == 0) 1103 printf("SHOULD UPDATE TPSRAM\n"); 1104 err = t3_init_hw(sc, 0); 1105 if (err) 1106 goto out; 1107 1108 t3_write_reg(sc, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12)); 1109 1110 err = setup_sge_qsets(sc); 1111 if (err) 1112 goto out; 1113 1114 setup_rss(sc); 1115 sc->flags |= FULL_INIT_DONE; 1116 } 1117 1118 t3_intr_clear(sc); 1119 1120 /* If it's MSI or INTx, allocate a single interrupt for everything */ 1121 if ((sc->flags & USING_MSIX) == 0) { 1122 if (pci_intr_map(&sc->pa, &sc->intr_handle)) 1123 { 1124 device_printf(sc->dev, "Cannot allocate interrupt\n"); 1125 err = EINVAL; 1126 goto out; 1127 } 1128 device_printf(sc->dev, "allocated intr_handle=%d\n", sc->intr_handle); 1129 sc->intr_cookie = pci_intr_establish_xname(sc->pa.pa_pc, 1130 sc->intr_handle, IPL_NET, 1131 sc->cxgb_intr, sc, device_xname(sc->dev)); 1132 if (sc->intr_cookie == NULL) 1133 { 1134 device_printf(sc->dev, "Cannot establish interrupt\n"); 1135 err = EINVAL; 1136 goto irq_err; 1137 } 1138 } else { 1139 printf("Using MSIX?!?!?!\n"); 1140 INT3; 1141 cxgb_setup_msix(sc, sc->msi_count); 1142 } 1143 1144 t3_sge_start(sc); 1145 t3_intr_enable(sc); 1146 1147 if (!(sc->flags & QUEUES_BOUND)) { 1148 bind_qsets(sc); 1149 sc->flags |= QUEUES_BOUND; 1150 } 1151 out: 1152 return (err); 1153 irq_err: 1154 CH_ERR(sc, "request_irq failed, err %d\n", err); 1155 goto out; 1156 } 1157 1158 1159 /* 1160 * Release resources when all the ports and offloading have been stopped. 1161 */ 1162 static void 1163 cxgb_down_locked(struct adapter *sc) 1164 { 1165 t3_sge_stop(sc); 1166 t3_intr_disable(sc); 1167 1168 INT3; // XXXXXXXXXXXXXXXXXX 1169 1170 if (sc->flags & USING_MSIX) 1171 cxgb_teardown_msix(sc); 1172 ADAPTER_UNLOCK(sc); 1173 1174 callout_drain(&sc->cxgb_tick_ch); 1175 callout_drain(&sc->sge_timer_ch); 1176 1177 #ifdef notyet 1178 1179 if (sc->port[i].tq != NULL) 1180 #endif 1181 1182 } 1183 1184 static int 1185 cxgb_init(struct ifnet *ifp) 1186 { 1187 struct port_info *p = ifp->if_softc; 1188 1189 PORT_LOCK(p); 1190 cxgb_init_locked(p); 1191 PORT_UNLOCK(p); 1192 1193 return (0); // ???????????? 1194 } 1195 1196 static void 1197 cxgb_init_locked(struct port_info *p) 1198 { 1199 struct ifnet *ifp; 1200 adapter_t *sc = p->adapter; 1201 int err; 1202 1203 PORT_LOCK_ASSERT_OWNED(p); 1204 ifp = p->ifp; 1205 1206 ADAPTER_LOCK(p->adapter); 1207 if ((sc->open_device_map == 0) && (err = cxgb_up(sc))) { 1208 ADAPTER_UNLOCK(p->adapter); 1209 cxgb_stop_locked(p); 1210 return; 1211 } 1212 if (p->adapter->open_device_map == 0) { 1213 t3_intr_clear(sc); 1214 t3_sge_init_adapter(sc); 1215 } 1216 setbit(&p->adapter->open_device_map, p->port_id); 1217 ADAPTER_UNLOCK(p->adapter); 1218 1219 cxgb_link_start(p); 1220 t3_link_changed(sc, p->port_id); 1221 ifp->if_baudrate = p->link_config.speed * 1000000; 1222 1223 device_printf(sc->dev, "enabling interrupts on port=%d\n", p->port_id); 1224 t3_port_intr_enable(sc, p->port_id); 1225 1226 callout_reset(&sc->cxgb_tick_ch, sc->params.stats_update_period * hz, 1227 cxgb_tick, sc); 1228 1229 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1230 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1231 } 1232 1233 static void 1234 cxgb_set_rxmode(struct port_info *p) 1235 { 1236 struct t3_rx_mode rm; 1237 struct cmac *mac = &p->mac; 1238 1239 PORT_LOCK_ASSERT_OWNED(p); 1240 1241 t3_init_rx_mode(&rm, p); 1242 t3_mac_set_rx_mode(mac, &rm); 1243 } 1244 1245 static void 1246 cxgb_stop_locked(struct port_info *p) 1247 { 1248 struct ifnet *ifp; 1249 1250 PORT_LOCK_ASSERT_OWNED(p); 1251 ADAPTER_LOCK_ASSERT_NOTOWNED(p->adapter); 1252 1253 ifp = p->ifp; 1254 1255 t3_port_intr_disable(p->adapter, p->port_id); 1256 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1257 p->phy.ops->power_down(&p->phy, 1); 1258 t3_mac_disable(&p->mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX); 1259 1260 ADAPTER_LOCK(p->adapter); 1261 clrbit(&p->adapter->open_device_map, p->port_id); 1262 1263 1264 if (p->adapter->open_device_map == 0) { 1265 cxgb_down_locked(p->adapter); 1266 } else 1267 ADAPTER_UNLOCK(p->adapter); 1268 1269 } 1270 1271 static int 1272 cxgb_set_mtu(struct port_info *p, int mtu) 1273 { 1274 struct ifnet *ifp = p->ifp; 1275 struct ifreq ifr; 1276 int error = 0; 1277 1278 ifr.ifr_mtu = mtu; 1279 1280 if ((mtu < ETHERMIN) || (mtu > ETHER_MAX_LEN_JUMBO)) 1281 error = EINVAL; 1282 else if ((error = ifioctl_common(ifp, SIOCSIFMTU, &ifr)) == ENETRESET) { 1283 error = 0; 1284 PORT_LOCK(p); 1285 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1286 callout_stop(&p->adapter->cxgb_tick_ch); 1287 cxgb_stop_locked(p); 1288 cxgb_init_locked(p); 1289 } 1290 PORT_UNLOCK(p); 1291 } 1292 return (error); 1293 } 1294 1295 static int 1296 cxgb_ioctl(struct ifnet *ifp, unsigned long command, void *data) 1297 { 1298 struct port_info *p = ifp->if_softc; 1299 struct ifaddr *ifa = (struct ifaddr *)data; 1300 struct ifreq *ifr = (struct ifreq *)data; 1301 int flags, error = 0; 1302 1303 /* 1304 * XXX need to check that we aren't in the middle of an unload 1305 */ 1306 printf("cxgb_ioctl(%d): command=%08lx\n", __LINE__, command); 1307 switch (command) { 1308 case SIOCSIFMTU: 1309 error = cxgb_set_mtu(p, ifr->ifr_mtu); 1310 printf("SIOCSIFMTU: error=%d\n", error); 1311 break; 1312 case SIOCINITIFADDR: 1313 printf("SIOCINITIFADDR:\n"); 1314 PORT_LOCK(p); 1315 if (ifa->ifa_addr->sa_family == AF_INET) { 1316 ifp->if_flags |= IFF_UP; 1317 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1318 cxgb_init_locked(p); 1319 arp_ifinit(ifp, ifa); 1320 } else 1321 error = ether_ioctl(ifp, command, data); 1322 PORT_UNLOCK(p); 1323 break; 1324 case SIOCSIFFLAGS: 1325 printf("SIOCSIFFLAGS:\n"); 1326 #if 0 1327 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1328 break; 1329 #endif 1330 callout_drain(&p->adapter->cxgb_tick_ch); 1331 PORT_LOCK(p); 1332 if (ifp->if_flags & IFF_UP) { 1333 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1334 flags = p->if_flags; 1335 if (((ifp->if_flags ^ flags) & IFF_PROMISC) || 1336 ((ifp->if_flags ^ flags) & IFF_ALLMULTI)) 1337 cxgb_set_rxmode(p); 1338 } else 1339 cxgb_init_locked(p); 1340 p->if_flags = ifp->if_flags; 1341 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1342 cxgb_stop_locked(p); 1343 1344 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1345 adapter_t *sc = p->adapter; 1346 callout_reset(&sc->cxgb_tick_ch, 1347 sc->params.stats_update_period * hz, 1348 cxgb_tick, sc); 1349 } 1350 PORT_UNLOCK(p); 1351 break; 1352 case SIOCSIFMEDIA: 1353 printf("SIOCSIFMEDIA:\n"); 1354 case SIOCGIFMEDIA: 1355 error = ifmedia_ioctl(ifp, ifr, &p->media, command); 1356 printf("SIOCGIFMEDIA: error=%d\n", error); 1357 break; 1358 default: 1359 printf("Dir = %x Len = %x Group = '%c' Num = %x\n", 1360 (unsigned int)(command&0xe0000000)>>28, (unsigned int)(command&0x1fff0000)>>16, 1361 (unsigned int)(command&0xff00)>>8, (unsigned int)command&0xff); 1362 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1363 break; 1364 error = 0; 1365 break; 1366 } 1367 return (error); 1368 } 1369 1370 static int 1371 cxgb_start_tx(struct ifnet *ifp, uint32_t txmax) 1372 { 1373 struct sge_qset *qs; 1374 struct sge_txq *txq; 1375 struct port_info *p = ifp->if_softc; 1376 struct mbuf *m = NULL; 1377 int err, in_use_init, free_it; 1378 1379 if (!p->link_config.link_ok) 1380 { 1381 return (ENXIO); 1382 } 1383 1384 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1385 { 1386 return (ENOBUFS); 1387 } 1388 1389 qs = &p->adapter->sge.qs[p->first_qset]; 1390 txq = &qs->txq[TXQ_ETH]; 1391 err = 0; 1392 1393 if (txq->flags & TXQ_TRANSMITTING) 1394 { 1395 return (EINPROGRESS); 1396 } 1397 1398 mtx_lock(&txq->lock); 1399 txq->flags |= TXQ_TRANSMITTING; 1400 in_use_init = txq->in_use; 1401 while ((txq->in_use - in_use_init < txmax) && 1402 (txq->size > txq->in_use + TX_MAX_DESC)) { 1403 free_it = 0; 1404 IFQ_DEQUEUE(&ifp->if_snd, m); 1405 if (m == NULL) 1406 break; 1407 /* 1408 * Convert chain to M_IOVEC 1409 */ 1410 KASSERT((m->m_flags & M_IOVEC) == 0); 1411 #ifdef notyet 1412 m0 = m; 1413 if (collapse_mbufs && m->m_pkthdr.len > MCLBYTES && 1414 m_collapse(m, TX_MAX_SEGS, &m0) == EFBIG) { 1415 if ((m0 = m_defrag(m, M_NOWAIT)) != NULL) { 1416 m = m0; 1417 m_collapse(m, TX_MAX_SEGS, &m0); 1418 } else 1419 break; 1420 } 1421 m = m0; 1422 #endif 1423 if ((err = t3_encap(p, &m, &free_it)) != 0) 1424 { 1425 printf("t3_encap() returned %d\n", err); 1426 break; 1427 } 1428 // bpf_mtap(ifp, m, BPF_D_OUT); 1429 if (free_it) 1430 { 1431 m_freem(m); 1432 } 1433 } 1434 txq->flags &= ~TXQ_TRANSMITTING; 1435 mtx_unlock(&txq->lock); 1436 1437 if (__predict_false(err)) { 1438 if (err == ENOMEM) { 1439 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1440 // XXXXXXXXXX lock/unlock?? 1441 IF_PREPEND(&ifp->if_snd, m); 1442 } 1443 } 1444 if (err == 0 && m == NULL) 1445 err = ENOBUFS; 1446 else if ((err == 0) && (txq->size <= txq->in_use + TX_MAX_DESC) && 1447 (ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) { 1448 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1449 err = ENOSPC; 1450 } 1451 return (err); 1452 } 1453 1454 static void 1455 cxgb_start_proc(struct work *wk, void *arg) 1456 { 1457 struct ifnet *ifp = arg; 1458 struct port_info *pi = ifp->if_softc; 1459 struct sge_qset *qs; 1460 struct sge_txq *txq; 1461 int error; 1462 1463 qs = &pi->adapter->sge.qs[pi->first_qset]; 1464 txq = &qs->txq[TXQ_ETH]; 1465 1466 do { 1467 if (desc_reclaimable(txq) > TX_CLEAN_MAX_DESC >> 2) 1468 workqueue_enqueue(pi->timer_reclaim_task.wq, &pi->timer_reclaim_task.w, NULL); 1469 1470 error = cxgb_start_tx(ifp, TX_START_MAX_DESC); 1471 } while (error == 0); 1472 } 1473 1474 static void 1475 cxgb_start(struct ifnet *ifp) 1476 { 1477 struct port_info *pi = ifp->if_softc; 1478 struct sge_qset *qs; 1479 struct sge_txq *txq; 1480 int err; 1481 1482 qs = &pi->adapter->sge.qs[pi->first_qset]; 1483 txq = &qs->txq[TXQ_ETH]; 1484 1485 if (desc_reclaimable(txq) > TX_CLEAN_MAX_DESC >> 2) 1486 workqueue_enqueue(pi->timer_reclaim_task.wq, &pi->timer_reclaim_task.w, NULL); 1487 1488 err = cxgb_start_tx(ifp, TX_START_MAX_DESC); 1489 1490 if (err == 0) 1491 workqueue_enqueue(pi->start_task.wq, &pi->start_task.w, NULL); 1492 } 1493 1494 static void 1495 cxgb_stop(struct ifnet *ifp, int reason) 1496 { 1497 struct port_info *pi = ifp->if_softc; 1498 1499 printf("cxgb_stop(): pi=%p, reason=%d\n", pi, reason); 1500 INT3; 1501 } 1502 1503 static int 1504 cxgb_media_change(struct ifnet *ifp) 1505 { 1506 printf("media change not supported: ifp=%p\n", ifp); 1507 return (ENXIO); 1508 } 1509 1510 static void 1511 cxgb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1512 { 1513 struct port_info *p; 1514 1515 p = ifp->if_softc; 1516 1517 ifmr->ifm_status = IFM_AVALID; 1518 ifmr->ifm_active = IFM_ETHER; 1519 1520 if (!p->link_config.link_ok) 1521 return; 1522 1523 ifmr->ifm_status |= IFM_ACTIVE; 1524 1525 switch (p->link_config.speed) { 1526 case 10: 1527 ifmr->ifm_active |= IFM_10_T; 1528 break; 1529 case 100: 1530 ifmr->ifm_active |= IFM_100_TX; 1531 break; 1532 case 1000: 1533 ifmr->ifm_active |= IFM_1000_T; 1534 break; 1535 } 1536 1537 if (p->link_config.duplex) 1538 ifmr->ifm_active |= IFM_FDX; 1539 else 1540 ifmr->ifm_active |= IFM_HDX; 1541 } 1542 1543 static int 1544 cxgb_async_intr(void *data) 1545 { 1546 adapter_t *sc = data; 1547 1548 if (cxgb_debug) 1549 device_printf(sc->dev, "cxgb_async_intr\n"); 1550 /* 1551 * May need to sleep - defer to taskqueue 1552 */ 1553 workqueue_enqueue(sc->slow_intr_task.wq, &sc->slow_intr_task.w, NULL); 1554 1555 return (1); 1556 } 1557 1558 static void 1559 cxgb_ext_intr_handler(struct work *wk, void *arg) 1560 { 1561 adapter_t *sc = (adapter_t *)arg; 1562 1563 if (cxgb_debug) 1564 printf("cxgb_ext_intr_handler\n"); 1565 1566 t3_phy_intr_handler(sc); 1567 1568 /* Now reenable external interrupts */ 1569 ADAPTER_LOCK(sc); 1570 if (sc->slow_intr_mask) { 1571 sc->slow_intr_mask |= F_T3DBG; 1572 t3_write_reg(sc, A_PL_INT_CAUSE0, F_T3DBG); 1573 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask); 1574 } 1575 ADAPTER_UNLOCK(sc); 1576 } 1577 1578 static void 1579 check_link_status(adapter_t *sc) 1580 { 1581 int i; 1582 1583 for (i = 0; i < (sc)->params.nports; ++i) { 1584 struct port_info *p = &sc->port[i]; 1585 1586 if (!(p->port_type->caps & SUPPORTED_IRQ)) 1587 t3_link_changed(sc, i); 1588 p->ifp->if_baudrate = p->link_config.speed * 1000000; 1589 } 1590 } 1591 1592 static void 1593 check_t3b2_mac(struct adapter *adapter) 1594 { 1595 int i; 1596 1597 for_each_port(adapter, i) { 1598 struct port_info *p = &adapter->port[i]; 1599 struct ifnet *ifp = p->ifp; 1600 int status; 1601 1602 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1603 continue; 1604 1605 status = 0; 1606 PORT_LOCK(p); 1607 if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) 1608 status = t3b2_mac_watchdog_task(&p->mac); 1609 if (status == 1) 1610 p->mac.stats.num_toggled++; 1611 else if (status == 2) { 1612 struct cmac *mac = &p->mac; 1613 1614 t3_mac_set_mtu(mac, ifp->if_mtu + ETHER_HDR_LEN 1615 + ETHER_VLAN_ENCAP_LEN); 1616 t3_mac_set_address(mac, 0, p->hw_addr); 1617 cxgb_set_rxmode(p); 1618 t3_link_start(&p->phy, mac, &p->link_config); 1619 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 1620 t3_port_intr_enable(adapter, p->port_id); 1621 p->mac.stats.num_resets++; 1622 } 1623 PORT_UNLOCK(p); 1624 } 1625 } 1626 1627 static void 1628 cxgb_tick(void *arg) 1629 { 1630 adapter_t *sc = (adapter_t *)arg; 1631 1632 workqueue_enqueue(sc->tick_task.wq, &sc->tick_task.w, NULL); 1633 1634 if (sc->open_device_map != 0) 1635 callout_reset(&sc->cxgb_tick_ch, sc->params.stats_update_period * hz, 1636 cxgb_tick, sc); 1637 } 1638 1639 static void 1640 cxgb_tick_handler(struct work *wk, void *arg) 1641 { 1642 adapter_t *sc = (adapter_t *)arg; 1643 const struct adapter_params *p = &sc->params; 1644 1645 ADAPTER_LOCK(sc); 1646 if (p->linkpoll_period) 1647 check_link_status(sc); 1648 1649 /* 1650 * adapter lock can currently only be acquire after the 1651 * port lock 1652 */ 1653 ADAPTER_UNLOCK(sc); 1654 1655 if (p->rev == T3_REV_B2 && p->nports < 4) 1656 check_t3b2_mac(sc); 1657 } 1658 1659 static void 1660 touch_bars(device_t dev) 1661 { 1662 /* 1663 * Don't enable yet 1664 */ 1665 #if !defined(__LP64__) && 0 1666 u32 v; 1667 1668 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_1, &v); 1669 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_1, v); 1670 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_3, &v); 1671 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_3, v); 1672 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &v); 1673 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_5, v); 1674 #endif 1675 } 1676 1677 static __inline void 1678 reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start, 1679 unsigned int end) 1680 { 1681 uint32_t *p = (uint32_t *)buf + start; 1682 1683 for ( ; start <= end; start += sizeof(uint32_t)) 1684 *p++ = t3_read_reg(ap, start); 1685 } 1686 1687