1 /* $NetBSD: cz.c,v 1.54 2010/07/26 22:33:24 jym Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Zembu Labs, Inc. 5 * All rights reserved. 6 * 7 * Authors: Jason R. Thorpe <thorpej@zembu.com> 8 * Bill Studenmund <wrstuden@zembu.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Zembu Labs, Inc. 21 * 4. Neither the name of Zembu Labs nor the names of its employees may 22 * be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY ZEMBU LABS, INC. ``AS IS'' AND ANY EXPRESS 26 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR- 27 * RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS- 28 * CLAIMED. IN NO EVENT SHALL ZEMBU LABS BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Cyclades-Z series multi-port serial adapter driver for NetBSD. 39 * 40 * Some notes: 41 * 42 * - The Cyclades-Z has fully automatic hardware (and software!) 43 * flow control. We only use RTS/CTS flow control here, 44 * and it is implemented in a very simplistic manner. This 45 * may be an area of future work. 46 * 47 * - The PLX can map the either the board's RAM or host RAM 48 * into the MIPS's memory window. This would enable us to 49 * use less expensive (for us) memory reads/writes to host 50 * RAM, rather than time-consuming reads/writes to PCI 51 * memory space. However, the PLX can only map a 0-128M 52 * window, so we would have to ensure that the DMA address 53 * of the host RAM fits there. This is kind of a pain, 54 * so we just don't bother right now. 55 * 56 * - In a perfect world, we would use the autoconfiguration 57 * mechanism to attach the TTYs that we find. However, 58 * that leads to somewhat icky looking autoconfiguration 59 * messages (one for every TTY, up to 64 per board!). So 60 * we don't do it that way, but assign minors as if there 61 * were the max of 64 ports per board. 62 * 63 * - We don't bother with PPS support here. There are so many 64 * ports, each with a large amount of buffer space, that the 65 * normal mode of operation is to poll the boards regularly 66 * (generally, every 20ms or so). This makes this driver 67 * unsuitable for PPS, as the latency will be generally too 68 * high. 69 */ 70 /* 71 * This driver inspired by the FreeBSD driver written by Brian J. McGovern 72 * for FreeBSD 3.2. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: cz.c,v 1.54 2010/07/26 22:33:24 jym Exp $"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/proc.h> 81 #include <sys/device.h> 82 #include <sys/malloc.h> 83 #include <sys/tty.h> 84 #include <sys/conf.h> 85 #include <sys/time.h> 86 #include <sys/kernel.h> 87 #include <sys/fcntl.h> 88 #include <sys/syslog.h> 89 #include <sys/kauth.h> 90 91 #include <sys/callout.h> 92 93 #include <dev/pci/pcireg.h> 94 #include <dev/pci/pcivar.h> 95 #include <dev/pci/pcidevs.h> 96 #include <dev/pci/czreg.h> 97 98 #include <dev/pci/plx9060reg.h> 99 #include <dev/pci/plx9060var.h> 100 101 #include <dev/microcode/cyclades-z/cyzfirm.h> 102 103 #define CZ_DRIVER_VERSION 0x20000411 104 105 #define CZ_POLL_MS 20 106 107 /* These are the interrupts we always use. */ 108 #define CZ_INTERRUPTS \ 109 (C_IN_MDSR | C_IN_MRI | C_IN_MRTS | C_IN_MCTS | C_IN_TXBEMPTY | \ 110 C_IN_TXFEMPTY | C_IN_TXLOWWM | C_IN_RXHIWM | C_IN_RXNNDT | \ 111 C_IN_MDCD | C_IN_PR_ERROR | C_IN_FR_ERROR | C_IN_OVR_ERROR | \ 112 C_IN_RXOFL | C_IN_IOCTLW | C_IN_RXBRK) 113 114 /* 115 * cztty_softc: 116 * 117 * Per-channel (TTY) state. 118 */ 119 struct cztty_softc { 120 struct cz_softc *sc_parent; 121 struct tty *sc_tty; 122 123 callout_t sc_diag_ch; 124 125 int sc_channel; /* Also used to flag unattached chan */ 126 #define CZTTY_CHANNEL_DEAD -1 127 128 bus_space_tag_t sc_chan_st; /* channel space tag */ 129 bus_space_handle_t sc_chan_sh; /* channel space handle */ 130 bus_space_handle_t sc_buf_sh; /* buffer space handle */ 131 132 u_int sc_overflows, 133 sc_parity_errors, 134 sc_framing_errors, 135 sc_errors; 136 137 int sc_swflags; 138 139 u_int32_t sc_rs_control_dtr, 140 sc_chanctl_hw_flow, 141 sc_chanctl_comm_baud, 142 sc_chanctl_rs_control, 143 sc_chanctl_comm_data_l, 144 sc_chanctl_comm_parity; 145 }; 146 147 /* 148 * cz_softc: 149 * 150 * Per-board state. 151 */ 152 struct cz_softc { 153 struct device cz_dev; /* generic device info */ 154 struct plx9060_config cz_plx; /* PLX 9060 config info */ 155 bus_space_tag_t cz_win_st; /* window space tag */ 156 bus_space_handle_t cz_win_sh; /* window space handle */ 157 callout_t cz_callout; /* callout for polling-mode */ 158 159 void *cz_ih; /* interrupt handle */ 160 161 u_int32_t cz_mailbox0; /* our MAILBOX0 value */ 162 int cz_nchannels; /* number of channels */ 163 int cz_nopenchan; /* number of open channels */ 164 struct cztty_softc *cz_ports; /* our array of ports */ 165 166 bus_addr_t cz_fwctl; /* offset of firmware control */ 167 }; 168 169 static int cz_wait_pci_doorbell(struct cz_softc *, const char *); 170 171 static int cz_load_firmware(struct cz_softc *); 172 173 static int cz_intr(void *); 174 static void cz_poll(void *); 175 static int cztty_transmit(struct cztty_softc *, struct tty *); 176 static int cztty_receive(struct cztty_softc *, struct tty *); 177 178 static struct cztty_softc *cztty_getttysoftc(dev_t dev); 179 static int cztty_attached_ttys; 180 static int cz_timeout_ticks; 181 182 static void czttystart(struct tty *tp); 183 static int czttyparam(struct tty *tp, struct termios *t); 184 static void cztty_shutdown(struct cztty_softc *sc); 185 static void cztty_modem(struct cztty_softc *sc, int onoff); 186 static void cztty_break(struct cztty_softc *sc, int onoff); 187 static void tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits); 188 static int cztty_to_tiocm(struct cztty_softc *sc); 189 static void cztty_diag(void *arg); 190 191 extern struct cfdriver cz_cd; 192 193 /* 194 * Macros to read and write the PLX. 195 */ 196 #define CZ_PLX_READ(cz, reg) \ 197 bus_space_read_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, (reg)) 198 #define CZ_PLX_WRITE(cz, reg, val) \ 199 bus_space_write_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, \ 200 (reg), (val)) 201 202 /* 203 * Macros to read and write the FPGA. We must already be in the FPGA 204 * window for this. 205 */ 206 #define CZ_FPGA_READ(cz, reg) \ 207 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg)) 208 #define CZ_FPGA_WRITE(cz, reg, val) \ 209 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg), (val)) 210 211 /* 212 * Macros to read and write the firmware control structures in board RAM. 213 */ 214 #define CZ_FWCTL_READ(cz, off) \ 215 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 216 (cz)->cz_fwctl + (off)) 217 218 #define CZ_FWCTL_WRITE(cz, off, val) \ 219 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 220 (cz)->cz_fwctl + (off), (val)) 221 222 /* 223 * Convenience macros for cztty routines. PLX window MUST be to RAM. 224 */ 225 #define CZTTY_CHAN_READ(sc, off) \ 226 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_chan_sh, (off)) 227 228 #define CZTTY_CHAN_WRITE(sc, off, val) \ 229 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_chan_sh, \ 230 (off), (val)) 231 232 #define CZTTY_BUF_READ(sc, off) \ 233 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_buf_sh, (off)) 234 235 #define CZTTY_BUF_WRITE(sc, off, val) \ 236 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_buf_sh, \ 237 (off), (val)) 238 239 /* 240 * Convenience macros. 241 */ 242 #define CZ_WIN_RAM(cz) \ 243 do { \ 244 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_RAM); \ 245 delay(100); \ 246 } while (0) 247 248 #define CZ_WIN_FPGA(cz) \ 249 do { \ 250 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_FPGA); \ 251 delay(100); \ 252 } while (0) 253 254 /***************************************************************************** 255 * Cyclades-Z controller code starts here... 256 *****************************************************************************/ 257 258 /* 259 * cz_match: 260 * 261 * Determine if the given PCI device is a Cyclades-Z board. 262 */ 263 static int 264 cz_match(device_t parent, cfdata_t match, void *aux) 265 { 266 struct pci_attach_args *pa = aux; 267 268 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYCLADES) { 269 switch (PCI_PRODUCT(pa->pa_id)) { 270 case PCI_PRODUCT_CYCLADES_CYCLOMZ_2: 271 return (1); 272 } 273 } 274 275 return (0); 276 } 277 278 /* 279 * cz_attach: 280 * 281 * A Cyclades-Z board was found; attach it. 282 */ 283 static void 284 cz_attach(device_t parent, device_t self, void *aux) 285 { 286 extern const struct cdevsw cz_cdevsw; /* XXX */ 287 struct cz_softc *cz = device_private(self); 288 struct pci_attach_args *pa = aux; 289 pci_intr_handle_t ih; 290 const char *intrstr = NULL; 291 struct cztty_softc *sc; 292 struct tty *tp; 293 int i; 294 295 aprint_naive(": Multi-port serial controller\n"); 296 aprint_normal(": Cyclades-Z multiport serial\n"); 297 298 cz->cz_plx.plx_pc = pa->pa_pc; 299 cz->cz_plx.plx_tag = pa->pa_tag; 300 301 if (pci_mapreg_map(pa, PLX_PCI_RUNTIME_MEMADDR, 302 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 303 &cz->cz_plx.plx_st, &cz->cz_plx.plx_sh, NULL, NULL) != 0) { 304 aprint_error_dev(&cz->cz_dev, "unable to map PLX registers\n"); 305 return; 306 } 307 if (pci_mapreg_map(pa, PLX_PCI_LOCAL_ADDR0, 308 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 309 &cz->cz_win_st, &cz->cz_win_sh, NULL, NULL) != 0) { 310 aprint_error_dev(&cz->cz_dev, "unable to map device window\n"); 311 return; 312 } 313 314 cz->cz_mailbox0 = CZ_PLX_READ(cz, PLX_MAILBOX0); 315 cz->cz_nopenchan = 0; 316 317 /* 318 * Make sure that the board is completely stopped. 319 */ 320 CZ_WIN_FPGA(cz); 321 CZ_FPGA_WRITE(cz, FPGA_CPU_STOP, 0); 322 323 /* 324 * Load the board's firmware. 325 */ 326 if (cz_load_firmware(cz) != 0) 327 return; 328 329 /* 330 * Now that we're ready to roll, map and establish the interrupt 331 * handler. 332 */ 333 if (pci_intr_map(pa, &ih) != 0) { 334 /* 335 * The common case is for Cyclades-Z boards to run 336 * in polling mode, and thus not have an interrupt 337 * mapped for them. Don't bother reporting that 338 * the interrupt is not mappable, since this isn't 339 * really an error. 340 */ 341 cz->cz_ih = NULL; 342 goto polling_mode; 343 } else { 344 intrstr = pci_intr_string(pa->pa_pc, ih); 345 cz->cz_ih = pci_intr_establish(pa->pa_pc, ih, IPL_TTY, 346 cz_intr, cz); 347 } 348 if (cz->cz_ih == NULL) { 349 aprint_error_dev(&cz->cz_dev, "unable to establish interrupt"); 350 if (intrstr != NULL) 351 aprint_error(" at %s", intrstr); 352 aprint_error("\n"); 353 /* We will fall-back on polling mode. */ 354 } else 355 aprint_normal_dev(&cz->cz_dev, "interrupting at %s\n", 356 intrstr); 357 358 polling_mode: 359 if (cz->cz_ih == NULL) { 360 callout_init(&cz->cz_callout, 0); 361 if (cz_timeout_ticks == 0) 362 cz_timeout_ticks = max(1, hz * CZ_POLL_MS / 1000); 363 aprint_normal_dev(&cz->cz_dev, "polling mode, %d ms interval (%d tick%s)\n", 364 CZ_POLL_MS, cz_timeout_ticks, 365 cz_timeout_ticks == 1 ? "" : "s"); 366 } 367 368 /* 369 * Allocate sufficient pointers for the children and 370 * attach them. Set all ports to a reasonable initial 371 * configuration while we're at it: 372 * 373 * disabled 374 * 8N1 375 * default baud rate 376 * hardware flow control. 377 */ 378 CZ_WIN_RAM(cz); 379 380 if (cz->cz_nchannels == 0) { 381 /* No channels? No more work to do! */ 382 return; 383 } 384 385 cz->cz_ports = malloc(sizeof(struct cztty_softc) * cz->cz_nchannels, 386 M_DEVBUF, M_WAITOK|M_ZERO); 387 cztty_attached_ttys += cz->cz_nchannels; 388 389 for (i = 0; i < cz->cz_nchannels; i++) { 390 sc = &cz->cz_ports[i]; 391 392 sc->sc_channel = i; 393 sc->sc_chan_st = cz->cz_win_st; 394 sc->sc_parent = cz; 395 396 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 397 cz->cz_fwctl + ZFIRM_CHNCTL_OFF(i, 0), 398 ZFIRM_CHNCTL_SIZE, &sc->sc_chan_sh)) { 399 aprint_error_dev(&cz->cz_dev, 400 "unable to subregion channel %d control\n", i); 401 sc->sc_channel = CZTTY_CHANNEL_DEAD; 402 continue; 403 } 404 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 405 cz->cz_fwctl + ZFIRM_BUFCTL_OFF(i, 0), 406 ZFIRM_BUFCTL_SIZE, &sc->sc_buf_sh)) { 407 aprint_error_dev(&cz->cz_dev, 408 "unable to subregion channel %d buffer\n", i); 409 sc->sc_channel = CZTTY_CHANNEL_DEAD; 410 continue; 411 } 412 413 callout_init(&sc->sc_diag_ch, 0); 414 415 tp = ttymalloc(); 416 tp->t_dev = makedev(cdevsw_lookup_major(&cz_cdevsw), 417 (device_unit(&cz->cz_dev) * ZFIRM_MAX_CHANNELS) + i); 418 tp->t_oproc = czttystart; 419 tp->t_param = czttyparam; 420 tty_attach(tp); 421 422 sc->sc_tty = tp; 423 424 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 425 CZTTY_CHAN_WRITE(sc, CHNCTL_INTR_ENABLE, CZ_INTERRUPTS); 426 CZTTY_CHAN_WRITE(sc, CHNCTL_SW_FLOW, 0); 427 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XON, 0x11); 428 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XOFF, 0x13); 429 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, TTYDEF_SPEED); 430 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, C_PR_NONE); 431 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, C_DL_CS8 | C_DL_1STOP); 432 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_FLAGS, 0); 433 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, C_RS_CTS | C_RS_RTS); 434 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, 0); 435 } 436 } 437 438 CFATTACH_DECL(cz, sizeof(struct cz_softc), 439 cz_match, cz_attach, NULL, NULL); 440 441 #if 0 442 /* 443 * cz_reset_board: 444 * 445 * Reset the board via the PLX. 446 */ 447 static void 448 cz_reset_board(struct cz_softc *cz) 449 { 450 u_int32_t reg; 451 452 reg = CZ_PLX_READ(cz, PLX_CONTROL); 453 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_SWR); 454 delay(1000); 455 456 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 457 delay(1000); 458 459 /* Now reload the PLX from its EEPROM. */ 460 reg = CZ_PLX_READ(cz, PLX_CONTROL); 461 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_RELOADCFG); 462 delay(1000); 463 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 464 } 465 #endif 466 467 /* 468 * cz_load_firmware: 469 * 470 * Load the ZFIRM firmware into the board's RAM and start it 471 * running. 472 */ 473 static int 474 cz_load_firmware(struct cz_softc *cz) 475 { 476 const struct zfirm_header *zfh; 477 const struct zfirm_config *zfc; 478 const struct zfirm_block *zfb, *zblocks; 479 const u_int8_t *cp; 480 const char *board; 481 u_int32_t fid; 482 int i, j, nconfigs, nblocks, nbytes; 483 484 zfh = (const struct zfirm_header *) cycladesz_firmware; 485 486 /* Find the config header. */ 487 if (le32toh(zfh->zfh_configoff) & (sizeof(u_int32_t) - 1)) { 488 aprint_error_dev(&cz->cz_dev, "bad ZFIRM config offset: 0x%x\n", 489 le32toh(zfh->zfh_configoff)); 490 return (EIO); 491 } 492 zfc = (const struct zfirm_config *)(cycladesz_firmware + 493 le32toh(zfh->zfh_configoff)); 494 nconfigs = le32toh(zfh->zfh_nconfig); 495 496 /* Locate the correct configuration for our board. */ 497 for (i = 0; i < nconfigs; i++, zfc++) { 498 if (le32toh(zfc->zfc_mailbox) == cz->cz_mailbox0 && 499 le32toh(zfc->zfc_function) == ZFC_FUNCTION_NORMAL) 500 break; 501 } 502 if (i == nconfigs) { 503 aprint_error_dev(&cz->cz_dev, "unable to locate config header\n"); 504 return (EIO); 505 } 506 507 nblocks = le32toh(zfc->zfc_nblocks); 508 zblocks = (const struct zfirm_block *)(cycladesz_firmware + 509 le32toh(zfh->zfh_blockoff)); 510 511 /* 512 * 8Zo ver. 1 doesn't have an FPGA. Load it on all others if 513 * necessary. 514 */ 515 if (cz->cz_mailbox0 != MAILBOX0_8Zo_V1 516 #if 0 517 && ((CZ_PLX_READ(cz, PLX_CONTROL) & CONTROL_FPGA_LOADED) == 0) 518 #endif 519 ) { 520 #ifdef CZ_DEBUG 521 aprint_debug_dev(&cz->cz_dev, "Loading FPGA..."); 522 #endif 523 CZ_WIN_FPGA(cz); 524 for (i = 0; i < nblocks; i++) { 525 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 526 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 527 if (le32toh(zfb->zfb_type) == ZFB_TYPE_FPGA) { 528 nbytes = le32toh(zfb->zfb_size); 529 cp = &cycladesz_firmware[ 530 le32toh(zfb->zfb_fileoff)]; 531 for (j = 0; j < nbytes; j++, cp++) { 532 bus_space_write_1(cz->cz_win_st, 533 cz->cz_win_sh, 0, *cp); 534 /* FPGA needs 30-100us to settle. */ 535 delay(10); 536 } 537 } 538 } 539 #ifdef CZ_DEBUG 540 aprint_debug("done\n"); 541 #endif 542 } 543 544 /* Now load the firmware. */ 545 CZ_WIN_RAM(cz); 546 547 for (i = 0; i < nblocks; i++) { 548 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 549 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 550 if (le32toh(zfb->zfb_type) == ZFB_TYPE_FIRMWARE) { 551 const u_int32_t *lp; 552 u_int32_t ro = le32toh(zfb->zfb_ramoff); 553 nbytes = le32toh(zfb->zfb_size); 554 lp = (const u_int32_t *) 555 &cycladesz_firmware[le32toh(zfb->zfb_fileoff)]; 556 for (j = 0; j < nbytes; j += 4, lp++) { 557 bus_space_write_4(cz->cz_win_st, cz->cz_win_sh, 558 ro + j, le32toh(*lp)); 559 delay(10); 560 } 561 } 562 } 563 564 /* Now restart the MIPS. */ 565 CZ_WIN_FPGA(cz); 566 CZ_FPGA_WRITE(cz, FPGA_CPU_START, 0); 567 568 /* Wait for the MIPS to start, then report the results. */ 569 CZ_WIN_RAM(cz); 570 571 #ifdef CZ_DEBUG 572 aprint_debug_dev(&cz->cz_dev, "waiting for MIPS to start"); 573 #endif 574 for (i = 0; i < 100; i++) { 575 fid = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 576 ZFIRM_SIG_OFF); 577 if (fid == ZFIRM_SIG) { 578 /* MIPS has booted. */ 579 break; 580 } else if (fid == ZFIRM_HLT) { 581 /* 582 * The MIPS has halted, usually due to a power 583 * shortage on the expansion module. 584 */ 585 aprint_error_dev(&cz->cz_dev, "MIPS halted; possible power supply " 586 "problem\n"); 587 return (EIO); 588 } else { 589 #ifdef CZ_DEBUG 590 if ((i % 8) == 0) 591 aprint_debug("."); 592 #endif 593 delay(250000); 594 } 595 } 596 #ifdef CZ_DEBUG 597 aprint_debug("\n"); 598 #endif 599 if (i == 100) { 600 CZ_WIN_FPGA(cz); 601 aprint_error_dev(&cz->cz_dev, 602 "MIPS failed to start; wanted 0x%08x got 0x%08x\n", 603 ZFIRM_SIG, fid); 604 aprint_error_dev(&cz->cz_dev, "FPGA ID 0x%08x, FPGA version 0x%08x\n", 605 CZ_FPGA_READ(cz, FPGA_ID), 606 CZ_FPGA_READ(cz, FPGA_VERSION)); 607 return (EIO); 608 } 609 610 /* 611 * Locate the firmware control structures. 612 */ 613 cz->cz_fwctl = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 614 ZFIRM_CTRLADDR_OFF); 615 #ifdef CZ_DEBUG 616 aprint_debug_dev(&cz->cz_dev, "FWCTL structure at offset " 617 "%#08" PRIxPADDR "\n", cz->cz_fwctl); 618 #endif 619 620 CZ_FWCTL_WRITE(cz, BRDCTL_C_OS, C_OS_BSD); 621 CZ_FWCTL_WRITE(cz, BRDCTL_DRVERSION, CZ_DRIVER_VERSION); 622 623 cz->cz_nchannels = CZ_FWCTL_READ(cz, BRDCTL_NCHANNEL); 624 625 switch (cz->cz_mailbox0) { 626 case MAILBOX0_8Zo_V1: 627 board = "Cyclades-8Zo ver. 1"; 628 break; 629 630 case MAILBOX0_8Zo_V2: 631 board = "Cyclades-8Zo ver. 2"; 632 break; 633 634 case MAILBOX0_Ze_V1: 635 board = "Cyclades-Ze"; 636 break; 637 638 default: 639 board = "unknown Cyclades Z-series"; 640 break; 641 } 642 643 fid = CZ_FWCTL_READ(cz, BRDCTL_FWVERSION); 644 aprint_normal_dev(&cz->cz_dev, "%s, ", board); 645 if (cz->cz_nchannels == 0) 646 aprint_normal("no channels attached, "); 647 else 648 aprint_normal("%d channels (ttyCZ%04d..ttyCZ%04d), ", 649 cz->cz_nchannels, cztty_attached_ttys, 650 cztty_attached_ttys + (cz->cz_nchannels - 1)); 651 aprint_normal("firmware %x.%x.%x\n", 652 (fid >> 8) & 0xf, (fid >> 4) & 0xf, fid & 0xf); 653 654 return (0); 655 } 656 657 /* 658 * cz_poll: 659 * 660 * This card doesn't do interrupts, so scan it for activity every CZ_POLL_MS 661 * ms. 662 */ 663 static void 664 cz_poll(void *arg) 665 { 666 int s = spltty(); 667 struct cz_softc *cz = arg; 668 669 cz_intr(cz); 670 callout_reset(&cz->cz_callout, cz_timeout_ticks, cz_poll, cz); 671 672 splx(s); 673 } 674 675 /* 676 * cz_intr: 677 * 678 * Interrupt service routine. 679 * 680 * We either are receiving an interrupt directly from the board, or we are 681 * in polling mode and it's time to poll. 682 */ 683 static int 684 cz_intr(void *arg) 685 { 686 int rval = 0; 687 u_int command, channel, param; 688 struct cz_softc *cz = arg; 689 struct cztty_softc *sc; 690 struct tty *tp; 691 692 while ((command = (CZ_PLX_READ(cz, PLX_LOCAL_PCI_DOORBELL) & 0xff))) { 693 rval = 1; 694 channel = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_CHANNEL); 695 param = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_PARAM); 696 697 /* now clear this interrupt, posslibly enabling another */ 698 CZ_PLX_WRITE(cz, PLX_LOCAL_PCI_DOORBELL, command); 699 700 if (cz->cz_ports == NULL) { 701 #ifdef CZ_DEBUG 702 printf("%s: interrupt on channel %d, but no channels\n", 703 device_xname(&cz->cz_dev), channel); 704 #endif 705 continue; 706 } 707 708 sc = &cz->cz_ports[channel]; 709 710 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 711 break; 712 713 tp = sc->sc_tty; 714 715 switch (command) { 716 case C_CM_TXFEMPTY: /* transmit cases */ 717 case C_CM_TXBEMPTY: 718 case C_CM_TXLOWWM: 719 case C_CM_INTBACK: 720 if (!ISSET(tp->t_state, TS_ISOPEN)) { 721 #ifdef CZ_DEBUG 722 printf("%s: tx intr on closed channel %d\n", 723 device_xname(&cz->cz_dev), channel); 724 #endif 725 break; 726 } 727 728 if (cztty_transmit(sc, tp)) { 729 /* 730 * Do wakeup stuff here. 731 */ 732 mutex_spin_enter(&tty_lock); /* XXX */ 733 ttwakeup(tp); 734 mutex_spin_exit(&tty_lock); /* XXX */ 735 wakeup(tp); 736 } 737 break; 738 739 case C_CM_RXNNDT: /* receive cases */ 740 case C_CM_RXHIWM: 741 case C_CM_INTBACK2: /* from restart ?? */ 742 #if 0 743 case C_CM_ICHAR: 744 #endif 745 if (!ISSET(tp->t_state, TS_ISOPEN)) { 746 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 747 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 748 break; 749 } 750 751 if (cztty_receive(sc, tp)) { 752 /* 753 * Do wakeup stuff here. 754 */ 755 mutex_spin_enter(&tty_lock); /* XXX */ 756 ttwakeup(tp); 757 mutex_spin_exit(&tty_lock); /* XXX */ 758 wakeup(tp); 759 } 760 break; 761 762 case C_CM_MDCD: 763 if (!ISSET(tp->t_state, TS_ISOPEN)) 764 break; 765 766 (void) (*tp->t_linesw->l_modem)(tp, 767 ISSET(C_RS_DCD, CZTTY_CHAN_READ(sc, 768 CHNCTL_RS_STATUS))); 769 break; 770 771 case C_CM_MDSR: 772 case C_CM_MRI: 773 case C_CM_MCTS: 774 case C_CM_MRTS: 775 break; 776 777 case C_CM_IOCTLW: 778 break; 779 780 case C_CM_PR_ERROR: 781 sc->sc_parity_errors++; 782 goto error_common; 783 784 case C_CM_FR_ERROR: 785 sc->sc_framing_errors++; 786 goto error_common; 787 788 case C_CM_OVR_ERROR: 789 sc->sc_overflows++; 790 error_common: 791 if (sc->sc_errors++ == 0) 792 callout_reset(&sc->sc_diag_ch, 60 * hz, 793 cztty_diag, sc); 794 break; 795 796 case C_CM_RXBRK: 797 if (!ISSET(tp->t_state, TS_ISOPEN)) 798 break; 799 800 /* 801 * A break is a \000 character with TTY_FE error 802 * flags set. So TTY_FE by itself works. 803 */ 804 (*tp->t_linesw->l_rint)(TTY_FE, tp); 805 mutex_spin_enter(&tty_lock); /* XXX */ 806 ttwakeup(tp); 807 mutex_spin_exit(&tty_lock); /* XXX */ 808 wakeup(tp); 809 break; 810 811 default: 812 #ifdef CZ_DEBUG 813 printf("%s: channel %d: Unknown interrupt 0x%x\n", 814 device_xname(&cz->cz_dev), sc->sc_channel, command); 815 #endif 816 break; 817 } 818 } 819 820 return (rval); 821 } 822 823 /* 824 * cz_wait_pci_doorbell: 825 * 826 * Wait for the pci doorbell to be clear - wait for pending 827 * activity to drain. 828 */ 829 static int 830 cz_wait_pci_doorbell(struct cz_softc *cz, const char *wstring) 831 { 832 int error; 833 834 while (CZ_PLX_READ(cz, PLX_PCI_LOCAL_DOORBELL)) { 835 error = tsleep(cz, TTIPRI | PCATCH, wstring, max(1, hz/100)); 836 if ((error != 0) && (error != EWOULDBLOCK)) 837 return (error); 838 } 839 return (0); 840 } 841 842 /***************************************************************************** 843 * Cyclades-Z TTY code starts here... 844 *****************************************************************************/ 845 846 #define CZTTYDIALOUT_MASK 0x80000 847 848 #define CZTTY_DIALOUT(dev) (minor((dev)) & CZTTYDIALOUT_MASK) 849 #define CZTTY_CZ(sc) ((sc)->sc_parent) 850 851 #define CZTTY_SOFTC(dev) cztty_getttysoftc(dev) 852 853 static struct cztty_softc * 854 cztty_getttysoftc(dev_t dev) 855 { 856 int i, j, k = 0, u = minor(dev) & ~CZTTYDIALOUT_MASK; 857 struct cz_softc *cz = NULL; 858 859 for (i = 0, j = 0; i < cz_cd.cd_ndevs; i++) { 860 k = j; 861 cz = device_lookup_private(&cz_cd, i); 862 if (cz == NULL) 863 continue; 864 if (cz->cz_ports == NULL) 865 continue; 866 j += cz->cz_nchannels; 867 if (j > u) 868 break; 869 } 870 871 if (i >= cz_cd.cd_ndevs) 872 return (NULL); 873 else 874 return (&cz->cz_ports[u - k]); 875 } 876 877 /* 878 * czttytty: 879 * 880 * Return a pointer to our tty. 881 */ 882 static struct tty * 883 czttytty(dev_t dev) 884 { 885 struct cztty_softc *sc = CZTTY_SOFTC(dev); 886 887 #ifdef DIAGNOSTIC 888 if (sc == NULL) 889 panic("czttytty"); 890 #endif 891 892 return (sc->sc_tty); 893 } 894 895 /* 896 * cztty_shutdown: 897 * 898 * Shut down a port. 899 */ 900 static void 901 cztty_shutdown(struct cztty_softc *sc) 902 { 903 struct cz_softc *cz = CZTTY_CZ(sc); 904 struct tty *tp = sc->sc_tty; 905 int s; 906 907 s = spltty(); 908 909 /* Clear any break condition set with TIOCSBRK. */ 910 cztty_break(sc, 0); 911 912 /* 913 * Hang up if necessary. Wait a bit, so the other side has time to 914 * notice even if we immediately open the port again. 915 */ 916 if (ISSET(tp->t_cflag, HUPCL)) { 917 cztty_modem(sc, 0); 918 (void) tsleep(tp, TTIPRI, ttclos, hz); 919 } 920 921 /* Disable the channel. */ 922 cz_wait_pci_doorbell(cz, "czdis"); 923 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 924 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 925 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTL); 926 927 if ((--cz->cz_nopenchan == 0) && (cz->cz_ih == NULL)) { 928 #ifdef CZ_DEBUG 929 printf("%s: Disabling polling\n", device_xname(&cz->cz_dev)); 930 #endif 931 callout_stop(&cz->cz_callout); 932 } 933 934 splx(s); 935 } 936 937 /* 938 * czttyopen: 939 * 940 * Open a Cyclades-Z serial port. 941 */ 942 static int 943 czttyopen(dev_t dev, int flags, int mode, struct lwp *l) 944 { 945 struct cztty_softc *sc = CZTTY_SOFTC(dev); 946 struct cz_softc *cz; 947 struct tty *tp; 948 int s, error; 949 950 if (sc == NULL) 951 return (ENXIO); 952 953 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 954 return (ENXIO); 955 956 cz = CZTTY_CZ(sc); 957 tp = sc->sc_tty; 958 959 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 960 return (EBUSY); 961 962 s = spltty(); 963 964 /* 965 * Do the following iff this is a first open. 966 */ 967 if (!ISSET(tp->t_state, TS_ISOPEN) && (tp->t_wopen == 0)) { 968 struct termios t; 969 970 tp->t_dev = dev; 971 972 /* If we're turning things on, enable interrupts */ 973 if ((cz->cz_nopenchan++ == 0) && (cz->cz_ih == NULL)) { 974 #ifdef CZ_DEBUG 975 printf("%s: Enabling polling.\n", 976 device_xname(&cz->cz_dev)); 977 #endif 978 callout_reset(&cz->cz_callout, cz_timeout_ticks, 979 cz_poll, cz); 980 } 981 982 /* 983 * Enable the channel. Don't actually ring the 984 * doorbell here; czttyparam() will do it for us. 985 */ 986 cz_wait_pci_doorbell(cz, "czopen"); 987 988 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_ENABLE); 989 990 /* 991 * Initialize the termios status to the defaults. Add in the 992 * sticky bits from TIOCSFLAGS. 993 */ 994 t.c_ispeed = 0; 995 t.c_ospeed = TTYDEF_SPEED; 996 t.c_cflag = TTYDEF_CFLAG; 997 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 998 SET(t.c_cflag, CLOCAL); 999 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1000 SET(t.c_cflag, CRTSCTS); 1001 1002 /* 1003 * Reset the input and output rings. Do this before 1004 * we call czttyparam(), as that function enables 1005 * the channel. 1006 */ 1007 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 1008 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 1009 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, 1010 CZTTY_BUF_READ(sc, BUFCTL_TX_GET)); 1011 1012 /* Make sure czttyparam() will see changes. */ 1013 tp->t_ospeed = 0; 1014 (void) czttyparam(tp, &t); 1015 tp->t_iflag = TTYDEF_IFLAG; 1016 tp->t_oflag = TTYDEF_OFLAG; 1017 tp->t_lflag = TTYDEF_LFLAG; 1018 ttychars(tp); 1019 ttsetwater(tp); 1020 1021 /* 1022 * Turn on DTR. We must always do this, even if carrier is not 1023 * present, because otherwise we'd have to use TIOCSDTR 1024 * immediately after setting CLOCAL, which applications do not 1025 * expect. We always assert DTR while the device is open 1026 * unless explicitly requested to deassert it. 1027 */ 1028 cztty_modem(sc, 1); 1029 } 1030 1031 splx(s); 1032 1033 error = ttyopen(tp, CZTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK)); 1034 if (error) 1035 goto bad; 1036 1037 error = (*tp->t_linesw->l_open)(dev, tp); 1038 if (error) 1039 goto bad; 1040 1041 return (0); 1042 1043 bad: 1044 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1045 /* 1046 * We failed to open the device, and nobody else had it opened. 1047 * Clean up the state as appropriate. 1048 */ 1049 cztty_shutdown(sc); 1050 } 1051 1052 return (error); 1053 } 1054 1055 /* 1056 * czttyclose: 1057 * 1058 * Close a Cyclades-Z serial port. 1059 */ 1060 static int 1061 czttyclose(dev_t dev, int flags, int mode, struct lwp *l) 1062 { 1063 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1064 struct tty *tp = sc->sc_tty; 1065 1066 /* XXX This is for cons.c. */ 1067 if (!ISSET(tp->t_state, TS_ISOPEN)) 1068 return (0); 1069 1070 (*tp->t_linesw->l_close)(tp, flags); 1071 ttyclose(tp); 1072 1073 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1074 /* 1075 * Although we got a last close, the device may still be in 1076 * use; e.g. if this was the dialout node, and there are still 1077 * processes waiting for carrier on the non-dialout node. 1078 */ 1079 cztty_shutdown(sc); 1080 } 1081 1082 return (0); 1083 } 1084 1085 /* 1086 * czttyread: 1087 * 1088 * Read from a Cyclades-Z serial port. 1089 */ 1090 static int 1091 czttyread(dev_t dev, struct uio *uio, int flags) 1092 { 1093 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1094 struct tty *tp = sc->sc_tty; 1095 1096 return ((*tp->t_linesw->l_read)(tp, uio, flags)); 1097 } 1098 1099 /* 1100 * czttywrite: 1101 * 1102 * Write to a Cyclades-Z serial port. 1103 */ 1104 static int 1105 czttywrite(dev_t dev, struct uio *uio, int flags) 1106 { 1107 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1108 struct tty *tp = sc->sc_tty; 1109 1110 return ((*tp->t_linesw->l_write)(tp, uio, flags)); 1111 } 1112 1113 /* 1114 * czttypoll: 1115 * 1116 * Poll a Cyclades-Z serial port. 1117 */ 1118 static int 1119 czttypoll(dev_t dev, int events, struct lwp *l) 1120 { 1121 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1122 struct tty *tp = sc->sc_tty; 1123 1124 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1125 } 1126 1127 /* 1128 * czttyioctl: 1129 * 1130 * Perform a control operation on a Cyclades-Z serial port. 1131 */ 1132 static int 1133 czttyioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1134 { 1135 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1136 struct tty *tp = sc->sc_tty; 1137 int s, error; 1138 1139 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1140 if (error != EPASSTHROUGH) 1141 return (error); 1142 1143 error = ttioctl(tp, cmd, data, flag, l); 1144 if (error != EPASSTHROUGH) 1145 return (error); 1146 1147 error = 0; 1148 1149 s = spltty(); 1150 1151 switch (cmd) { 1152 case TIOCSBRK: 1153 cztty_break(sc, 1); 1154 break; 1155 1156 case TIOCCBRK: 1157 cztty_break(sc, 0); 1158 break; 1159 1160 case TIOCGFLAGS: 1161 *(int *)data = sc->sc_swflags; 1162 break; 1163 1164 case TIOCSFLAGS: 1165 error = kauth_authorize_device_tty(l->l_cred, 1166 KAUTH_DEVICE_TTY_PRIVSET, tp); 1167 if (error) 1168 break; 1169 sc->sc_swflags = *(int *)data; 1170 break; 1171 1172 case TIOCSDTR: 1173 cztty_modem(sc, 1); 1174 break; 1175 1176 case TIOCCDTR: 1177 cztty_modem(sc, 0); 1178 break; 1179 1180 case TIOCMSET: 1181 case TIOCMBIS: 1182 case TIOCMBIC: 1183 tiocm_to_cztty(sc, cmd, *(int *)data); 1184 break; 1185 1186 case TIOCMGET: 1187 *(int *)data = cztty_to_tiocm(sc); 1188 break; 1189 1190 default: 1191 error = EPASSTHROUGH; 1192 break; 1193 } 1194 1195 splx(s); 1196 1197 return (error); 1198 } 1199 1200 /* 1201 * cztty_break: 1202 * 1203 * Set or clear BREAK on a port. 1204 */ 1205 static void 1206 cztty_break(struct cztty_softc *sc, int onoff) 1207 { 1208 struct cz_softc *cz = CZTTY_CZ(sc); 1209 1210 cz_wait_pci_doorbell(cz, "czbreak"); 1211 1212 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1213 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, 1214 onoff ? C_CM_SET_BREAK : C_CM_CLR_BREAK); 1215 } 1216 1217 /* 1218 * cztty_modem: 1219 * 1220 * Set or clear DTR on a port. 1221 */ 1222 static void 1223 cztty_modem(struct cztty_softc *sc, int onoff) 1224 { 1225 struct cz_softc *cz = CZTTY_CZ(sc); 1226 1227 if (sc->sc_rs_control_dtr == 0) 1228 return; 1229 1230 cz_wait_pci_doorbell(cz, "czmod"); 1231 1232 if (onoff) 1233 sc->sc_chanctl_rs_control |= sc->sc_rs_control_dtr; 1234 else 1235 sc->sc_chanctl_rs_control &= ~sc->sc_rs_control_dtr; 1236 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1237 1238 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1239 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1240 } 1241 1242 /* 1243 * tiocm_to_cztty: 1244 * 1245 * Process TIOCM* ioctls. 1246 */ 1247 static void 1248 tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits) 1249 { 1250 struct cz_softc *cz = CZTTY_CZ(sc); 1251 u_int32_t czttybits; 1252 1253 czttybits = 0; 1254 if (ISSET(ttybits, TIOCM_DTR)) 1255 SET(czttybits, C_RS_DTR); 1256 if (ISSET(ttybits, TIOCM_RTS)) 1257 SET(czttybits, C_RS_RTS); 1258 1259 cz_wait_pci_doorbell(cz, "cztiocm"); 1260 1261 switch (how) { 1262 case TIOCMBIC: 1263 CLR(sc->sc_chanctl_rs_control, czttybits); 1264 break; 1265 1266 case TIOCMBIS: 1267 SET(sc->sc_chanctl_rs_control, czttybits); 1268 break; 1269 1270 case TIOCMSET: 1271 CLR(sc->sc_chanctl_rs_control, C_RS_DTR | C_RS_RTS); 1272 SET(sc->sc_chanctl_rs_control, czttybits); 1273 break; 1274 } 1275 1276 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1277 1278 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1279 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1280 } 1281 1282 /* 1283 * cztty_to_tiocm: 1284 * 1285 * Process the TIOCMGET ioctl. 1286 */ 1287 static int 1288 cztty_to_tiocm(struct cztty_softc *sc) 1289 { 1290 struct cz_softc *cz = CZTTY_CZ(sc); 1291 u_int32_t rs_status, op_mode; 1292 int ttybits = 0; 1293 1294 cz_wait_pci_doorbell(cz, "cztty"); 1295 1296 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1297 op_mode = CZTTY_CHAN_READ(sc, CHNCTL_OP_MODE); 1298 1299 if (ISSET(rs_status, C_RS_RTS)) 1300 SET(ttybits, TIOCM_RTS); 1301 if (ISSET(rs_status, C_RS_CTS)) 1302 SET(ttybits, TIOCM_CTS); 1303 if (ISSET(rs_status, C_RS_DCD)) 1304 SET(ttybits, TIOCM_CAR); 1305 if (ISSET(rs_status, C_RS_DTR)) 1306 SET(ttybits, TIOCM_DTR); 1307 if (ISSET(rs_status, C_RS_RI)) 1308 SET(ttybits, TIOCM_RNG); 1309 if (ISSET(rs_status, C_RS_DSR)) 1310 SET(ttybits, TIOCM_DSR); 1311 1312 if (ISSET(op_mode, C_CH_ENABLE)) 1313 SET(ttybits, TIOCM_LE); 1314 1315 return (ttybits); 1316 } 1317 1318 /* 1319 * czttyparam: 1320 * 1321 * Set Cyclades-Z serial port parameters from termios. 1322 * 1323 * XXX Should just copy the whole termios after making 1324 * XXX sure all the changes could be done. 1325 */ 1326 static int 1327 czttyparam(struct tty *tp, struct termios *t) 1328 { 1329 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1330 struct cz_softc *cz = CZTTY_CZ(sc); 1331 u_int32_t rs_status; 1332 int ospeed, cflag; 1333 1334 ospeed = t->c_ospeed; 1335 cflag = t->c_cflag; 1336 1337 /* Check requested parameters. */ 1338 if (ospeed < 0) 1339 return (EINVAL); 1340 if (t->c_ispeed && t->c_ispeed != ospeed) 1341 return (EINVAL); 1342 1343 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR)) { 1344 SET(cflag, CLOCAL); 1345 CLR(cflag, HUPCL); 1346 } 1347 1348 /* 1349 * If there were no changes, don't do anything. This avoids dropping 1350 * input and improves performance when all we did was frob things like 1351 * VMIN and VTIME. 1352 */ 1353 if (tp->t_ospeed == ospeed && 1354 tp->t_cflag == cflag) 1355 return (0); 1356 1357 /* Data bits. */ 1358 sc->sc_chanctl_comm_data_l = 0; 1359 switch (t->c_cflag & CSIZE) { 1360 case CS5: 1361 sc->sc_chanctl_comm_data_l |= C_DL_CS5; 1362 break; 1363 1364 case CS6: 1365 sc->sc_chanctl_comm_data_l |= C_DL_CS6; 1366 break; 1367 1368 case CS7: 1369 sc->sc_chanctl_comm_data_l |= C_DL_CS7; 1370 break; 1371 1372 case CS8: 1373 sc->sc_chanctl_comm_data_l |= C_DL_CS8; 1374 break; 1375 } 1376 1377 /* Stop bits. */ 1378 if (t->c_cflag & CSTOPB) { 1379 if ((sc->sc_chanctl_comm_data_l & C_DL_CS) == C_DL_CS5) 1380 sc->sc_chanctl_comm_data_l |= C_DL_15STOP; 1381 else 1382 sc->sc_chanctl_comm_data_l |= C_DL_2STOP; 1383 } else 1384 sc->sc_chanctl_comm_data_l |= C_DL_1STOP; 1385 1386 /* Parity. */ 1387 if (t->c_cflag & PARENB) { 1388 if (t->c_cflag & PARODD) 1389 sc->sc_chanctl_comm_parity = C_PR_ODD; 1390 else 1391 sc->sc_chanctl_comm_parity = C_PR_EVEN; 1392 } else 1393 sc->sc_chanctl_comm_parity = C_PR_NONE; 1394 1395 /* 1396 * Initialize flow control pins depending on the current flow control 1397 * mode. 1398 */ 1399 if (ISSET(t->c_cflag, CRTSCTS)) { 1400 sc->sc_rs_control_dtr = C_RS_DTR; 1401 sc->sc_chanctl_hw_flow = C_RS_CTS | C_RS_RTS; 1402 } else if (ISSET(t->c_cflag, MDMBUF)) { 1403 sc->sc_rs_control_dtr = 0; 1404 sc->sc_chanctl_hw_flow = C_RS_DCD | C_RS_DTR; 1405 } else { 1406 /* 1407 * If no flow control, then always set RTS. This will make 1408 * the other side happy if it mistakenly thinks we're doing 1409 * RTS/CTS flow control. 1410 */ 1411 sc->sc_rs_control_dtr = C_RS_DTR | C_RS_RTS; 1412 sc->sc_chanctl_hw_flow = 0; 1413 if (ISSET(sc->sc_chanctl_rs_control, C_RS_DTR)) 1414 SET(sc->sc_chanctl_rs_control, C_RS_RTS); 1415 else 1416 CLR(sc->sc_chanctl_rs_control, C_RS_RTS); 1417 } 1418 1419 /* Baud rate. */ 1420 sc->sc_chanctl_comm_baud = ospeed; 1421 1422 /* Copy to tty. */ 1423 tp->t_ispeed = 0; 1424 tp->t_ospeed = t->c_ospeed; 1425 tp->t_cflag = t->c_cflag; 1426 1427 /* 1428 * Now load the channel control structure. 1429 */ 1430 1431 cz_wait_pci_doorbell(cz, "czparam"); 1432 1433 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, sc->sc_chanctl_comm_baud); 1434 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, sc->sc_chanctl_comm_data_l); 1435 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, sc->sc_chanctl_comm_parity); 1436 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, sc->sc_chanctl_hw_flow); 1437 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1438 1439 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1440 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLW); 1441 1442 cz_wait_pci_doorbell(cz, "czparam"); 1443 1444 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1445 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1446 1447 cz_wait_pci_doorbell(cz, "czparam"); 1448 1449 /* 1450 * Update the tty layer's idea of the carrier bit, in case we changed 1451 * CLOCAL. We don't hang up here; we only do that by explicit 1452 * request. 1453 */ 1454 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1455 (void) (*tp->t_linesw->l_modem)(tp, ISSET(rs_status, C_RS_DCD)); 1456 1457 return (0); 1458 } 1459 1460 /* 1461 * czttystart: 1462 * 1463 * Start or restart transmission. 1464 */ 1465 static void 1466 czttystart(struct tty *tp) 1467 { 1468 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1469 int s; 1470 1471 s = spltty(); 1472 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1473 goto out; 1474 if (!ttypull(tp)) 1475 goto out; 1476 cztty_transmit(sc, tp); 1477 out: 1478 splx(s); 1479 } 1480 1481 /* 1482 * czttystop: 1483 * 1484 * Stop output, e.g., for ^S or output flush. 1485 */ 1486 static void 1487 czttystop(struct tty *tp, int flag) 1488 { 1489 1490 /* 1491 * XXX We don't do anything here, yet. Mostly, I don't know 1492 * XXX exactly how this should be implemented on this device. 1493 * XXX We've given a big chunk of data to the MIPS already, 1494 * XXX and I don't know how we request the MIPS to stop sending 1495 * XXX the data. So, punt for now. --thorpej 1496 */ 1497 } 1498 1499 /* 1500 * cztty_diag: 1501 * 1502 * Issue a scheduled diagnostic message. 1503 */ 1504 static void 1505 cztty_diag(void *arg) 1506 { 1507 struct cztty_softc *sc = arg; 1508 struct cz_softc *cz = CZTTY_CZ(sc); 1509 u_int overflows, parity_errors, framing_errors; 1510 int s; 1511 1512 s = spltty(); 1513 1514 overflows = sc->sc_overflows; 1515 sc->sc_overflows = 0; 1516 1517 parity_errors = sc->sc_parity_errors; 1518 sc->sc_parity_errors = 0; 1519 1520 framing_errors = sc->sc_framing_errors; 1521 sc->sc_framing_errors = 0; 1522 1523 sc->sc_errors = 0; 1524 1525 splx(s); 1526 1527 log(LOG_WARNING, 1528 "%s: channel %d: %u overflow%s, %u parity, %u framing error%s\n", 1529 device_xname(&cz->cz_dev), sc->sc_channel, 1530 overflows, overflows == 1 ? "" : "s", 1531 parity_errors, 1532 framing_errors, framing_errors == 1 ? "" : "s"); 1533 } 1534 1535 const struct cdevsw cz_cdevsw = { 1536 czttyopen, czttyclose, czttyread, czttywrite, czttyioctl, 1537 czttystop, czttytty, czttypoll, nommap, ttykqfilter, D_TTY 1538 }; 1539 1540 /* 1541 * tx and rx ring buffer size macros: 1542 * 1543 * The transmitter and receiver both use ring buffers. For each one, there 1544 * is a get (consumer) and a put (producer) offset. The get value is the 1545 * next byte to be read from the ring, and the put is the next one to be 1546 * put into the ring. get == put means the ring is empty. 1547 * 1548 * For each ring, the firmware controls one of (get, put) and this driver 1549 * controls the other. For transmission, this driver updates put to point 1550 * past the valid data, and the firmware moves get as bytes are sent. Likewise 1551 * for receive, the driver controls put, and this driver controls get. 1552 */ 1553 #define TX_MOVEABLE(g, p, s) (((g) > (p)) ? ((g) - (p) - 1) : ((s) - (p))) 1554 #define RX_MOVEABLE(g, p, s) (((g) > (p)) ? ((s) - (g)) : ((p) - (g))) 1555 1556 /* 1557 * cztty_transmit() 1558 * 1559 * Look at the tty for this port and start sending. 1560 */ 1561 static int 1562 cztty_transmit(struct cztty_softc *sc, struct tty *tp) 1563 { 1564 struct cz_softc *cz = CZTTY_CZ(sc); 1565 u_int move, get, put, size, address; 1566 #ifdef HOSTRAMCODE 1567 int error, done = 0; 1568 #else 1569 int done = 0; 1570 #endif 1571 1572 size = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFSIZE); 1573 get = CZTTY_BUF_READ(sc, BUFCTL_TX_GET); 1574 put = CZTTY_BUF_READ(sc, BUFCTL_TX_PUT); 1575 address = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFADDR); 1576 1577 while ((tp->t_outq.c_cc > 0) && ((move = TX_MOVEABLE(get, put, size)))){ 1578 #ifdef HOSTRAMCODE 1579 if (0) { 1580 move = min(tp->t_outq.c_cc, move); 1581 error = q_to_b(&tp->t_outq, 0, move); 1582 if (error != move) { 1583 printf("%s: channel %d: error moving to " 1584 "transmit buf\n", device_xname(&cz->cz_dev), 1585 sc->sc_channel); 1586 move = error; 1587 } 1588 } else { 1589 #endif 1590 move = min(ndqb(&tp->t_outq, 0), move); 1591 bus_space_write_region_1(cz->cz_win_st, cz->cz_win_sh, 1592 address + put, tp->t_outq.c_cf, move); 1593 ndflush(&tp->t_outq, move); 1594 #ifdef HOSTRAMCODE 1595 } 1596 #endif 1597 1598 put = ((put + move) % size); 1599 done = 1; 1600 } 1601 if (done) { 1602 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, put); 1603 } 1604 return (done); 1605 } 1606 1607 static int 1608 cztty_receive(struct cztty_softc *sc, struct tty *tp) 1609 { 1610 struct cz_softc *cz = CZTTY_CZ(sc); 1611 u_int get, put, size, address; 1612 int done = 0, ch; 1613 1614 size = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFSIZE); 1615 get = CZTTY_BUF_READ(sc, BUFCTL_RX_GET); 1616 put = CZTTY_BUF_READ(sc, BUFCTL_RX_PUT); 1617 address = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFADDR); 1618 1619 while ((get != put) && ((tp->t_canq.c_cc + tp->t_rawq.c_cc) < tp->t_hiwat)) { 1620 #ifdef HOSTRAMCODE 1621 if (hostram) { 1622 ch = ((char *)fifoaddr)[get]; 1623 } else { 1624 #endif 1625 ch = bus_space_read_1(cz->cz_win_st, cz->cz_win_sh, 1626 address + get); 1627 #ifdef HOSTRAMCODE 1628 } 1629 #endif 1630 (*tp->t_linesw->l_rint)(ch, tp); 1631 get = (get + 1) % size; 1632 done = 1; 1633 } 1634 if (done) { 1635 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, get); 1636 } 1637 return (done); 1638 } 1639