1 /* $NetBSD: cz.c,v 1.19 2002/03/17 19:40:59 atatat Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Zembu Labs, Inc. 5 * All rights reserved. 6 * 7 * Authors: Jason R. Thorpe <thorpej@zembu.com> 8 * Bill Studenmund <wrstuden@zembu.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Zembu Labs, Inc. 21 * 4. Neither the name of Zembu Labs nor the names of its employees may 22 * be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY ZEMBU LABS, INC. ``AS IS'' AND ANY EXPRESS 26 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR- 27 * RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS- 28 * CLAIMED. IN NO EVENT SHALL ZEMBU LABS BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Cyclades-Z series multi-port serial adapter driver for NetBSD. 39 * 40 * Some notes: 41 * 42 * - The Cyclades-Z has fully automatic hardware (and software!) 43 * flow control. We only utilize RTS/CTS flow control here, 44 * and it is implemented in a very simplistic manner. This 45 * may be an area of future work. 46 * 47 * - The PLX can map the either the board's RAM or host RAM 48 * into the MIPS's memory window. This would enable us to 49 * use less expensive (for us) memory reads/writes to host 50 * RAM, rather than time-consuming reads/writes to PCI 51 * memory space. However, the PLX can only map a 0-128M 52 * window, so we would have to ensure that the DMA address 53 * of the host RAM fits there. This is kind of a pain, 54 * so we just don't bother right now. 55 * 56 * - In a perfect world, we would use the autoconfiguration 57 * mechanism to attach the TTYs that we find. However, 58 * that leads to somewhat icky looking autoconfiguration 59 * messages (one for every TTY, up to 64 per board!). So 60 * we don't do it that way, but assign minors as if there 61 * were the max of 64 ports per board. 62 * 63 * - We don't bother with PPS support here. There are so many 64 * ports, each with a large amount of buffer space, that the 65 * normal mode of operation is to poll the boards regularly 66 * (generally, every 20ms or so). This makes this driver 67 * unsuitable for PPS, as the latency will be generally too 68 * high. 69 */ 70 /* 71 * This driver inspired by the FreeBSD driver written by Brian J. McGovern 72 * for FreeBSD 3.2. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: cz.c,v 1.19 2002/03/17 19:40:59 atatat Exp $"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/proc.h> 81 #include <sys/device.h> 82 #include <sys/malloc.h> 83 #include <sys/tty.h> 84 #include <sys/conf.h> 85 #include <sys/time.h> 86 #include <sys/kernel.h> 87 #include <sys/fcntl.h> 88 #include <sys/syslog.h> 89 90 #include <sys/callout.h> 91 92 #include <dev/pci/pcireg.h> 93 #include <dev/pci/pcivar.h> 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/czreg.h> 96 97 #include <dev/pci/plx9060reg.h> 98 #include <dev/pci/plx9060var.h> 99 100 #include <dev/microcode/cyclades-z/cyzfirm.h> 101 102 #define CZ_DRIVER_VERSION 0x20000411 103 104 #define CZ_POLL_MS 20 105 106 /* These are the interrupts we always use. */ 107 #define CZ_INTERRUPTS \ 108 (C_IN_MDSR | C_IN_MRI | C_IN_MRTS | C_IN_MCTS | C_IN_TXBEMPTY | \ 109 C_IN_TXFEMPTY | C_IN_TXLOWWM | C_IN_RXHIWM | C_IN_RXNNDT | \ 110 C_IN_MDCD | C_IN_PR_ERROR | C_IN_FR_ERROR | C_IN_OVR_ERROR | \ 111 C_IN_RXOFL | C_IN_IOCTLW | C_IN_RXBRK) 112 113 /* 114 * cztty_softc: 115 * 116 * Per-channel (TTY) state. 117 */ 118 struct cztty_softc { 119 struct cz_softc *sc_parent; 120 struct tty *sc_tty; 121 122 struct callout sc_diag_ch; 123 124 int sc_channel; /* Also used to flag unattached chan */ 125 #define CZTTY_CHANNEL_DEAD -1 126 127 bus_space_tag_t sc_chan_st; /* channel space tag */ 128 bus_space_handle_t sc_chan_sh; /* channel space handle */ 129 bus_space_handle_t sc_buf_sh; /* buffer space handle */ 130 131 u_int sc_overflows, 132 sc_parity_errors, 133 sc_framing_errors, 134 sc_errors; 135 136 int sc_swflags; 137 138 u_int32_t sc_rs_control_dtr, 139 sc_chanctl_hw_flow, 140 sc_chanctl_comm_baud, 141 sc_chanctl_rs_control, 142 sc_chanctl_comm_data_l, 143 sc_chanctl_comm_parity; 144 }; 145 146 /* 147 * cz_softc: 148 * 149 * Per-board state. 150 */ 151 struct cz_softc { 152 struct device cz_dev; /* generic device info */ 153 struct plx9060_config cz_plx; /* PLX 9060 config info */ 154 bus_space_tag_t cz_win_st; /* window space tag */ 155 bus_space_handle_t cz_win_sh; /* window space handle */ 156 struct callout cz_callout; /* callout for polling-mode */ 157 158 void *cz_ih; /* interrupt handle */ 159 160 u_int32_t cz_mailbox0; /* our MAILBOX0 value */ 161 int cz_nchannels; /* number of channels */ 162 int cz_nopenchan; /* number of open channels */ 163 struct cztty_softc *cz_ports; /* our array of ports */ 164 165 bus_addr_t cz_fwctl; /* offset of firmware control */ 166 }; 167 168 int cz_match(struct device *, struct cfdata *, void *); 169 void cz_attach(struct device *, struct device *, void *); 170 int cz_wait_pci_doorbell(struct cz_softc *, const char *); 171 172 struct cfattach cz_ca = { 173 sizeof(struct cz_softc), cz_match, cz_attach 174 }; 175 176 void cz_reset_board(struct cz_softc *); 177 int cz_load_firmware(struct cz_softc *); 178 179 int cz_intr(void *); 180 void cz_poll(void *); 181 int cztty_transmit(struct cztty_softc *, struct tty *); 182 int cztty_receive(struct cztty_softc *, struct tty *); 183 184 struct cztty_softc * cztty_getttysoftc(dev_t dev); 185 int cztty_findmajor(void); 186 int cztty_major; 187 int cztty_attached_ttys; 188 int cz_timeout_ticks; 189 190 cdev_decl(cztty); 191 192 void czttystart(struct tty *tp); 193 int czttyparam(struct tty *tp, struct termios *t); 194 void cztty_shutdown(struct cztty_softc *sc); 195 void cztty_modem(struct cztty_softc *sc, int onoff); 196 void cztty_break(struct cztty_softc *sc, int onoff); 197 void tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits); 198 int cztty_to_tiocm(struct cztty_softc *sc); 199 void cztty_diag(void *arg); 200 201 extern struct cfdriver cz_cd; 202 203 /* Macros to clear/set/test flags. */ 204 #define SET(t, f) (t) |= (f) 205 #define CLR(t, f) (t) &= ~(f) 206 #define ISSET(t, f) ((t) & (f)) 207 208 /* 209 * Macros to read and write the PLX. 210 */ 211 #define CZ_PLX_READ(cz, reg) \ 212 bus_space_read_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, (reg)) 213 #define CZ_PLX_WRITE(cz, reg, val) \ 214 bus_space_write_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, \ 215 (reg), (val)) 216 217 /* 218 * Macros to read and write the FPGA. We must already be in the FPGA 219 * window for this. 220 */ 221 #define CZ_FPGA_READ(cz, reg) \ 222 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg)) 223 #define CZ_FPGA_WRITE(cz, reg, val) \ 224 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg), (val)) 225 226 /* 227 * Macros to read and write the firmware control structures in board RAM. 228 */ 229 #define CZ_FWCTL_READ(cz, off) \ 230 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 231 (cz)->cz_fwctl + (off)) 232 233 #define CZ_FWCTL_WRITE(cz, off, val) \ 234 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 235 (cz)->cz_fwctl + (off), (val)) 236 237 /* 238 * Convenience macros for cztty routines. PLX window MUST be to RAM. 239 */ 240 #define CZTTY_CHAN_READ(sc, off) \ 241 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_chan_sh, (off)) 242 243 #define CZTTY_CHAN_WRITE(sc, off, val) \ 244 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_chan_sh, \ 245 (off), (val)) 246 247 #define CZTTY_BUF_READ(sc, off) \ 248 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_buf_sh, (off)) 249 250 #define CZTTY_BUF_WRITE(sc, off, val) \ 251 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_buf_sh, \ 252 (off), (val)) 253 254 /* 255 * Convenience macros. 256 */ 257 #define CZ_WIN_RAM(cz) \ 258 do { \ 259 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_RAM); \ 260 delay(100); \ 261 } while (0) 262 263 #define CZ_WIN_FPGA(cz) \ 264 do { \ 265 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_FPGA); \ 266 delay(100); \ 267 } while (0) 268 269 /***************************************************************************** 270 * Cyclades-Z controller code starts here... 271 *****************************************************************************/ 272 273 /* 274 * cz_match: 275 * 276 * Determine if the given PCI device is a Cyclades-Z board. 277 */ 278 int 279 cz_match(struct device *parent, 280 struct cfdata *match, 281 void *aux) 282 { 283 struct pci_attach_args *pa = aux; 284 285 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYCLADES) { 286 switch (PCI_PRODUCT(pa->pa_id)) { 287 case PCI_PRODUCT_CYCLADES_CYCLOMZ_2: 288 return (1); 289 } 290 } 291 292 return (0); 293 } 294 295 /* 296 * cz_attach: 297 * 298 * A Cyclades-Z board was found; attach it. 299 */ 300 void 301 cz_attach(struct device *parent, 302 struct device *self, 303 void *aux) 304 { 305 struct cz_softc *cz = (void *) self; 306 struct pci_attach_args *pa = aux; 307 pci_intr_handle_t ih; 308 const char *intrstr = NULL; 309 struct cztty_softc *sc; 310 struct tty *tp; 311 int i; 312 313 printf(": Cyclades-Z multiport serial\n"); 314 315 cz->cz_plx.plx_pc = pa->pa_pc; 316 cz->cz_plx.plx_tag = pa->pa_tag; 317 318 if (pci_mapreg_map(pa, PLX_PCI_RUNTIME_MEMADDR, 319 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 320 &cz->cz_plx.plx_st, &cz->cz_plx.plx_sh, NULL, NULL) != 0) { 321 printf("%s: unable to map PLX registers\n", 322 cz->cz_dev.dv_xname); 323 return; 324 } 325 if (pci_mapreg_map(pa, PLX_PCI_LOCAL_ADDR0, 326 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 327 &cz->cz_win_st, &cz->cz_win_sh, NULL, NULL) != 0) { 328 printf("%s: unable to map device window\n", 329 cz->cz_dev.dv_xname); 330 return; 331 } 332 333 cz->cz_mailbox0 = CZ_PLX_READ(cz, PLX_MAILBOX0); 334 cz->cz_nopenchan = 0; 335 336 /* 337 * Make sure that the board is completely stopped. 338 */ 339 CZ_WIN_FPGA(cz); 340 CZ_FPGA_WRITE(cz, FPGA_CPU_STOP, 0); 341 342 /* 343 * Load the board's firmware. 344 */ 345 if (cz_load_firmware(cz) != 0) 346 return; 347 348 /* 349 * Now that we're ready to roll, map and establish the interrupt 350 * handler. 351 */ 352 if (pci_intr_map(pa, &ih) != 0) { 353 /* 354 * The common case is for Cyclades-Z boards to run 355 * in polling mode, and thus not have an interrupt 356 * mapped for them. Don't bother reporting that 357 * the interrupt is not mappable, since this isn't 358 * really an error. 359 */ 360 cz->cz_ih = NULL; 361 goto polling_mode; 362 } else { 363 intrstr = pci_intr_string(pa->pa_pc, ih); 364 cz->cz_ih = pci_intr_establish(pa->pa_pc, ih, IPL_TTY, 365 cz_intr, cz); 366 } 367 if (cz->cz_ih == NULL) { 368 printf("%s: unable to establish interrupt", 369 cz->cz_dev.dv_xname); 370 if (intrstr != NULL) 371 printf(" at %s", intrstr); 372 printf("\n"); 373 /* We will fall-back on polling mode. */ 374 } else 375 printf("%s: interrupting at %s\n", 376 cz->cz_dev.dv_xname, intrstr); 377 378 polling_mode: 379 if (cz->cz_ih == NULL) { 380 callout_init(&cz->cz_callout); 381 if (cz_timeout_ticks == 0) 382 cz_timeout_ticks = max(1, hz * CZ_POLL_MS / 1000); 383 printf("%s: polling mode, %d ms interval (%d tick%s)\n", 384 cz->cz_dev.dv_xname, CZ_POLL_MS, cz_timeout_ticks, 385 cz_timeout_ticks == 1 ? "" : "s"); 386 } 387 388 if (cztty_major == 0) 389 cztty_major = cztty_findmajor(); 390 /* 391 * Allocate sufficient pointers for the children and 392 * attach them. Set all ports to a reasonable initial 393 * configuration while we're at it: 394 * 395 * disabled 396 * 8N1 397 * default baud rate 398 * hardware flow control. 399 */ 400 CZ_WIN_RAM(cz); 401 402 if (cz->cz_nchannels == 0) { 403 /* No channels? No more work to do! */ 404 return; 405 } 406 407 cz->cz_ports = malloc(sizeof(struct cztty_softc) * cz->cz_nchannels, 408 M_DEVBUF, M_WAITOK|M_ZERO); 409 cztty_attached_ttys += cz->cz_nchannels; 410 411 for (i = 0; i < cz->cz_nchannels; i++) { 412 sc = &cz->cz_ports[i]; 413 414 sc->sc_channel = i; 415 sc->sc_chan_st = cz->cz_win_st; 416 sc->sc_parent = cz; 417 418 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 419 cz->cz_fwctl + ZFIRM_CHNCTL_OFF(i, 0), 420 ZFIRM_CHNCTL_SIZE, &sc->sc_chan_sh)) { 421 printf("%s: unable to subregion channel %d control\n", 422 cz->cz_dev.dv_xname, i); 423 sc->sc_channel = CZTTY_CHANNEL_DEAD; 424 continue; 425 } 426 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 427 cz->cz_fwctl + ZFIRM_BUFCTL_OFF(i, 0), 428 ZFIRM_BUFCTL_SIZE, &sc->sc_buf_sh)) { 429 printf("%s: unable to subregion channel %d buffer\n", 430 cz->cz_dev.dv_xname, i); 431 sc->sc_channel = CZTTY_CHANNEL_DEAD; 432 continue; 433 } 434 435 callout_init(&sc->sc_diag_ch); 436 437 tp = ttymalloc(); 438 tp->t_dev = makedev(cztty_major, 439 (cz->cz_dev.dv_unit * ZFIRM_MAX_CHANNELS) + i); 440 tp->t_oproc = czttystart; 441 tp->t_param = czttyparam; 442 tty_attach(tp); 443 444 sc->sc_tty = tp; 445 446 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 447 CZTTY_CHAN_WRITE(sc, CHNCTL_INTR_ENABLE, CZ_INTERRUPTS); 448 CZTTY_CHAN_WRITE(sc, CHNCTL_SW_FLOW, 0); 449 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XON, 0x11); 450 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XOFF, 0x13); 451 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, TTYDEF_SPEED); 452 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, C_PR_NONE); 453 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, C_DL_CS8 | C_DL_1STOP); 454 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_FLAGS, 0); 455 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, C_RS_CTS | C_RS_RTS); 456 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, 0); 457 } 458 } 459 460 /* 461 * cz_reset_board: 462 * 463 * Reset the board via the PLX. 464 */ 465 void 466 cz_reset_board(struct cz_softc *cz) 467 { 468 u_int32_t reg; 469 470 reg = CZ_PLX_READ(cz, PLX_CONTROL); 471 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_SWR); 472 delay(1000); 473 474 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 475 delay(1000); 476 477 /* Now reload the PLX from its EEPROM. */ 478 reg = CZ_PLX_READ(cz, PLX_CONTROL); 479 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_RELOADCFG); 480 delay(1000); 481 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 482 } 483 484 /* 485 * cz_load_firmware: 486 * 487 * Load the ZFIRM firmware into the board's RAM and start it 488 * running. 489 */ 490 int 491 cz_load_firmware(struct cz_softc *cz) 492 { 493 struct zfirm_header *zfh; 494 struct zfirm_config *zfc; 495 struct zfirm_block *zfb, *zblocks; 496 const u_int8_t *cp; 497 const char *board; 498 u_int32_t fid; 499 int i, j, nconfigs, nblocks, nbytes; 500 501 zfh = (struct zfirm_header *) cycladesz_firmware; 502 503 /* Find the config header. */ 504 if (le32toh(zfh->zfh_configoff) & (sizeof(u_int32_t) - 1)) { 505 printf("%s: bad ZFIRM config offset: 0x%x\n", 506 cz->cz_dev.dv_xname, le32toh(zfh->zfh_configoff)); 507 return (EIO); 508 } 509 zfc = (struct zfirm_config *)(cycladesz_firmware + 510 le32toh(zfh->zfh_configoff)); 511 nconfigs = le32toh(zfh->zfh_nconfig); 512 513 /* Locate the correct configuration for our board. */ 514 for (i = 0; i < nconfigs; i++, zfc++) { 515 if (le32toh(zfc->zfc_mailbox) == cz->cz_mailbox0 && 516 le32toh(zfc->zfc_function) == ZFC_FUNCTION_NORMAL) 517 break; 518 } 519 if (i == nconfigs) { 520 printf("%s: unable to locate config header\n", 521 cz->cz_dev.dv_xname); 522 return (EIO); 523 } 524 525 nblocks = le32toh(zfc->zfc_nblocks); 526 zblocks = (struct zfirm_block *)(cycladesz_firmware + 527 le32toh(zfh->zfh_blockoff)); 528 529 /* 530 * 8Zo ver. 1 doesn't have an FPGA. Load it on all others if 531 * necessary. 532 */ 533 if (cz->cz_mailbox0 != MAILBOX0_8Zo_V1 534 #if 0 535 && ((CZ_PLX_READ(cz, PLX_CONTROL) & CONTROL_FPGA_LOADED) == 0) 536 #endif 537 ) { 538 #ifdef CZ_DEBUG 539 printf("%s: Loading FPGA...", cz->cz_dev.dv_xname); 540 #endif 541 CZ_WIN_FPGA(cz); 542 for (i = 0; i < nblocks; i++) { 543 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 544 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 545 if (le32toh(zfb->zfb_type) == ZFB_TYPE_FPGA) { 546 nbytes = le32toh(zfb->zfb_size); 547 cp = &cycladesz_firmware[ 548 le32toh(zfb->zfb_fileoff)]; 549 for (j = 0; j < nbytes; j++, cp++) { 550 bus_space_write_1(cz->cz_win_st, 551 cz->cz_win_sh, 0, *cp); 552 /* FPGA needs 30-100us to settle. */ 553 delay(10); 554 } 555 } 556 } 557 #ifdef CZ_DEBUG 558 printf("done\n"); 559 #endif 560 } 561 562 /* Now load the firmware. */ 563 CZ_WIN_RAM(cz); 564 565 for (i = 0; i < nblocks; i++) { 566 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 567 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 568 if (le32toh(zfb->zfb_type) == ZFB_TYPE_FIRMWARE) { 569 const u_int32_t *lp; 570 u_int32_t ro = le32toh(zfb->zfb_ramoff); 571 nbytes = le32toh(zfb->zfb_size); 572 lp = (const u_int32_t *) 573 &cycladesz_firmware[le32toh(zfb->zfb_fileoff)]; 574 for (j = 0; j < nbytes; j += 4, lp++) { 575 bus_space_write_4(cz->cz_win_st, cz->cz_win_sh, 576 ro + j, le32toh(*lp)); 577 delay(10); 578 } 579 } 580 } 581 582 /* Now restart the MIPS. */ 583 CZ_WIN_FPGA(cz); 584 CZ_FPGA_WRITE(cz, FPGA_CPU_START, 0); 585 586 /* Wait for the MIPS to start, then report the results. */ 587 CZ_WIN_RAM(cz); 588 589 #ifdef CZ_DEBUG 590 printf("%s: waiting for MIPS to start", cz->cz_dev.dv_xname); 591 #endif 592 for (i = 0; i < 100; i++) { 593 fid = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 594 ZFIRM_SIG_OFF); 595 if (fid == ZFIRM_SIG) { 596 /* MIPS has booted. */ 597 break; 598 } else if (fid == ZFIRM_HLT) { 599 /* 600 * The MIPS has halted, usually due to a power 601 * shortage on the expansion module. 602 */ 603 printf("%s: MIPS halted; possible power supply " 604 "problem\n", cz->cz_dev.dv_xname); 605 return (EIO); 606 } else { 607 #ifdef CZ_DEBUG 608 if ((i % 8) == 0) 609 printf("."); 610 #endif 611 delay(250000); 612 } 613 } 614 #ifdef CZ_DEBUG 615 printf("\n"); 616 #endif 617 if (i == 100) { 618 CZ_WIN_FPGA(cz); 619 printf("%s: MIPS failed to start; wanted 0x%08x got 0x%08x\n", 620 cz->cz_dev.dv_xname, ZFIRM_SIG, fid); 621 printf("%s: FPGA ID 0x%08x, FPGA version 0x%08x\n", 622 cz->cz_dev.dv_xname, CZ_FPGA_READ(cz, FPGA_ID), 623 CZ_FPGA_READ(cz, FPGA_VERSION)); 624 return (EIO); 625 } 626 627 /* 628 * Locate the firmware control structures. 629 */ 630 cz->cz_fwctl = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 631 ZFIRM_CTRLADDR_OFF); 632 #ifdef CZ_DEBUG 633 printf("%s: FWCTL structure at offset 0x%08lx\n", 634 cz->cz_dev.dv_xname, cz->cz_fwctl); 635 #endif 636 637 CZ_FWCTL_WRITE(cz, BRDCTL_C_OS, C_OS_BSD); 638 CZ_FWCTL_WRITE(cz, BRDCTL_DRVERSION, CZ_DRIVER_VERSION); 639 640 cz->cz_nchannels = CZ_FWCTL_READ(cz, BRDCTL_NCHANNEL); 641 642 switch (cz->cz_mailbox0) { 643 case MAILBOX0_8Zo_V1: 644 board = "Cyclades-8Zo ver. 1"; 645 break; 646 647 case MAILBOX0_8Zo_V2: 648 board = "Cyclades-8Zo ver. 2"; 649 break; 650 651 case MAILBOX0_Ze_V1: 652 board = "Cyclades-Ze"; 653 break; 654 655 default: 656 board = "unknown Cyclades Z-series"; 657 break; 658 } 659 660 fid = CZ_FWCTL_READ(cz, BRDCTL_FWVERSION); 661 printf("%s: %s, ", cz->cz_dev.dv_xname, board); 662 if (cz->cz_nchannels == 0) 663 printf("no channels attached, "); 664 else 665 printf("%d channels (ttyCZ%04d..ttyCZ%04d), ", 666 cz->cz_nchannels, cztty_attached_ttys, 667 cztty_attached_ttys + (cz->cz_nchannels - 1)); 668 printf("firmware %x.%x.%x\n", 669 (fid >> 8) & 0xf, (fid >> 4) & 0xf, fid & 0xf); 670 671 return (0); 672 } 673 674 /* 675 * cz_poll: 676 * 677 * This card doesn't do interrupts, so scan it for activity every CZ_POLL_MS 678 * ms. 679 */ 680 void 681 cz_poll(void *arg) 682 { 683 int s = spltty(); 684 struct cz_softc *cz = arg; 685 686 cz_intr(cz); 687 callout_reset(&cz->cz_callout, cz_timeout_ticks, cz_poll, cz); 688 689 splx(s); 690 } 691 692 /* 693 * cz_intr: 694 * 695 * Interrupt service routine. 696 * 697 * We either are receiving an interrupt directly from the board, or we are 698 * in polling mode and it's time to poll. 699 */ 700 int 701 cz_intr(void *arg) 702 { 703 int rval = 0; 704 u_int command, channel, param; 705 struct cz_softc *cz = arg; 706 struct cztty_softc *sc; 707 struct tty *tp; 708 709 while ((command = (CZ_PLX_READ(cz, PLX_LOCAL_PCI_DOORBELL) & 0xff))) { 710 rval = 1; 711 channel = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_CHANNEL); 712 param = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_PARAM); 713 714 /* now clear this interrupt, posslibly enabling another */ 715 CZ_PLX_WRITE(cz, PLX_LOCAL_PCI_DOORBELL, command); 716 717 if (cz->cz_ports == NULL) { 718 #ifdef CZ_DEBUG 719 printf("%s: interrupt on channel %d, but no channels\n", 720 cz->cz_dev.dv_xname, channel); 721 #endif 722 continue; 723 } 724 725 sc = &cz->cz_ports[channel]; 726 727 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 728 break; 729 730 tp = sc->sc_tty; 731 732 switch (command) { 733 case C_CM_TXFEMPTY: /* transmit cases */ 734 case C_CM_TXBEMPTY: 735 case C_CM_TXLOWWM: 736 case C_CM_INTBACK: 737 if (!ISSET(tp->t_state, TS_ISOPEN)) { 738 #ifdef CZ_DEBUG 739 printf("%s: tx intr on closed channel %d\n", 740 cz->cz_dev.dv_xname, channel); 741 #endif 742 break; 743 } 744 745 if (cztty_transmit(sc, tp)) { 746 /* 747 * Do wakeup stuff here. 748 */ 749 ttwakeup(tp); 750 wakeup(tp); 751 } 752 break; 753 754 case C_CM_RXNNDT: /* receive cases */ 755 case C_CM_RXHIWM: 756 case C_CM_INTBACK2: /* from restart ?? */ 757 #if 0 758 case C_CM_ICHAR: 759 #endif 760 if (!ISSET(tp->t_state, TS_ISOPEN)) { 761 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 762 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 763 break; 764 } 765 766 if (cztty_receive(sc, tp)) { 767 /* 768 * Do wakeup stuff here. 769 */ 770 ttwakeup(tp); 771 wakeup(tp); 772 } 773 break; 774 775 case C_CM_MDCD: 776 if (!ISSET(tp->t_state, TS_ISOPEN)) 777 break; 778 779 (void) (*tp->t_linesw->l_modem)(tp, 780 ISSET(C_RS_DCD, CZTTY_CHAN_READ(sc, 781 CHNCTL_RS_STATUS))); 782 break; 783 784 case C_CM_MDSR: 785 case C_CM_MRI: 786 case C_CM_MCTS: 787 case C_CM_MRTS: 788 break; 789 790 case C_CM_IOCTLW: 791 break; 792 793 case C_CM_PR_ERROR: 794 sc->sc_parity_errors++; 795 goto error_common; 796 797 case C_CM_FR_ERROR: 798 sc->sc_framing_errors++; 799 goto error_common; 800 801 case C_CM_OVR_ERROR: 802 sc->sc_overflows++; 803 error_common: 804 if (sc->sc_errors++ == 0) 805 callout_reset(&sc->sc_diag_ch, 60 * hz, 806 cztty_diag, sc); 807 break; 808 809 case C_CM_RXBRK: 810 if (!ISSET(tp->t_state, TS_ISOPEN)) 811 break; 812 813 /* 814 * A break is a \000 character with TTY_FE error 815 * flags set. So TTY_FE by itself works. 816 */ 817 (*tp->t_linesw->l_rint)(TTY_FE, tp); 818 ttwakeup(tp); 819 wakeup(tp); 820 break; 821 822 default: 823 #ifdef CZ_DEBUG 824 printf("%s: channel %d: Unknown interrupt 0x%x\n", 825 cz->cz_dev.dv_xname, sc->sc_channel, command); 826 #endif 827 break; 828 } 829 } 830 831 return (rval); 832 } 833 834 /* 835 * cz_wait_pci_doorbell: 836 * 837 * Wait for the pci doorbell to be clear - wait for pending 838 * activity to drain. 839 */ 840 int 841 cz_wait_pci_doorbell(struct cz_softc *cz, const char *wstring) 842 { 843 int error; 844 845 while (CZ_PLX_READ(cz, PLX_PCI_LOCAL_DOORBELL)) { 846 error = tsleep(cz, TTIPRI | PCATCH, wstring, max(1, hz/100)); 847 if ((error != 0) && (error != EWOULDBLOCK)) 848 return (error); 849 } 850 return (0); 851 } 852 853 /***************************************************************************** 854 * Cyclades-Z TTY code starts here... 855 *****************************************************************************/ 856 857 #define CZTTYDIALOUT_MASK 0x80000 858 859 #define CZTTY_DIALOUT(dev) (minor((dev)) & CZTTYDIALOUT_MASK) 860 #define CZTTY_CZ(sc) ((sc)->sc_parent) 861 862 #define CZTTY_SOFTC(dev) cztty_getttysoftc(dev) 863 864 struct cztty_softc * 865 cztty_getttysoftc(dev_t dev) 866 { 867 int i, j, k, u = minor(dev) & ~CZTTYDIALOUT_MASK; 868 struct cz_softc *cz; 869 870 for (i = 0, j = 0; i < cz_cd.cd_ndevs; i++) { 871 k = j; 872 cz = device_lookup(&cz_cd, i); 873 if (cz == NULL) 874 continue; 875 if (cz->cz_ports == NULL) 876 continue; 877 j += cz->cz_nchannels; 878 if (j > u) 879 break; 880 } 881 882 if (i >= cz_cd.cd_ndevs) 883 return (NULL); 884 else 885 return (&cz->cz_ports[u - k]); 886 } 887 888 int 889 cztty_findmajor(void) 890 { 891 int maj; 892 893 for (maj = 0; maj < nchrdev; maj++) { 894 if (cdevsw[maj].d_open == czttyopen) 895 break; 896 } 897 898 return (maj == nchrdev) ? 0 : maj; 899 } 900 901 /* 902 * czttytty: 903 * 904 * Return a pointer to our tty. 905 */ 906 struct tty * 907 czttytty(dev_t dev) 908 { 909 struct cztty_softc *sc = CZTTY_SOFTC(dev); 910 911 #ifdef DIAGNOSTIC 912 if (sc == NULL) 913 panic("czttytty"); 914 #endif 915 916 return (sc->sc_tty); 917 } 918 919 /* 920 * cztty_shutdown: 921 * 922 * Shut down a port. 923 */ 924 void 925 cztty_shutdown(struct cztty_softc *sc) 926 { 927 struct cz_softc *cz = CZTTY_CZ(sc); 928 struct tty *tp = sc->sc_tty; 929 int s; 930 931 s = spltty(); 932 933 /* Clear any break condition set with TIOCSBRK. */ 934 cztty_break(sc, 0); 935 936 /* 937 * Hang up if necessary. Wait a bit, so the other side has time to 938 * notice even if we immediately open the port again. 939 */ 940 if (ISSET(tp->t_cflag, HUPCL)) { 941 cztty_modem(sc, 0); 942 (void) tsleep(tp, TTIPRI, ttclos, hz); 943 } 944 945 /* Disable the channel. */ 946 cz_wait_pci_doorbell(cz, "czdis"); 947 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 948 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 949 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTL); 950 951 if ((--cz->cz_nopenchan == 0) && (cz->cz_ih == NULL)) { 952 #ifdef CZ_DEBUG 953 printf("%s: Disabling polling\n", cz->cz_dev.dv_xname); 954 #endif 955 callout_stop(&cz->cz_callout); 956 } 957 958 splx(s); 959 } 960 961 /* 962 * czttyopen: 963 * 964 * Open a Cyclades-Z serial port. 965 */ 966 int 967 czttyopen(dev_t dev, int flags, int mode, struct proc *p) 968 { 969 struct cztty_softc *sc = CZTTY_SOFTC(dev); 970 struct cz_softc *cz; 971 struct tty *tp; 972 int s, error; 973 974 if (sc == NULL) 975 return (ENXIO); 976 977 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 978 return (ENXIO); 979 980 cz = CZTTY_CZ(sc); 981 tp = sc->sc_tty; 982 983 if (ISSET(tp->t_state, TS_ISOPEN) && 984 ISSET(tp->t_state, TS_XCLUDE) && 985 p->p_ucred->cr_uid != 0) 986 return (EBUSY); 987 988 s = spltty(); 989 990 /* 991 * Do the following iff this is a first open. 992 */ 993 if (!ISSET(tp->t_state, TS_ISOPEN) && (tp->t_wopen == 0)) { 994 struct termios t; 995 996 tp->t_dev = dev; 997 998 /* If we're turning things on, enable interrupts */ 999 if ((cz->cz_nopenchan++ == 0) && (cz->cz_ih == NULL)) { 1000 #ifdef CZ_DEBUG 1001 printf("%s: Enabling polling.\n", 1002 cz->cz_dev.dv_xname); 1003 #endif 1004 callout_reset(&cz->cz_callout, cz_timeout_ticks, 1005 cz_poll, cz); 1006 } 1007 1008 /* 1009 * Enable the channel. Don't actually ring the 1010 * doorbell here; czttyparam() will do it for us. 1011 */ 1012 cz_wait_pci_doorbell(cz, "czopen"); 1013 1014 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_ENABLE); 1015 1016 /* 1017 * Initialize the termios status to the defaults. Add in the 1018 * sticky bits from TIOCSFLAGS. 1019 */ 1020 t.c_ispeed = 0; 1021 t.c_ospeed = TTYDEF_SPEED; 1022 t.c_cflag = TTYDEF_CFLAG; 1023 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1024 SET(t.c_cflag, CLOCAL); 1025 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1026 SET(t.c_cflag, CRTSCTS); 1027 1028 /* 1029 * Reset the input and output rings. Do this before 1030 * we call czttyparam(), as that function enables 1031 * the channel. 1032 */ 1033 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 1034 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 1035 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, 1036 CZTTY_BUF_READ(sc, BUFCTL_TX_GET)); 1037 1038 /* Make sure czttyparam() will see changes. */ 1039 tp->t_ospeed = 0; 1040 (void) czttyparam(tp, &t); 1041 tp->t_iflag = TTYDEF_IFLAG; 1042 tp->t_oflag = TTYDEF_OFLAG; 1043 tp->t_lflag = TTYDEF_LFLAG; 1044 ttychars(tp); 1045 ttsetwater(tp); 1046 1047 /* 1048 * Turn on DTR. We must always do this, even if carrier is not 1049 * present, because otherwise we'd have to use TIOCSDTR 1050 * immediately after setting CLOCAL, which applications do not 1051 * expect. We always assert DTR while the device is open 1052 * unless explicitly requested to deassert it. 1053 */ 1054 cztty_modem(sc, 1); 1055 } 1056 1057 splx(s); 1058 1059 error = ttyopen(tp, CZTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK)); 1060 if (error) 1061 goto bad; 1062 1063 error = (*tp->t_linesw->l_open)(dev, tp); 1064 if (error) 1065 goto bad; 1066 1067 return (0); 1068 1069 bad: 1070 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1071 /* 1072 * We failed to open the device, and nobody else had it opened. 1073 * Clean up the state as appropriate. 1074 */ 1075 cztty_shutdown(sc); 1076 } 1077 1078 return (error); 1079 } 1080 1081 /* 1082 * czttyclose: 1083 * 1084 * Close a Cyclades-Z serial port. 1085 */ 1086 int 1087 czttyclose(dev_t dev, int flags, int mode, struct proc *p) 1088 { 1089 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1090 struct tty *tp = sc->sc_tty; 1091 1092 /* XXX This is for cons.c. */ 1093 if (!ISSET(tp->t_state, TS_ISOPEN)) 1094 return (0); 1095 1096 (*tp->t_linesw->l_close)(tp, flags); 1097 ttyclose(tp); 1098 1099 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1100 /* 1101 * Although we got a last close, the device may still be in 1102 * use; e.g. if this was the dialout node, and there are still 1103 * processes waiting for carrier on the non-dialout node. 1104 */ 1105 cztty_shutdown(sc); 1106 } 1107 1108 return (0); 1109 } 1110 1111 /* 1112 * czttyread: 1113 * 1114 * Read from a Cyclades-Z serial port. 1115 */ 1116 int 1117 czttyread(dev_t dev, struct uio *uio, int flags) 1118 { 1119 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1120 struct tty *tp = sc->sc_tty; 1121 1122 return ((*tp->t_linesw->l_read)(tp, uio, flags)); 1123 } 1124 1125 /* 1126 * czttywrite: 1127 * 1128 * Write to a Cyclades-Z serial port. 1129 */ 1130 int 1131 czttywrite(dev_t dev, struct uio *uio, int flags) 1132 { 1133 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1134 struct tty *tp = sc->sc_tty; 1135 1136 return ((*tp->t_linesw->l_write)(tp, uio, flags)); 1137 } 1138 1139 /* 1140 * czttypoll: 1141 * 1142 * Poll a Cyclades-Z serial port. 1143 */ 1144 int 1145 czttypoll(dev, events, p) 1146 dev_t dev; 1147 int events; 1148 struct proc *p; 1149 { 1150 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1151 struct tty *tp = sc->sc_tty; 1152 1153 return ((*tp->t_linesw->l_poll)(tp, events, p)); 1154 } 1155 1156 /* 1157 * czttyioctl: 1158 * 1159 * Perform a control operation on a Cyclades-Z serial port. 1160 */ 1161 int 1162 czttyioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 1163 { 1164 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1165 struct tty *tp = sc->sc_tty; 1166 int s, error; 1167 1168 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p); 1169 if (error != EPASSTHROUGH) 1170 return (error); 1171 1172 error = ttioctl(tp, cmd, data, flag, p); 1173 if (error != EPASSTHROUGH) 1174 return (error); 1175 1176 error = 0; 1177 1178 s = spltty(); 1179 1180 switch (cmd) { 1181 case TIOCSBRK: 1182 cztty_break(sc, 1); 1183 break; 1184 1185 case TIOCCBRK: 1186 cztty_break(sc, 0); 1187 break; 1188 1189 case TIOCGFLAGS: 1190 *(int *)data = sc->sc_swflags; 1191 break; 1192 1193 case TIOCSFLAGS: 1194 error = suser(p->p_ucred, &p->p_acflag); 1195 if (error) 1196 break; 1197 sc->sc_swflags = *(int *)data; 1198 break; 1199 1200 case TIOCSDTR: 1201 cztty_modem(sc, 1); 1202 break; 1203 1204 case TIOCCDTR: 1205 cztty_modem(sc, 0); 1206 break; 1207 1208 case TIOCMSET: 1209 case TIOCMBIS: 1210 case TIOCMBIC: 1211 tiocm_to_cztty(sc, cmd, *(int *)data); 1212 break; 1213 1214 case TIOCMGET: 1215 *(int *)data = cztty_to_tiocm(sc); 1216 break; 1217 1218 default: 1219 error = EPASSTHROUGH; 1220 break; 1221 } 1222 1223 splx(s); 1224 1225 return (error); 1226 } 1227 1228 /* 1229 * cztty_break: 1230 * 1231 * Set or clear BREAK on a port. 1232 */ 1233 void 1234 cztty_break(struct cztty_softc *sc, int onoff) 1235 { 1236 struct cz_softc *cz = CZTTY_CZ(sc); 1237 1238 cz_wait_pci_doorbell(cz, "czbreak"); 1239 1240 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1241 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, 1242 onoff ? C_CM_SET_BREAK : C_CM_CLR_BREAK); 1243 } 1244 1245 /* 1246 * cztty_modem: 1247 * 1248 * Set or clear DTR on a port. 1249 */ 1250 void 1251 cztty_modem(struct cztty_softc *sc, int onoff) 1252 { 1253 struct cz_softc *cz = CZTTY_CZ(sc); 1254 1255 if (sc->sc_rs_control_dtr == 0) 1256 return; 1257 1258 cz_wait_pci_doorbell(cz, "czmod"); 1259 1260 if (onoff) 1261 sc->sc_chanctl_rs_control |= sc->sc_rs_control_dtr; 1262 else 1263 sc->sc_chanctl_rs_control &= ~sc->sc_rs_control_dtr; 1264 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1265 1266 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1267 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1268 } 1269 1270 /* 1271 * tiocm_to_cztty: 1272 * 1273 * Process TIOCM* ioctls. 1274 */ 1275 void 1276 tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits) 1277 { 1278 struct cz_softc *cz = CZTTY_CZ(sc); 1279 u_int32_t czttybits; 1280 1281 czttybits = 0; 1282 if (ISSET(ttybits, TIOCM_DTR)) 1283 SET(czttybits, C_RS_DTR); 1284 if (ISSET(ttybits, TIOCM_RTS)) 1285 SET(czttybits, C_RS_RTS); 1286 1287 cz_wait_pci_doorbell(cz, "cztiocm"); 1288 1289 switch (how) { 1290 case TIOCMBIC: 1291 CLR(sc->sc_chanctl_rs_control, czttybits); 1292 break; 1293 1294 case TIOCMBIS: 1295 SET(sc->sc_chanctl_rs_control, czttybits); 1296 break; 1297 1298 case TIOCMSET: 1299 CLR(sc->sc_chanctl_rs_control, C_RS_DTR | C_RS_RTS); 1300 SET(sc->sc_chanctl_rs_control, czttybits); 1301 break; 1302 } 1303 1304 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1305 1306 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1307 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1308 } 1309 1310 /* 1311 * cztty_to_tiocm: 1312 * 1313 * Process the TIOCMGET ioctl. 1314 */ 1315 int 1316 cztty_to_tiocm(struct cztty_softc *sc) 1317 { 1318 struct cz_softc *cz = CZTTY_CZ(sc); 1319 u_int32_t rs_status, op_mode; 1320 int ttybits = 0; 1321 1322 cz_wait_pci_doorbell(cz, "cztty"); 1323 1324 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1325 op_mode = CZTTY_CHAN_READ(sc, CHNCTL_OP_MODE); 1326 1327 if (ISSET(rs_status, C_RS_RTS)) 1328 SET(ttybits, TIOCM_RTS); 1329 if (ISSET(rs_status, C_RS_CTS)) 1330 SET(ttybits, TIOCM_CTS); 1331 if (ISSET(rs_status, C_RS_DCD)) 1332 SET(ttybits, TIOCM_CAR); 1333 if (ISSET(rs_status, C_RS_DTR)) 1334 SET(ttybits, TIOCM_DTR); 1335 if (ISSET(rs_status, C_RS_RI)) 1336 SET(ttybits, TIOCM_RNG); 1337 if (ISSET(rs_status, C_RS_DSR)) 1338 SET(ttybits, TIOCM_DSR); 1339 1340 if (ISSET(op_mode, C_CH_ENABLE)) 1341 SET(ttybits, TIOCM_LE); 1342 1343 return (ttybits); 1344 } 1345 1346 /* 1347 * czttyparam: 1348 * 1349 * Set Cyclades-Z serial port parameters from termios. 1350 * 1351 * XXX Should just copy the whole termios after making 1352 * XXX sure all the changes could be done. 1353 */ 1354 int 1355 czttyparam(struct tty *tp, struct termios *t) 1356 { 1357 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1358 struct cz_softc *cz = CZTTY_CZ(sc); 1359 u_int32_t rs_status; 1360 int ospeed, cflag; 1361 1362 ospeed = t->c_ospeed; 1363 cflag = t->c_cflag; 1364 1365 /* Check requested parameters. */ 1366 if (ospeed < 0) 1367 return (EINVAL); 1368 if (t->c_ispeed && t->c_ispeed != ospeed) 1369 return (EINVAL); 1370 1371 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR)) { 1372 SET(cflag, CLOCAL); 1373 CLR(cflag, HUPCL); 1374 } 1375 1376 /* 1377 * If there were no changes, don't do anything. This avoids dropping 1378 * input and improves performance when all we did was frob things like 1379 * VMIN and VTIME. 1380 */ 1381 if (tp->t_ospeed == ospeed && 1382 tp->t_cflag == cflag) 1383 return (0); 1384 1385 /* Data bits. */ 1386 sc->sc_chanctl_comm_data_l = 0; 1387 switch (t->c_cflag & CSIZE) { 1388 case CS5: 1389 sc->sc_chanctl_comm_data_l |= C_DL_CS5; 1390 break; 1391 1392 case CS6: 1393 sc->sc_chanctl_comm_data_l |= C_DL_CS6; 1394 break; 1395 1396 case CS7: 1397 sc->sc_chanctl_comm_data_l |= C_DL_CS7; 1398 break; 1399 1400 case CS8: 1401 sc->sc_chanctl_comm_data_l |= C_DL_CS8; 1402 break; 1403 } 1404 1405 /* Stop bits. */ 1406 if (t->c_cflag & CSTOPB) { 1407 if ((sc->sc_chanctl_comm_data_l & C_DL_CS) == C_DL_CS5) 1408 sc->sc_chanctl_comm_data_l |= C_DL_15STOP; 1409 else 1410 sc->sc_chanctl_comm_data_l |= C_DL_2STOP; 1411 } else 1412 sc->sc_chanctl_comm_data_l |= C_DL_1STOP; 1413 1414 /* Parity. */ 1415 if (t->c_cflag & PARENB) { 1416 if (t->c_cflag & PARODD) 1417 sc->sc_chanctl_comm_parity = C_PR_ODD; 1418 else 1419 sc->sc_chanctl_comm_parity = C_PR_EVEN; 1420 } else 1421 sc->sc_chanctl_comm_parity = C_PR_NONE; 1422 1423 /* 1424 * Initialize flow control pins depending on the current flow control 1425 * mode. 1426 */ 1427 if (ISSET(t->c_cflag, CRTSCTS)) { 1428 sc->sc_rs_control_dtr = C_RS_DTR; 1429 sc->sc_chanctl_hw_flow = C_RS_CTS | C_RS_RTS; 1430 } else if (ISSET(t->c_cflag, MDMBUF)) { 1431 sc->sc_rs_control_dtr = 0; 1432 sc->sc_chanctl_hw_flow = C_RS_DCD | C_RS_DTR; 1433 } else { 1434 /* 1435 * If no flow control, then always set RTS. This will make 1436 * the other side happy if it mistakenly thinks we're doing 1437 * RTS/CTS flow control. 1438 */ 1439 sc->sc_rs_control_dtr = C_RS_DTR | C_RS_RTS; 1440 sc->sc_chanctl_hw_flow = 0; 1441 if (ISSET(sc->sc_chanctl_rs_control, C_RS_DTR)) 1442 SET(sc->sc_chanctl_rs_control, C_RS_RTS); 1443 else 1444 CLR(sc->sc_chanctl_rs_control, C_RS_RTS); 1445 } 1446 1447 /* Baud rate. */ 1448 sc->sc_chanctl_comm_baud = ospeed; 1449 1450 /* Copy to tty. */ 1451 tp->t_ispeed = 0; 1452 tp->t_ospeed = t->c_ospeed; 1453 tp->t_cflag = t->c_cflag; 1454 1455 /* 1456 * Now load the channel control structure. 1457 */ 1458 1459 cz_wait_pci_doorbell(cz, "czparam"); 1460 1461 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, sc->sc_chanctl_comm_baud); 1462 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, sc->sc_chanctl_comm_data_l); 1463 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, sc->sc_chanctl_comm_parity); 1464 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, sc->sc_chanctl_hw_flow); 1465 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1466 1467 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1468 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLW); 1469 1470 cz_wait_pci_doorbell(cz, "czparam"); 1471 1472 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1473 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1474 1475 cz_wait_pci_doorbell(cz, "czparam"); 1476 1477 /* 1478 * Update the tty layer's idea of the carrier bit, in case we changed 1479 * CLOCAL. We don't hang up here; we only do that by explicit 1480 * request. 1481 */ 1482 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1483 (void) (*tp->t_linesw->l_modem)(tp, ISSET(rs_status, C_RS_DCD)); 1484 1485 return (0); 1486 } 1487 1488 /* 1489 * czttystart: 1490 * 1491 * Start or restart transmission. 1492 */ 1493 void 1494 czttystart(struct tty *tp) 1495 { 1496 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1497 int s; 1498 1499 s = spltty(); 1500 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1501 goto out; 1502 1503 if (tp->t_outq.c_cc <= tp->t_lowat) { 1504 if (ISSET(tp->t_state, TS_ASLEEP)) { 1505 CLR(tp->t_state, TS_ASLEEP); 1506 wakeup(&tp->t_outq); 1507 } 1508 selwakeup(&tp->t_wsel); 1509 if (tp->t_outq.c_cc == 0) 1510 goto out; 1511 } 1512 1513 cztty_transmit(sc, tp); 1514 out: 1515 splx(s); 1516 } 1517 1518 /* 1519 * czttystop: 1520 * 1521 * Stop output, e.g., for ^S or output flush. 1522 */ 1523 void 1524 czttystop(struct tty *tp, int flag) 1525 { 1526 1527 /* 1528 * XXX We don't do anything here, yet. Mostly, I don't know 1529 * XXX exactly how this should be implemented on this device. 1530 * XXX We've given a big chunk of data to the MIPS already, 1531 * XXX and I don't know how we request the MIPS to stop sending 1532 * XXX the data. So, punt for now. --thorpej 1533 */ 1534 } 1535 1536 /* 1537 * cztty_diag: 1538 * 1539 * Issue a scheduled diagnostic message. 1540 */ 1541 void 1542 cztty_diag(void *arg) 1543 { 1544 struct cztty_softc *sc = arg; 1545 struct cz_softc *cz = CZTTY_CZ(sc); 1546 u_int overflows, parity_errors, framing_errors; 1547 int s; 1548 1549 s = spltty(); 1550 1551 overflows = sc->sc_overflows; 1552 sc->sc_overflows = 0; 1553 1554 parity_errors = sc->sc_parity_errors; 1555 sc->sc_parity_errors = 0; 1556 1557 framing_errors = sc->sc_framing_errors; 1558 sc->sc_framing_errors = 0; 1559 1560 sc->sc_errors = 0; 1561 1562 splx(s); 1563 1564 log(LOG_WARNING, 1565 "%s: channel %d: %u overflow%s, %u parity, %u framing error%s\n", 1566 cz->cz_dev.dv_xname, sc->sc_channel, 1567 overflows, overflows == 1 ? "" : "s", 1568 parity_errors, 1569 framing_errors, framing_errors == 1 ? "" : "s"); 1570 } 1571 1572 /* 1573 * tx and rx ring buffer size macros: 1574 * 1575 * The transmitter and receiver both use ring buffers. For each one, there 1576 * is a get (consumer) and a put (producer) offset. The get value is the 1577 * next byte to be read from the ring, and the put is the next one to be 1578 * put into the ring. get == put means the ring is empty. 1579 * 1580 * For each ring, the firmware controls one of (get, put) and this driver 1581 * controls the other. For transmission, this driver updates put to point 1582 * past the valid data, and the firmware moves get as bytes are sent. Likewise 1583 * for receive, the driver controls put, and this driver controls get. 1584 */ 1585 #define TX_MOVEABLE(g, p, s) (((g) > (p)) ? ((g) - (p) - 1) : ((s) - (p))) 1586 #define RX_MOVEABLE(g, p, s) (((g) > (p)) ? ((s) - (g)) : ((p) - (g))) 1587 1588 /* 1589 * cztty_transmit() 1590 * 1591 * Look at the tty for this port and start sending. 1592 */ 1593 int 1594 cztty_transmit(struct cztty_softc *sc, struct tty *tp) 1595 { 1596 struct cz_softc *cz = CZTTY_CZ(sc); 1597 u_int move, get, put, size, address; 1598 #ifdef HOSTRAMCODE 1599 int error, done = 0; 1600 #else 1601 int done = 0; 1602 #endif 1603 1604 size = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFSIZE); 1605 get = CZTTY_BUF_READ(sc, BUFCTL_TX_GET); 1606 put = CZTTY_BUF_READ(sc, BUFCTL_TX_PUT); 1607 address = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFADDR); 1608 1609 while ((tp->t_outq.c_cc > 0) && ((move = TX_MOVEABLE(get, put, size)))){ 1610 #ifdef HOSTRAMCODE 1611 if (0) { 1612 move = min(tp->t_outq.c_cc, move); 1613 error = q_to_b(&tp->t_outq, 0, move); 1614 if (error != move) { 1615 printf("%s: channel %d: error moving to " 1616 "transmit buf\n", cz->cz_dev.dv_xname, 1617 sc->sc_channel); 1618 move = error; 1619 } 1620 } else { 1621 #endif 1622 move = min(ndqb(&tp->t_outq, 0), move); 1623 bus_space_write_region_1(cz->cz_win_st, cz->cz_win_sh, 1624 address + put, tp->t_outq.c_cf, move); 1625 ndflush(&tp->t_outq, move); 1626 #ifdef HOSTRAMCODE 1627 } 1628 #endif 1629 1630 put = ((put + move) % size); 1631 done = 1; 1632 } 1633 if (done) { 1634 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, put); 1635 } 1636 return (done); 1637 } 1638 1639 int 1640 cztty_receive(struct cztty_softc *sc, struct tty *tp) 1641 { 1642 struct cz_softc *cz = CZTTY_CZ(sc); 1643 u_int get, put, size, address; 1644 int done = 0, ch; 1645 1646 size = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFSIZE); 1647 get = CZTTY_BUF_READ(sc, BUFCTL_RX_GET); 1648 put = CZTTY_BUF_READ(sc, BUFCTL_RX_PUT); 1649 address = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFADDR); 1650 1651 while ((get != put) && ((tp->t_canq.c_cc + tp->t_rawq.c_cc) < tp->t_hiwat)) { 1652 #ifdef HOSTRAMCODE 1653 if (hostram) 1654 ch = ((char *)fifoaddr)[get]; 1655 } else { 1656 #endif 1657 ch = bus_space_read_1(cz->cz_win_st, cz->cz_win_sh, 1658 address + get); 1659 #ifdef HOSTRAMCODE 1660 } 1661 #endif 1662 (*tp->t_linesw->l_rint)(ch, tp); 1663 get = (get + 1) % size; 1664 done = 1; 1665 } 1666 if (done) { 1667 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, get); 1668 } 1669 return (done); 1670 } 1671