1 /* $NetBSD: cz.c,v 1.24 2002/10/23 09:13:31 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Zembu Labs, Inc. 5 * All rights reserved. 6 * 7 * Authors: Jason R. Thorpe <thorpej@zembu.com> 8 * Bill Studenmund <wrstuden@zembu.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Zembu Labs, Inc. 21 * 4. Neither the name of Zembu Labs nor the names of its employees may 22 * be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY ZEMBU LABS, INC. ``AS IS'' AND ANY EXPRESS 26 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR- 27 * RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS- 28 * CLAIMED. IN NO EVENT SHALL ZEMBU LABS BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Cyclades-Z series multi-port serial adapter driver for NetBSD. 39 * 40 * Some notes: 41 * 42 * - The Cyclades-Z has fully automatic hardware (and software!) 43 * flow control. We only utilize RTS/CTS flow control here, 44 * and it is implemented in a very simplistic manner. This 45 * may be an area of future work. 46 * 47 * - The PLX can map the either the board's RAM or host RAM 48 * into the MIPS's memory window. This would enable us to 49 * use less expensive (for us) memory reads/writes to host 50 * RAM, rather than time-consuming reads/writes to PCI 51 * memory space. However, the PLX can only map a 0-128M 52 * window, so we would have to ensure that the DMA address 53 * of the host RAM fits there. This is kind of a pain, 54 * so we just don't bother right now. 55 * 56 * - In a perfect world, we would use the autoconfiguration 57 * mechanism to attach the TTYs that we find. However, 58 * that leads to somewhat icky looking autoconfiguration 59 * messages (one for every TTY, up to 64 per board!). So 60 * we don't do it that way, but assign minors as if there 61 * were the max of 64 ports per board. 62 * 63 * - We don't bother with PPS support here. There are so many 64 * ports, each with a large amount of buffer space, that the 65 * normal mode of operation is to poll the boards regularly 66 * (generally, every 20ms or so). This makes this driver 67 * unsuitable for PPS, as the latency will be generally too 68 * high. 69 */ 70 /* 71 * This driver inspired by the FreeBSD driver written by Brian J. McGovern 72 * for FreeBSD 3.2. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: cz.c,v 1.24 2002/10/23 09:13:31 jdolecek Exp $"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/proc.h> 81 #include <sys/device.h> 82 #include <sys/malloc.h> 83 #include <sys/tty.h> 84 #include <sys/conf.h> 85 #include <sys/time.h> 86 #include <sys/kernel.h> 87 #include <sys/fcntl.h> 88 #include <sys/syslog.h> 89 90 #include <sys/callout.h> 91 92 #include <dev/pci/pcireg.h> 93 #include <dev/pci/pcivar.h> 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/czreg.h> 96 97 #include <dev/pci/plx9060reg.h> 98 #include <dev/pci/plx9060var.h> 99 100 #include <dev/microcode/cyclades-z/cyzfirm.h> 101 102 #define CZ_DRIVER_VERSION 0x20000411 103 104 #define CZ_POLL_MS 20 105 106 /* These are the interrupts we always use. */ 107 #define CZ_INTERRUPTS \ 108 (C_IN_MDSR | C_IN_MRI | C_IN_MRTS | C_IN_MCTS | C_IN_TXBEMPTY | \ 109 C_IN_TXFEMPTY | C_IN_TXLOWWM | C_IN_RXHIWM | C_IN_RXNNDT | \ 110 C_IN_MDCD | C_IN_PR_ERROR | C_IN_FR_ERROR | C_IN_OVR_ERROR | \ 111 C_IN_RXOFL | C_IN_IOCTLW | C_IN_RXBRK) 112 113 /* 114 * cztty_softc: 115 * 116 * Per-channel (TTY) state. 117 */ 118 struct cztty_softc { 119 struct cz_softc *sc_parent; 120 struct tty *sc_tty; 121 122 struct callout sc_diag_ch; 123 124 int sc_channel; /* Also used to flag unattached chan */ 125 #define CZTTY_CHANNEL_DEAD -1 126 127 bus_space_tag_t sc_chan_st; /* channel space tag */ 128 bus_space_handle_t sc_chan_sh; /* channel space handle */ 129 bus_space_handle_t sc_buf_sh; /* buffer space handle */ 130 131 u_int sc_overflows, 132 sc_parity_errors, 133 sc_framing_errors, 134 sc_errors; 135 136 int sc_swflags; 137 138 u_int32_t sc_rs_control_dtr, 139 sc_chanctl_hw_flow, 140 sc_chanctl_comm_baud, 141 sc_chanctl_rs_control, 142 sc_chanctl_comm_data_l, 143 sc_chanctl_comm_parity; 144 }; 145 146 /* 147 * cz_softc: 148 * 149 * Per-board state. 150 */ 151 struct cz_softc { 152 struct device cz_dev; /* generic device info */ 153 struct plx9060_config cz_plx; /* PLX 9060 config info */ 154 bus_space_tag_t cz_win_st; /* window space tag */ 155 bus_space_handle_t cz_win_sh; /* window space handle */ 156 struct callout cz_callout; /* callout for polling-mode */ 157 158 void *cz_ih; /* interrupt handle */ 159 160 u_int32_t cz_mailbox0; /* our MAILBOX0 value */ 161 int cz_nchannels; /* number of channels */ 162 int cz_nopenchan; /* number of open channels */ 163 struct cztty_softc *cz_ports; /* our array of ports */ 164 165 bus_addr_t cz_fwctl; /* offset of firmware control */ 166 }; 167 168 int cz_match(struct device *, struct cfdata *, void *); 169 void cz_attach(struct device *, struct device *, void *); 170 int cz_wait_pci_doorbell(struct cz_softc *, const char *); 171 172 CFATTACH_DECL(cz, sizeof(struct cz_softc), 173 cz_match, cz_attach, NULL, NULL); 174 175 void cz_reset_board(struct cz_softc *); 176 int cz_load_firmware(struct cz_softc *); 177 178 int cz_intr(void *); 179 void cz_poll(void *); 180 int cztty_transmit(struct cztty_softc *, struct tty *); 181 int cztty_receive(struct cztty_softc *, struct tty *); 182 183 struct cztty_softc * cztty_getttysoftc(dev_t dev); 184 int cztty_attached_ttys; 185 int cz_timeout_ticks; 186 187 void czttystart(struct tty *tp); 188 int czttyparam(struct tty *tp, struct termios *t); 189 void cztty_shutdown(struct cztty_softc *sc); 190 void cztty_modem(struct cztty_softc *sc, int onoff); 191 void cztty_break(struct cztty_softc *sc, int onoff); 192 void tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits); 193 int cztty_to_tiocm(struct cztty_softc *sc); 194 void cztty_diag(void *arg); 195 196 extern struct cfdriver cz_cd; 197 198 dev_type_open(czttyopen); 199 dev_type_close(czttyclose); 200 dev_type_read(czttyread); 201 dev_type_write(czttywrite); 202 dev_type_ioctl(czttyioctl); 203 dev_type_stop(czttystop); 204 dev_type_tty(czttytty); 205 dev_type_poll(czttypoll); 206 207 const struct cdevsw cz_cdevsw = { 208 czttyopen, czttyclose, czttyread, czttywrite, czttyioctl, 209 czttystop, czttytty, czttypoll, nommap, ttykqfilter, D_TTY 210 }; 211 212 /* Macros to clear/set/test flags. */ 213 #define SET(t, f) (t) |= (f) 214 #define CLR(t, f) (t) &= ~(f) 215 #define ISSET(t, f) ((t) & (f)) 216 217 /* 218 * Macros to read and write the PLX. 219 */ 220 #define CZ_PLX_READ(cz, reg) \ 221 bus_space_read_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, (reg)) 222 #define CZ_PLX_WRITE(cz, reg, val) \ 223 bus_space_write_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, \ 224 (reg), (val)) 225 226 /* 227 * Macros to read and write the FPGA. We must already be in the FPGA 228 * window for this. 229 */ 230 #define CZ_FPGA_READ(cz, reg) \ 231 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg)) 232 #define CZ_FPGA_WRITE(cz, reg, val) \ 233 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg), (val)) 234 235 /* 236 * Macros to read and write the firmware control structures in board RAM. 237 */ 238 #define CZ_FWCTL_READ(cz, off) \ 239 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 240 (cz)->cz_fwctl + (off)) 241 242 #define CZ_FWCTL_WRITE(cz, off, val) \ 243 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 244 (cz)->cz_fwctl + (off), (val)) 245 246 /* 247 * Convenience macros for cztty routines. PLX window MUST be to RAM. 248 */ 249 #define CZTTY_CHAN_READ(sc, off) \ 250 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_chan_sh, (off)) 251 252 #define CZTTY_CHAN_WRITE(sc, off, val) \ 253 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_chan_sh, \ 254 (off), (val)) 255 256 #define CZTTY_BUF_READ(sc, off) \ 257 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_buf_sh, (off)) 258 259 #define CZTTY_BUF_WRITE(sc, off, val) \ 260 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_buf_sh, \ 261 (off), (val)) 262 263 /* 264 * Convenience macros. 265 */ 266 #define CZ_WIN_RAM(cz) \ 267 do { \ 268 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_RAM); \ 269 delay(100); \ 270 } while (0) 271 272 #define CZ_WIN_FPGA(cz) \ 273 do { \ 274 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_FPGA); \ 275 delay(100); \ 276 } while (0) 277 278 /***************************************************************************** 279 * Cyclades-Z controller code starts here... 280 *****************************************************************************/ 281 282 /* 283 * cz_match: 284 * 285 * Determine if the given PCI device is a Cyclades-Z board. 286 */ 287 int 288 cz_match(struct device *parent, 289 struct cfdata *match, 290 void *aux) 291 { 292 struct pci_attach_args *pa = aux; 293 294 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYCLADES) { 295 switch (PCI_PRODUCT(pa->pa_id)) { 296 case PCI_PRODUCT_CYCLADES_CYCLOMZ_2: 297 return (1); 298 } 299 } 300 301 return (0); 302 } 303 304 /* 305 * cz_attach: 306 * 307 * A Cyclades-Z board was found; attach it. 308 */ 309 void 310 cz_attach(struct device *parent, 311 struct device *self, 312 void *aux) 313 { 314 struct cz_softc *cz = (void *) self; 315 struct pci_attach_args *pa = aux; 316 pci_intr_handle_t ih; 317 const char *intrstr = NULL; 318 struct cztty_softc *sc; 319 struct tty *tp; 320 int i; 321 322 printf(": Cyclades-Z multiport serial\n"); 323 324 cz->cz_plx.plx_pc = pa->pa_pc; 325 cz->cz_plx.plx_tag = pa->pa_tag; 326 327 if (pci_mapreg_map(pa, PLX_PCI_RUNTIME_MEMADDR, 328 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 329 &cz->cz_plx.plx_st, &cz->cz_plx.plx_sh, NULL, NULL) != 0) { 330 printf("%s: unable to map PLX registers\n", 331 cz->cz_dev.dv_xname); 332 return; 333 } 334 if (pci_mapreg_map(pa, PLX_PCI_LOCAL_ADDR0, 335 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 336 &cz->cz_win_st, &cz->cz_win_sh, NULL, NULL) != 0) { 337 printf("%s: unable to map device window\n", 338 cz->cz_dev.dv_xname); 339 return; 340 } 341 342 cz->cz_mailbox0 = CZ_PLX_READ(cz, PLX_MAILBOX0); 343 cz->cz_nopenchan = 0; 344 345 /* 346 * Make sure that the board is completely stopped. 347 */ 348 CZ_WIN_FPGA(cz); 349 CZ_FPGA_WRITE(cz, FPGA_CPU_STOP, 0); 350 351 /* 352 * Load the board's firmware. 353 */ 354 if (cz_load_firmware(cz) != 0) 355 return; 356 357 /* 358 * Now that we're ready to roll, map and establish the interrupt 359 * handler. 360 */ 361 if (pci_intr_map(pa, &ih) != 0) { 362 /* 363 * The common case is for Cyclades-Z boards to run 364 * in polling mode, and thus not have an interrupt 365 * mapped for them. Don't bother reporting that 366 * the interrupt is not mappable, since this isn't 367 * really an error. 368 */ 369 cz->cz_ih = NULL; 370 goto polling_mode; 371 } else { 372 intrstr = pci_intr_string(pa->pa_pc, ih); 373 cz->cz_ih = pci_intr_establish(pa->pa_pc, ih, IPL_TTY, 374 cz_intr, cz); 375 } 376 if (cz->cz_ih == NULL) { 377 printf("%s: unable to establish interrupt", 378 cz->cz_dev.dv_xname); 379 if (intrstr != NULL) 380 printf(" at %s", intrstr); 381 printf("\n"); 382 /* We will fall-back on polling mode. */ 383 } else 384 printf("%s: interrupting at %s\n", 385 cz->cz_dev.dv_xname, intrstr); 386 387 polling_mode: 388 if (cz->cz_ih == NULL) { 389 callout_init(&cz->cz_callout); 390 if (cz_timeout_ticks == 0) 391 cz_timeout_ticks = max(1, hz * CZ_POLL_MS / 1000); 392 printf("%s: polling mode, %d ms interval (%d tick%s)\n", 393 cz->cz_dev.dv_xname, CZ_POLL_MS, cz_timeout_ticks, 394 cz_timeout_ticks == 1 ? "" : "s"); 395 } 396 397 /* 398 * Allocate sufficient pointers for the children and 399 * attach them. Set all ports to a reasonable initial 400 * configuration while we're at it: 401 * 402 * disabled 403 * 8N1 404 * default baud rate 405 * hardware flow control. 406 */ 407 CZ_WIN_RAM(cz); 408 409 if (cz->cz_nchannels == 0) { 410 /* No channels? No more work to do! */ 411 return; 412 } 413 414 cz->cz_ports = malloc(sizeof(struct cztty_softc) * cz->cz_nchannels, 415 M_DEVBUF, M_WAITOK|M_ZERO); 416 cztty_attached_ttys += cz->cz_nchannels; 417 418 for (i = 0; i < cz->cz_nchannels; i++) { 419 sc = &cz->cz_ports[i]; 420 421 sc->sc_channel = i; 422 sc->sc_chan_st = cz->cz_win_st; 423 sc->sc_parent = cz; 424 425 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 426 cz->cz_fwctl + ZFIRM_CHNCTL_OFF(i, 0), 427 ZFIRM_CHNCTL_SIZE, &sc->sc_chan_sh)) { 428 printf("%s: unable to subregion channel %d control\n", 429 cz->cz_dev.dv_xname, i); 430 sc->sc_channel = CZTTY_CHANNEL_DEAD; 431 continue; 432 } 433 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 434 cz->cz_fwctl + ZFIRM_BUFCTL_OFF(i, 0), 435 ZFIRM_BUFCTL_SIZE, &sc->sc_buf_sh)) { 436 printf("%s: unable to subregion channel %d buffer\n", 437 cz->cz_dev.dv_xname, i); 438 sc->sc_channel = CZTTY_CHANNEL_DEAD; 439 continue; 440 } 441 442 callout_init(&sc->sc_diag_ch); 443 444 tp = ttymalloc(); 445 tp->t_dev = makedev(cdevsw_lookup_major(&cz_cdevsw), 446 (cz->cz_dev.dv_unit * ZFIRM_MAX_CHANNELS) + i); 447 tp->t_oproc = czttystart; 448 tp->t_param = czttyparam; 449 tty_attach(tp); 450 451 sc->sc_tty = tp; 452 453 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 454 CZTTY_CHAN_WRITE(sc, CHNCTL_INTR_ENABLE, CZ_INTERRUPTS); 455 CZTTY_CHAN_WRITE(sc, CHNCTL_SW_FLOW, 0); 456 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XON, 0x11); 457 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XOFF, 0x13); 458 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, TTYDEF_SPEED); 459 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, C_PR_NONE); 460 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, C_DL_CS8 | C_DL_1STOP); 461 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_FLAGS, 0); 462 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, C_RS_CTS | C_RS_RTS); 463 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, 0); 464 } 465 } 466 467 /* 468 * cz_reset_board: 469 * 470 * Reset the board via the PLX. 471 */ 472 void 473 cz_reset_board(struct cz_softc *cz) 474 { 475 u_int32_t reg; 476 477 reg = CZ_PLX_READ(cz, PLX_CONTROL); 478 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_SWR); 479 delay(1000); 480 481 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 482 delay(1000); 483 484 /* Now reload the PLX from its EEPROM. */ 485 reg = CZ_PLX_READ(cz, PLX_CONTROL); 486 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_RELOADCFG); 487 delay(1000); 488 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 489 } 490 491 /* 492 * cz_load_firmware: 493 * 494 * Load the ZFIRM firmware into the board's RAM and start it 495 * running. 496 */ 497 int 498 cz_load_firmware(struct cz_softc *cz) 499 { 500 struct zfirm_header *zfh; 501 struct zfirm_config *zfc; 502 struct zfirm_block *zfb, *zblocks; 503 const u_int8_t *cp; 504 const char *board; 505 u_int32_t fid; 506 int i, j, nconfigs, nblocks, nbytes; 507 508 zfh = (struct zfirm_header *) cycladesz_firmware; 509 510 /* Find the config header. */ 511 if (le32toh(zfh->zfh_configoff) & (sizeof(u_int32_t) - 1)) { 512 printf("%s: bad ZFIRM config offset: 0x%x\n", 513 cz->cz_dev.dv_xname, le32toh(zfh->zfh_configoff)); 514 return (EIO); 515 } 516 zfc = (struct zfirm_config *)(cycladesz_firmware + 517 le32toh(zfh->zfh_configoff)); 518 nconfigs = le32toh(zfh->zfh_nconfig); 519 520 /* Locate the correct configuration for our board. */ 521 for (i = 0; i < nconfigs; i++, zfc++) { 522 if (le32toh(zfc->zfc_mailbox) == cz->cz_mailbox0 && 523 le32toh(zfc->zfc_function) == ZFC_FUNCTION_NORMAL) 524 break; 525 } 526 if (i == nconfigs) { 527 printf("%s: unable to locate config header\n", 528 cz->cz_dev.dv_xname); 529 return (EIO); 530 } 531 532 nblocks = le32toh(zfc->zfc_nblocks); 533 zblocks = (struct zfirm_block *)(cycladesz_firmware + 534 le32toh(zfh->zfh_blockoff)); 535 536 /* 537 * 8Zo ver. 1 doesn't have an FPGA. Load it on all others if 538 * necessary. 539 */ 540 if (cz->cz_mailbox0 != MAILBOX0_8Zo_V1 541 #if 0 542 && ((CZ_PLX_READ(cz, PLX_CONTROL) & CONTROL_FPGA_LOADED) == 0) 543 #endif 544 ) { 545 #ifdef CZ_DEBUG 546 printf("%s: Loading FPGA...", cz->cz_dev.dv_xname); 547 #endif 548 CZ_WIN_FPGA(cz); 549 for (i = 0; i < nblocks; i++) { 550 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 551 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 552 if (le32toh(zfb->zfb_type) == ZFB_TYPE_FPGA) { 553 nbytes = le32toh(zfb->zfb_size); 554 cp = &cycladesz_firmware[ 555 le32toh(zfb->zfb_fileoff)]; 556 for (j = 0; j < nbytes; j++, cp++) { 557 bus_space_write_1(cz->cz_win_st, 558 cz->cz_win_sh, 0, *cp); 559 /* FPGA needs 30-100us to settle. */ 560 delay(10); 561 } 562 } 563 } 564 #ifdef CZ_DEBUG 565 printf("done\n"); 566 #endif 567 } 568 569 /* Now load the firmware. */ 570 CZ_WIN_RAM(cz); 571 572 for (i = 0; i < nblocks; i++) { 573 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 574 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 575 if (le32toh(zfb->zfb_type) == ZFB_TYPE_FIRMWARE) { 576 const u_int32_t *lp; 577 u_int32_t ro = le32toh(zfb->zfb_ramoff); 578 nbytes = le32toh(zfb->zfb_size); 579 lp = (const u_int32_t *) 580 &cycladesz_firmware[le32toh(zfb->zfb_fileoff)]; 581 for (j = 0; j < nbytes; j += 4, lp++) { 582 bus_space_write_4(cz->cz_win_st, cz->cz_win_sh, 583 ro + j, le32toh(*lp)); 584 delay(10); 585 } 586 } 587 } 588 589 /* Now restart the MIPS. */ 590 CZ_WIN_FPGA(cz); 591 CZ_FPGA_WRITE(cz, FPGA_CPU_START, 0); 592 593 /* Wait for the MIPS to start, then report the results. */ 594 CZ_WIN_RAM(cz); 595 596 #ifdef CZ_DEBUG 597 printf("%s: waiting for MIPS to start", cz->cz_dev.dv_xname); 598 #endif 599 for (i = 0; i < 100; i++) { 600 fid = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 601 ZFIRM_SIG_OFF); 602 if (fid == ZFIRM_SIG) { 603 /* MIPS has booted. */ 604 break; 605 } else if (fid == ZFIRM_HLT) { 606 /* 607 * The MIPS has halted, usually due to a power 608 * shortage on the expansion module. 609 */ 610 printf("%s: MIPS halted; possible power supply " 611 "problem\n", cz->cz_dev.dv_xname); 612 return (EIO); 613 } else { 614 #ifdef CZ_DEBUG 615 if ((i % 8) == 0) 616 printf("."); 617 #endif 618 delay(250000); 619 } 620 } 621 #ifdef CZ_DEBUG 622 printf("\n"); 623 #endif 624 if (i == 100) { 625 CZ_WIN_FPGA(cz); 626 printf("%s: MIPS failed to start; wanted 0x%08x got 0x%08x\n", 627 cz->cz_dev.dv_xname, ZFIRM_SIG, fid); 628 printf("%s: FPGA ID 0x%08x, FPGA version 0x%08x\n", 629 cz->cz_dev.dv_xname, CZ_FPGA_READ(cz, FPGA_ID), 630 CZ_FPGA_READ(cz, FPGA_VERSION)); 631 return (EIO); 632 } 633 634 /* 635 * Locate the firmware control structures. 636 */ 637 cz->cz_fwctl = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 638 ZFIRM_CTRLADDR_OFF); 639 #ifdef CZ_DEBUG 640 printf("%s: FWCTL structure at offset 0x%08lx\n", 641 cz->cz_dev.dv_xname, cz->cz_fwctl); 642 #endif 643 644 CZ_FWCTL_WRITE(cz, BRDCTL_C_OS, C_OS_BSD); 645 CZ_FWCTL_WRITE(cz, BRDCTL_DRVERSION, CZ_DRIVER_VERSION); 646 647 cz->cz_nchannels = CZ_FWCTL_READ(cz, BRDCTL_NCHANNEL); 648 649 switch (cz->cz_mailbox0) { 650 case MAILBOX0_8Zo_V1: 651 board = "Cyclades-8Zo ver. 1"; 652 break; 653 654 case MAILBOX0_8Zo_V2: 655 board = "Cyclades-8Zo ver. 2"; 656 break; 657 658 case MAILBOX0_Ze_V1: 659 board = "Cyclades-Ze"; 660 break; 661 662 default: 663 board = "unknown Cyclades Z-series"; 664 break; 665 } 666 667 fid = CZ_FWCTL_READ(cz, BRDCTL_FWVERSION); 668 printf("%s: %s, ", cz->cz_dev.dv_xname, board); 669 if (cz->cz_nchannels == 0) 670 printf("no channels attached, "); 671 else 672 printf("%d channels (ttyCZ%04d..ttyCZ%04d), ", 673 cz->cz_nchannels, cztty_attached_ttys, 674 cztty_attached_ttys + (cz->cz_nchannels - 1)); 675 printf("firmware %x.%x.%x\n", 676 (fid >> 8) & 0xf, (fid >> 4) & 0xf, fid & 0xf); 677 678 return (0); 679 } 680 681 /* 682 * cz_poll: 683 * 684 * This card doesn't do interrupts, so scan it for activity every CZ_POLL_MS 685 * ms. 686 */ 687 void 688 cz_poll(void *arg) 689 { 690 int s = spltty(); 691 struct cz_softc *cz = arg; 692 693 cz_intr(cz); 694 callout_reset(&cz->cz_callout, cz_timeout_ticks, cz_poll, cz); 695 696 splx(s); 697 } 698 699 /* 700 * cz_intr: 701 * 702 * Interrupt service routine. 703 * 704 * We either are receiving an interrupt directly from the board, or we are 705 * in polling mode and it's time to poll. 706 */ 707 int 708 cz_intr(void *arg) 709 { 710 int rval = 0; 711 u_int command, channel, param; 712 struct cz_softc *cz = arg; 713 struct cztty_softc *sc; 714 struct tty *tp; 715 716 while ((command = (CZ_PLX_READ(cz, PLX_LOCAL_PCI_DOORBELL) & 0xff))) { 717 rval = 1; 718 channel = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_CHANNEL); 719 param = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_PARAM); 720 721 /* now clear this interrupt, posslibly enabling another */ 722 CZ_PLX_WRITE(cz, PLX_LOCAL_PCI_DOORBELL, command); 723 724 if (cz->cz_ports == NULL) { 725 #ifdef CZ_DEBUG 726 printf("%s: interrupt on channel %d, but no channels\n", 727 cz->cz_dev.dv_xname, channel); 728 #endif 729 continue; 730 } 731 732 sc = &cz->cz_ports[channel]; 733 734 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 735 break; 736 737 tp = sc->sc_tty; 738 739 switch (command) { 740 case C_CM_TXFEMPTY: /* transmit cases */ 741 case C_CM_TXBEMPTY: 742 case C_CM_TXLOWWM: 743 case C_CM_INTBACK: 744 if (!ISSET(tp->t_state, TS_ISOPEN)) { 745 #ifdef CZ_DEBUG 746 printf("%s: tx intr on closed channel %d\n", 747 cz->cz_dev.dv_xname, channel); 748 #endif 749 break; 750 } 751 752 if (cztty_transmit(sc, tp)) { 753 /* 754 * Do wakeup stuff here. 755 */ 756 ttwakeup(tp); 757 wakeup(tp); 758 } 759 break; 760 761 case C_CM_RXNNDT: /* receive cases */ 762 case C_CM_RXHIWM: 763 case C_CM_INTBACK2: /* from restart ?? */ 764 #if 0 765 case C_CM_ICHAR: 766 #endif 767 if (!ISSET(tp->t_state, TS_ISOPEN)) { 768 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 769 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 770 break; 771 } 772 773 if (cztty_receive(sc, tp)) { 774 /* 775 * Do wakeup stuff here. 776 */ 777 ttwakeup(tp); 778 wakeup(tp); 779 } 780 break; 781 782 case C_CM_MDCD: 783 if (!ISSET(tp->t_state, TS_ISOPEN)) 784 break; 785 786 (void) (*tp->t_linesw->l_modem)(tp, 787 ISSET(C_RS_DCD, CZTTY_CHAN_READ(sc, 788 CHNCTL_RS_STATUS))); 789 break; 790 791 case C_CM_MDSR: 792 case C_CM_MRI: 793 case C_CM_MCTS: 794 case C_CM_MRTS: 795 break; 796 797 case C_CM_IOCTLW: 798 break; 799 800 case C_CM_PR_ERROR: 801 sc->sc_parity_errors++; 802 goto error_common; 803 804 case C_CM_FR_ERROR: 805 sc->sc_framing_errors++; 806 goto error_common; 807 808 case C_CM_OVR_ERROR: 809 sc->sc_overflows++; 810 error_common: 811 if (sc->sc_errors++ == 0) 812 callout_reset(&sc->sc_diag_ch, 60 * hz, 813 cztty_diag, sc); 814 break; 815 816 case C_CM_RXBRK: 817 if (!ISSET(tp->t_state, TS_ISOPEN)) 818 break; 819 820 /* 821 * A break is a \000 character with TTY_FE error 822 * flags set. So TTY_FE by itself works. 823 */ 824 (*tp->t_linesw->l_rint)(TTY_FE, tp); 825 ttwakeup(tp); 826 wakeup(tp); 827 break; 828 829 default: 830 #ifdef CZ_DEBUG 831 printf("%s: channel %d: Unknown interrupt 0x%x\n", 832 cz->cz_dev.dv_xname, sc->sc_channel, command); 833 #endif 834 break; 835 } 836 } 837 838 return (rval); 839 } 840 841 /* 842 * cz_wait_pci_doorbell: 843 * 844 * Wait for the pci doorbell to be clear - wait for pending 845 * activity to drain. 846 */ 847 int 848 cz_wait_pci_doorbell(struct cz_softc *cz, const char *wstring) 849 { 850 int error; 851 852 while (CZ_PLX_READ(cz, PLX_PCI_LOCAL_DOORBELL)) { 853 error = tsleep(cz, TTIPRI | PCATCH, wstring, max(1, hz/100)); 854 if ((error != 0) && (error != EWOULDBLOCK)) 855 return (error); 856 } 857 return (0); 858 } 859 860 /***************************************************************************** 861 * Cyclades-Z TTY code starts here... 862 *****************************************************************************/ 863 864 #define CZTTYDIALOUT_MASK 0x80000 865 866 #define CZTTY_DIALOUT(dev) (minor((dev)) & CZTTYDIALOUT_MASK) 867 #define CZTTY_CZ(sc) ((sc)->sc_parent) 868 869 #define CZTTY_SOFTC(dev) cztty_getttysoftc(dev) 870 871 struct cztty_softc * 872 cztty_getttysoftc(dev_t dev) 873 { 874 int i, j, k, u = minor(dev) & ~CZTTYDIALOUT_MASK; 875 struct cz_softc *cz; 876 877 for (i = 0, j = 0; i < cz_cd.cd_ndevs; i++) { 878 k = j; 879 cz = device_lookup(&cz_cd, i); 880 if (cz == NULL) 881 continue; 882 if (cz->cz_ports == NULL) 883 continue; 884 j += cz->cz_nchannels; 885 if (j > u) 886 break; 887 } 888 889 if (i >= cz_cd.cd_ndevs) 890 return (NULL); 891 else 892 return (&cz->cz_ports[u - k]); 893 } 894 895 /* 896 * czttytty: 897 * 898 * Return a pointer to our tty. 899 */ 900 struct tty * 901 czttytty(dev_t dev) 902 { 903 struct cztty_softc *sc = CZTTY_SOFTC(dev); 904 905 #ifdef DIAGNOSTIC 906 if (sc == NULL) 907 panic("czttytty"); 908 #endif 909 910 return (sc->sc_tty); 911 } 912 913 /* 914 * cztty_shutdown: 915 * 916 * Shut down a port. 917 */ 918 void 919 cztty_shutdown(struct cztty_softc *sc) 920 { 921 struct cz_softc *cz = CZTTY_CZ(sc); 922 struct tty *tp = sc->sc_tty; 923 int s; 924 925 s = spltty(); 926 927 /* Clear any break condition set with TIOCSBRK. */ 928 cztty_break(sc, 0); 929 930 /* 931 * Hang up if necessary. Wait a bit, so the other side has time to 932 * notice even if we immediately open the port again. 933 */ 934 if (ISSET(tp->t_cflag, HUPCL)) { 935 cztty_modem(sc, 0); 936 (void) tsleep(tp, TTIPRI, ttclos, hz); 937 } 938 939 /* Disable the channel. */ 940 cz_wait_pci_doorbell(cz, "czdis"); 941 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 942 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 943 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTL); 944 945 if ((--cz->cz_nopenchan == 0) && (cz->cz_ih == NULL)) { 946 #ifdef CZ_DEBUG 947 printf("%s: Disabling polling\n", cz->cz_dev.dv_xname); 948 #endif 949 callout_stop(&cz->cz_callout); 950 } 951 952 splx(s); 953 } 954 955 /* 956 * czttyopen: 957 * 958 * Open a Cyclades-Z serial port. 959 */ 960 int 961 czttyopen(dev_t dev, int flags, int mode, struct proc *p) 962 { 963 struct cztty_softc *sc = CZTTY_SOFTC(dev); 964 struct cz_softc *cz; 965 struct tty *tp; 966 int s, error; 967 968 if (sc == NULL) 969 return (ENXIO); 970 971 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 972 return (ENXIO); 973 974 cz = CZTTY_CZ(sc); 975 tp = sc->sc_tty; 976 977 if (ISSET(tp->t_state, TS_ISOPEN) && 978 ISSET(tp->t_state, TS_XCLUDE) && 979 p->p_ucred->cr_uid != 0) 980 return (EBUSY); 981 982 s = spltty(); 983 984 /* 985 * Do the following iff this is a first open. 986 */ 987 if (!ISSET(tp->t_state, TS_ISOPEN) && (tp->t_wopen == 0)) { 988 struct termios t; 989 990 tp->t_dev = dev; 991 992 /* If we're turning things on, enable interrupts */ 993 if ((cz->cz_nopenchan++ == 0) && (cz->cz_ih == NULL)) { 994 #ifdef CZ_DEBUG 995 printf("%s: Enabling polling.\n", 996 cz->cz_dev.dv_xname); 997 #endif 998 callout_reset(&cz->cz_callout, cz_timeout_ticks, 999 cz_poll, cz); 1000 } 1001 1002 /* 1003 * Enable the channel. Don't actually ring the 1004 * doorbell here; czttyparam() will do it for us. 1005 */ 1006 cz_wait_pci_doorbell(cz, "czopen"); 1007 1008 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_ENABLE); 1009 1010 /* 1011 * Initialize the termios status to the defaults. Add in the 1012 * sticky bits from TIOCSFLAGS. 1013 */ 1014 t.c_ispeed = 0; 1015 t.c_ospeed = TTYDEF_SPEED; 1016 t.c_cflag = TTYDEF_CFLAG; 1017 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1018 SET(t.c_cflag, CLOCAL); 1019 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1020 SET(t.c_cflag, CRTSCTS); 1021 1022 /* 1023 * Reset the input and output rings. Do this before 1024 * we call czttyparam(), as that function enables 1025 * the channel. 1026 */ 1027 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 1028 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 1029 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, 1030 CZTTY_BUF_READ(sc, BUFCTL_TX_GET)); 1031 1032 /* Make sure czttyparam() will see changes. */ 1033 tp->t_ospeed = 0; 1034 (void) czttyparam(tp, &t); 1035 tp->t_iflag = TTYDEF_IFLAG; 1036 tp->t_oflag = TTYDEF_OFLAG; 1037 tp->t_lflag = TTYDEF_LFLAG; 1038 ttychars(tp); 1039 ttsetwater(tp); 1040 1041 /* 1042 * Turn on DTR. We must always do this, even if carrier is not 1043 * present, because otherwise we'd have to use TIOCSDTR 1044 * immediately after setting CLOCAL, which applications do not 1045 * expect. We always assert DTR while the device is open 1046 * unless explicitly requested to deassert it. 1047 */ 1048 cztty_modem(sc, 1); 1049 } 1050 1051 splx(s); 1052 1053 error = ttyopen(tp, CZTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK)); 1054 if (error) 1055 goto bad; 1056 1057 error = (*tp->t_linesw->l_open)(dev, tp); 1058 if (error) 1059 goto bad; 1060 1061 return (0); 1062 1063 bad: 1064 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1065 /* 1066 * We failed to open the device, and nobody else had it opened. 1067 * Clean up the state as appropriate. 1068 */ 1069 cztty_shutdown(sc); 1070 } 1071 1072 return (error); 1073 } 1074 1075 /* 1076 * czttyclose: 1077 * 1078 * Close a Cyclades-Z serial port. 1079 */ 1080 int 1081 czttyclose(dev_t dev, int flags, int mode, struct proc *p) 1082 { 1083 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1084 struct tty *tp = sc->sc_tty; 1085 1086 /* XXX This is for cons.c. */ 1087 if (!ISSET(tp->t_state, TS_ISOPEN)) 1088 return (0); 1089 1090 (*tp->t_linesw->l_close)(tp, flags); 1091 ttyclose(tp); 1092 1093 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1094 /* 1095 * Although we got a last close, the device may still be in 1096 * use; e.g. if this was the dialout node, and there are still 1097 * processes waiting for carrier on the non-dialout node. 1098 */ 1099 cztty_shutdown(sc); 1100 } 1101 1102 return (0); 1103 } 1104 1105 /* 1106 * czttyread: 1107 * 1108 * Read from a Cyclades-Z serial port. 1109 */ 1110 int 1111 czttyread(dev_t dev, struct uio *uio, int flags) 1112 { 1113 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1114 struct tty *tp = sc->sc_tty; 1115 1116 return ((*tp->t_linesw->l_read)(tp, uio, flags)); 1117 } 1118 1119 /* 1120 * czttywrite: 1121 * 1122 * Write to a Cyclades-Z serial port. 1123 */ 1124 int 1125 czttywrite(dev_t dev, struct uio *uio, int flags) 1126 { 1127 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1128 struct tty *tp = sc->sc_tty; 1129 1130 return ((*tp->t_linesw->l_write)(tp, uio, flags)); 1131 } 1132 1133 /* 1134 * czttypoll: 1135 * 1136 * Poll a Cyclades-Z serial port. 1137 */ 1138 int 1139 czttypoll(dev, events, p) 1140 dev_t dev; 1141 int events; 1142 struct proc *p; 1143 { 1144 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1145 struct tty *tp = sc->sc_tty; 1146 1147 return ((*tp->t_linesw->l_poll)(tp, events, p)); 1148 } 1149 1150 /* 1151 * czttyioctl: 1152 * 1153 * Perform a control operation on a Cyclades-Z serial port. 1154 */ 1155 int 1156 czttyioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 1157 { 1158 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1159 struct tty *tp = sc->sc_tty; 1160 int s, error; 1161 1162 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p); 1163 if (error != EPASSTHROUGH) 1164 return (error); 1165 1166 error = ttioctl(tp, cmd, data, flag, p); 1167 if (error != EPASSTHROUGH) 1168 return (error); 1169 1170 error = 0; 1171 1172 s = spltty(); 1173 1174 switch (cmd) { 1175 case TIOCSBRK: 1176 cztty_break(sc, 1); 1177 break; 1178 1179 case TIOCCBRK: 1180 cztty_break(sc, 0); 1181 break; 1182 1183 case TIOCGFLAGS: 1184 *(int *)data = sc->sc_swflags; 1185 break; 1186 1187 case TIOCSFLAGS: 1188 error = suser(p->p_ucred, &p->p_acflag); 1189 if (error) 1190 break; 1191 sc->sc_swflags = *(int *)data; 1192 break; 1193 1194 case TIOCSDTR: 1195 cztty_modem(sc, 1); 1196 break; 1197 1198 case TIOCCDTR: 1199 cztty_modem(sc, 0); 1200 break; 1201 1202 case TIOCMSET: 1203 case TIOCMBIS: 1204 case TIOCMBIC: 1205 tiocm_to_cztty(sc, cmd, *(int *)data); 1206 break; 1207 1208 case TIOCMGET: 1209 *(int *)data = cztty_to_tiocm(sc); 1210 break; 1211 1212 default: 1213 error = EPASSTHROUGH; 1214 break; 1215 } 1216 1217 splx(s); 1218 1219 return (error); 1220 } 1221 1222 /* 1223 * cztty_break: 1224 * 1225 * Set or clear BREAK on a port. 1226 */ 1227 void 1228 cztty_break(struct cztty_softc *sc, int onoff) 1229 { 1230 struct cz_softc *cz = CZTTY_CZ(sc); 1231 1232 cz_wait_pci_doorbell(cz, "czbreak"); 1233 1234 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1235 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, 1236 onoff ? C_CM_SET_BREAK : C_CM_CLR_BREAK); 1237 } 1238 1239 /* 1240 * cztty_modem: 1241 * 1242 * Set or clear DTR on a port. 1243 */ 1244 void 1245 cztty_modem(struct cztty_softc *sc, int onoff) 1246 { 1247 struct cz_softc *cz = CZTTY_CZ(sc); 1248 1249 if (sc->sc_rs_control_dtr == 0) 1250 return; 1251 1252 cz_wait_pci_doorbell(cz, "czmod"); 1253 1254 if (onoff) 1255 sc->sc_chanctl_rs_control |= sc->sc_rs_control_dtr; 1256 else 1257 sc->sc_chanctl_rs_control &= ~sc->sc_rs_control_dtr; 1258 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1259 1260 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1261 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1262 } 1263 1264 /* 1265 * tiocm_to_cztty: 1266 * 1267 * Process TIOCM* ioctls. 1268 */ 1269 void 1270 tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits) 1271 { 1272 struct cz_softc *cz = CZTTY_CZ(sc); 1273 u_int32_t czttybits; 1274 1275 czttybits = 0; 1276 if (ISSET(ttybits, TIOCM_DTR)) 1277 SET(czttybits, C_RS_DTR); 1278 if (ISSET(ttybits, TIOCM_RTS)) 1279 SET(czttybits, C_RS_RTS); 1280 1281 cz_wait_pci_doorbell(cz, "cztiocm"); 1282 1283 switch (how) { 1284 case TIOCMBIC: 1285 CLR(sc->sc_chanctl_rs_control, czttybits); 1286 break; 1287 1288 case TIOCMBIS: 1289 SET(sc->sc_chanctl_rs_control, czttybits); 1290 break; 1291 1292 case TIOCMSET: 1293 CLR(sc->sc_chanctl_rs_control, C_RS_DTR | C_RS_RTS); 1294 SET(sc->sc_chanctl_rs_control, czttybits); 1295 break; 1296 } 1297 1298 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1299 1300 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1301 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1302 } 1303 1304 /* 1305 * cztty_to_tiocm: 1306 * 1307 * Process the TIOCMGET ioctl. 1308 */ 1309 int 1310 cztty_to_tiocm(struct cztty_softc *sc) 1311 { 1312 struct cz_softc *cz = CZTTY_CZ(sc); 1313 u_int32_t rs_status, op_mode; 1314 int ttybits = 0; 1315 1316 cz_wait_pci_doorbell(cz, "cztty"); 1317 1318 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1319 op_mode = CZTTY_CHAN_READ(sc, CHNCTL_OP_MODE); 1320 1321 if (ISSET(rs_status, C_RS_RTS)) 1322 SET(ttybits, TIOCM_RTS); 1323 if (ISSET(rs_status, C_RS_CTS)) 1324 SET(ttybits, TIOCM_CTS); 1325 if (ISSET(rs_status, C_RS_DCD)) 1326 SET(ttybits, TIOCM_CAR); 1327 if (ISSET(rs_status, C_RS_DTR)) 1328 SET(ttybits, TIOCM_DTR); 1329 if (ISSET(rs_status, C_RS_RI)) 1330 SET(ttybits, TIOCM_RNG); 1331 if (ISSET(rs_status, C_RS_DSR)) 1332 SET(ttybits, TIOCM_DSR); 1333 1334 if (ISSET(op_mode, C_CH_ENABLE)) 1335 SET(ttybits, TIOCM_LE); 1336 1337 return (ttybits); 1338 } 1339 1340 /* 1341 * czttyparam: 1342 * 1343 * Set Cyclades-Z serial port parameters from termios. 1344 * 1345 * XXX Should just copy the whole termios after making 1346 * XXX sure all the changes could be done. 1347 */ 1348 int 1349 czttyparam(struct tty *tp, struct termios *t) 1350 { 1351 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1352 struct cz_softc *cz = CZTTY_CZ(sc); 1353 u_int32_t rs_status; 1354 int ospeed, cflag; 1355 1356 ospeed = t->c_ospeed; 1357 cflag = t->c_cflag; 1358 1359 /* Check requested parameters. */ 1360 if (ospeed < 0) 1361 return (EINVAL); 1362 if (t->c_ispeed && t->c_ispeed != ospeed) 1363 return (EINVAL); 1364 1365 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR)) { 1366 SET(cflag, CLOCAL); 1367 CLR(cflag, HUPCL); 1368 } 1369 1370 /* 1371 * If there were no changes, don't do anything. This avoids dropping 1372 * input and improves performance when all we did was frob things like 1373 * VMIN and VTIME. 1374 */ 1375 if (tp->t_ospeed == ospeed && 1376 tp->t_cflag == cflag) 1377 return (0); 1378 1379 /* Data bits. */ 1380 sc->sc_chanctl_comm_data_l = 0; 1381 switch (t->c_cflag & CSIZE) { 1382 case CS5: 1383 sc->sc_chanctl_comm_data_l |= C_DL_CS5; 1384 break; 1385 1386 case CS6: 1387 sc->sc_chanctl_comm_data_l |= C_DL_CS6; 1388 break; 1389 1390 case CS7: 1391 sc->sc_chanctl_comm_data_l |= C_DL_CS7; 1392 break; 1393 1394 case CS8: 1395 sc->sc_chanctl_comm_data_l |= C_DL_CS8; 1396 break; 1397 } 1398 1399 /* Stop bits. */ 1400 if (t->c_cflag & CSTOPB) { 1401 if ((sc->sc_chanctl_comm_data_l & C_DL_CS) == C_DL_CS5) 1402 sc->sc_chanctl_comm_data_l |= C_DL_15STOP; 1403 else 1404 sc->sc_chanctl_comm_data_l |= C_DL_2STOP; 1405 } else 1406 sc->sc_chanctl_comm_data_l |= C_DL_1STOP; 1407 1408 /* Parity. */ 1409 if (t->c_cflag & PARENB) { 1410 if (t->c_cflag & PARODD) 1411 sc->sc_chanctl_comm_parity = C_PR_ODD; 1412 else 1413 sc->sc_chanctl_comm_parity = C_PR_EVEN; 1414 } else 1415 sc->sc_chanctl_comm_parity = C_PR_NONE; 1416 1417 /* 1418 * Initialize flow control pins depending on the current flow control 1419 * mode. 1420 */ 1421 if (ISSET(t->c_cflag, CRTSCTS)) { 1422 sc->sc_rs_control_dtr = C_RS_DTR; 1423 sc->sc_chanctl_hw_flow = C_RS_CTS | C_RS_RTS; 1424 } else if (ISSET(t->c_cflag, MDMBUF)) { 1425 sc->sc_rs_control_dtr = 0; 1426 sc->sc_chanctl_hw_flow = C_RS_DCD | C_RS_DTR; 1427 } else { 1428 /* 1429 * If no flow control, then always set RTS. This will make 1430 * the other side happy if it mistakenly thinks we're doing 1431 * RTS/CTS flow control. 1432 */ 1433 sc->sc_rs_control_dtr = C_RS_DTR | C_RS_RTS; 1434 sc->sc_chanctl_hw_flow = 0; 1435 if (ISSET(sc->sc_chanctl_rs_control, C_RS_DTR)) 1436 SET(sc->sc_chanctl_rs_control, C_RS_RTS); 1437 else 1438 CLR(sc->sc_chanctl_rs_control, C_RS_RTS); 1439 } 1440 1441 /* Baud rate. */ 1442 sc->sc_chanctl_comm_baud = ospeed; 1443 1444 /* Copy to tty. */ 1445 tp->t_ispeed = 0; 1446 tp->t_ospeed = t->c_ospeed; 1447 tp->t_cflag = t->c_cflag; 1448 1449 /* 1450 * Now load the channel control structure. 1451 */ 1452 1453 cz_wait_pci_doorbell(cz, "czparam"); 1454 1455 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, sc->sc_chanctl_comm_baud); 1456 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, sc->sc_chanctl_comm_data_l); 1457 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, sc->sc_chanctl_comm_parity); 1458 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, sc->sc_chanctl_hw_flow); 1459 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1460 1461 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1462 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLW); 1463 1464 cz_wait_pci_doorbell(cz, "czparam"); 1465 1466 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1467 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1468 1469 cz_wait_pci_doorbell(cz, "czparam"); 1470 1471 /* 1472 * Update the tty layer's idea of the carrier bit, in case we changed 1473 * CLOCAL. We don't hang up here; we only do that by explicit 1474 * request. 1475 */ 1476 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1477 (void) (*tp->t_linesw->l_modem)(tp, ISSET(rs_status, C_RS_DCD)); 1478 1479 return (0); 1480 } 1481 1482 /* 1483 * czttystart: 1484 * 1485 * Start or restart transmission. 1486 */ 1487 void 1488 czttystart(struct tty *tp) 1489 { 1490 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1491 int s; 1492 1493 s = spltty(); 1494 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1495 goto out; 1496 1497 if (tp->t_outq.c_cc <= tp->t_lowat) { 1498 if (ISSET(tp->t_state, TS_ASLEEP)) { 1499 CLR(tp->t_state, TS_ASLEEP); 1500 wakeup(&tp->t_outq); 1501 } 1502 selwakeup(&tp->t_wsel); 1503 if (tp->t_outq.c_cc == 0) 1504 goto out; 1505 } 1506 1507 cztty_transmit(sc, tp); 1508 out: 1509 splx(s); 1510 } 1511 1512 /* 1513 * czttystop: 1514 * 1515 * Stop output, e.g., for ^S or output flush. 1516 */ 1517 void 1518 czttystop(struct tty *tp, int flag) 1519 { 1520 1521 /* 1522 * XXX We don't do anything here, yet. Mostly, I don't know 1523 * XXX exactly how this should be implemented on this device. 1524 * XXX We've given a big chunk of data to the MIPS already, 1525 * XXX and I don't know how we request the MIPS to stop sending 1526 * XXX the data. So, punt for now. --thorpej 1527 */ 1528 } 1529 1530 /* 1531 * cztty_diag: 1532 * 1533 * Issue a scheduled diagnostic message. 1534 */ 1535 void 1536 cztty_diag(void *arg) 1537 { 1538 struct cztty_softc *sc = arg; 1539 struct cz_softc *cz = CZTTY_CZ(sc); 1540 u_int overflows, parity_errors, framing_errors; 1541 int s; 1542 1543 s = spltty(); 1544 1545 overflows = sc->sc_overflows; 1546 sc->sc_overflows = 0; 1547 1548 parity_errors = sc->sc_parity_errors; 1549 sc->sc_parity_errors = 0; 1550 1551 framing_errors = sc->sc_framing_errors; 1552 sc->sc_framing_errors = 0; 1553 1554 sc->sc_errors = 0; 1555 1556 splx(s); 1557 1558 log(LOG_WARNING, 1559 "%s: channel %d: %u overflow%s, %u parity, %u framing error%s\n", 1560 cz->cz_dev.dv_xname, sc->sc_channel, 1561 overflows, overflows == 1 ? "" : "s", 1562 parity_errors, 1563 framing_errors, framing_errors == 1 ? "" : "s"); 1564 } 1565 1566 /* 1567 * tx and rx ring buffer size macros: 1568 * 1569 * The transmitter and receiver both use ring buffers. For each one, there 1570 * is a get (consumer) and a put (producer) offset. The get value is the 1571 * next byte to be read from the ring, and the put is the next one to be 1572 * put into the ring. get == put means the ring is empty. 1573 * 1574 * For each ring, the firmware controls one of (get, put) and this driver 1575 * controls the other. For transmission, this driver updates put to point 1576 * past the valid data, and the firmware moves get as bytes are sent. Likewise 1577 * for receive, the driver controls put, and this driver controls get. 1578 */ 1579 #define TX_MOVEABLE(g, p, s) (((g) > (p)) ? ((g) - (p) - 1) : ((s) - (p))) 1580 #define RX_MOVEABLE(g, p, s) (((g) > (p)) ? ((s) - (g)) : ((p) - (g))) 1581 1582 /* 1583 * cztty_transmit() 1584 * 1585 * Look at the tty for this port and start sending. 1586 */ 1587 int 1588 cztty_transmit(struct cztty_softc *sc, struct tty *tp) 1589 { 1590 struct cz_softc *cz = CZTTY_CZ(sc); 1591 u_int move, get, put, size, address; 1592 #ifdef HOSTRAMCODE 1593 int error, done = 0; 1594 #else 1595 int done = 0; 1596 #endif 1597 1598 size = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFSIZE); 1599 get = CZTTY_BUF_READ(sc, BUFCTL_TX_GET); 1600 put = CZTTY_BUF_READ(sc, BUFCTL_TX_PUT); 1601 address = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFADDR); 1602 1603 while ((tp->t_outq.c_cc > 0) && ((move = TX_MOVEABLE(get, put, size)))){ 1604 #ifdef HOSTRAMCODE 1605 if (0) { 1606 move = min(tp->t_outq.c_cc, move); 1607 error = q_to_b(&tp->t_outq, 0, move); 1608 if (error != move) { 1609 printf("%s: channel %d: error moving to " 1610 "transmit buf\n", cz->cz_dev.dv_xname, 1611 sc->sc_channel); 1612 move = error; 1613 } 1614 } else { 1615 #endif 1616 move = min(ndqb(&tp->t_outq, 0), move); 1617 bus_space_write_region_1(cz->cz_win_st, cz->cz_win_sh, 1618 address + put, tp->t_outq.c_cf, move); 1619 ndflush(&tp->t_outq, move); 1620 #ifdef HOSTRAMCODE 1621 } 1622 #endif 1623 1624 put = ((put + move) % size); 1625 done = 1; 1626 } 1627 if (done) { 1628 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, put); 1629 } 1630 return (done); 1631 } 1632 1633 int 1634 cztty_receive(struct cztty_softc *sc, struct tty *tp) 1635 { 1636 struct cz_softc *cz = CZTTY_CZ(sc); 1637 u_int get, put, size, address; 1638 int done = 0, ch; 1639 1640 size = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFSIZE); 1641 get = CZTTY_BUF_READ(sc, BUFCTL_RX_GET); 1642 put = CZTTY_BUF_READ(sc, BUFCTL_RX_PUT); 1643 address = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFADDR); 1644 1645 while ((get != put) && ((tp->t_canq.c_cc + tp->t_rawq.c_cc) < tp->t_hiwat)) { 1646 #ifdef HOSTRAMCODE 1647 if (hostram) 1648 ch = ((char *)fifoaddr)[get]; 1649 } else { 1650 #endif 1651 ch = bus_space_read_1(cz->cz_win_st, cz->cz_win_sh, 1652 address + get); 1653 #ifdef HOSTRAMCODE 1654 } 1655 #endif 1656 (*tp->t_linesw->l_rint)(ch, tp); 1657 get = (get + 1) % size; 1658 done = 1; 1659 } 1660 if (done) { 1661 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, get); 1662 } 1663 return (done); 1664 } 1665