1 /* $NetBSD: esoreg.h,v 1.5 1999/12/10 19:13:00 kleink Exp $ */ 2 3 /* 4 * Copyright (c) 1999 Klaus J. Klein 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #ifndef _DEV_PCI_ESOREG_H_ 32 #define _DEV_PCI_ESOREG_H_ 33 34 /* 35 * PCI Configuration Registers 36 */ 37 #define ESO_PCI_BAR_IO 0x10 /* I/O space base address */ 38 #define ESO_PCI_BAR_SB 0x14 /* SB I/O space base address */ 39 #define ESO_PCI_BAR_VC 0x18 /* VC I/O space base address */ 40 #define ESO_PCI_BAR_MPU 0x1c /* MPU-401 I/O space base address */ 41 #define ESO_PCI_BAR_GAME 0x20 /* Game port I/O space base address */ 42 #define ESO_PCI_S1C 0x50 /* Solo-1 Configuration */ 43 #define ESO_PCI_S1C_IRQP_MASK 0x0006000 /* ISA IRQ emulation policy */ 44 #define ESO_PCI_S1C_DMAP_MASK 0x0000700 /* DMA policy */ 45 #define ESO_PCI_DDMAC 0x60 /* DDMA Control base address */ 46 #define ESO_PCI_DDMAC_DE 0x01 /* Distributed DMA enable */ 47 48 /* PCI Revision IDs of the Solo-1 PCI AudioDrive family */ 49 #define ESO_PCI_REVISION_ES1938 0x00 /* ES1938 */ 50 #define ESO_PCI_REVISION_ES1946 0x01 /* ES1946 */ 51 #define ESO_PCI_REVISION_ES1946E 0x02 /* ES1946 Revision E */ 52 53 /* 54 * Check the validity of a PCI I/O space base address for use in 55 * ESO_PCI_DDMAC; see the relevant comment in the attach function. 56 */ 57 #define ESO_VALID_DDMAC_BASE(addr) \ 58 (((addr) & 0x03ff) != 0) 59 60 /* 61 * I/O Port offsets 62 */ 63 /* I/O Device ports */ 64 #define ESO_IO_A2DMAA 0x00 /* [RW] Audio 2 b/c DMA address */ 65 #define ESO_IO_A2DMAC 0x04 /* [RW] Audio 2 b/c DMA count */ 66 #define ESO_IO_A2DMAM 0x06 /* [RW] Solo-1 mode register */ 67 #define ESO_IO_A2DMAM_DMAENB 0x02 /* DMA enable */ 68 #define ESO_IO_A2DMAM_AUTO 0x08 /* Auto-Initialize DMA enable */ 69 #define ESO_IO_IRQCTL 0x07 /* [RW] IRQ control register */ 70 #define ESO_IO_IRQCTL_A1IRQ 0x10 /* Audio 1 IRQ */ 71 #define ESO_IO_IRQCTL_A2IRQ 0x20 /* Audio 2 IRQ */ 72 #define ESO_IO_IRQCTL_HVIRQ 0x40 /* Hardware volume IRQ */ 73 #define ESO_IO_IRQCTL_MPUIRQ 0x80 /* MPU-401 IRQ */ 74 #define ESO_IO_IRQCTL_MASK 0xf0 /* all of the above */ 75 76 /* Audio/FM Device ports */ 77 #define ESO_SB_STATUS 0x00 /* [R] FM Status */ 78 #define ESO_SB_LBA 0x00 /* [W] FM Low Bank Address */ 79 #define ESO_SB_LBDW 0x01 /* [W] FM Low Bank Data Write */ 80 #define ESO_SB_HBA 0x02 /* [W] FM High Bank Address */ 81 #define ESO_SB_HBDW 0x03 /* [W] FM High Bank Data Write */ 82 #define ESO_SB_MIXERADDR 0x04 /* [RW] Mixer Address Register */ 83 #define ESO_SB_MIXERDATA 0x05 /* [RW] Mixer Data Register */ 84 #define ESO_SB_RESET 0x06 /* [W] Reset */ 85 #define ESO_SB_RESET_SW 0x01 /* SW Reset */ 86 #define ESO_SB_RESET_FIFO 0x02 /* FIFO Reset */ 87 #define ESO_SB_STATUSFLAGS 0x06 /* [R] Status Flags */ 88 #define ESO_SB_PMR 0x07 /* [RW] Power Management Register */ 89 #define ESO_SB_RDR 0x0a /* [R] Read Data Register */ 90 #define ESO_SB_RDR_RESETMAGIC 0xaa /* Indicates SW reset completion */ 91 #define ESO_SB_WDR 0x0c /* [W] Write Data Register */ 92 #define ESO_SB_RSR 0x0c /* [R] Read Status Register */ 93 #define ESO_SB_RSR_BUSY 0x80 /* WDR not available or Solo-1 busy */ 94 #define ESO_SB_RBSR 0x0e /* [R] Read Buffer Status Register */ 95 #define ESO_SB_RBSR_RDAV 0x80 /* Data available in RDR */ 96 #define ESO_SB_PIOAFR 0x0f /* [RW] PIO Access to FIFO Register */ 97 98 /* Game Port Device ports */ 99 #define ESO_GAME_JSTK_OFFSET 0x01 /* Offset from base address */ 100 #define ESO_GAME_JSTK_SIZE 0x01 /* Size of region */ 101 102 /* (Audio 1) DMAC Device ports */ 103 #define ESO_DMAC_DMAA 0x00 /* [RW] DMA Current/Base Address */ 104 #define ESO_DMAC_DMAC 0x04 /* [RW] DMA Current/Base Count */ 105 #define ESO_DMAC_COMMAND 0x08 /* [W] DMA Command */ 106 #define ESO_DMAC_COMMAND_ENB 0x04 /* Controller enable */ 107 #define ESO_DMAC_COMMAND_DREQPOL 0x40 /* DREQ signal polarity */ 108 #define ESO_DMAC_COMMAND_DACKPOL 0x80 /* DACK signal polarity */ 109 #define ESO_DMAC_STATUS 0x08 /* [R] DMA Status */ 110 #define ESO_DMAC_MODE 0x0b /* [W] DMA Mode */ 111 #define ESO_DMAC_CLEAR 0x0d /* [W] DMA Master Clear */ 112 #define ESO_DMAC_MASK 0x0f /* [RW] DMA Mask */ 113 #define ESO_DMAC_MASK_MASK 0x01 /* Mask DREQ */ 114 115 /* Controller commands */ 116 #define ESO_CMD_RCR 0xc0 /* Read ext. controller registers */ 117 #define ESO_CMD_EXTENB 0xc6 /* Enable Solo-1 Extension commands */ 118 #define ESO_CMD_EXTDIS 0xc7 /* Disable Solo-1 Extension commands */ 119 120 /* Mixer registers */ 121 #define ESO_MIXREG_RESET 0x00 /* Reset mixer registers */ 122 #define ESO_MIXREG_RESET_RESET 0x00 /* Any value will do */ 123 #define ESO_MIXREG_PVR_MIC 0x1a /* Playback mixer: Microphone */ 124 #define ESO_MIXREG_ERS 0x1c /* Extended record source */ 125 #define ESO_MIXREG_ERS_MIC 0x00 /* Microphone */ 126 #define ESO_MIXREG_ERS_CD 0x02 /* CD */ 127 #define ESO_MIXREG_ERS_MIC2 0x04 /* Microphone (again?) */ 128 #define ESO_MIXREG_ERS_MIXER 0x05 /* Record mixer */ 129 #define ESO_MIXREG_ERS_LINE 0x06 /* Line */ 130 #define ESO_MIXREG_ERS_MUTE 0x10 /* Mutes input to filters for rec */ 131 #define ESO_MIXREG_PCSVR 0x3c /* PC Speaker Volume Register */ 132 #define ESO_MIXREG_PCSVR_RESV 0xf8 /* Reserved */ 133 #define ESO_MIXREG_PVR_SYNTH 0x36 /* Playback mixer: FM/Synth */ 134 #define ESO_MIXREG_PVR_CD 0x38 /* Playback mixer: AuxA/CD */ 135 #define ESO_MIXREG_PVR_AUXB 0x3a /* Playback mixer: AuxB */ 136 #define ESO_MIXREG_PCSPKR_VOL 0x3c /* PC speaker volume */ 137 #define ESO_MIXREG_PVR_LINE 0x3e /* Playback mixer: Line */ 138 #define ESO_MIXREG_SPAT 0x50 /* Spatializer Enable and Mode */ 139 #define ESO_MIXREG_SPAT_MONO 0x02 /* 0 = Stereo in, 1 = Mono in */ 140 #define ESO_MIXREG_SPAT_RSTREL 0x04 /* 0 = reset, 1 = release from reset */ 141 #define ESO_MIXREG_SPAT_ENB 0x08 /* Spatializer Enable */ 142 #define ESO_MIXREG_SPATLVL 0x52 /* Spatializer Level */ 143 #define ESO_MIXREG_LMVM 0x60 /* Left Master Volume and Mute */ 144 #define ESO_MIXREG_LMVM_MUTE 0x40 /* Mute enable */ 145 #define ESO_MIXREG_LHVCC 0x61 /* Left Hardware Volume Control Ctr */ 146 #define ESO_MIXREG_RMVM 0x62 /* Right Master Volume and Mute */ 147 #define ESO_MIXREG_RMVM_MUTE 0x40 /* Mute enable */ 148 #define ESO_MIXREG_RHVCC 0x63 /* Left Hardware Volume Control Ctr */ 149 #define ESO_MIXREG_MVCTL 0x64 /* Master Volume Control */ 150 #define ESO_MIXREG_MVCTL_HVIRQM 0x02 /* Hardware Volume Control intr mask */ 151 #define ESO_MIXREG_MVCTL_MPUIRQM 0x40 /* MPU-401 interrupt unmask */ 152 #define ESO_MIXREG_MVCTL_SPLIT 0x80 /* Split xHVCC/xMVM registers */ 153 #define ESO_MIXREG_CHVIR 0x66 /* Clear Hardware Volume IRQ */ 154 #define ESO_MIXREG_CHVIR_CHVIR 0x00 /* Any value will do */ 155 #define ESO_MIXREG_RVR_MIC 0x68 /* Record mixer: Microphone */ 156 #define ESO_MIXREG_RVR_A2 0x69 /* Record mixer: Audio 2 */ 157 #define ESO_MIXREG_RVR_CD 0x6a /* Record mixer: AuxA/CD */ 158 #define ESO_MIXREG_RVR_SYNTH 0x6b /* Record mixer: FM/Synth */ 159 #define ESO_MIXREG_RVR_AUXB 0x6c /* Record mixer: AuxB */ 160 #define ESO_MIXREG_PVR_MONO 0x6d /* Playback mixer: Mono In */ 161 #define ESO_MIXREG_RVR_LINE 0x6e /* Record mixer: Line */ 162 #define ESO_MIXREG_RVR_MONO 0x6f /* Record mixer: Mono In */ 163 #define ESO_MIXREG_A2SRG 0x70 /* Audio 2 Sample Rate Generator */ 164 #define ESO_MIXREG_A2MODE 0x71 /* Audio 2 Mode */ 165 #define ESO_MIXREG_A2MODE_ASYNC 0x02 /* A2 SRG and FLTDIV async wrt A1 */ 166 #define ESO_MIXREG_A2MODE_NEWA1 0x20 /* New-style SRG for Audio 1 */ 167 #define ESO_MIXREG_A2FLTDIV 0x72 /* Audio 2 Filter Rate Divider */ 168 #define ESO_MIXREG_A2TCRLO 0x74 /* Audio 2 Transfer Count Reload LO */ 169 #define ESO_MIXREG_A2TCRHI 0x76 /* Audio 2 Transfer Count Reload HI */ 170 #define ESO_MIXREG_A2C1 0x78 /* Audio 2 Control 1 */ 171 #define ESO_MIXREG_A2C1_FIFOENB 0x01 /* FIFO enable */ 172 #define ESO_MIXREG_A2C1_DMAENB 0x02 /* DMA enable */ 173 #define ESO_MIXREG_A2C1_RESV0 0xcc /* Reserved, always write 0 XXXb5? */ 174 #define ESO_MIXREG_A2C1_AUTO 0x10 /* Auto-initialize mode */ 175 #define ESO_MIXREG_A2C2 0x7a /* Audio 2 Control 2 */ 176 #define ESO_MIXREG_A2C2_16BIT 0x01 /* 1 = 16-bit, 0 = 8-bit */ 177 #define ESO_MIXREG_A2C2_STEREO 0x02 /* 1 = Stereo, 0 = Mono */ 178 #define ESO_MIXREG_A2C2_SIGNED 0x04 /* 1 = Signed data, 0 = unsigned */ 179 #define ESO_MIXREG_A2C2_RESV0 0x38 /* Reserved, always write 0 */ 180 #define ESO_MIXREG_A2C2_IRQM 0x40 /* IRQ mask */ 181 #define ESO_MIXREG_A2C2_IRQ 0x80 /* IRQ latch */ 182 #define ESO_MIXREG_PVR_A2 0x7c /* Playback mixer: Audio 2 */ 183 #define ESO_MIXREG_MPM 0x7d /* Microphone Preamp, Mono In/Out */ 184 #define ESO_MIXREG_MPM_MOMASK 0x03 /* MONO_OUT value mask */ 185 #define ESO_MIXREG_MPM_MOMUTE 0x00 /* MONO_OUT mute */ 186 #define ESO_MIXREG_MPM_MOCINR 0x01 /* MONO_OUT source CIN_R */ 187 #define ESO_MIXREG_MPM_MOA2R 0x02 /* MONO_OUT source Audio 2 Right */ 188 #define ESO_MIXREG_MPM_MOREC 0x03 /* MONO_OUT source record stage */ 189 #define ESO_MIXREG_MPM_PREAMP 0x08 /* Preamp enable */ 190 #define ESO_MIXREG_MPM_RESV0 0xf0 /* Reserved, always write 0 */ 191 192 /* Controller registers */ 193 #define ESO_CTLREG_SRG 0xa1 /* Sample Rate Generator */ 194 #define ESO_CTLREG_FLTDIV 0xa2 /* Filter Rate Divider */ 195 #define ESO_CTLREG_A1TCRLO 0xa4 /* Audio 1 Transfer Count Reload LO */ 196 #define ESO_CTLREG_A1TCRHI 0xa5 /* Audio 1 Transfer Count Reload HI */ 197 #define ESO_CTLREG_ACTL 0xa8 /* Analog Control */ 198 #define ESO_CTLREG_ACTL_STEREO 0x01 /* DMA converters stereo */ 199 #define ESO_CTLREG_ACTL_MONO 0x02 /* DMA converters mono */ 200 #define ESO_CTLREG_ACTL_RESV1 0x10 /* Reserved, always write 1 */ 201 #define ESO_CTLREG_ACTL_RESV0 0xe4 /* Reserved, always write 0 */ 202 #define ESO_CTLREG_ACTL_RECMON 0x08 /* Record Monitor enable */ 203 #define ESO_CTLREG_LAIC 0xb1 /* Legacy Audio Interrupt Control */ 204 #define ESO_CTLREG_LAIC_PINENB 0x10 /* Interrupt pin enable */ 205 #define ESO_CTLREG_LAIC_EXTENB 0x40 /* Extended mode IRQ enable */ 206 #define ESO_CTLREG_DRQCTL 0xb2 /* DRQ Control */ 207 #define ESO_CTLREG_DRQCTL_ENB1 0x10 /* Supposedly no function, but ... */ 208 #define ESO_CTLREG_DRQCTL_EXTENB 0x40 /* Extended mode DRQ enable */ 209 #define ESO_CTLREG_RECLVL 0xb4 /* Record Level */ 210 #define ESO_CTLREG_A1C1 0xb7 /* Audio 1 Control 1 */ 211 #define ESO_CTLREG_A1C1_LOAD 0x01 /* Generate load signal */ 212 #define ESO_CTLREG_A1C1_RESV0 0x02 /* Reserved, always write 0 */ 213 #define ESO_CTLREG_A1C1_16BIT 0x04 /* 1 = 16-bit, 0 = 8-bit */ 214 #define ESO_CTLREG_A1C1_STEREO 0x08 /* DMA FIFO Stereo */ 215 #define ESO_CTLREG_A1C1_RESV1 0x10 /* Reserved, always write 1 */ 216 #define ESO_CTLREG_A1C1_SIGNED 0x20 /* 1 = Signed data, 0 = unsigned */ 217 #define ESO_CTLREG_A1C1_MONO 0x40 /* DMA FIFO Mono */ 218 #define ESO_CTLREG_A1C1_FIFOENB 0x80 /* DMA FIFO enable */ 219 #define ESO_CTLREG_A1C2 0xb8 /* Audio 1 Control 2 */ 220 #define ESO_CTLREG_A1C2_DMAENB 0x01 /* DMA enable */ 221 #define ESO_CTLREG_A1C2_READ 0x02 /* 1 = DMA read/ADC, 0 = write/DAC */ 222 #define ESO_CTLREG_A1C2_AUTO 0x04 /* Auto-initialize DMA enable */ 223 #define ESO_CTLREG_A1C2_ADC 0x08 /* 1 = ADC mode, 0 = DAC mode */ 224 #define ESO_CTLREG_A1TT 0xb9 /* Audio 1 Transfer Type */ 225 #define ESO_CTLREG_A1TT_SINGLE 0x00 /* Single-Transfer */ 226 #define ESO_CTLREG_A1TT_DEMAND2 0x01 /* Demand-Transfer, 2 bytes/DREQ */ 227 #define ESO_CTLREG_A1TT_DEMAND4 0x02 /* Demand-Transfer, 4 bytes/DREQ */ 228 229 /* 230 * Sample rate related constants. 231 * Note: the use of these clock sources must be explicitly enabled for Audio 1. 232 */ 233 #define ESO_MINRATE 6000 234 #define ESO_MAXRATE 48000 235 #define ESO_CLK0 793800L /* Clock source 0 frequency */ 236 #define ESO_CLK1 768000L /* Clock source 1 frequency */ 237 #define ESO_CLK1_SELECT 0x80 /* MSb of divider selects clock src */ 238 239 /* 240 * Upper bounds on several polling loop iterations. 241 */ 242 #define ESO_RESET_TIMEOUT 5000 243 #define ESO_RDR_TIMEOUT 5000 244 #define ESO_WDR_TIMEOUT 5000 245 246 /* 247 * Mixer state data conversions. 248 */ 249 /* Truncate MI 8-bit precision gain values to the width of chip registers. */ 250 #define ESO_GAIN_TO_3BIT(x) ((x) & 0xe0) 251 #define ESO_GAIN_TO_4BIT(x) ((x) & 0xf0) 252 #define ESO_GAIN_TO_6BIT(x) ((x) & 0xfc) 253 /* Convert two 4-bit gain values to standard mixer stereo register layout. */ 254 #define ESO_4BIT_GAIN_TO_STEREO(l,r) ((l) | ((r) >> 4)) 255 256 #endif /* !_DEV_PCI_ESOREG_H_ */ 257