1 /* $NetBSD: hifn7751reg.h,v 1.1 2000/10/12 02:59:59 itojun Exp $ */ 2 /* $OpenBSD: hifn7751reg.h,v 1.15 2000/09/21 13:34:58 jason Exp $ */ 3 4 /* 5 * Invertex AEON / Hi/fn 7751 driver 6 * Copyright (c) 1999 Invertex Inc. All rights reserved. 7 * Copyright (c) 1999 Theo de Raadt 8 * Copyright (c) 2000 Network Security Technologies, Inc. 9 * http://www.netsec.net 10 * 11 * Please send any comments, feedback, bug-fixes, or feature requests to 12 * software@invertex.com. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. The name of the author may not be used to endorse or promote products 24 * derived from this software without specific prior written permission. 25 * 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 29 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 31 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 32 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 36 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 #ifndef __DEV_PCI_HIFN7751REG_H__ 39 #define __DEV_PCI_HIFN7751REG_H__ 40 41 #include <machine/endian.h> 42 43 /* 44 * Some PCI configuration space offset defines. The names were made 45 * identical to the names used by the Linux kernel. 46 */ 47 #define HIFN_BAR0 (PCI_MAPREG_START + 0) /* PUC register map */ 48 #define HIFN_BAR1 (PCI_MAPREG_START + 4) /* DMA register map */ 49 50 /* 51 * Some configurable values for the driver 52 */ 53 #define HIFN_D_CMD_RSIZE 24 54 #define HIFN_D_SRC_RSIZE 80 55 #define HIFN_D_DST_RSIZE 80 56 #define HIFN_D_RES_RSIZE 24 57 58 /* 59 * The values below should multiple of 4 -- and be large enough to handle 60 * any command the driver implements. 61 * 62 * MAX_COMMAND = base command + mac command + encrypt command + 63 * mac-key + des-iv + 3des-key 64 * MAX_RESULT = base result + mac result + mac + encrypt result 65 * 66 * 67 */ 68 #define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 8 + 24) 69 #define HIFN_MAX_RESULT (8 + 4 + 20 + 4) 70 71 /* 72 * hifn_desc_t 73 * 74 * Holds an individual descriptor for any of the rings. 75 */ 76 typedef struct hifn_desc { 77 volatile u_int32_t l; /* length and status bits */ 78 volatile u_int32_t p; 79 } hifn_desc_t; 80 81 /* 82 * Masks for the "length" field of struct hifn_desc. 83 */ 84 #define HIFN_D_LENGTH 0x0000ffff /* length bit mask */ 85 #define HIFN_D_MASKDONEIRQ 0x02000000 /* mask the done interrupt */ 86 #define HIFN_D_DESTOVER 0x04000000 /* destination overflow */ 87 #define HIFN_D_OVER 0x08000000 /* overflow */ 88 #define HIFN_D_LAST 0x20000000 /* last descriptor in chain */ 89 #define HIFN_D_JUMP 0x40000000 /* jump descriptor */ 90 #define HIFN_D_VALID 0x80000000 /* valid bit */ 91 92 /* 93 * hifn_callback_t 94 * 95 * Type for callback function when dest data is ready. 96 */ 97 typedef void (*hifn_callback_t)(hifn_command_t *); 98 99 /* 100 * Data structure to hold all 4 rings and any other ring related data. 101 */ 102 struct hifn_dma { 103 /* 104 * Descriptor rings. We add +1 to the size to accomidate the 105 * jump descriptor. 106 */ 107 struct hifn_desc cmdr[HIFN_D_CMD_RSIZE+1]; 108 struct hifn_desc srcr[HIFN_D_SRC_RSIZE+1]; 109 struct hifn_desc dstr[HIFN_D_DST_RSIZE+1]; 110 struct hifn_desc resr[HIFN_D_RES_RSIZE+1]; 111 112 struct hifn_command *hifn_commands[HIFN_D_RES_RSIZE]; 113 114 u_char command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND]; 115 u_char result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT]; 116 117 /* 118 * Our current positions for insertion and removal from the desriptor 119 * rings. 120 */ 121 int cmdi, srci, dsti, resi; 122 volatile int cmdu, srcu, dstu, resu; 123 int cmdk, srck, dstk, resk; 124 }; 125 126 struct hifn_session { 127 int hs_flags; 128 u_int8_t hs_iv[HIFN_IV_LENGTH]; 129 }; 130 131 /* 132 * Holds data specific to a single HIFN board. 133 */ 134 struct hifn_softc { 135 struct device sc_dv; /* generic device */ 136 void * sc_ih; /* interrupt handler cookie */ 137 u_int32_t sc_drammodel; /* 1=dram, 0=sram */ 138 139 bus_space_handle_t sc_sh0, sc_sh1; 140 bus_space_tag_t sc_st0, sc_st1; 141 bus_dma_tag_t sc_dmat; 142 143 struct hifn_dma *sc_dma; 144 int32_t sc_cid; 145 int sc_maxses; 146 int sc_ramsize; 147 struct hifn_session sc_sessions[2048]; 148 }; 149 150 /* 151 * Processing Unit Registers (offset from BASEREG0) 152 */ 153 #define HIFN_0_PUDATA 0x00 /* Processing Unit Data */ 154 #define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */ 155 #define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */ 156 #define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */ 157 #define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */ 158 #define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */ 159 #define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */ 160 #define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */ 161 #define HIFN_0_SPACESIZE 0x20 /* Register space size */ 162 163 /* Processing Unit Control Register (HIFN_0_PUCTRL) */ 164 #define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */ 165 #define HIFN_PUCTRL_STOP 0x0008 /* stop pu */ 166 #define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */ 167 #define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */ 168 #define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */ 169 170 /* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */ 171 #define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */ 172 #define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */ 173 #define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ 174 #define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ 175 #define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */ 176 #define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */ 177 #define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */ 178 #define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */ 179 #define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */ 180 #define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */ 181 182 /* Processing Unit Configuration Register (HIFN_0_PUCNFG) */ 183 #define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */ 184 #define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */ 185 #define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */ 186 #define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */ 187 #define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */ 188 #define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */ 189 #define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */ 190 #define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */ 191 #define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */ 192 #define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */ 193 #define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */ 194 #define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */ 195 #define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */ 196 #define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */ 197 #define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */ 198 #define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */ 199 #define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */ 200 #define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */ 201 #define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */ 202 #define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */ 203 #define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */ 204 #define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */ 205 #define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */ 206 207 /* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */ 208 #define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */ 209 #define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */ 210 #define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ 211 #define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ 212 #define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */ 213 #define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */ 214 #define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */ 215 #define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */ 216 #define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */ 217 #define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */ 218 219 /* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */ 220 #define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */ 221 #define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */ 222 #define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ 223 #define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ 224 #define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */ 225 #define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */ 226 #define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */ 227 #define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */ 228 #define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */ 229 #define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */ 230 #define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */ 231 #define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */ 232 #define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */ 233 #define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */ 234 #define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */ 235 #define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */ 236 #define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */ 237 238 /* FIFO Status Register (HIFN_0_FIFOSTAT) */ 239 #define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */ 240 #define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */ 241 242 /* FIFO Configuration Register (HIFN_0_FIFOCNFG) */ 243 #define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as 1 */ 244 245 /* 246 * DMA Interface Registers (offset from BASEREG1) 247 */ 248 #define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */ 249 #define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */ 250 #define HIFN_1_DMA_RRAR 0x2c /* DMA Resultt Ring Address */ 251 #define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */ 252 #define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ 253 #define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */ 254 #define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */ 255 #define HIFN_1_REVID 0x98 /* Revision ID */ 256 257 /* DMA Status and Control Register (HIFN_1_DMA_CSR) */ 258 #define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */ 259 #define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */ 260 #define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */ 261 #define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */ 262 #define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */ 263 #define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */ 264 #define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */ 265 #define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */ 266 #define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */ 267 #define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */ 268 #define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */ 269 #define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */ 270 #define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */ 271 #define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */ 272 #define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */ 273 #define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */ 274 #define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */ 275 #define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */ 276 #define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */ 277 #define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */ 278 #define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */ 279 #define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */ 280 #define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */ 281 #define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */ 282 #define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */ 283 #define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */ 284 #define HIFN_DMACSR_S_OVER 0x00000200 /* Source Ring Overflow */ 285 #define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */ 286 #define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */ 287 #define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */ 288 #define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */ 289 #define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */ 290 #define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */ 291 #define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */ 292 #define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */ 293 #define HIFN_DMACSR_C_EIRQ 0x00000001 /* Command Ring Engine IRQ */ 294 295 /* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */ 296 #define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */ 297 #define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */ 298 #define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */ 299 #define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */ 300 #define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */ 301 #define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */ 302 #define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */ 303 #define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */ 304 #define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */ 305 #define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */ 306 #define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */ 307 #define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */ 308 #define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */ 309 #define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */ 310 #define HIFN_DMAIER_S_OVER 0x00000200 /* Source Ring Overflow */ 311 #define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */ 312 #define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */ 313 #define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */ 314 #define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */ 315 #define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */ 316 317 /* DMA Configuration Register (HIFN_1_DMA_CNFG) */ 318 #define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */ 319 #define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */ 320 #define HIFN_DMACNFG_UNLOCK 0x00000800 321 #define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */ 322 #define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */ 323 #define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */ 324 #define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */ 325 #define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */ 326 327 #define WRITE_REG_0(sc,reg,val) \ 328 bus_space_write_4((sc)->sc_st0, (sc)->sc_sh0, reg, val) 329 #define READ_REG_0(sc,reg) \ 330 bus_space_read_4((sc)->sc_st0, (sc)->sc_sh0, reg) 331 332 /* 333 * Register offsets in register set 1 334 */ 335 336 #define HIFN_UNLOCK_SECRET1 0xf4 337 #define HIFN_UNLOCK_SECRET2 0xfc 338 339 #define WRITE_REG_1(sc,reg,val) \ 340 bus_space_write_4((sc)->sc_st1, (sc)->sc_sh1, reg, val) 341 #define READ_REG_1(sc,reg) \ 342 bus_space_read_4((sc)->sc_st1, (sc)->sc_sh1, reg) 343 344 /********************************************************************* 345 * Structs for board commands 346 * 347 *********************************************************************/ 348 349 /* 350 * Structure to help build up the command data structure. 351 */ 352 typedef struct hifn_base_command { 353 volatile u_int16_t masks; 354 volatile u_int16_t session_num; 355 volatile u_int16_t total_source_count; 356 volatile u_int16_t total_dest_count; 357 } hifn_base_command_t; 358 359 #define HIFN_BASE_CMD_MAC (0x1 << 10) 360 #define HIFN_BASE_CMD_CRYPT (0x1 << 11) 361 #define HIFN_BASE_CMD_DECODE (0x1 << 13) 362 363 /* 364 * Structure to help build up the command data structure. 365 */ 366 typedef struct hifn_crypt_command { 367 volatile u_int16_t masks; 368 volatile u_int16_t header_skip; 369 volatile u_int32_t source_count; 370 } hifn_crypt_command_t; 371 372 #define HIFN_CRYPT_CMD_ALG_MASK (0x3 << 0) 373 #define HIFN_CRYPT_CMD_ALG_DES (0x0 << 0) 374 #define HIFN_CRYPT_CMD_ALG_3DES (0x1 << 0) 375 #define HIFN_CRYPT_CMD_MODE_CBC (0x1 << 3) 376 #define HIFN_CRYPT_CMD_NEW_KEY (0x1 << 11) 377 #define HIFN_CRYPT_CMD_NEW_IV (0x1 << 12) 378 379 /* 380 * Structure to help build up the command data structure. 381 */ 382 typedef struct hifn_mac_command { 383 volatile u_int16_t masks; 384 volatile u_int16_t header_skip; 385 volatile u_int32_t source_count; 386 } hifn_mac_command_t; 387 388 #define HIFN_MAC_CMD_ALG_MD5 (0x1 << 0) 389 #define HIFN_MAC_CMD_ALG_SHA1 (0x0 << 0) 390 #define HIFN_MAC_CMD_MODE_HMAC (0x0 << 2) 391 #define HIFN_MAC_CMD_TRUNC (0x1 << 4) 392 #define HIFN_MAC_CMD_RESULT (0x1 << 5) 393 #define HIFN_MAC_CMD_APPEND (0x1 << 6) 394 /* 395 * MAC POS IPSec initiates authentication after encryption on encodes 396 * and before decryption on decodes. 397 */ 398 #define HIFN_MAC_CMD_POS_IPSEC (0x2 << 8) 399 #define HIFN_MAC_CMD_NEW_KEY (0x1 << 11) 400 401 /* 402 * The poll frequency and poll scalar defines are unshifted values used 403 * to set fields in the DMA Configuration Register. 404 */ 405 #ifndef HIFN_POLL_FREQUENCY 406 #define HIFN_POLL_FREQUENCY 0x1 407 #endif 408 409 #ifndef HIFN_POLL_SCALAR 410 #define HIFN_POLL_SCALAR 0x0 411 #endif 412 413 #endif /* __DEV_PCI_HIFN7751REG_H__ */ 414