1 /* $NetBSD: if_bge.c,v 1.388 2022/10/11 22:03:37 andvar Exp $ */
2
3 /*
4 * Copyright (c) 2001 Wind River Systems
5 * Copyright (c) 1997, 1998, 1999, 2001
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $
36 */
37
38 /*
39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD.
40 *
41 * NetBSD version by:
42 *
43 * Frank van der Linden <fvdl@wasabisystems.com>
44 * Jason Thorpe <thorpej@wasabisystems.com>
45 * Jonathan Stone <jonathan@dsg.stanford.edu>
46 *
47 * Originally written for FreeBSD by Bill Paul <wpaul@windriver.com>
48 * Senior Engineer, Wind River Systems
49 */
50
51 /*
52 * The Broadcom BCM5700 is based on technology originally developed by
53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
57 * frames, highly configurable RX filtering, and 16 RX and TX queues
58 * (which, along with RX filter rules, can be used for QOS applications).
59 * Other features, such as TCP segmentation, may be available as part
60 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
61 * firmware images can be stored in hardware and need not be compiled
62 * into the driver.
63 *
64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus.
66 *
67 * The BCM5701 is a single-chip solution incorporating both the BCM5700
68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
69 * does not support external SSRAM.
70 *
71 * Broadcom also produces a variation of the BCM5700 under the "Altima"
72 * brand name, which is functionally similar but lacks PCI-X support.
73 *
74 * Without external SSRAM, you can only have at most 4 TX rings,
75 * and the use of the mini RX ring is disabled. This seems to imply
76 * that these features are simply not available on the BCM5701. As a
77 * result, this driver does not implement any support for the mini RX
78 * ring.
79 */
80
81 #include <sys/cdefs.h>
82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.388 2022/10/11 22:03:37 andvar Exp $");
83
84 #include <sys/param.h>
85 #include <sys/types.h>
86
87 #include <sys/callout.h>
88 #include <sys/device.h>
89 #include <sys/kernel.h>
90 #include <sys/kmem.h>
91 #include <sys/mbuf.h>
92 #include <sys/rndsource.h>
93 #include <sys/socket.h>
94 #include <sys/sockio.h>
95 #include <sys/sysctl.h>
96 #include <sys/systm.h>
97
98 #include <net/if.h>
99 #include <net/if_dl.h>
100 #include <net/if_media.h>
101 #include <net/if_ether.h>
102 #include <net/bpf.h>
103
104 /* Headers for TCP Segmentation Offload (TSO) */
105 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */
106 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */
107 #include <netinet/ip.h> /* for struct ip */
108 #include <netinet/tcp.h> /* for struct tcphdr */
109
110 #include <dev/pci/pcireg.h>
111 #include <dev/pci/pcivar.h>
112 #include <dev/pci/pcidevs.h>
113
114 #include <dev/mii/mii.h>
115 #include <dev/mii/miivar.h>
116 #include <dev/mii/miidevs.h>
117 #include <dev/mii/brgphyreg.h>
118
119 #include <dev/pci/if_bgereg.h>
120 #include <dev/pci/if_bgevar.h>
121
122 #include <prop/proplib.h>
123
124 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
125
126
127 /*
128 * Tunable thresholds for rx-side bge interrupt mitigation.
129 */
130
131 /*
132 * The pairs of values below were obtained from empirical measurement
133 * on bcm5700 rev B2; they ar designed to give roughly 1 receive
134 * interrupt for every N packets received, where N is, approximately,
135 * the second value (rx_max_bds) in each pair. The values are chosen
136 * such that moving from one pair to the succeeding pair was observed
137 * to roughly halve interrupt rate under sustained input packet load.
138 * The values were empirically chosen to avoid overflowing internal
139 * limits on the bcm5700: increasing rx_ticks much beyond 600
140 * results in internal wrapping and higher interrupt rates.
141 * The limit of 46 frames was chosen to match NFS workloads.
142 *
143 * These values also work well on bcm5701, bcm5704C, and (less
144 * tested) bcm5703. On other chipsets, (including the Altima chip
145 * family), the larger values may overflow internal chip limits,
146 * leading to increasing interrupt rates rather than lower interrupt
147 * rates.
148 *
149 * Applications using heavy interrupt mitigation (interrupting every
150 * 32 or 46 frames) in both directions may need to increase the TCP
151 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain
152 * full link bandwidth, due to ACKs and window updates lingering
153 * in the RX queue during the 30-to-40-frame interrupt-mitigation window.
154 */
155 static const struct bge_load_rx_thresh {
156 int rx_ticks;
157 int rx_max_bds; }
158 bge_rx_threshes[] = {
159 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */
160 { 32, 2 },
161 { 50, 4 },
162 { 100, 8 },
163 { 192, 16 },
164 { 416, 32 },
165 { 598, 46 }
166 };
167 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0]))
168
169 /* XXX patchable; should be sysctl'able */
170 static int bge_auto_thresh = 1;
171 static int bge_rx_thresh_lvl;
172
173 static int bge_rxthresh_nodenum;
174
175 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
176
177 static uint32_t bge_chipid(const struct pci_attach_args *);
178 static int bge_can_use_msi(struct bge_softc *);
179 static int bge_probe(device_t, cfdata_t, void *);
180 static void bge_attach(device_t, device_t, void *);
181 static int bge_detach(device_t, int);
182 static void bge_release_resources(struct bge_softc *);
183
184 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]);
185 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
186 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
187 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
188 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
189
190 static void bge_txeof(struct bge_softc *);
191 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *);
192 static void bge_rxeof(struct bge_softc *);
193
194 static void bge_asf_driver_up (struct bge_softc *);
195 static void bge_tick(void *);
196 static void bge_stats_update(struct bge_softc *);
197 static void bge_stats_update_regs(struct bge_softc *);
198 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *);
199
200 static int bge_intr(void *);
201 static void bge_start(struct ifnet *);
202 static void bge_start_locked(struct ifnet *);
203 static int bge_ifflags_cb(struct ethercom *);
204 static int bge_ioctl(struct ifnet *, u_long, void *);
205 static int bge_init(struct ifnet *);
206 static int bge_init_locked(struct ifnet *);
207 static void bge_stop(struct ifnet *, int);
208 static void bge_stop_locked(struct ifnet *, bool);
209 static bool bge_watchdog_tick(struct ifnet *);
210 static int bge_ifmedia_upd(struct ifnet *);
211 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
212 static void bge_handle_reset_work(struct work *, void *);
213
214 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
215 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int);
216
217 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
218 static int bge_read_eeprom(struct bge_softc *, void *, int, int);
219 static void bge_setmulti(struct bge_softc *);
220
221 static void bge_handle_events(struct bge_softc *);
222 static int bge_alloc_jumbo_mem(struct bge_softc *);
223 static void bge_free_jumbo_mem(struct bge_softc *);
224 static void *bge_jalloc(struct bge_softc *);
225 static void bge_jfree(struct mbuf *, void *, size_t, void *);
226 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
227 static int bge_init_rx_ring_jumbo(struct bge_softc *);
228 static void bge_free_rx_ring_jumbo(struct bge_softc *);
229
230 static int bge_newbuf_std(struct bge_softc *, int);
231 static int bge_init_rx_ring_std(struct bge_softc *);
232 static void bge_fill_rx_ring_std(struct bge_softc *);
233 static void bge_free_rx_ring_std(struct bge_softc *m);
234
235 static void bge_free_tx_ring(struct bge_softc *m, bool);
236 static int bge_init_tx_ring(struct bge_softc *);
237
238 static int bge_chipinit(struct bge_softc *);
239 static int bge_blockinit(struct bge_softc *);
240 static int bge_phy_addr(struct bge_softc *);
241 static uint32_t bge_readmem_ind(struct bge_softc *, int);
242 static void bge_writemem_ind(struct bge_softc *, int, int);
243 static void bge_writembx(struct bge_softc *, int, int);
244 static void bge_writembx_flush(struct bge_softc *, int, int);
245 static void bge_writemem_direct(struct bge_softc *, int, int);
246 static void bge_writereg_ind(struct bge_softc *, int, int);
247 static void bge_set_max_readrq(struct bge_softc *);
248
249 static int bge_miibus_readreg(device_t, int, int, uint16_t *);
250 static int bge_miibus_writereg(device_t, int, int, uint16_t);
251 static void bge_miibus_statchg(struct ifnet *);
252
253 #define BGE_RESET_SHUTDOWN 0
254 #define BGE_RESET_START 1
255 #define BGE_RESET_SUSPEND 2
256 static void bge_sig_post_reset(struct bge_softc *, int);
257 static void bge_sig_legacy(struct bge_softc *, int);
258 static void bge_sig_pre_reset(struct bge_softc *, int);
259 static void bge_wait_for_event_ack(struct bge_softc *);
260 static void bge_stop_fw(struct bge_softc *);
261 static int bge_reset(struct bge_softc *);
262 static void bge_link_upd(struct bge_softc *);
263 static void bge_sysctl_init(struct bge_softc *);
264 static int bge_sysctl_verify(SYSCTLFN_PROTO);
265
266 static void bge_ape_lock_init(struct bge_softc *);
267 static void bge_ape_read_fw_ver(struct bge_softc *);
268 static int bge_ape_lock(struct bge_softc *, int);
269 static void bge_ape_unlock(struct bge_softc *, int);
270 static void bge_ape_send_event(struct bge_softc *, uint32_t);
271 static void bge_ape_driver_state_change(struct bge_softc *, int);
272
273 #ifdef BGE_DEBUG
274 #define DPRINTF(x) if (bgedebug) printf x
275 #define DPRINTFN(n, x) if (bgedebug >= (n)) printf x
276 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0)
277 int bgedebug = 0;
278 int bge_tso_debug = 0;
279 void bge_debug_info(struct bge_softc *);
280 #else
281 #define DPRINTF(x)
282 #define DPRINTFN(n, x)
283 #define BGE_TSO_PRINTF(x)
284 #endif
285
286 #ifdef BGE_EVENT_COUNTERS
287 #define BGE_EVCNT_INCR(ev) (ev).ev_count++
288 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val)
289 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val)
290 #else
291 #define BGE_EVCNT_INCR(ev) /* nothing */
292 #define BGE_EVCNT_ADD(ev, val) /* nothing */
293 #define BGE_EVCNT_UPD(ev, val) /* nothing */
294 #endif
295
296 #define VIDDID(a, b) PCI_VENDOR_ ## a, PCI_PRODUCT_ ## a ## _ ## b
297 /*
298 * The BCM5700 documentation seems to indicate that the hardware still has the
299 * Alteon vendor ID burned into it, though it should always be overridden by
300 * the value in the EEPROM. We'll check for it anyway.
301 */
302 static const struct bge_product {
303 pci_vendor_id_t bp_vendor;
304 pci_product_id_t bp_product;
305 const char *bp_name;
306 } bge_products[] = {
307 { VIDDID(ALTEON, BCM5700), "Broadcom BCM5700 Gigabit" },
308 { VIDDID(ALTEON, BCM5701), "Broadcom BCM5701 Gigabit" },
309 { VIDDID(ALTIMA, AC1000), "Altima AC1000 Gigabit" },
310 { VIDDID(ALTIMA, AC1001), "Altima AC1001 Gigabit" },
311 { VIDDID(ALTIMA, AC1003), "Altima AC1003 Gigabit" },
312 { VIDDID(ALTIMA, AC9100), "Altima AC9100 Gigabit" },
313 { VIDDID(APPLE, BCM5701), "APPLE BCM5701 Gigabit" },
314 { VIDDID(BROADCOM, BCM5700), "Broadcom BCM5700 Gigabit" },
315 { VIDDID(BROADCOM, BCM5701), "Broadcom BCM5701 Gigabit" },
316 { VIDDID(BROADCOM, BCM5702), "Broadcom BCM5702 Gigabit" },
317 { VIDDID(BROADCOM, BCM5702FE), "Broadcom BCM5702FE Fast" },
318 { VIDDID(BROADCOM, BCM5702X), "Broadcom BCM5702X Gigabit" },
319 { VIDDID(BROADCOM, BCM5703), "Broadcom BCM5703 Gigabit" },
320 { VIDDID(BROADCOM, BCM5703X), "Broadcom BCM5703X Gigabit" },
321 { VIDDID(BROADCOM, BCM5703_ALT),"Broadcom BCM5703 Gigabit" },
322 { VIDDID(BROADCOM, BCM5704C), "Broadcom BCM5704C Dual Gigabit" },
323 { VIDDID(BROADCOM, BCM5704S), "Broadcom BCM5704S Dual Gigabit" },
324 { VIDDID(BROADCOM, BCM5704S_ALT),"Broadcom BCM5704S Dual Gigabit" },
325 { VIDDID(BROADCOM, BCM5705), "Broadcom BCM5705 Gigabit" },
326 { VIDDID(BROADCOM, BCM5705F), "Broadcom BCM5705F Gigabit" },
327 { VIDDID(BROADCOM, BCM5705K), "Broadcom BCM5705K Gigabit" },
328 { VIDDID(BROADCOM, BCM5705M), "Broadcom BCM5705M Gigabit" },
329 { VIDDID(BROADCOM, BCM5705M_ALT),"Broadcom BCM5705M Gigabit" },
330 { VIDDID(BROADCOM, BCM5714), "Broadcom BCM5714 Gigabit" },
331 { VIDDID(BROADCOM, BCM5714S), "Broadcom BCM5714S Gigabit" },
332 { VIDDID(BROADCOM, BCM5715), "Broadcom BCM5715 Gigabit" },
333 { VIDDID(BROADCOM, BCM5715S), "Broadcom BCM5715S Gigabit" },
334 { VIDDID(BROADCOM, BCM5717), "Broadcom BCM5717 Gigabit" },
335 { VIDDID(BROADCOM, BCM5717C), "Broadcom BCM5717 Gigabit" },
336 { VIDDID(BROADCOM, BCM5718), "Broadcom BCM5718 Gigabit" },
337 { VIDDID(BROADCOM, BCM5719), "Broadcom BCM5719 Gigabit" },
338 { VIDDID(BROADCOM, BCM5720), "Broadcom BCM5720 Gigabit" },
339 { VIDDID(BROADCOM, BCM5721), "Broadcom BCM5721 Gigabit" },
340 { VIDDID(BROADCOM, BCM5722), "Broadcom BCM5722 Gigabit" },
341 { VIDDID(BROADCOM, BCM5723), "Broadcom BCM5723 Gigabit" },
342 { VIDDID(BROADCOM, BCM5725), "Broadcom BCM5725 Gigabit" },
343 { VIDDID(BROADCOM, BCM5727), "Broadcom BCM5727 Gigabit" },
344 { VIDDID(BROADCOM, BCM5750), "Broadcom BCM5750 Gigabit" },
345 { VIDDID(BROADCOM, BCM5751), "Broadcom BCM5751 Gigabit" },
346 { VIDDID(BROADCOM, BCM5751F), "Broadcom BCM5751F Gigabit" },
347 { VIDDID(BROADCOM, BCM5751M), "Broadcom BCM5751M Gigabit" },
348 { VIDDID(BROADCOM, BCM5752), "Broadcom BCM5752 Gigabit" },
349 { VIDDID(BROADCOM, BCM5752M), "Broadcom BCM5752M Gigabit" },
350 { VIDDID(BROADCOM, BCM5753), "Broadcom BCM5753 Gigabit" },
351 { VIDDID(BROADCOM, BCM5753F), "Broadcom BCM5753F Gigabit" },
352 { VIDDID(BROADCOM, BCM5753M), "Broadcom BCM5753M Gigabit" },
353 { VIDDID(BROADCOM, BCM5754), "Broadcom BCM5754 Gigabit" },
354 { VIDDID(BROADCOM, BCM5754M), "Broadcom BCM5754M Gigabit" },
355 { VIDDID(BROADCOM, BCM5755), "Broadcom BCM5755 Gigabit" },
356 { VIDDID(BROADCOM, BCM5755M), "Broadcom BCM5755M Gigabit" },
357 { VIDDID(BROADCOM, BCM5756), "Broadcom BCM5756 Gigabit" },
358 { VIDDID(BROADCOM, BCM5761), "Broadcom BCM5761 Gigabit" },
359 { VIDDID(BROADCOM, BCM5761E), "Broadcom BCM5761E Gigabit" },
360 { VIDDID(BROADCOM, BCM5761S), "Broadcom BCM5761S Gigabit" },
361 { VIDDID(BROADCOM, BCM5761SE), "Broadcom BCM5761SE Gigabit" },
362 { VIDDID(BROADCOM, BCM5762), "Broadcom BCM5762 Gigabit" },
363 { VIDDID(BROADCOM, BCM5764), "Broadcom BCM5764 Gigabit" },
364 { VIDDID(BROADCOM, BCM5780), "Broadcom BCM5780 Gigabit" },
365 { VIDDID(BROADCOM, BCM5780S), "Broadcom BCM5780S Gigabit" },
366 { VIDDID(BROADCOM, BCM5781), "Broadcom BCM5781 Gigabit" },
367 { VIDDID(BROADCOM, BCM5782), "Broadcom BCM5782 Gigabit" },
368 { VIDDID(BROADCOM, BCM5784M), "BCM5784M NetLink 1000baseT" },
369 { VIDDID(BROADCOM, BCM5785F), "BCM5785F NetLink 10/100" },
370 { VIDDID(BROADCOM, BCM5785G), "BCM5785G NetLink 1000baseT" },
371 { VIDDID(BROADCOM, BCM5786), "Broadcom BCM5786 Gigabit" },
372 { VIDDID(BROADCOM, BCM5787), "Broadcom BCM5787 Gigabit" },
373 { VIDDID(BROADCOM, BCM5787F), "Broadcom BCM5787F 10/100" },
374 { VIDDID(BROADCOM, BCM5787M), "Broadcom BCM5787M Gigabit" },
375 { VIDDID(BROADCOM, BCM5788), "Broadcom BCM5788 Gigabit" },
376 { VIDDID(BROADCOM, BCM5789), "Broadcom BCM5789 Gigabit" },
377 { VIDDID(BROADCOM, BCM5901), "Broadcom BCM5901 Fast" },
378 { VIDDID(BROADCOM, BCM5901A2), "Broadcom BCM5901A2 Fast" },
379 { VIDDID(BROADCOM, BCM5903M), "Broadcom BCM5903M Fast" },
380 { VIDDID(BROADCOM, BCM5906), "Broadcom BCM5906 Fast" },
381 { VIDDID(BROADCOM, BCM5906M), "Broadcom BCM5906M Fast" },
382 { VIDDID(BROADCOM, BCM57760), "Broadcom BCM57760 Gigabit" },
383 { VIDDID(BROADCOM, BCM57761), "Broadcom BCM57761 Gigabit" },
384 { VIDDID(BROADCOM, BCM57762), "Broadcom BCM57762 Gigabit" },
385 { VIDDID(BROADCOM, BCM57764), "Broadcom BCM57764 Gigabit" },
386 { VIDDID(BROADCOM, BCM57765), "Broadcom BCM57765 Gigabit" },
387 { VIDDID(BROADCOM, BCM57766), "Broadcom BCM57766 Gigabit" },
388 { VIDDID(BROADCOM, BCM57767), "Broadcom BCM57767 Gigabit" },
389 { VIDDID(BROADCOM, BCM57780), "Broadcom BCM57780 Gigabit" },
390 { VIDDID(BROADCOM, BCM57781), "Broadcom BCM57781 Gigabit" },
391 { VIDDID(BROADCOM, BCM57782), "Broadcom BCM57782 Gigabit" },
392 { VIDDID(BROADCOM, BCM57785), "Broadcom BCM57785 Gigabit" },
393 { VIDDID(BROADCOM, BCM57786), "Broadcom BCM57786 Gigabit" },
394 { VIDDID(BROADCOM, BCM57787), "Broadcom BCM57787 Gigabit" },
395 { VIDDID(BROADCOM, BCM57788), "Broadcom BCM57788 Gigabit" },
396 { VIDDID(BROADCOM, BCM57790), "Broadcom BCM57790 Gigabit" },
397 { VIDDID(BROADCOM, BCM57791), "Broadcom BCM57791 Gigabit" },
398 { VIDDID(BROADCOM, BCM57795), "Broadcom BCM57795 Gigabit" },
399 { VIDDID(SCHNEIDERKOCH, SK_9DX1),"SysKonnect SK-9Dx1 Gigabit" },
400 { VIDDID(SCHNEIDERKOCH, SK_9MXX),"SysKonnect SK-9Mxx Gigabit" },
401 { VIDDID(3COM, 3C996), "3Com 3c996 Gigabit" },
402 { VIDDID(FUJITSU4, PW008GE4), "Fujitsu PW008GE4 Gigabit" },
403 { VIDDID(FUJITSU4, PW008GE5), "Fujitsu PW008GE5 Gigabit" },
404 { VIDDID(FUJITSU4, PP250_450_LAN),"Fujitsu Primepower 250/450 Gigabit" },
405 { 0, 0, NULL },
406 };
407
408 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGEF_JUMBO_CAPABLE)
409 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGEF_5700_FAMILY)
410 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGEF_5705_PLUS)
411 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGEF_5714_FAMILY)
412 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGEF_575X_PLUS)
413 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGEF_5755_PLUS)
414 #define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGEF_57765_FAMILY)
415 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGEF_57765_PLUS)
416 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGEF_5717_PLUS)
417
418 static const struct bge_revision {
419 uint32_t br_chipid;
420 const char *br_name;
421 } bge_revisions[] = {
422 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" },
423 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" },
424 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" },
425 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" },
426 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" },
427 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" },
428 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" },
429 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" },
430 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" },
431 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" },
432 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" },
433 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" },
434 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" },
435 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" },
436 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" },
437 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" },
438 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" },
439 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" },
440 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" },
441 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" },
442 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" },
443 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" },
444 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" },
445 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" },
446 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" },
447 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" },
448 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" },
449 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" },
450 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" },
451 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" },
452 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" },
453 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" },
454 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" },
455 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" },
456 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" },
457 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" },
458 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" },
459 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" },
460 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" },
461 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" },
462 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
463 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
464 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" },
465 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" },
466 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" },
467 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" },
468 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" },
469 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" },
470 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" },
471 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" },
472 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" },
473 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" },
474 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" },
475 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" },
476 { BGE_CHIPID_BCM5762_B0, "BCM5762 B0" },
477 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" },
478 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" },
479 { BGE_CHIPID_BCM5784_B0, "BCM5784 B0" },
480 /* 5754 and 5787 share the same ASIC ID */
481 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" },
482 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" },
483 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" },
484 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" },
485 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" },
486 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" },
487 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" },
488 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" },
489 { BGE_CHIPID_BCM57766_A0, "BCM57766 A0" },
490 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" },
491 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" },
492
493 { 0, NULL }
494 };
495
496 /*
497 * Some defaults for major revisions, so that newer steppings
498 * that we don't know about have a shot at working.
499 */
500 static const struct bge_revision bge_majorrevs[] = {
501 { BGE_ASICREV_BCM5700, "unknown BCM5700" },
502 { BGE_ASICREV_BCM5701, "unknown BCM5701" },
503 { BGE_ASICREV_BCM5703, "unknown BCM5703" },
504 { BGE_ASICREV_BCM5704, "unknown BCM5704" },
505 { BGE_ASICREV_BCM5705, "unknown BCM5705" },
506 { BGE_ASICREV_BCM5750, "unknown BCM5750" },
507 { BGE_ASICREV_BCM5714, "unknown BCM5714" },
508 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" },
509 { BGE_ASICREV_BCM5752, "unknown BCM5752" },
510 { BGE_ASICREV_BCM5780, "unknown BCM5780" },
511 { BGE_ASICREV_BCM5755, "unknown BCM5755" },
512 { BGE_ASICREV_BCM5761, "unknown BCM5761" },
513 { BGE_ASICREV_BCM5784, "unknown BCM5784" },
514 { BGE_ASICREV_BCM5785, "unknown BCM5785" },
515 /* 5754 and 5787 share the same ASIC ID */
516 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" },
517 { BGE_ASICREV_BCM5906, "unknown BCM5906" },
518 { BGE_ASICREV_BCM57765, "unknown BCM57765" },
519 { BGE_ASICREV_BCM57766, "unknown BCM57766" },
520 { BGE_ASICREV_BCM57780, "unknown BCM57780" },
521 { BGE_ASICREV_BCM5717, "unknown BCM5717" },
522 { BGE_ASICREV_BCM5719, "unknown BCM5719" },
523 { BGE_ASICREV_BCM5720, "unknown BCM5720" },
524 { BGE_ASICREV_BCM5762, "unknown BCM5762" },
525
526 { 0, NULL }
527 };
528
529 static int bge_allow_asf = 1;
530
531 #ifndef BGE_WATCHDOG_TIMEOUT
532 #define BGE_WATCHDOG_TIMEOUT 5
533 #endif
534 static int bge_watchdog_timeout = BGE_WATCHDOG_TIMEOUT;
535
536
537 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc),
538 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN);
539
540 static uint32_t
bge_readmem_ind(struct bge_softc * sc,int off)541 bge_readmem_ind(struct bge_softc *sc, int off)
542 {
543 pcireg_t val;
544
545 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 &&
546 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
547 return 0;
548
549 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off);
550 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA);
551 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0);
552 return val;
553 }
554
555 static void
bge_writemem_ind(struct bge_softc * sc,int off,int val)556 bge_writemem_ind(struct bge_softc *sc, int off, int val)
557 {
558
559 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off);
560 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val);
561 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0);
562 }
563
564 /*
565 * PCI Express only
566 */
567 static void
bge_set_max_readrq(struct bge_softc * sc)568 bge_set_max_readrq(struct bge_softc *sc)
569 {
570 pcireg_t val;
571
572 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap
573 + PCIE_DCSR);
574 val &= ~PCIE_DCSR_MAX_READ_REQ;
575 switch (sc->bge_expmrq) {
576 case 2048:
577 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048;
578 break;
579 case 4096:
580 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096;
581 break;
582 default:
583 panic("incorrect expmrq value(%d)", sc->bge_expmrq);
584 break;
585 }
586 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap
587 + PCIE_DCSR, val);
588 }
589
590 #ifdef notdef
591 static uint32_t
bge_readreg_ind(struct bge_softc * sc,int off)592 bge_readreg_ind(struct bge_softc *sc, int off)
593 {
594 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off);
595 return pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA);
596 }
597 #endif
598
599 static void
bge_writereg_ind(struct bge_softc * sc,int off,int val)600 bge_writereg_ind(struct bge_softc *sc, int off, int val)
601 {
602 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off);
603 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val);
604 }
605
606 static void
bge_writemem_direct(struct bge_softc * sc,int off,int val)607 bge_writemem_direct(struct bge_softc *sc, int off, int val)
608 {
609 CSR_WRITE_4(sc, off, val);
610 }
611
612 static void
bge_writembx(struct bge_softc * sc,int off,int val)613 bge_writembx(struct bge_softc *sc, int off, int val)
614 {
615 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
616 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
617
618 CSR_WRITE_4(sc, off, val);
619 }
620
621 static void
bge_writembx_flush(struct bge_softc * sc,int off,int val)622 bge_writembx_flush(struct bge_softc *sc, int off, int val)
623 {
624 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
625 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
626
627 CSR_WRITE_4_FLUSH(sc, off, val);
628 }
629
630 /*
631 * Clear all stale locks and select the lock for this driver instance.
632 */
633 void
bge_ape_lock_init(struct bge_softc * sc)634 bge_ape_lock_init(struct bge_softc *sc)
635 {
636 struct pci_attach_args *pa = &(sc->bge_pa);
637 uint32_t bit, regbase;
638 int i;
639
640 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761)
641 regbase = BGE_APE_LOCK_GRANT;
642 else
643 regbase = BGE_APE_PER_LOCK_GRANT;
644
645 /* Clear any stale locks. */
646 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) {
647 switch (i) {
648 case BGE_APE_LOCK_PHY0:
649 case BGE_APE_LOCK_PHY1:
650 case BGE_APE_LOCK_PHY2:
651 case BGE_APE_LOCK_PHY3:
652 bit = BGE_APE_LOCK_GRANT_DRIVER0;
653 break;
654 default:
655 if (pa->pa_function == 0)
656 bit = BGE_APE_LOCK_GRANT_DRIVER0;
657 else
658 bit = (1 << pa->pa_function);
659 }
660 APE_WRITE_4(sc, regbase + 4 * i, bit);
661 }
662
663 /* Select the PHY lock based on the device's function number. */
664 switch (pa->pa_function) {
665 case 0:
666 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0;
667 break;
668 case 1:
669 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1;
670 break;
671 case 2:
672 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2;
673 break;
674 case 3:
675 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3;
676 break;
677 default:
678 printf("%s: PHY lock not supported on function\n",
679 device_xname(sc->bge_dev));
680 break;
681 }
682 }
683
684 /*
685 * Check for APE firmware, set flags, and print version info.
686 */
687 void
bge_ape_read_fw_ver(struct bge_softc * sc)688 bge_ape_read_fw_ver(struct bge_softc *sc)
689 {
690 const char *fwtype;
691 uint32_t apedata, features;
692
693 /* Check for a valid APE signature in shared memory. */
694 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG);
695 if (apedata != BGE_APE_SEG_SIG_MAGIC) {
696 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE;
697 return;
698 }
699
700 /* Check if APE firmware is running. */
701 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS);
702 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) {
703 printf("%s: APE signature found but FW status not ready! "
704 "0x%08x\n", device_xname(sc->bge_dev), apedata);
705 return;
706 }
707
708 sc->bge_mfw_flags |= BGE_MFW_ON_APE;
709
710 /* Fetch the APE firwmare type and version. */
711 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION);
712 features = APE_READ_4(sc, BGE_APE_FW_FEATURES);
713 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) {
714 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI;
715 fwtype = "NCSI";
716 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) {
717 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH;
718 fwtype = "DASH";
719 } else
720 fwtype = "UNKN";
721
722 /* Print the APE firmware version. */
723 aprint_normal_dev(sc->bge_dev, "APE firmware %s %d.%d.%d.%d\n", fwtype,
724 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT,
725 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT,
726 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT,
727 (apedata & BGE_APE_FW_VERSION_BLDMSK));
728 }
729
730 int
bge_ape_lock(struct bge_softc * sc,int locknum)731 bge_ape_lock(struct bge_softc *sc, int locknum)
732 {
733 struct pci_attach_args *pa = &(sc->bge_pa);
734 uint32_t bit, gnt, req, status;
735 int i, off;
736
737 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
738 return 0;
739
740 /* Lock request/grant registers have different bases. */
741 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) {
742 req = BGE_APE_LOCK_REQ;
743 gnt = BGE_APE_LOCK_GRANT;
744 } else {
745 req = BGE_APE_PER_LOCK_REQ;
746 gnt = BGE_APE_PER_LOCK_GRANT;
747 }
748
749 off = 4 * locknum;
750
751 switch (locknum) {
752 case BGE_APE_LOCK_GPIO:
753 /* Lock required when using GPIO. */
754 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761)
755 return 0;
756 if (pa->pa_function == 0)
757 bit = BGE_APE_LOCK_REQ_DRIVER0;
758 else
759 bit = (1 << pa->pa_function);
760 break;
761 case BGE_APE_LOCK_GRC:
762 /* Lock required to reset the device. */
763 if (pa->pa_function == 0)
764 bit = BGE_APE_LOCK_REQ_DRIVER0;
765 else
766 bit = (1 << pa->pa_function);
767 break;
768 case BGE_APE_LOCK_MEM:
769 /* Lock required when accessing certain APE memory. */
770 if (pa->pa_function == 0)
771 bit = BGE_APE_LOCK_REQ_DRIVER0;
772 else
773 bit = (1 << pa->pa_function);
774 break;
775 case BGE_APE_LOCK_PHY0:
776 case BGE_APE_LOCK_PHY1:
777 case BGE_APE_LOCK_PHY2:
778 case BGE_APE_LOCK_PHY3:
779 /* Lock required when accessing PHYs. */
780 bit = BGE_APE_LOCK_REQ_DRIVER0;
781 break;
782 default:
783 return EINVAL;
784 }
785
786 /* Request a lock. */
787 APE_WRITE_4_FLUSH(sc, req + off, bit);
788
789 /* Wait up to 1 second to acquire lock. */
790 for (i = 0; i < 20000; i++) {
791 status = APE_READ_4(sc, gnt + off);
792 if (status == bit)
793 break;
794 DELAY(50);
795 }
796
797 /* Handle any errors. */
798 if (status != bit) {
799 printf("%s: APE lock %d request failed! "
800 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n",
801 device_xname(sc->bge_dev),
802 locknum, req + off, bit & 0xFFFF, gnt + off,
803 status & 0xFFFF);
804 /* Revoke the lock request. */
805 APE_WRITE_4(sc, gnt + off, bit);
806 return EBUSY;
807 }
808
809 return 0;
810 }
811
812 void
bge_ape_unlock(struct bge_softc * sc,int locknum)813 bge_ape_unlock(struct bge_softc *sc, int locknum)
814 {
815 struct pci_attach_args *pa = &(sc->bge_pa);
816 uint32_t bit, gnt;
817 int off;
818
819 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
820 return;
821
822 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761)
823 gnt = BGE_APE_LOCK_GRANT;
824 else
825 gnt = BGE_APE_PER_LOCK_GRANT;
826
827 off = 4 * locknum;
828
829 switch (locknum) {
830 case BGE_APE_LOCK_GPIO:
831 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761)
832 return;
833 if (pa->pa_function == 0)
834 bit = BGE_APE_LOCK_GRANT_DRIVER0;
835 else
836 bit = (1 << pa->pa_function);
837 break;
838 case BGE_APE_LOCK_GRC:
839 if (pa->pa_function == 0)
840 bit = BGE_APE_LOCK_GRANT_DRIVER0;
841 else
842 bit = (1 << pa->pa_function);
843 break;
844 case BGE_APE_LOCK_MEM:
845 if (pa->pa_function == 0)
846 bit = BGE_APE_LOCK_GRANT_DRIVER0;
847 else
848 bit = (1 << pa->pa_function);
849 break;
850 case BGE_APE_LOCK_PHY0:
851 case BGE_APE_LOCK_PHY1:
852 case BGE_APE_LOCK_PHY2:
853 case BGE_APE_LOCK_PHY3:
854 bit = BGE_APE_LOCK_GRANT_DRIVER0;
855 break;
856 default:
857 return;
858 }
859
860 /* Write and flush for consecutive bge_ape_lock() */
861 APE_WRITE_4_FLUSH(sc, gnt + off, bit);
862 }
863
864 /*
865 * Send an event to the APE firmware.
866 */
867 void
bge_ape_send_event(struct bge_softc * sc,uint32_t event)868 bge_ape_send_event(struct bge_softc *sc, uint32_t event)
869 {
870 uint32_t apedata;
871 int i;
872
873 /* NCSI does not support APE events. */
874 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
875 return;
876
877 /* Wait up to 1ms for APE to service previous event. */
878 for (i = 10; i > 0; i--) {
879 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0)
880 break;
881 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS);
882 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) {
883 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event |
884 BGE_APE_EVENT_STATUS_EVENT_PENDING);
885 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
886 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1);
887 break;
888 }
889 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
890 DELAY(100);
891 }
892 if (i == 0) {
893 printf("%s: APE event 0x%08x send timed out\n",
894 device_xname(sc->bge_dev), event);
895 }
896 }
897
898 void
bge_ape_driver_state_change(struct bge_softc * sc,int kind)899 bge_ape_driver_state_change(struct bge_softc *sc, int kind)
900 {
901 uint32_t apedata, event;
902
903 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
904 return;
905
906 switch (kind) {
907 case BGE_RESET_START:
908 /* If this is the first load, clear the load counter. */
909 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG);
910 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC)
911 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0);
912 else {
913 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT);
914 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata);
915 }
916 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG,
917 BGE_APE_HOST_SEG_SIG_MAGIC);
918 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN,
919 BGE_APE_HOST_SEG_LEN_MAGIC);
920
921 /* Add some version info if bge(4) supports it. */
922 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID,
923 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0));
924 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR,
925 BGE_APE_HOST_BEHAV_NO_PHYLOCK);
926 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS,
927 BGE_APE_HOST_HEARTBEAT_INT_DISABLE);
928 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
929 BGE_APE_HOST_DRVR_STATE_START);
930 event = BGE_APE_EVENT_STATUS_STATE_START;
931 break;
932 case BGE_RESET_SHUTDOWN:
933 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
934 BGE_APE_HOST_DRVR_STATE_UNLOAD);
935 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD;
936 break;
937 case BGE_RESET_SUSPEND:
938 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND;
939 break;
940 default:
941 return;
942 }
943
944 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT |
945 BGE_APE_EVENT_STATUS_STATE_CHNGE);
946 }
947
948 static uint8_t
bge_nvram_getbyte(struct bge_softc * sc,int addr,uint8_t * dest)949 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
950 {
951 uint32_t access, byte = 0;
952 int i;
953
954 /* Lock. */
955 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
956 for (i = 0; i < 8000; i++) {
957 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
958 break;
959 DELAY(20);
960 }
961 if (i == 8000)
962 return 1;
963
964 /* Enable access. */
965 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
966 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
967
968 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
969 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
970 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
971 DELAY(10);
972 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
973 DELAY(10);
974 break;
975 }
976 }
977
978 if (i == BGE_TIMEOUT * 10) {
979 aprint_error_dev(sc->bge_dev, "nvram read timed out\n");
980 return 1;
981 }
982
983 /* Get result. */
984 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
985
986 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
987
988 /* Disable access. */
989 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
990
991 /* Unlock. */
992 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
993
994 return 0;
995 }
996
997 /*
998 * Read a sequence of bytes from NVRAM.
999 */
1000 static int
bge_read_nvram(struct bge_softc * sc,uint8_t * dest,int off,int cnt)1001 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt)
1002 {
1003 int error = 0, i;
1004 uint8_t byte = 0;
1005
1006 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)
1007 return 1;
1008
1009 for (i = 0; i < cnt; i++) {
1010 error = bge_nvram_getbyte(sc, off + i, &byte);
1011 if (error)
1012 break;
1013 *(dest + i) = byte;
1014 }
1015
1016 return error ? 1 : 0;
1017 }
1018
1019 /*
1020 * Read a byte of data stored in the EEPROM at address 'addr.' The
1021 * BCM570x supports both the traditional bitbang interface and an
1022 * auto access interface for reading the EEPROM. We use the auto
1023 * access method.
1024 */
1025 static uint8_t
bge_eeprom_getbyte(struct bge_softc * sc,int addr,uint8_t * dest)1026 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1027 {
1028 int i;
1029 uint32_t byte = 0;
1030
1031 /*
1032 * Enable use of auto EEPROM access so we can avoid
1033 * having to use the bitbang method.
1034 */
1035 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
1036
1037 /* Reset the EEPROM, load the clock period. */
1038 CSR_WRITE_4_FLUSH(sc, BGE_EE_ADDR,
1039 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
1040 DELAY(20);
1041
1042 /* Issue the read EEPROM command. */
1043 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
1044
1045 /* Wait for completion */
1046 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
1047 DELAY(10);
1048 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
1049 break;
1050 }
1051
1052 if (i == BGE_TIMEOUT * 10) {
1053 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n");
1054 return 1;
1055 }
1056
1057 /* Get result. */
1058 byte = CSR_READ_4(sc, BGE_EE_DATA);
1059
1060 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
1061
1062 return 0;
1063 }
1064
1065 /*
1066 * Read a sequence of bytes from the EEPROM.
1067 */
1068 static int
bge_read_eeprom(struct bge_softc * sc,void * destv,int off,int cnt)1069 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt)
1070 {
1071 int error = 0, i;
1072 uint8_t byte = 0;
1073 char *dest = destv;
1074
1075 for (i = 0; i < cnt; i++) {
1076 error = bge_eeprom_getbyte(sc, off + i, &byte);
1077 if (error)
1078 break;
1079 *(dest + i) = byte;
1080 }
1081
1082 return error ? 1 : 0;
1083 }
1084
1085 static int
bge_miibus_readreg(device_t dev,int phy,int reg,uint16_t * val)1086 bge_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)
1087 {
1088 struct bge_softc * const sc = device_private(dev);
1089 uint32_t data;
1090 uint32_t autopoll;
1091 int rv = 0;
1092 int i;
1093
1094 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1095 return -1;
1096
1097 /* Reading with autopolling on may trigger PCI errors */
1098 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
1099 if (autopoll & BGE_MIMODE_AUTOPOLL) {
1100 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL);
1101 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
1102 DELAY(80);
1103 }
1104
1105 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
1106 BGE_MIPHY(phy) | BGE_MIREG(reg));
1107
1108 for (i = 0; i < BGE_TIMEOUT; i++) {
1109 delay(10);
1110 data = CSR_READ_4(sc, BGE_MI_COMM);
1111 if (!(data & BGE_MICOMM_BUSY)) {
1112 DELAY(5);
1113 data = CSR_READ_4(sc, BGE_MI_COMM);
1114 break;
1115 }
1116 }
1117
1118 if (i == BGE_TIMEOUT) {
1119 aprint_error_dev(sc->bge_dev, "PHY read timed out\n");
1120 rv = ETIMEDOUT;
1121 } else if ((data & BGE_MICOMM_READFAIL) != 0) {
1122 /* XXX This error occurs on some devices while attaching. */
1123 aprint_debug_dev(sc->bge_dev, "PHY read I/O error\n");
1124 rv = EIO;
1125 } else
1126 *val = data & BGE_MICOMM_DATA;
1127
1128 if (autopoll & BGE_MIMODE_AUTOPOLL) {
1129 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL);
1130 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
1131 DELAY(80);
1132 }
1133
1134 bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1135
1136 return rv;
1137 }
1138
1139 static int
bge_miibus_writereg(device_t dev,int phy,int reg,uint16_t val)1140 bge_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)
1141 {
1142 struct bge_softc * const sc = device_private(dev);
1143 uint32_t data, autopoll;
1144 int rv = 0;
1145 int i;
1146
1147 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 &&
1148 (reg == MII_GTCR || reg == BRGPHY_MII_AUXCTL))
1149 return 0;
1150
1151 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1152 return -1;
1153
1154 /* Reading with autopolling on may trigger PCI errors */
1155 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
1156 if (autopoll & BGE_MIMODE_AUTOPOLL) {
1157 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL);
1158 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
1159 DELAY(80);
1160 }
1161
1162 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
1163 BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
1164
1165 for (i = 0; i < BGE_TIMEOUT; i++) {
1166 delay(10);
1167 data = CSR_READ_4(sc, BGE_MI_COMM);
1168 if (!(data & BGE_MICOMM_BUSY)) {
1169 delay(5);
1170 data = CSR_READ_4(sc, BGE_MI_COMM);
1171 break;
1172 }
1173 }
1174
1175 if (i == BGE_TIMEOUT) {
1176 aprint_error_dev(sc->bge_dev, "PHY write timed out\n");
1177 rv = ETIMEDOUT;
1178 } else if ((data & BGE_MICOMM_READFAIL) != 0) {
1179 aprint_error_dev(sc->bge_dev, "PHY write I/O error\n");
1180 rv = EIO;
1181 }
1182
1183 if (autopoll & BGE_MIMODE_AUTOPOLL) {
1184 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL);
1185 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
1186 delay(80);
1187 }
1188
1189 bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1190
1191 return rv;
1192 }
1193
1194 static void
bge_miibus_statchg(struct ifnet * ifp)1195 bge_miibus_statchg(struct ifnet *ifp)
1196 {
1197 struct bge_softc * const sc = ifp->if_softc;
1198 struct mii_data *mii = &sc->bge_mii;
1199 uint32_t mac_mode, rx_mode, tx_mode;
1200
1201 /*
1202 * Get flow control negotiation result.
1203 */
1204 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO &&
1205 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags)
1206 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK;
1207
1208 if (!BGE_STS_BIT(sc, BGE_STS_LINK) &&
1209 mii->mii_media_status & IFM_ACTIVE &&
1210 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1211 BGE_STS_SETBIT(sc, BGE_STS_LINK);
1212 else if (BGE_STS_BIT(sc, BGE_STS_LINK) &&
1213 (!(mii->mii_media_status & IFM_ACTIVE) ||
1214 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE))
1215 BGE_STS_CLRBIT(sc, BGE_STS_LINK);
1216
1217 if (!BGE_STS_BIT(sc, BGE_STS_LINK))
1218 return;
1219
1220 /* Set the port mode (MII/GMII) to match the link speed. */
1221 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &
1222 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX);
1223 tx_mode = CSR_READ_4(sc, BGE_TX_MODE);
1224 rx_mode = CSR_READ_4(sc, BGE_RX_MODE);
1225 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1226 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
1227 mac_mode |= BGE_PORTMODE_GMII;
1228 else
1229 mac_mode |= BGE_PORTMODE_MII;
1230
1231 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE;
1232 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE;
1233 if ((mii->mii_media_active & IFM_FDX) != 0) {
1234 if (sc->bge_flowflags & IFM_ETH_TXPAUSE)
1235 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE;
1236 if (sc->bge_flowflags & IFM_ETH_RXPAUSE)
1237 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE;
1238 } else
1239 mac_mode |= BGE_MACMODE_HALF_DUPLEX;
1240
1241 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode);
1242 DELAY(40);
1243 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode);
1244 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode);
1245 }
1246
1247 /*
1248 * Update rx threshold levels to values in a particular slot
1249 * of the interrupt-mitigation table bge_rx_threshes.
1250 */
1251 static void
bge_set_thresh(struct ifnet * ifp,int lvl)1252 bge_set_thresh(struct ifnet *ifp, int lvl)
1253 {
1254 struct bge_softc * const sc = ifp->if_softc;
1255
1256 /*
1257 * For now, just save the new Rx-intr thresholds and record
1258 * that a threshold update is pending. Updating the hardware
1259 * registers here (even at splhigh()) is observed to
1260 * occasionally cause glitches where Rx-interrupts are not
1261 * honoured for up to 10 seconds. jonathan@NetBSD.org, 2003-04-05
1262 */
1263 mutex_enter(sc->sc_intr_lock);
1264 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks;
1265 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds;
1266 sc->bge_pending_rxintr_change = true;
1267 mutex_exit(sc->sc_intr_lock);
1268 }
1269
1270
1271 /*
1272 * Update Rx thresholds of all bge devices
1273 */
1274 static void
bge_update_all_threshes(int lvl)1275 bge_update_all_threshes(int lvl)
1276 {
1277 const char * const namebuf = "bge";
1278 const size_t namelen = strlen(namebuf);
1279 struct ifnet *ifp;
1280
1281 if (lvl < 0)
1282 lvl = 0;
1283 else if (lvl >= NBGE_RX_THRESH)
1284 lvl = NBGE_RX_THRESH - 1;
1285
1286 /*
1287 * Now search all the interfaces for this name/number
1288 */
1289 int s = pserialize_read_enter();
1290 IFNET_READER_FOREACH(ifp) {
1291 if (strncmp(ifp->if_xname, namebuf, namelen) != 0)
1292 continue;
1293 /* We got a match: update if doing auto-threshold-tuning */
1294 if (bge_auto_thresh)
1295 bge_set_thresh(ifp, lvl);
1296 }
1297 pserialize_read_exit(s);
1298 }
1299
1300 /*
1301 * Handle events that have triggered interrupts.
1302 */
1303 static void
bge_handle_events(struct bge_softc * sc)1304 bge_handle_events(struct bge_softc *sc)
1305 {
1306
1307 return;
1308 }
1309
1310 /*
1311 * Memory management for jumbo frames.
1312 */
1313
1314 static int
bge_alloc_jumbo_mem(struct bge_softc * sc)1315 bge_alloc_jumbo_mem(struct bge_softc *sc)
1316 {
1317 char *ptr, *kva;
1318 int i, rseg, state, error;
1319 struct bge_jpool_entry *entry;
1320
1321 state = error = 0;
1322
1323 /* Grab a big chunk o' storage. */
1324 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0,
1325 &sc->bge_cdata.bge_rx_jumbo_seg, 1, &rseg, BUS_DMA_WAITOK)) {
1326 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n");
1327 return ENOBUFS;
1328 }
1329
1330 state = 1;
1331 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_cdata.bge_rx_jumbo_seg,
1332 rseg, BGE_JMEM, (void **)&kva, BUS_DMA_WAITOK)) {
1333 aprint_error_dev(sc->bge_dev,
1334 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM);
1335 error = ENOBUFS;
1336 goto out;
1337 }
1338
1339 state = 2;
1340 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0,
1341 BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_jumbo_map)) {
1342 aprint_error_dev(sc->bge_dev, "can't create DMA map\n");
1343 error = ENOBUFS;
1344 goto out;
1345 }
1346
1347 state = 3;
1348 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map,
1349 kva, BGE_JMEM, NULL, BUS_DMA_WAITOK)) {
1350 aprint_error_dev(sc->bge_dev, "can't load DMA map\n");
1351 error = ENOBUFS;
1352 goto out;
1353 }
1354
1355 state = 4;
1356 sc->bge_cdata.bge_jumbo_buf = (void *)kva;
1357 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf));
1358
1359 SLIST_INIT(&sc->bge_jfree_listhead);
1360 SLIST_INIT(&sc->bge_jinuse_listhead);
1361
1362 /*
1363 * Now divide it up into 9K pieces and save the addresses
1364 * in an array.
1365 */
1366 ptr = sc->bge_cdata.bge_jumbo_buf;
1367 for (i = 0; i < BGE_JSLOTS; i++) {
1368 sc->bge_cdata.bge_jslots[i] = ptr;
1369 ptr += BGE_JLEN;
1370 entry = kmem_alloc(sizeof(*entry), KM_SLEEP);
1371 entry->slot = i;
1372 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
1373 entry, jpool_entries);
1374 }
1375 out:
1376 if (error != 0) {
1377 switch (state) {
1378 case 4:
1379 bus_dmamap_unload(sc->bge_dmatag,
1380 sc->bge_cdata.bge_rx_jumbo_map);
1381 /* FALLTHROUGH */
1382 case 3:
1383 bus_dmamap_destroy(sc->bge_dmatag,
1384 sc->bge_cdata.bge_rx_jumbo_map);
1385 /* FALLTHROUGH */
1386 case 2:
1387 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM);
1388 /* FALLTHROUGH */
1389 case 1:
1390 bus_dmamem_free(sc->bge_dmatag,
1391 &sc->bge_cdata.bge_rx_jumbo_seg, rseg);
1392 break;
1393 default:
1394 break;
1395 }
1396 }
1397
1398 return error;
1399 }
1400
1401 static void
bge_free_jumbo_mem(struct bge_softc * sc)1402 bge_free_jumbo_mem(struct bge_softc *sc)
1403 {
1404 struct bge_jpool_entry *entry, *tmp;
1405
1406 KASSERT(SLIST_EMPTY(&sc->bge_jinuse_listhead));
1407
1408 SLIST_FOREACH_SAFE(entry, &sc->bge_jfree_listhead, jpool_entries, tmp) {
1409 kmem_free(entry, sizeof(*entry));
1410 }
1411
1412 bus_dmamap_unload(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map);
1413
1414 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map);
1415
1416 bus_dmamem_unmap(sc->bge_dmatag, sc->bge_cdata.bge_jumbo_buf, BGE_JMEM);
1417
1418 bus_dmamem_free(sc->bge_dmatag, &sc->bge_cdata.bge_rx_jumbo_seg, 1);
1419 }
1420
1421 /*
1422 * Allocate a jumbo buffer.
1423 */
1424 static void *
bge_jalloc(struct bge_softc * sc)1425 bge_jalloc(struct bge_softc *sc)
1426 {
1427 struct bge_jpool_entry *entry;
1428
1429 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
1430
1431 if (entry == NULL) {
1432 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n");
1433 return NULL;
1434 }
1435
1436 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries);
1437 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries);
1438 return sc->bge_cdata.bge_jslots[entry->slot];
1439 }
1440
1441 /*
1442 * Release a jumbo buffer.
1443 */
1444 static void
bge_jfree(struct mbuf * m,void * buf,size_t size,void * arg)1445 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg)
1446 {
1447 struct bge_jpool_entry *entry;
1448 struct bge_softc * const sc = arg;
1449
1450 if (sc == NULL)
1451 panic("bge_jfree: can't find softc pointer!");
1452
1453 /* calculate the slot this buffer belongs to */
1454 int i = ((char *)buf - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN;
1455
1456 if (i < 0 || i >= BGE_JSLOTS)
1457 panic("bge_jfree: asked to free buffer that we don't manage!");
1458
1459 mutex_enter(sc->sc_intr_lock);
1460 entry = SLIST_FIRST(&sc->bge_jinuse_listhead);
1461 if (entry == NULL)
1462 panic("bge_jfree: buffer not in use!");
1463 entry->slot = i;
1464 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries);
1465 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries);
1466 mutex_exit(sc->sc_intr_lock);
1467
1468 if (__predict_true(m != NULL))
1469 pool_cache_put(mb_cache, m);
1470 }
1471
1472
1473 /*
1474 * Initialize a standard receive ring descriptor.
1475 */
1476 static int
bge_newbuf_std(struct bge_softc * sc,int i)1477 bge_newbuf_std(struct bge_softc *sc, int i)
1478 {
1479 const bus_dmamap_t dmamap = sc->bge_cdata.bge_rx_std_map[i];
1480 struct mbuf *m;
1481
1482 MGETHDR(m, M_DONTWAIT, MT_DATA);
1483 if (m == NULL)
1484 return ENOBUFS;
1485
1486 MCLGET(m, M_DONTWAIT);
1487 if (!(m->m_flags & M_EXT)) {
1488 m_freem(m);
1489 return ENOBUFS;
1490 }
1491 m->m_len = m->m_pkthdr.len = MCLBYTES;
1492
1493 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG))
1494 m_adj(m, ETHER_ALIGN);
1495 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m,
1496 BUS_DMA_READ | BUS_DMA_NOWAIT)) {
1497 m_freem(m);
1498 return ENOBUFS;
1499 }
1500 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize,
1501 BUS_DMASYNC_PREREAD);
1502 sc->bge_cdata.bge_rx_std_chain[i] = m;
1503
1504 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
1505 offsetof(struct bge_ring_data, bge_rx_std_ring) +
1506 i * sizeof(struct bge_rx_bd),
1507 sizeof(struct bge_rx_bd),
1508 BUS_DMASYNC_POSTWRITE);
1509
1510 struct bge_rx_bd * const r = &sc->bge_rdata->bge_rx_std_ring[i];
1511 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr);
1512 r->bge_flags = BGE_RXBDFLAG_END;
1513 r->bge_len = m->m_len;
1514 r->bge_idx = i;
1515
1516 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
1517 offsetof(struct bge_ring_data, bge_rx_std_ring) +
1518 i * sizeof(struct bge_rx_bd),
1519 sizeof(struct bge_rx_bd),
1520 BUS_DMASYNC_PREWRITE);
1521
1522 sc->bge_std_cnt++;
1523
1524 return 0;
1525 }
1526
1527 /*
1528 * Initialize a jumbo receive ring descriptor. This allocates
1529 * a jumbo buffer from the pool managed internally by the driver.
1530 */
1531 static int
bge_newbuf_jumbo(struct bge_softc * sc,int i,struct mbuf * m)1532 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
1533 {
1534 struct mbuf *m_new = NULL;
1535 struct bge_rx_bd *r;
1536 void *buf = NULL;
1537
1538 if (m == NULL) {
1539
1540 /* Allocate the mbuf. */
1541 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1542 if (m_new == NULL)
1543 return ENOBUFS;
1544
1545 /* Allocate the jumbo buffer */
1546 buf = bge_jalloc(sc);
1547 if (buf == NULL) {
1548 m_freem(m_new);
1549 aprint_error_dev(sc->bge_dev,
1550 "jumbo allocation failed -- packet dropped!\n");
1551 return ENOBUFS;
1552 }
1553
1554 /* Attach the buffer to the mbuf. */
1555 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN;
1556 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF,
1557 bge_jfree, sc);
1558 m_new->m_flags |= M_EXT_RW;
1559 } else {
1560 m_new = m;
1561 buf = m_new->m_data = m_new->m_ext.ext_buf;
1562 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
1563 }
1564 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG))
1565 m_adj(m_new, ETHER_ALIGN);
1566 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map,
1567 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf,
1568 BGE_JLEN, BUS_DMASYNC_PREREAD);
1569
1570 /* Set up the descriptor. */
1571 r = &sc->bge_rdata->bge_rx_jumbo_ring[i];
1572 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
1573 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new));
1574 r->bge_flags = BGE_RXBDFLAG_END | BGE_RXBDFLAG_JUMBO_RING;
1575 r->bge_len = m_new->m_len;
1576 r->bge_idx = i;
1577
1578 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
1579 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) +
1580 i * sizeof(struct bge_rx_bd),
1581 sizeof(struct bge_rx_bd),
1582 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1583
1584 return 0;
1585 }
1586
1587 static int
bge_init_rx_ring_std(struct bge_softc * sc)1588 bge_init_rx_ring_std(struct bge_softc *sc)
1589 {
1590 bus_dmamap_t dmamap;
1591 int error = 0;
1592 u_int i;
1593
1594 if (sc->bge_flags & BGEF_RXRING_VALID)
1595 return 0;
1596
1597 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1598 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1,
1599 MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &dmamap);
1600 if (error)
1601 goto uncreate;
1602
1603 sc->bge_cdata.bge_rx_std_map[i] = dmamap;
1604 memset(&sc->bge_rdata->bge_rx_std_ring[i], 0,
1605 sizeof(struct bge_rx_bd));
1606 }
1607
1608 sc->bge_std = i - 1;
1609 sc->bge_std_cnt = 0;
1610 bge_fill_rx_ring_std(sc);
1611
1612 sc->bge_flags |= BGEF_RXRING_VALID;
1613
1614 return 0;
1615
1616 uncreate:
1617 while (--i) {
1618 bus_dmamap_destroy(sc->bge_dmatag,
1619 sc->bge_cdata.bge_rx_std_map[i]);
1620 }
1621 return error;
1622 }
1623
1624 static void
bge_fill_rx_ring_std(struct bge_softc * sc)1625 bge_fill_rx_ring_std(struct bge_softc *sc)
1626 {
1627 int i = sc->bge_std;
1628 bool post = false;
1629
1630 while (sc->bge_std_cnt < BGE_STD_RX_RING_CNT) {
1631 BGE_INC(i, BGE_STD_RX_RING_CNT);
1632
1633 if (bge_newbuf_std(sc, i) != 0)
1634 break;
1635
1636 sc->bge_std = i;
1637 post = true;
1638 }
1639
1640 if (post)
1641 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1642 }
1643
1644
1645 static void
bge_free_rx_ring_std(struct bge_softc * sc)1646 bge_free_rx_ring_std(struct bge_softc *sc)
1647 {
1648
1649 if (!(sc->bge_flags & BGEF_RXRING_VALID))
1650 return;
1651
1652 for (u_int i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1653 const bus_dmamap_t dmap = sc->bge_cdata.bge_rx_std_map[i];
1654 struct mbuf * const m = sc->bge_cdata.bge_rx_std_chain[i];
1655 if (m != NULL) {
1656 bus_dmamap_sync(sc->bge_dmatag, dmap, 0,
1657 dmap->dm_mapsize, BUS_DMASYNC_POSTREAD);
1658 bus_dmamap_unload(sc->bge_dmatag, dmap);
1659 m_freem(m);
1660 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1661 }
1662 bus_dmamap_destroy(sc->bge_dmatag,
1663 sc->bge_cdata.bge_rx_std_map[i]);
1664 sc->bge_cdata.bge_rx_std_map[i] = NULL;
1665 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0,
1666 sizeof(struct bge_rx_bd));
1667 }
1668
1669 sc->bge_flags &= ~BGEF_RXRING_VALID;
1670 }
1671
1672 static int
bge_init_rx_ring_jumbo(struct bge_softc * sc)1673 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1674 {
1675 int i;
1676 volatile struct bge_rcb *rcb;
1677
1678 if (sc->bge_flags & BGEF_JUMBO_RXRING_VALID)
1679 return 0;
1680
1681 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1682 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
1683 return ENOBUFS;
1684 }
1685
1686 sc->bge_jumbo = i - 1;
1687 sc->bge_flags |= BGEF_JUMBO_RXRING_VALID;
1688
1689 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
1690 rcb->bge_maxlen_flags = 0;
1691 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1692
1693 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1694
1695 return 0;
1696 }
1697
1698 static void
bge_free_rx_ring_jumbo(struct bge_softc * sc)1699 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1700 {
1701 int i;
1702
1703 if (!(sc->bge_flags & BGEF_JUMBO_RXRING_VALID))
1704 return;
1705
1706 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1707 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1708 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1709 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1710 }
1711 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0,
1712 sizeof(struct bge_rx_bd));
1713 }
1714
1715 sc->bge_flags &= ~BGEF_JUMBO_RXRING_VALID;
1716 }
1717
1718 static void
bge_free_tx_ring(struct bge_softc * sc,bool disable)1719 bge_free_tx_ring(struct bge_softc *sc, bool disable)
1720 {
1721 int i;
1722 struct txdmamap_pool_entry *dma;
1723
1724 if (!(sc->bge_flags & BGEF_TXRING_VALID))
1725 return;
1726
1727 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1728 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1729 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1730 sc->bge_cdata.bge_tx_chain[i] = NULL;
1731 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i],
1732 link);
1733 sc->txdma[i] = 0;
1734 }
1735 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0,
1736 sizeof(struct bge_tx_bd));
1737 }
1738
1739 if (disable) {
1740 while ((dma = SLIST_FIRST(&sc->txdma_list))) {
1741 SLIST_REMOVE_HEAD(&sc->txdma_list, link);
1742 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap);
1743 if (sc->bge_dma64) {
1744 bus_dmamap_destroy(sc->bge_dmatag32,
1745 dma->dmamap32);
1746 }
1747 kmem_free(dma, sizeof(*dma));
1748 }
1749 SLIST_INIT(&sc->txdma_list);
1750 }
1751
1752 sc->bge_flags &= ~BGEF_TXRING_VALID;
1753 }
1754
1755 static int
bge_init_tx_ring(struct bge_softc * sc)1756 bge_init_tx_ring(struct bge_softc *sc)
1757 {
1758 struct ifnet * const ifp = &sc->ethercom.ec_if;
1759 int i;
1760 bus_dmamap_t dmamap, dmamap32;
1761 bus_size_t maxsegsz;
1762 struct txdmamap_pool_entry *dma;
1763
1764 if (sc->bge_flags & BGEF_TXRING_VALID)
1765 return 0;
1766
1767 sc->bge_txcnt = 0;
1768 sc->bge_tx_saved_considx = 0;
1769
1770 /* Initialize transmit producer index for host-memory send ring. */
1771 sc->bge_tx_prodidx = 0;
1772 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1773 /* 5700 b2 errata */
1774 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)
1775 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1776
1777 /* NIC-memory send ring not used; initialize to zero. */
1778 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1779 /* 5700 b2 errata */
1780 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)
1781 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1782
1783 /* Limit DMA segment size for some chips */
1784 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) &&
1785 (ifp->if_mtu <= ETHERMTU))
1786 maxsegsz = 2048;
1787 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719)
1788 maxsegsz = 4096;
1789 else
1790 maxsegsz = ETHER_MAX_LEN_JUMBO;
1791
1792 if (SLIST_FIRST(&sc->txdma_list) != NULL)
1793 goto alloc_done;
1794
1795 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1796 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX,
1797 BGE_NTXSEG, maxsegsz, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW,
1798 &dmamap))
1799 return ENOBUFS;
1800 if (dmamap == NULL)
1801 panic("dmamap NULL in bge_init_tx_ring");
1802 if (sc->bge_dma64) {
1803 if (bus_dmamap_create(sc->bge_dmatag32, BGE_TXDMA_MAX,
1804 BGE_NTXSEG, maxsegsz, 0,
1805 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW,
1806 &dmamap32)) {
1807 bus_dmamap_destroy(sc->bge_dmatag, dmamap);
1808 return ENOBUFS;
1809 }
1810 if (dmamap32 == NULL)
1811 panic("dmamap32 NULL in bge_init_tx_ring");
1812 } else
1813 dmamap32 = dmamap;
1814 dma = kmem_alloc(sizeof(*dma), KM_NOSLEEP);
1815 if (dma == NULL) {
1816 aprint_error_dev(sc->bge_dev,
1817 "can't alloc txdmamap_pool_entry\n");
1818 bus_dmamap_destroy(sc->bge_dmatag, dmamap);
1819 if (sc->bge_dma64)
1820 bus_dmamap_destroy(sc->bge_dmatag32, dmamap32);
1821 return ENOMEM;
1822 }
1823 dma->dmamap = dmamap;
1824 dma->dmamap32 = dmamap32;
1825 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link);
1826 }
1827 alloc_done:
1828 sc->bge_flags |= BGEF_TXRING_VALID;
1829
1830 return 0;
1831 }
1832
1833 static void
bge_setmulti(struct bge_softc * sc)1834 bge_setmulti(struct bge_softc *sc)
1835 {
1836 struct ethercom * const ec = &sc->ethercom;
1837 struct ether_multi *enm;
1838 struct ether_multistep step;
1839 uint32_t hashes[4] = { 0, 0, 0, 0 };
1840 uint32_t h;
1841 int i;
1842
1843 KASSERT(mutex_owned(sc->sc_core_lock));
1844 if (sc->bge_if_flags & IFF_PROMISC)
1845 goto allmulti;
1846
1847 /* Now program new ones. */
1848 ETHER_LOCK(ec);
1849 ETHER_FIRST_MULTI(step, ec, enm);
1850 while (enm != NULL) {
1851 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
1852 /*
1853 * We must listen to a range of multicast addresses.
1854 * For now, just accept all multicasts, rather than
1855 * trying to set only those filter bits needed to match
1856 * the range. (At this time, the only use of address
1857 * ranges is for IP multicast routing, for which the
1858 * range is big enough to require all bits set.)
1859 */
1860 ETHER_UNLOCK(ec);
1861 goto allmulti;
1862 }
1863
1864 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
1865
1866 /* Just want the 7 least-significant bits. */
1867 h &= 0x7f;
1868
1869 hashes[(h & 0x60) >> 5] |= 1U << (h & 0x1F);
1870 ETHER_NEXT_MULTI(step, enm);
1871 }
1872 ec->ec_flags &= ~ETHER_F_ALLMULTI;
1873 ETHER_UNLOCK(ec);
1874
1875 goto setit;
1876
1877 allmulti:
1878 ETHER_LOCK(ec);
1879 ec->ec_flags |= ETHER_F_ALLMULTI;
1880 ETHER_UNLOCK(ec);
1881 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff;
1882
1883 setit:
1884 for (i = 0; i < 4; i++)
1885 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1886 }
1887
1888 static void
bge_sig_pre_reset(struct bge_softc * sc,int type)1889 bge_sig_pre_reset(struct bge_softc *sc, int type)
1890 {
1891
1892 /*
1893 * Some chips don't like this so only do this if ASF is enabled
1894 */
1895 if (sc->bge_asf_mode)
1896 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
1897
1898 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1899 switch (type) {
1900 case BGE_RESET_START:
1901 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1902 BGE_FW_DRV_STATE_START);
1903 break;
1904 case BGE_RESET_SHUTDOWN:
1905 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1906 BGE_FW_DRV_STATE_UNLOAD);
1907 break;
1908 case BGE_RESET_SUSPEND:
1909 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1910 BGE_FW_DRV_STATE_SUSPEND);
1911 break;
1912 }
1913 }
1914
1915 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND)
1916 bge_ape_driver_state_change(sc, type);
1917 }
1918
1919 static void
bge_sig_post_reset(struct bge_softc * sc,int type)1920 bge_sig_post_reset(struct bge_softc *sc, int type)
1921 {
1922
1923 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1924 switch (type) {
1925 case BGE_RESET_START:
1926 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1927 BGE_FW_DRV_STATE_START_DONE);
1928 /* START DONE */
1929 break;
1930 case BGE_RESET_SHUTDOWN:
1931 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1932 BGE_FW_DRV_STATE_UNLOAD_DONE);
1933 break;
1934 }
1935 }
1936
1937 if (type == BGE_RESET_SHUTDOWN)
1938 bge_ape_driver_state_change(sc, type);
1939 }
1940
1941 static void
bge_sig_legacy(struct bge_softc * sc,int type)1942 bge_sig_legacy(struct bge_softc *sc, int type)
1943 {
1944
1945 if (sc->bge_asf_mode) {
1946 switch (type) {
1947 case BGE_RESET_START:
1948 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1949 BGE_FW_DRV_STATE_START);
1950 break;
1951 case BGE_RESET_SHUTDOWN:
1952 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1953 BGE_FW_DRV_STATE_UNLOAD);
1954 break;
1955 }
1956 }
1957 }
1958
1959 static void
bge_wait_for_event_ack(struct bge_softc * sc)1960 bge_wait_for_event_ack(struct bge_softc *sc)
1961 {
1962 int i;
1963
1964 /* wait up to 2500usec */
1965 for (i = 0; i < 250; i++) {
1966 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
1967 BGE_RX_CPU_DRV_EVENT))
1968 break;
1969 DELAY(10);
1970 }
1971 }
1972
1973 static void
bge_stop_fw(struct bge_softc * sc)1974 bge_stop_fw(struct bge_softc *sc)
1975 {
1976
1977 if (sc->bge_asf_mode) {
1978 bge_wait_for_event_ack(sc);
1979
1980 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
1981 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT,
1982 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
1983
1984 bge_wait_for_event_ack(sc);
1985 }
1986 }
1987
1988 static int
bge_poll_fw(struct bge_softc * sc)1989 bge_poll_fw(struct bge_softc *sc)
1990 {
1991 uint32_t val;
1992 int i;
1993
1994 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) {
1995 for (i = 0; i < BGE_TIMEOUT; i++) {
1996 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
1997 if (val & BGE_VCPU_STATUS_INIT_DONE)
1998 break;
1999 DELAY(100);
2000 }
2001 if (i >= BGE_TIMEOUT) {
2002 aprint_error_dev(sc->bge_dev, "reset timed out\n");
2003 return -1;
2004 }
2005 } else {
2006 /*
2007 * Poll the value location we just wrote until
2008 * we see the 1's complement of the magic number.
2009 * This indicates that the firmware initialization
2010 * is complete.
2011 * XXX 1000ms for Flash and 10000ms for SEEPROM.
2012 */
2013 for (i = 0; i < BGE_TIMEOUT; i++) {
2014 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
2015 if (val == ~BGE_SRAM_FW_MB_MAGIC)
2016 break;
2017 DELAY(10);
2018 }
2019
2020 if ((i >= BGE_TIMEOUT)
2021 && ((sc->bge_flags & BGEF_NO_EEPROM) == 0)) {
2022 aprint_error_dev(sc->bge_dev,
2023 "firmware handshake timed out, val = %x\n", val);
2024 return -1;
2025 }
2026 }
2027
2028 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) {
2029 /* tg3 says we have to wait extra time */
2030 delay(10 * 1000);
2031 }
2032
2033 return 0;
2034 }
2035
2036 int
bge_phy_addr(struct bge_softc * sc)2037 bge_phy_addr(struct bge_softc *sc)
2038 {
2039 struct pci_attach_args *pa = &(sc->bge_pa);
2040 int phy_addr = 1;
2041
2042 /*
2043 * PHY address mapping for various devices.
2044 *
2045 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
2046 * ---------+-------+-------+-------+-------+
2047 * BCM57XX | 1 | X | X | X |
2048 * BCM5704 | 1 | X | 1 | X |
2049 * BCM5717 | 1 | 8 | 2 | 9 |
2050 * BCM5719 | 1 | 8 | 2 | 9 |
2051 * BCM5720 | 1 | 8 | 2 | 9 |
2052 *
2053 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr |
2054 * ---------+-------+-------+-------+-------+
2055 * BCM57XX | X | X | X | X |
2056 * BCM5704 | X | X | X | X |
2057 * BCM5717 | X | X | X | X |
2058 * BCM5719 | 3 | 10 | 4 | 11 |
2059 * BCM5720 | X | X | X | X |
2060 *
2061 * Other addresses may respond but they are not
2062 * IEEE compliant PHYs and should be ignored.
2063 */
2064 switch (BGE_ASICREV(sc->bge_chipid)) {
2065 case BGE_ASICREV_BCM5717:
2066 case BGE_ASICREV_BCM5719:
2067 case BGE_ASICREV_BCM5720:
2068 phy_addr = pa->pa_function;
2069 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) {
2070 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) &
2071 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1;
2072 } else {
2073 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
2074 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1;
2075 }
2076 }
2077
2078 return phy_addr;
2079 }
2080
2081 /*
2082 * Do endian, PCI and DMA initialization. Also check the on-board ROM
2083 * self-test results.
2084 */
2085 static int
bge_chipinit(struct bge_softc * sc)2086 bge_chipinit(struct bge_softc *sc)
2087 {
2088 uint32_t dma_rw_ctl, misc_ctl, mode_ctl, reg;
2089 int i;
2090
2091 /* Set endianness before we access any non-PCI registers. */
2092 misc_ctl = BGE_INIT;
2093 if (sc->bge_flags & BGEF_TAGGED_STATUS)
2094 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS;
2095 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL,
2096 misc_ctl);
2097
2098 /*
2099 * Clear the MAC statistics block in the NIC's
2100 * internal memory.
2101 */
2102 for (i = BGE_STATS_BLOCK;
2103 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
2104 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0);
2105
2106 for (i = BGE_STATUS_BLOCK;
2107 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
2108 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0);
2109
2110 /* 5717 workaround from tg3 */
2111 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) {
2112 /* Save */
2113 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
2114
2115 /* Temporary modify MODE_CTL to control TLP */
2116 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK;
2117 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1);
2118
2119 /* Control TLP */
2120 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG +
2121 BGE_TLP_PHYCTL1);
2122 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1,
2123 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD);
2124
2125 /* Restore */
2126 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
2127 }
2128
2129 if (BGE_IS_57765_FAMILY(sc)) {
2130 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) {
2131 /* Save */
2132 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
2133
2134 /* Temporary modify MODE_CTL to control TLP */
2135 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK;
2136 CSR_WRITE_4(sc, BGE_MODE_CTL,
2137 reg | BGE_MODECTL_PCIE_TLPADDR1);
2138
2139 /* Control TLP */
2140 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG +
2141 BGE_TLP_PHYCTL5);
2142 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5,
2143 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ);
2144
2145 /* Restore */
2146 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
2147 }
2148 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) {
2149 /*
2150 * For the 57766 and non Ax versions of 57765, bootcode
2151 * needs to setup the PCIE Fast Training Sequence (FTS)
2152 * value to prevent transmit hangs.
2153 */
2154 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL);
2155 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL,
2156 reg | BGE_CPMU_PADRNG_CTL_RDIV2);
2157
2158 /* Save */
2159 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
2160
2161 /* Temporary modify MODE_CTL to control TLP */
2162 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK;
2163 CSR_WRITE_4(sc, BGE_MODE_CTL,
2164 reg | BGE_MODECTL_PCIE_TLPADDR0);
2165
2166 /* Control TLP */
2167 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG +
2168 BGE_TLP_FTSMAX);
2169 reg &= ~BGE_TLP_FTSMAX_MSK;
2170 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX,
2171 reg | BGE_TLP_FTSMAX_VAL);
2172
2173 /* Restore */
2174 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
2175 }
2176
2177 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);
2178 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK;
2179 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25;
2180 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg);
2181 }
2182
2183 /* Set up the PCI DMA control register. */
2184 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD;
2185 if (sc->bge_flags & BGEF_PCIE) {
2186 /* Read watermark not used, 128 bytes for write. */
2187 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n",
2188 device_xname(sc->bge_dev)));
2189 if (sc->bge_mps >= 256)
2190 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
2191 else
2192 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
2193 } else if (sc->bge_flags & BGEF_PCIX) {
2194 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n",
2195 device_xname(sc->bge_dev)));
2196 /* PCI-X bus */
2197 if (BGE_IS_5714_FAMILY(sc)) {
2198 /* 256 bytes for read and write. */
2199 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
2200 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
2201
2202 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780)
2203 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
2204 else
2205 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
2206 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) {
2207 /*
2208 * In the BCM5703, the DMA read watermark should
2209 * be set to less than or equal to the maximum
2210 * memory read byte count of the PCI-X command
2211 * register.
2212 */
2213 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
2214 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
2215 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) {
2216 /* 1536 bytes for read, 384 bytes for write. */
2217 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
2218 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
2219 } else {
2220 /* 384 bytes for read and write. */
2221 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
2222 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
2223 (0x0F);
2224 }
2225
2226 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 ||
2227 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) {
2228 uint32_t tmp;
2229
2230 /* Set ONEDMA_ATONCE for hardware workaround. */
2231 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
2232 if (tmp == 6 || tmp == 7)
2233 dma_rw_ctl |=
2234 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
2235
2236 /* Set PCI-X DMA write workaround. */
2237 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
2238 }
2239 } else {
2240 /* Conventional PCI bus: 256 bytes for read and write. */
2241 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n",
2242 device_xname(sc->bge_dev)));
2243 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
2244 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
2245
2246 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 &&
2247 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750)
2248 dma_rw_ctl |= 0x0F;
2249 }
2250
2251 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 ||
2252 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701)
2253 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
2254 BGE_PCIDMARWCTL_ASRT_ALL_BE;
2255
2256 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 ||
2257 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704)
2258 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
2259
2260 if (BGE_IS_57765_PLUS(sc)) {
2261 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
2262 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
2263 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
2264
2265 /*
2266 * Enable HW workaround for controllers that misinterpret
2267 * a status tag update and leave interrupts permanently
2268 * disabled.
2269 */
2270 if (!BGE_IS_57765_FAMILY(sc) &&
2271 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 &&
2272 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5762)
2273 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
2274 }
2275
2276 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL,
2277 dma_rw_ctl);
2278
2279 /*
2280 * Set up general mode register.
2281 */
2282 mode_ctl = BGE_DMA_SWAP_OPTIONS;
2283 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 ||
2284 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) {
2285 /* Retain Host-2-BMC settings written by APE firmware. */
2286 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &
2287 (BGE_MODECTL_BYTESWAP_B2HRX_DATA |
2288 BGE_MODECTL_WORDSWAP_B2HRX_DATA |
2289 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE);
2290 }
2291 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
2292 BGE_MODECTL_TX_NO_PHDR_CSUM;
2293
2294 /*
2295 * BCM5701 B5 have a bug causing data corruption when using
2296 * 64-bit DMA reads, which can be terminated early and then
2297 * completed later as 32-bit accesses, in combination with
2298 * certain bridges.
2299 */
2300 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 &&
2301 sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
2302 mode_ctl |= BGE_MODECTL_FORCE_PCI32;
2303
2304 /*
2305 * Tell the firmware the driver is running
2306 */
2307 if (sc->bge_asf_mode & ASF_STACKUP)
2308 mode_ctl |= BGE_MODECTL_STACKUP;
2309
2310 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
2311
2312 /*
2313 * Disable memory write invalidate. Apparently it is not supported
2314 * properly by these devices.
2315 */
2316 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG,
2317 PCI_COMMAND_INVALIDATE_ENABLE);
2318
2319 #ifdef __brokenalpha__
2320 /*
2321 * Must insure that we do not cross an 8K (bytes) boundary
2322 * for DMA reads. Our highest limit is 1K bytes. This is a
2323 * restriction on some ALPHA platforms with early revision
2324 * 21174 PCI chipsets, such as the AlphaPC 164lx
2325 */
2326 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4);
2327 #endif
2328
2329 /* Set the timer prescaler (always 66MHz) */
2330 CSR_WRITE_4_FLUSH(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
2331
2332 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) {
2333 DELAY(40); /* XXX */
2334
2335 /* Put PHY into ready state */
2336 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
2337 DELAY(40);
2338 }
2339
2340 return 0;
2341 }
2342
2343 static int
bge_blockinit(struct bge_softc * sc)2344 bge_blockinit(struct bge_softc *sc)
2345 {
2346 volatile struct bge_rcb *rcb;
2347 bus_size_t rcb_addr;
2348 struct ifnet * const ifp = &sc->ethercom.ec_if;
2349 bge_hostaddr taddr;
2350 uint32_t dmactl, rdmareg, mimode, val;
2351 int i, limit;
2352
2353 /*
2354 * Initialize the memory window pointer register so that
2355 * we can access the first 32K of internal NIC RAM. This will
2356 * allow us to set up the TX send ring RCBs and the RX return
2357 * ring RCBs, plus other things which live in NIC memory.
2358 */
2359 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0);
2360
2361 if (!BGE_IS_5705_PLUS(sc)) {
2362 /* 57XX step 33 */
2363 /* Configure mbuf memory pool */
2364 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
2365
2366 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704)
2367 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
2368 else
2369 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
2370
2371 /* 57XX step 34 */
2372 /* Configure DMA resource pool */
2373 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
2374 BGE_DMA_DESCRIPTORS);
2375 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
2376 }
2377
2378 /* 5718 step 11, 57XX step 35 */
2379 /*
2380 * Configure mbuf pool watermarks. New broadcom docs strongly
2381 * recommend these.
2382 */
2383 if (BGE_IS_5717_PLUS(sc)) {
2384 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2385 if (ifp->if_mtu > ETHERMTU) {
2386 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
2387 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
2388 } else {
2389 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
2390 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
2391 }
2392 } else if (BGE_IS_5705_PLUS(sc)) {
2393 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2394
2395 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) {
2396 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
2397 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
2398 } else {
2399 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
2400 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
2401 }
2402 } else {
2403 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
2404 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
2405 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
2406 }
2407
2408 /* 57XX step 36 */
2409 /* Configure DMA resource watermarks */
2410 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
2411 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
2412
2413 /* 5718 step 13, 57XX step 38 */
2414 /* Enable buffer manager */
2415 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN;
2416 /*
2417 * Change the arbitration algorithm of TXMBUF read request to
2418 * round-robin instead of priority based for BCM5719. When
2419 * TXFIFO is almost empty, RDMA will hold its request until
2420 * TXFIFO is not almost empty.
2421 */
2422 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719)
2423 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
2424 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 ||
2425 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 ||
2426 sc->bge_chipid == BGE_CHIPID_BCM5720_A0)
2427 val |= BGE_BMANMODE_LOMBUF_ATTN;
2428 CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
2429
2430 /* 57XX step 39 */
2431 /* Poll for buffer manager start indication */
2432 for (i = 0; i < BGE_TIMEOUT * 2; i++) {
2433 DELAY(10);
2434 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
2435 break;
2436 }
2437
2438 if (i == BGE_TIMEOUT * 2) {
2439 aprint_error_dev(sc->bge_dev,
2440 "buffer manager failed to start\n");
2441 return ENXIO;
2442 }
2443
2444 /* 57XX step 40 */
2445 /* Enable flow-through queues */
2446 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2447 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2448
2449 /* Wait until queue initialization is complete */
2450 for (i = 0; i < BGE_TIMEOUT * 2; i++) {
2451 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
2452 break;
2453 DELAY(10);
2454 }
2455
2456 if (i == BGE_TIMEOUT * 2) {
2457 aprint_error_dev(sc->bge_dev,
2458 "flow-through queue init failed\n");
2459 return ENXIO;
2460 }
2461
2462 /*
2463 * Summary of rings supported by the controller:
2464 *
2465 * Standard Receive Producer Ring
2466 * - This ring is used to feed receive buffers for "standard"
2467 * sized frames (typically 1536 bytes) to the controller.
2468 *
2469 * Jumbo Receive Producer Ring
2470 * - This ring is used to feed receive buffers for jumbo sized
2471 * frames (i.e. anything bigger than the "standard" frames)
2472 * to the controller.
2473 *
2474 * Mini Receive Producer Ring
2475 * - This ring is used to feed receive buffers for "mini"
2476 * sized frames to the controller.
2477 * - This feature required external memory for the controller
2478 * but was never used in a production system. Should always
2479 * be disabled.
2480 *
2481 * Receive Return Ring
2482 * - After the controller has placed an incoming frame into a
2483 * receive buffer that buffer is moved into a receive return
2484 * ring. The driver is then responsible to passing the
2485 * buffer up to the stack. Many versions of the controller
2486 * support multiple RR rings.
2487 *
2488 * Send Ring
2489 * - This ring is used for outgoing frames. Many versions of
2490 * the controller support multiple send rings.
2491 */
2492
2493 /* 5718 step 15, 57XX step 41 */
2494 /* Initialize the standard RX ring control block */
2495 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
2496 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring));
2497 /* 5718 step 16 */
2498 if (BGE_IS_57765_PLUS(sc)) {
2499 /*
2500 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
2501 * Bits 15-2 : Maximum RX frame size
2502 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
2503 * Bit 0 : Reserved
2504 */
2505 rcb->bge_maxlen_flags =
2506 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2);
2507 } else if (BGE_IS_5705_PLUS(sc)) {
2508 /*
2509 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
2510 * Bits 15-2 : Reserved (should be 0)
2511 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
2512 * Bit 0 : Reserved
2513 */
2514 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
2515 } else {
2516 /*
2517 * Ring size is always XXX entries
2518 * Bits 31-16: Maximum RX frame size
2519 * Bits 15-2 : Reserved (should be 0)
2520 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
2521 * Bit 0 : Reserved
2522 */
2523 rcb->bge_maxlen_flags =
2524 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
2525 }
2526 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 ||
2527 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 ||
2528 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720)
2529 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
2530 else
2531 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
2532 /* Write the standard receive producer ring control block. */
2533 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
2534 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
2535 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
2536 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
2537
2538 /* Reset the standard receive producer ring producer index. */
2539 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
2540
2541 /* 57XX step 42 */
2542 /*
2543 * Initialize the jumbo RX ring control block
2544 * We set the 'ring disabled' bit in the flags
2545 * field until we're actually ready to start
2546 * using this ring (i.e. once we set the MTU
2547 * high enough to require it).
2548 */
2549 if (BGE_IS_JUMBO_CAPABLE(sc)) {
2550 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
2551 BGE_HOSTADDR(rcb->bge_hostaddr,
2552 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring));
2553 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
2554 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
2555 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 ||
2556 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 ||
2557 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720)
2558 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
2559 else
2560 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
2561 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
2562 rcb->bge_hostaddr.bge_addr_hi);
2563 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
2564 rcb->bge_hostaddr.bge_addr_lo);
2565 /* Program the jumbo receive producer ring RCB parameters. */
2566 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
2567 rcb->bge_maxlen_flags);
2568 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
2569 /* Reset the jumbo receive producer ring producer index. */
2570 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
2571 }
2572
2573 /* 57XX step 43 */
2574 /* Disable the mini receive producer ring RCB. */
2575 if (BGE_IS_5700_FAMILY(sc)) {
2576 /* Set up dummy disabled mini ring RCB */
2577 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
2578 rcb->bge_maxlen_flags =
2579 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
2580 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
2581 rcb->bge_maxlen_flags);
2582 /* Reset the mini receive producer ring producer index. */
2583 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
2584
2585 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
2586 offsetof(struct bge_ring_data, bge_info),
2587 sizeof(struct bge_gib),
2588 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2589 }
2590
2591 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
2592 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) {
2593 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
2594 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
2595 sc->bge_chipid == BGE_CHIPID_BCM5906_A2)
2596 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
2597 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
2598 }
2599 /* 5718 step 14, 57XX step 44 */
2600 /*
2601 * The BD ring replenish thresholds control how often the
2602 * hardware fetches new BD's from the producer rings in host
2603 * memory. Setting the value too low on a busy system can
2604 * starve the hardware and recue the throughpout.
2605 *
2606 * Set the BD ring replenish thresholds. The recommended
2607 * values are 1/8th the number of descriptors allocated to
2608 * each ring, but since we try to avoid filling the entire
2609 * ring we set these to the minimal value of 8. This needs to
2610 * be done on several of the supported chip revisions anyway,
2611 * to work around HW bugs.
2612 */
2613 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8);
2614 if (BGE_IS_JUMBO_CAPABLE(sc))
2615 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8);
2616
2617 /* 5718 step 18 */
2618 if (BGE_IS_5717_PLUS(sc)) {
2619 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4);
2620 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4);
2621 }
2622
2623 /* 57XX step 45 */
2624 /*
2625 * Disable all send rings by setting the 'ring disabled' bit
2626 * in the flags field of all the TX send ring control blocks,
2627 * located in NIC memory.
2628 */
2629 if (BGE_IS_5700_FAMILY(sc)) {
2630 /* 5700 to 5704 had 16 send rings. */
2631 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
2632 } else if (BGE_IS_5717_PLUS(sc)) {
2633 limit = BGE_TX_RINGS_5717_MAX;
2634 } else if (BGE_IS_57765_FAMILY(sc) ||
2635 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) {
2636 limit = BGE_TX_RINGS_57765_MAX;
2637 } else
2638 limit = 1;
2639 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2640 for (i = 0; i < limit; i++) {
2641 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
2642 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
2643 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0);
2644 rcb_addr += sizeof(struct bge_rcb);
2645 }
2646
2647 /* 57XX step 46 and 47 */
2648 /* Configure send ring RCB 0 (we use only the first ring) */
2649 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2650 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring));
2651 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2652 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2653 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 ||
2654 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 ||
2655 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720)
2656 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717);
2657 else
2658 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr,
2659 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
2660 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
2661 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
2662
2663 /* 57XX step 48 */
2664 /*
2665 * Disable all receive return rings by setting the
2666 * 'ring diabled' bit in the flags field of all the receive
2667 * return ring control blocks, located in NIC memory.
2668 */
2669 if (BGE_IS_5717_PLUS(sc)) {
2670 /* Should be 17, use 16 until we get an SRAM map. */
2671 limit = 16;
2672 } else if (BGE_IS_5700_FAMILY(sc))
2673 limit = BGE_RX_RINGS_MAX;
2674 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 ||
2675 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762 ||
2676 BGE_IS_57765_FAMILY(sc))
2677 limit = 4;
2678 else
2679 limit = 1;
2680 /* Disable all receive return rings */
2681 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2682 for (i = 0; i < limit; i++) {
2683 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0);
2684 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0);
2685 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
2686 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
2687 BGE_RCB_FLAG_RING_DISABLED));
2688 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0);
2689 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
2690 (i * (sizeof(uint64_t))), 0);
2691 rcb_addr += sizeof(struct bge_rcb);
2692 }
2693
2694 /* 57XX step 49 */
2695 /*
2696 * Set up receive return ring 0. Note that the NIC address
2697 * for RX return rings is 0x0. The return rings live entirely
2698 * within the host, so the nicaddr field in the RCB isn't used.
2699 */
2700 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2701 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring));
2702 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2703 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2704 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000);
2705 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
2706 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
2707
2708 /* 5718 step 24, 57XX step 53 */
2709 /* Set random backoff seed for TX */
2710 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
2711 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] +
2712 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] +
2713 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) &
2714 BGE_TX_BACKOFF_SEED_MASK);
2715
2716 /* 5718 step 26, 57XX step 55 */
2717 /* Set inter-packet gap */
2718 val = 0x2620;
2719 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 ||
2720 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762)
2721 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
2722 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
2723 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
2724
2725 /* 5718 step 27, 57XX step 56 */
2726 /*
2727 * Specify which ring to use for packets that don't match
2728 * any RX rules.
2729 */
2730 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
2731
2732 /* 5718 step 28, 57XX step 57 */
2733 /*
2734 * Configure number of RX lists. One interrupt distribution
2735 * list, sixteen active lists, one bad frames class.
2736 */
2737 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
2738
2739 /* 5718 step 29, 57XX step 58 */
2740 /* Inialize RX list placement stats mask. */
2741 if (BGE_IS_575X_PLUS(sc)) {
2742 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK);
2743 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX;
2744 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val);
2745 } else
2746 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
2747
2748 /* 5718 step 30, 57XX step 59 */
2749 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
2750
2751 /* 5718 step 33, 57XX step 62 */
2752 /* Disable host coalescing until we get it set up */
2753 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
2754
2755 /* 5718 step 34, 57XX step 63 */
2756 /* Poll to make sure it's shut down. */
2757 for (i = 0; i < BGE_TIMEOUT * 2; i++) {
2758 DELAY(10);
2759 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
2760 break;
2761 }
2762
2763 if (i == BGE_TIMEOUT * 2) {
2764 aprint_error_dev(sc->bge_dev,
2765 "host coalescing engine failed to idle\n");
2766 return ENXIO;
2767 }
2768
2769 /* 5718 step 35, 36, 37 */
2770 /* Set up host coalescing defaults */
2771 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
2772 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
2773 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
2774 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
2775 if (!(BGE_IS_5705_PLUS(sc))) {
2776 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
2777 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
2778 }
2779 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
2780 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
2781
2782 /* Set up address of statistics block */
2783 if (BGE_IS_5700_FAMILY(sc)) {
2784 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats));
2785 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
2786 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
2787 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi);
2788 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo);
2789 }
2790
2791 /* 5718 step 38 */
2792 /* Set up address of status block */
2793 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block));
2794 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
2795 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi);
2796 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo);
2797 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0;
2798 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0;
2799
2800 /* Set up status block size. */
2801 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 &&
2802 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
2803 val = BGE_STATBLKSZ_FULL;
2804 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ);
2805 } else {
2806 val = BGE_STATBLKSZ_32BYTE;
2807 bzero(&sc->bge_rdata->bge_status_block, 32);
2808 }
2809
2810 /* 5718 step 39, 57XX step 73 */
2811 /* Turn on host coalescing state machine */
2812 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
2813
2814 /* 5718 step 40, 57XX step 74 */
2815 /* Turn on RX BD completion state machine and enable attentions */
2816 CSR_WRITE_4(sc, BGE_RBDC_MODE,
2817 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
2818
2819 /* 5718 step 41, 57XX step 75 */
2820 /* Turn on RX list placement state machine */
2821 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2822
2823 /* 57XX step 76 */
2824 /* Turn on RX list selector state machine. */
2825 if (!(BGE_IS_5705_PLUS(sc)))
2826 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2827
2828 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
2829 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
2830 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
2831 BGE_MACMODE_FRMHDR_DMA_ENB;
2832
2833 if (sc->bge_flags & BGEF_FIBER_TBI)
2834 val |= BGE_PORTMODE_TBI;
2835 else if (sc->bge_flags & BGEF_FIBER_MII)
2836 val |= BGE_PORTMODE_GMII;
2837 else
2838 val |= BGE_PORTMODE_MII;
2839
2840 /* 5718 step 42 and 43, 57XX step 77 and 78 */
2841 /* Allow APE to send/receive frames. */
2842 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
2843 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
2844
2845 /* Turn on DMA, clear stats */
2846 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val);
2847 /* 5718 step 44 */
2848 DELAY(40);
2849
2850 /* 5718 step 45, 57XX step 79 */
2851 /* Set misc. local control, enable interrupts on attentions */
2852 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
2853 if (BGE_IS_5717_PLUS(sc)) {
2854 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */
2855 /* 5718 step 46 */
2856 DELAY(100);
2857 }
2858
2859 /* 57XX step 81 */
2860 /* Turn on DMA completion state machine */
2861 if (!(BGE_IS_5705_PLUS(sc)))
2862 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2863
2864 /* 5718 step 47, 57XX step 82 */
2865 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
2866
2867 /* 5718 step 48 */
2868 /* Enable host coalescing bug fix. */
2869 if (BGE_IS_5755_PLUS(sc))
2870 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
2871
2872 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)
2873 val |= BGE_WDMAMODE_BURST_ALL_DATA;
2874
2875 /* Turn on write DMA state machine */
2876 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val);
2877 /* 5718 step 49 */
2878 DELAY(40);
2879
2880 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
2881
2882 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717)
2883 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
2884
2885 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 ||
2886 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 ||
2887 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780)
2888 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
2889 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
2890 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
2891
2892 if (sc->bge_flags & BGEF_PCIE)
2893 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
2894 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) {
2895 if (ifp->if_mtu <= ETHERMTU)
2896 val |= BGE_RDMAMODE_JMB_2K_MMRR;
2897 }
2898 if (sc->bge_flags & BGEF_TSO) {
2899 val |= BGE_RDMAMODE_TSO4_ENABLE;
2900 if (BGE_IS_5717_PLUS(sc))
2901 val |= BGE_RDMAMODE_TSO6_ENABLE;
2902 }
2903
2904 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 ||
2905 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) {
2906 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
2907 BGE_RDMAMODE_H2BNC_VLAN_DET;
2908 /*
2909 * Allow multiple outstanding read requests from
2910 * non-LSO read DMA engine.
2911 */
2912 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
2913 }
2914
2915 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 ||
2916 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 ||
2917 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 ||
2918 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 ||
2919 BGE_IS_57765_PLUS(sc)) {
2920 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762)
2921 rdmareg = BGE_RDMA_RSRVCTRL_REG2;
2922 else
2923 rdmareg = BGE_RDMA_RSRVCTRL;
2924 dmactl = CSR_READ_4(sc, rdmareg);
2925 /*
2926 * Adjust tx margin to prevent TX data corruption and
2927 * fix internal FIFO overflow.
2928 */
2929 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 ||
2930 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) {
2931 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
2932 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
2933 BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
2934 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
2935 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
2936 BGE_RDMA_RSRVCTRL_TXMRGN_320B;
2937 }
2938 /*
2939 * Enable fix for read DMA FIFO overruns.
2940 * The fix is to limit the number of RX BDs
2941 * the hardware would fetch at a time.
2942 */
2943 CSR_WRITE_4(sc, rdmareg, dmactl |
2944 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
2945 }
2946
2947 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) {
2948 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2949 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2950 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2951 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2952 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) {
2953 /*
2954 * Allow 4KB burst length reads for non-LSO frames.
2955 * Enable 512B burst length reads for buffer descriptors.
2956 */
2957 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2958 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2959 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
2960 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2961 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) {
2962 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2,
2963 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) |
2964 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2965 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2966 }
2967 /* Turn on read DMA state machine */
2968 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val);
2969 /* 5718 step 52 */
2970 delay(40);
2971
2972 if (sc->bge_flags & BGEF_RDMA_BUG) {
2973 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) {
2974 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4);
2975 if ((val & 0xFFFF) > BGE_FRAMELEN)
2976 break;
2977 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN)
2978 break;
2979 }
2980 if (i != BGE_NUM_RDMA_CHANNELS / 2) {
2981 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
2982 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719)
2983 val |= BGE_RDMA_TX_LENGTH_WA_5719;
2984 else
2985 val |= BGE_RDMA_TX_LENGTH_WA_5720;
2986 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
2987 }
2988 }
2989
2990 /* 5718 step 56, 57XX step 84 */
2991 /* Turn on RX data completion state machine */
2992 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2993
2994 /* Turn on RX data and RX BD initiator state machine */
2995 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
2996
2997 /* 57XX step 85 */
2998 /* Turn on Mbuf cluster free state machine */
2999 if (!BGE_IS_5705_PLUS(sc))
3000 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3001
3002 /* 5718 step 57, 57XX step 86 */
3003 /* Turn on send data completion state machine */
3004 val = BGE_SDCMODE_ENABLE;
3005 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761)
3006 val |= BGE_SDCMODE_CDELAY;
3007 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
3008
3009 /* 5718 step 58 */
3010 /* Turn on send BD completion state machine */
3011 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3012
3013 /* 57XX step 88 */
3014 /* Turn on RX BD initiator state machine */
3015 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3016
3017 /* 5718 step 60, 57XX step 90 */
3018 /* Turn on send data initiator state machine */
3019 if (sc->bge_flags & BGEF_TSO) {
3020 /* XXX: magic value from Linux driver */
3021 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
3022 BGE_SDIMODE_HW_LSO_PRE_DMA);
3023 } else
3024 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3025
3026 /* 5718 step 61, 57XX step 91 */
3027 /* Turn on send BD initiator state machine */
3028 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3029
3030 /* 5718 step 62, 57XX step 92 */
3031 /* Turn on send BD selector state machine */
3032 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3033
3034 /* 5718 step 31, 57XX step 60 */
3035 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
3036 /* 5718 step 32, 57XX step 61 */
3037 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
3038 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
3039
3040 /* ack/clear link change events */
3041 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3042 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3043 BGE_MACSTAT_LINK_CHANGED);
3044 CSR_WRITE_4(sc, BGE_MI_STS, 0);
3045
3046 /*
3047 * Enable attention when the link has changed state for
3048 * devices that use auto polling.
3049 */
3050 if (sc->bge_flags & BGEF_FIBER_TBI) {
3051 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
3052 } else {
3053 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0)
3054 mimode = BGE_MIMODE_500KHZ_CONST;
3055 else
3056 mimode = BGE_MIMODE_BASE;
3057 /* 5718 step 68. 5718 step 69 (optionally). */
3058 if (BGE_IS_5700_FAMILY(sc) ||
3059 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705) {
3060 mimode |= BGE_MIMODE_AUTOPOLL;
3061 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL);
3062 }
3063 mimode |= BGE_MIMODE_PHYADDR(sc->bge_phy_addr);
3064 CSR_WRITE_4(sc, BGE_MI_MODE, mimode);
3065 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700)
3066 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
3067 BGE_EVTENB_MI_INTERRUPT);
3068 }
3069
3070 /*
3071 * Clear any pending link state attention.
3072 * Otherwise some link state change events may be lost until attention
3073 * is cleared by bge_intr() -> bge_link_upd() sequence.
3074 * It's not necessary on newer BCM chips - perhaps enabling link
3075 * state change attentions implies clearing pending attention.
3076 */
3077 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3078 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3079 BGE_MACSTAT_LINK_CHANGED);
3080
3081 /* Enable link state change attentions. */
3082 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
3083
3084 return 0;
3085 }
3086
3087 static const struct bge_revision *
bge_lookup_rev(uint32_t chipid)3088 bge_lookup_rev(uint32_t chipid)
3089 {
3090 const struct bge_revision *br;
3091
3092 for (br = bge_revisions; br->br_name != NULL; br++) {
3093 if (br->br_chipid == chipid)
3094 return br;
3095 }
3096
3097 for (br = bge_majorrevs; br->br_name != NULL; br++) {
3098 if (br->br_chipid == BGE_ASICREV(chipid))
3099 return br;
3100 }
3101
3102 return NULL;
3103 }
3104
3105 static const struct bge_product *
bge_lookup(const struct pci_attach_args * pa)3106 bge_lookup(const struct pci_attach_args *pa)
3107 {
3108 const struct bge_product *bp;
3109
3110 for (bp = bge_products; bp->bp_name != NULL; bp++) {
3111 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor &&
3112 PCI_PRODUCT(pa->pa_id) == bp->bp_product)
3113 return bp;
3114 }
3115
3116 return NULL;
3117 }
3118
3119 static uint32_t
bge_chipid(const struct pci_attach_args * pa)3120 bge_chipid(const struct pci_attach_args *pa)
3121 {
3122 uint32_t id;
3123
3124 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL)
3125 >> BGE_PCIMISCCTL_ASICREV_SHIFT;
3126
3127 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) {
3128 switch (PCI_PRODUCT(pa->pa_id)) {
3129 case PCI_PRODUCT_BROADCOM_BCM5717:
3130 case PCI_PRODUCT_BROADCOM_BCM5718:
3131 case PCI_PRODUCT_BROADCOM_BCM5719:
3132 case PCI_PRODUCT_BROADCOM_BCM5720:
3133 case PCI_PRODUCT_BROADCOM_BCM5725:
3134 case PCI_PRODUCT_BROADCOM_BCM5727:
3135 case PCI_PRODUCT_BROADCOM_BCM5762:
3136 case PCI_PRODUCT_BROADCOM_BCM57764:
3137 case PCI_PRODUCT_BROADCOM_BCM57767:
3138 case PCI_PRODUCT_BROADCOM_BCM57787:
3139 id = pci_conf_read(pa->pa_pc, pa->pa_tag,
3140 BGE_PCI_GEN2_PRODID_ASICREV);
3141 break;
3142 case PCI_PRODUCT_BROADCOM_BCM57761:
3143 case PCI_PRODUCT_BROADCOM_BCM57762:
3144 case PCI_PRODUCT_BROADCOM_BCM57765:
3145 case PCI_PRODUCT_BROADCOM_BCM57766:
3146 case PCI_PRODUCT_BROADCOM_BCM57781:
3147 case PCI_PRODUCT_BROADCOM_BCM57782:
3148 case PCI_PRODUCT_BROADCOM_BCM57785:
3149 case PCI_PRODUCT_BROADCOM_BCM57786:
3150 case PCI_PRODUCT_BROADCOM_BCM57791:
3151 case PCI_PRODUCT_BROADCOM_BCM57795:
3152 id = pci_conf_read(pa->pa_pc, pa->pa_tag,
3153 BGE_PCI_GEN15_PRODID_ASICREV);
3154 break;
3155 default:
3156 id = pci_conf_read(pa->pa_pc, pa->pa_tag,
3157 BGE_PCI_PRODID_ASICREV);
3158 break;
3159 }
3160 }
3161
3162 return id;
3163 }
3164
3165 /*
3166 * Return true if MSI can be used with this device.
3167 */
3168 static int
bge_can_use_msi(struct bge_softc * sc)3169 bge_can_use_msi(struct bge_softc *sc)
3170 {
3171 int can_use_msi = 0;
3172
3173 switch (BGE_ASICREV(sc->bge_chipid)) {
3174 case BGE_ASICREV_BCM5714_A0:
3175 case BGE_ASICREV_BCM5714:
3176 /*
3177 * Apparently, MSI doesn't work when these chips are
3178 * configured in single-port mode.
3179 */
3180 break;
3181 case BGE_ASICREV_BCM5750:
3182 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_AX &&
3183 BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_BX)
3184 can_use_msi = 1;
3185 break;
3186 default:
3187 if (BGE_IS_575X_PLUS(sc))
3188 can_use_msi = 1;
3189 }
3190 return can_use_msi;
3191 }
3192
3193 /*
3194 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
3195 * against our list and return its name if we find a match. Note
3196 * that since the Broadcom controller contains VPD support, we
3197 * can get the device name string from the controller itself instead
3198 * of the compiled-in string. This is a little slow, but it guarantees
3199 * we'll always announce the right product name.
3200 */
3201 static int
bge_probe(device_t parent,cfdata_t match,void * aux)3202 bge_probe(device_t parent, cfdata_t match, void *aux)
3203 {
3204 struct pci_attach_args *pa = (struct pci_attach_args *)aux;
3205
3206 if (bge_lookup(pa) != NULL)
3207 return 1;
3208
3209 return 0;
3210 }
3211
3212 static void
bge_attach(device_t parent,device_t self,void * aux)3213 bge_attach(device_t parent, device_t self, void *aux)
3214 {
3215 struct bge_softc * const sc = device_private(self);
3216 struct pci_attach_args * const pa = aux;
3217 prop_dictionary_t dict;
3218 const struct bge_product *bp;
3219 const struct bge_revision *br;
3220 pci_chipset_tag_t pc;
3221 const char *intrstr = NULL;
3222 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5;
3223 uint32_t command;
3224 struct ifnet *ifp;
3225 struct mii_data * const mii = &sc->bge_mii;
3226 uint32_t misccfg, mimode, macmode;
3227 void * kva;
3228 u_char eaddr[ETHER_ADDR_LEN];
3229 pcireg_t memtype, subid, reg;
3230 bus_addr_t memaddr;
3231 uint32_t pm_ctl;
3232 bool no_seeprom;
3233 int capmask, trys;
3234 int mii_flags;
3235 int map_flags;
3236 char intrbuf[PCI_INTRSTR_LEN];
3237
3238 bp = bge_lookup(pa);
3239 KASSERT(bp != NULL);
3240
3241 sc->sc_pc = pa->pa_pc;
3242 sc->sc_pcitag = pa->pa_tag;
3243 sc->bge_dev = self;
3244
3245 sc->bge_pa = *pa;
3246 pc = sc->sc_pc;
3247 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG);
3248
3249 aprint_naive(": Ethernet controller\n");
3250 aprint_normal(": %s Ethernet\n", bp->bp_name);
3251
3252 /*
3253 * Map control/status registers.
3254 */
3255 DPRINTFN(5, ("Map control/status regs\n"));
3256 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG);
3257 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
3258 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command);
3259 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG);
3260
3261 if (!(command & PCI_COMMAND_MEM_ENABLE)) {
3262 aprint_error_dev(sc->bge_dev,
3263 "failed to enable memory mapping!\n");
3264 return;
3265 }
3266
3267 DPRINTFN(5, ("pci_mem_find\n"));
3268 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0);
3269 switch (memtype) {
3270 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
3271 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
3272 #if 0
3273 if (pci_mapreg_map(pa, BGE_PCI_BAR0,
3274 memtype, 0, &sc->bge_btag, &sc->bge_bhandle,
3275 &memaddr, &sc->bge_bsize) == 0)
3276 break;
3277 #else
3278 /*
3279 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based
3280 * system get NMI on boot (PR#48451). This problem might not be
3281 * the driver's bug but our PCI common part's bug. Until we
3282 * find a real reason, we ignore the prefetchable bit.
3283 */
3284 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0,
3285 memtype, &memaddr, &sc->bge_bsize, &map_flags) == 0) {
3286 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE;
3287 if (bus_space_map(pa->pa_memt, memaddr, sc->bge_bsize,
3288 map_flags, &sc->bge_bhandle) == 0) {
3289 sc->bge_btag = pa->pa_memt;
3290 break;
3291 }
3292 }
3293 #endif
3294 /* FALLTHROUGH */
3295 default:
3296 aprint_error_dev(sc->bge_dev, "can't find mem space\n");
3297 return;
3298 }
3299
3300 sc->bge_stopping = false;
3301 sc->bge_txrx_stopping = false;
3302
3303 /* Save various chip information. */
3304 sc->bge_chipid = bge_chipid(pa);
3305 sc->bge_phy_addr = bge_phy_addr(sc);
3306
3307 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS,
3308 &sc->bge_pciecap, NULL) != 0) {
3309 /* PCIe */
3310 sc->bge_flags |= BGEF_PCIE;
3311 /* Extract supported maximum payload size. */
3312 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
3313 sc->bge_pciecap + PCIE_DCAP);
3314 sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD);
3315 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 ||
3316 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720)
3317 sc->bge_expmrq = 2048;
3318 else
3319 sc->bge_expmrq = 4096;
3320 bge_set_max_readrq(sc);
3321 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) {
3322 /* PCIe without PCIe cap */
3323 sc->bge_flags |= BGEF_PCIE;
3324 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) &
3325 BGE_PCISTATE_PCI_BUSMODE) == 0) {
3326 /* PCI-X */
3327 sc->bge_flags |= BGEF_PCIX;
3328 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX,
3329 &sc->bge_pcixcap, NULL) == 0)
3330 aprint_error_dev(sc->bge_dev,
3331 "unable to find PCIX capability\n");
3332 }
3333
3334 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) {
3335 /*
3336 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?)
3337 * can clobber the chip's PCI config-space power control
3338 * registers, leaving the card in D3 powersave state. We do
3339 * not have memory-mapped registers in this state, so force
3340 * device into D0 state before starting initialization.
3341 */
3342 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD);
3343 pm_ctl &= ~(PCI_PWR_D0 | PCI_PWR_D1 | PCI_PWR_D2 | PCI_PWR_D3);
3344 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */
3345 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl);
3346 DELAY(1000); /* 27 usec is allegedly sufficient */
3347 }
3348
3349 /* Save chipset family. */
3350 switch (BGE_ASICREV(sc->bge_chipid)) {
3351 case BGE_ASICREV_BCM5717:
3352 case BGE_ASICREV_BCM5719:
3353 case BGE_ASICREV_BCM5720:
3354 sc->bge_flags |= BGEF_5717_PLUS;
3355 /* FALLTHROUGH */
3356 case BGE_ASICREV_BCM5762:
3357 case BGE_ASICREV_BCM57765:
3358 case BGE_ASICREV_BCM57766:
3359 if (!BGE_IS_5717_PLUS(sc))
3360 sc->bge_flags |= BGEF_57765_FAMILY;
3361 sc->bge_flags |= BGEF_57765_PLUS | BGEF_5755_PLUS |
3362 BGEF_575X_PLUS | BGEF_5705_PLUS | BGEF_JUMBO_CAPABLE;
3363 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 ||
3364 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) {
3365 /*
3366 * Enable work around for DMA engine miscalculation
3367 * of TXMBUF available space.
3368 */
3369 sc->bge_flags |= BGEF_RDMA_BUG;
3370
3371 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) &&
3372 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) {
3373 /* Jumbo frame on BCM5719 A0 does not work. */
3374 sc->bge_flags &= ~BGEF_JUMBO_CAPABLE;
3375 }
3376 }
3377 break;
3378 case BGE_ASICREV_BCM5755:
3379 case BGE_ASICREV_BCM5761:
3380 case BGE_ASICREV_BCM5784:
3381 case BGE_ASICREV_BCM5785:
3382 case BGE_ASICREV_BCM5787:
3383 case BGE_ASICREV_BCM57780:
3384 sc->bge_flags |= BGEF_5755_PLUS | BGEF_575X_PLUS | BGEF_5705_PLUS;
3385 break;
3386 case BGE_ASICREV_BCM5700:
3387 case BGE_ASICREV_BCM5701:
3388 case BGE_ASICREV_BCM5703:
3389 case BGE_ASICREV_BCM5704:
3390 sc->bge_flags |= BGEF_5700_FAMILY | BGEF_JUMBO_CAPABLE;
3391 break;
3392 case BGE_ASICREV_BCM5714_A0:
3393 case BGE_ASICREV_BCM5780:
3394 case BGE_ASICREV_BCM5714:
3395 sc->bge_flags |= BGEF_5714_FAMILY | BGEF_JUMBO_CAPABLE;
3396 /* FALLTHROUGH */
3397 case BGE_ASICREV_BCM5750:
3398 case BGE_ASICREV_BCM5752:
3399 case BGE_ASICREV_BCM5906:
3400 sc->bge_flags |= BGEF_575X_PLUS;
3401 /* FALLTHROUGH */
3402 case BGE_ASICREV_BCM5705:
3403 sc->bge_flags |= BGEF_5705_PLUS;
3404 break;
3405 }
3406
3407 /* Identify chips with APE processor. */
3408 switch (BGE_ASICREV(sc->bge_chipid)) {
3409 case BGE_ASICREV_BCM5717:
3410 case BGE_ASICREV_BCM5719:
3411 case BGE_ASICREV_BCM5720:
3412 case BGE_ASICREV_BCM5761:
3413 case BGE_ASICREV_BCM5762:
3414 sc->bge_flags |= BGEF_APE;
3415 break;
3416 }
3417
3418 /*
3419 * The 40bit DMA bug applies to the 5714/5715 controllers and is
3420 * not actually a MAC controller bug but an issue with the embedded
3421 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
3422 */
3423 if (BGE_IS_5714_FAMILY(sc) && ((sc->bge_flags & BGEF_PCIX) != 0))
3424 sc->bge_flags |= BGEF_40BIT_BUG;
3425
3426 /* Chips with APE need BAR2 access for APE registers/memory. */
3427 if ((sc->bge_flags & BGEF_APE) != 0) {
3428 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2);
3429 #if 0
3430 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0,
3431 &sc->bge_apetag, &sc->bge_apehandle, NULL,
3432 &sc->bge_apesize)) {
3433 aprint_error_dev(sc->bge_dev,
3434 "couldn't map BAR2 memory\n");
3435 return;
3436 }
3437 #else
3438 /*
3439 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based
3440 * system get NMI on boot (PR#48451). This problem might not be
3441 * the driver's bug but our PCI common part's bug. Until we
3442 * find a real reason, we ignore the prefetchable bit.
3443 */
3444 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2,
3445 memtype, &memaddr, &sc->bge_apesize, &map_flags) != 0) {
3446 aprint_error_dev(sc->bge_dev,
3447 "couldn't map BAR2 memory\n");
3448 return;
3449 }
3450
3451 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE;
3452 if (bus_space_map(pa->pa_memt, memaddr,
3453 sc->bge_apesize, map_flags, &sc->bge_apehandle) != 0) {
3454 aprint_error_dev(sc->bge_dev,
3455 "couldn't map BAR2 memory\n");
3456 return;
3457 }
3458 sc->bge_apetag = pa->pa_memt;
3459 #endif
3460
3461 /* Enable APE register/memory access by host driver. */
3462 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE);
3463 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
3464 BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
3465 BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
3466 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg);
3467
3468 bge_ape_lock_init(sc);
3469 bge_ape_read_fw_ver(sc);
3470 }
3471
3472 /* Identify the chips that use an CPMU. */
3473 if (BGE_IS_5717_PLUS(sc) ||
3474 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 ||
3475 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 ||
3476 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 ||
3477 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780)
3478 sc->bge_flags |= BGEF_CPMU_PRESENT;
3479
3480 /*
3481 * When using the BCM5701 in PCI-X mode, data corruption has
3482 * been observed in the first few bytes of some received packets.
3483 * Aligning the packet buffer in memory eliminates the corruption.
3484 * Unfortunately, this misaligns the packet payloads. On platforms
3485 * which do not support unaligned accesses, we will realign the
3486 * payloads by copying the received packets.
3487 */
3488 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 &&
3489 sc->bge_flags & BGEF_PCIX)
3490 sc->bge_flags |= BGEF_RX_ALIGNBUG;
3491
3492 if (BGE_IS_5700_FAMILY(sc))
3493 sc->bge_flags |= BGEF_JUMBO_CAPABLE;
3494
3495 misccfg = CSR_READ_4(sc, BGE_MISC_CFG);
3496 misccfg &= BGE_MISCCFG_BOARD_ID_MASK;
3497
3498 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 &&
3499 (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
3500 misccfg == BGE_MISCCFG_BOARD_ID_5788M))
3501 sc->bge_flags |= BGEF_IS_5788;
3502
3503 /*
3504 * Some controllers seem to require a special firmware to use
3505 * TSO. But the firmware is not available to FreeBSD and Linux
3506 * claims that the TSO performed by the firmware is slower than
3507 * hardware based TSO. Moreover the firmware based TSO has one
3508 * known bug which can't handle TSO if ethernet header + IP/TCP
3509 * header is greater than 80 bytes. The workaround for the TSO
3510 * bug exist but it seems it's too expensive than not using
3511 * TSO at all. Some hardwares also have the TSO bug so limit
3512 * the TSO to the controllers that are not affected TSO issues
3513 * (e.g. 5755 or higher).
3514 */
3515 if (BGE_IS_5755_PLUS(sc)) {
3516 /*
3517 * BCM5754 and BCM5787 shares the same ASIC id so
3518 * explicit device id check is required.
3519 */
3520 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) &&
3521 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M))
3522 sc->bge_flags |= BGEF_TSO;
3523 /* TSO on BCM5719 A0 does not work. */
3524 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) &&
3525 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0))
3526 sc->bge_flags &= ~BGEF_TSO;
3527 }
3528
3529 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */
3530 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 &&
3531 (misccfg == 0x4000 || misccfg == 0x8000)) ||
3532 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 &&
3533 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM &&
3534 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 ||
3535 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 ||
3536 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) ||
3537 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM &&
3538 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F ||
3539 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F ||
3540 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) ||
3541 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 ||
3542 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 ||
3543 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 ||
3544 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) {
3545 /* These chips are 10/100 only. */
3546 capmask &= ~BMSR_EXTSTAT;
3547 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED;
3548 }
3549
3550 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 ||
3551 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 &&
3552 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
3553 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)))
3554 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED;
3555
3556 /* Set various PHY bug flags. */
3557 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
3558 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
3559 sc->bge_phy_flags |= BGEPHYF_CRC_BUG;
3560 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX ||
3561 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX)
3562 sc->bge_phy_flags |= BGEPHYF_ADC_BUG;
3563 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
3564 sc->bge_phy_flags |= BGEPHYF_5704_A0_BUG;
3565 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 ||
3566 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) &&
3567 PCI_VENDOR(subid) == PCI_VENDOR_DELL)
3568 sc->bge_phy_flags |= BGEPHYF_NO_3LED;
3569 if (BGE_IS_5705_PLUS(sc) &&
3570 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 &&
3571 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 &&
3572 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 &&
3573 !BGE_IS_57765_PLUS(sc)) {
3574 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 ||
3575 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 ||
3576 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 ||
3577 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) {
3578 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 &&
3579 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756)
3580 sc->bge_phy_flags |= BGEPHYF_JITTER_BUG;
3581 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M)
3582 sc->bge_phy_flags |= BGEPHYF_ADJUST_TRIM;
3583 } else
3584 sc->bge_phy_flags |= BGEPHYF_BER_BUG;
3585 }
3586
3587 /*
3588 * SEEPROM check.
3589 * First check if firmware knows we do not have SEEPROM.
3590 */
3591 if (prop_dictionary_get_bool(device_properties(self),
3592 "without-seeprom", &no_seeprom) && no_seeprom)
3593 sc->bge_flags |= BGEF_NO_EEPROM;
3594
3595 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
3596 sc->bge_flags |= BGEF_NO_EEPROM;
3597
3598 /* Now check the 'ROM failed' bit on the RX CPU */
3599 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL)
3600 sc->bge_flags |= BGEF_NO_EEPROM;
3601
3602 sc->bge_asf_mode = 0;
3603 /* No ASF if APE present. */
3604 if ((sc->bge_flags & BGEF_APE) == 0) {
3605 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
3606 BGE_SRAM_DATA_SIG_MAGIC)) {
3607 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) &
3608 BGE_HWCFG_ASF) {
3609 sc->bge_asf_mode |= ASF_ENABLE;
3610 sc->bge_asf_mode |= ASF_STACKUP;
3611 if (BGE_IS_575X_PLUS(sc))
3612 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
3613 }
3614 }
3615 }
3616
3617 int counts[PCI_INTR_TYPE_SIZE] = {
3618 [PCI_INTR_TYPE_INTX] = 1,
3619 [PCI_INTR_TYPE_MSI] = 1,
3620 [PCI_INTR_TYPE_MSIX] = 1,
3621 };
3622 int max_type = PCI_INTR_TYPE_MSIX;
3623
3624 if (!bge_can_use_msi(sc)) {
3625 /* MSI broken, allow only INTx */
3626 max_type = PCI_INTR_TYPE_INTX;
3627 }
3628
3629 if (pci_intr_alloc(pa, &sc->bge_pihp, counts, max_type) != 0) {
3630 aprint_error_dev(sc->bge_dev, "couldn't alloc interrupt\n");
3631 return;
3632 }
3633
3634 DPRINTFN(5, ("pci_intr_string\n"));
3635 intrstr = pci_intr_string(pc, sc->bge_pihp[0], intrbuf,
3636 sizeof(intrbuf));
3637 DPRINTFN(5, ("pci_intr_establish\n"));
3638 sc->bge_intrhand = pci_intr_establish_xname(pc, sc->bge_pihp[0],
3639 IPL_NET, bge_intr, sc, device_xname(sc->bge_dev));
3640 if (sc->bge_intrhand == NULL) {
3641 pci_intr_release(pc, sc->bge_pihp, 1);
3642 sc->bge_pihp = NULL;
3643
3644 aprint_error_dev(self, "couldn't establish interrupt");
3645 if (intrstr != NULL)
3646 aprint_error(" at %s", intrstr);
3647 aprint_error("\n");
3648 return;
3649 }
3650 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr);
3651
3652 switch (pci_intr_type(pc, sc->bge_pihp[0])) {
3653 case PCI_INTR_TYPE_MSIX:
3654 case PCI_INTR_TYPE_MSI:
3655 KASSERT(bge_can_use_msi(sc));
3656 sc->bge_flags |= BGEF_MSI;
3657 break;
3658 default:
3659 /* nothing to do */
3660 break;
3661 }
3662
3663 char wqname[MAXCOMLEN];
3664 snprintf(wqname, sizeof(wqname), "%sReset", device_xname(sc->bge_dev));
3665 int error = workqueue_create(&sc->sc_reset_wq, wqname,
3666 bge_handle_reset_work, sc, PRI_NONE, IPL_SOFTCLOCK,
3667 WQ_MPSAFE);
3668 if (error) {
3669 aprint_error_dev(sc->bge_dev,
3670 "unable to create reset workqueue\n");
3671 return;
3672 }
3673
3674
3675 /*
3676 * All controllers except BCM5700 supports tagged status but
3677 * we use tagged status only for MSI case on BCM5717. Otherwise
3678 * MSI on BCM5717 does not work.
3679 */
3680 if (BGE_IS_57765_PLUS(sc) && sc->bge_flags & BGEF_MSI)
3681 sc->bge_flags |= BGEF_TAGGED_STATUS;
3682
3683 /*
3684 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM
3685 * lock in bge_reset().
3686 */
3687 CSR_WRITE_4_FLUSH(sc, BGE_EE_ADDR,
3688 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
3689 delay(1000);
3690 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
3691
3692 bge_stop_fw(sc);
3693 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
3694 if (bge_reset(sc))
3695 aprint_error_dev(sc->bge_dev, "chip reset failed\n");
3696
3697 /*
3698 * Read the hardware config word in the first 32k of NIC internal
3699 * memory, or fall back to the config word in the EEPROM.
3700 * Note: on some BCM5700 cards, this value appears to be unset.
3701 */
3702 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = hwcfg5 = 0;
3703 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
3704 BGE_SRAM_DATA_SIG_MAGIC) {
3705 uint32_t tmp;
3706
3707 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
3708 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >>
3709 BGE_SRAM_DATA_VER_SHIFT;
3710 if ((0 < tmp) && (tmp < 0x100))
3711 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2);
3712 if (sc->bge_flags & BGEF_PCIE)
3713 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3);
3714 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)
3715 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4);
3716 if (BGE_IS_5717_PLUS(sc))
3717 hwcfg5 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_5);
3718 } else if (!(sc->bge_flags & BGEF_NO_EEPROM)) {
3719 bge_read_eeprom(sc, (void *)&hwcfg,
3720 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg));
3721 hwcfg = be32toh(hwcfg);
3722 }
3723 aprint_normal_dev(sc->bge_dev,
3724 "HW config %08x, %08x, %08x, %08x %08x\n",
3725 hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5);
3726
3727 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
3728 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
3729
3730 if (bge_chipinit(sc)) {
3731 aprint_error_dev(sc->bge_dev, "chip initialization failed\n");
3732 bge_release_resources(sc);
3733 return;
3734 }
3735
3736 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) {
3737 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL,
3738 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUTEN1);
3739 DELAY(100);
3740 }
3741
3742 /* Set MI_MODE */
3743 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr);
3744 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0)
3745 mimode |= BGE_MIMODE_500KHZ_CONST;
3746 else
3747 mimode |= BGE_MIMODE_BASE;
3748 CSR_WRITE_4_FLUSH(sc, BGE_MI_MODE, mimode);
3749 DELAY(80);
3750
3751 /*
3752 * Get station address from the EEPROM.
3753 */
3754 if (bge_get_eaddr(sc, eaddr)) {
3755 aprint_error_dev(sc->bge_dev,
3756 "failed to read station address\n");
3757 bge_release_resources(sc);
3758 return;
3759 }
3760
3761 br = bge_lookup_rev(sc->bge_chipid);
3762
3763 if (br == NULL) {
3764 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)",
3765 sc->bge_chipid);
3766 } else {
3767 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)",
3768 br->br_name, sc->bge_chipid);
3769 }
3770 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr));
3771
3772 /* Allocate the general information block and ring buffers. */
3773 if (pci_dma64_available(pa)) {
3774 sc->bge_dmatag = pa->pa_dmat64;
3775 sc->bge_dmatag32 = pa->pa_dmat;
3776 sc->bge_dma64 = true;
3777 } else {
3778 sc->bge_dmatag = pa->pa_dmat;
3779 sc->bge_dmatag32 = pa->pa_dmat;
3780 sc->bge_dma64 = false;
3781 }
3782
3783 /* 40bit DMA workaround */
3784 if (sizeof(bus_addr_t) > 4) {
3785 if ((sc->bge_flags & BGEF_40BIT_BUG) != 0) {
3786 bus_dma_tag_t olddmatag = sc->bge_dmatag; /* save */
3787
3788 if (bus_dmatag_subregion(olddmatag, 0,
3789 (bus_addr_t)__MASK(40),
3790 &(sc->bge_dmatag), BUS_DMA_WAITOK) != 0) {
3791 aprint_error_dev(self,
3792 "WARNING: failed to restrict dma range,"
3793 " falling back to parent bus dma range\n");
3794 sc->bge_dmatag = olddmatag;
3795 }
3796 }
3797 }
3798 SLIST_INIT(&sc->txdma_list);
3799 DPRINTFN(5, ("bus_dmamem_alloc\n"));
3800 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data),
3801 PAGE_SIZE, 0, &sc->bge_ring_seg, 1,
3802 &sc->bge_ring_rseg, BUS_DMA_WAITOK)) {
3803 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n");
3804 return;
3805 }
3806 DPRINTFN(5, ("bus_dmamem_map\n"));
3807 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg,
3808 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva,
3809 BUS_DMA_WAITOK)) {
3810 aprint_error_dev(sc->bge_dev,
3811 "can't map DMA buffers (%zu bytes)\n",
3812 sizeof(struct bge_ring_data));
3813 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg,
3814 sc->bge_ring_rseg);
3815 return;
3816 }
3817 DPRINTFN(5, ("bus_dmamap_create\n"));
3818 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1,
3819 sizeof(struct bge_ring_data), 0,
3820 BUS_DMA_WAITOK, &sc->bge_ring_map)) {
3821 aprint_error_dev(sc->bge_dev, "can't create DMA map\n");
3822 bus_dmamem_unmap(sc->bge_dmatag, kva,
3823 sizeof(struct bge_ring_data));
3824 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg,
3825 sc->bge_ring_rseg);
3826 return;
3827 }
3828 DPRINTFN(5, ("bus_dmamap_load\n"));
3829 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva,
3830 sizeof(struct bge_ring_data), NULL,
3831 BUS_DMA_WAITOK)) {
3832 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map);
3833 bus_dmamem_unmap(sc->bge_dmatag, kva,
3834 sizeof(struct bge_ring_data));
3835 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg,
3836 sc->bge_ring_rseg);
3837 return;
3838 }
3839
3840 DPRINTFN(5, ("bzero\n"));
3841 sc->bge_rdata = (struct bge_ring_data *)kva;
3842
3843 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data));
3844
3845 /* Try to allocate memory for jumbo buffers. */
3846 if (BGE_IS_JUMBO_CAPABLE(sc)) {
3847 if (bge_alloc_jumbo_mem(sc)) {
3848 aprint_error_dev(sc->bge_dev,
3849 "jumbo buffer allocation failed\n");
3850 } else
3851 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
3852 }
3853
3854 /* Set default tuneable values. */
3855 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
3856 sc->bge_rx_coal_ticks = 150;
3857 sc->bge_rx_max_coal_bds = 64;
3858 sc->bge_tx_coal_ticks = 300;
3859 sc->bge_tx_max_coal_bds = 400;
3860 if (BGE_IS_5705_PLUS(sc)) {
3861 sc->bge_tx_coal_ticks = (12 * 5);
3862 sc->bge_tx_max_coal_bds = (12 * 5);
3863 aprint_verbose_dev(sc->bge_dev,
3864 "setting short Tx thresholds\n");
3865 }
3866
3867 if (BGE_IS_5717_PLUS(sc))
3868 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3869 else if (BGE_IS_5705_PLUS(sc))
3870 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
3871 else
3872 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3873
3874 sc->sc_core_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NONE);
3875 sc->sc_intr_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
3876
3877 /* Set up ifnet structure */
3878 ifp = &sc->ethercom.ec_if;
3879 ifp->if_softc = sc;
3880 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3881 ifp->if_extflags = IFEF_MPSAFE;
3882 ifp->if_ioctl = bge_ioctl;
3883 ifp->if_stop = bge_stop;
3884 ifp->if_start = bge_start;
3885 ifp->if_init = bge_init;
3886 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(BGE_TX_RING_CNT - 1, IFQ_MAXLEN));
3887 IFQ_SET_READY(&ifp->if_snd);
3888 DPRINTFN(5, ("strcpy if_xname\n"));
3889 strcpy(ifp->if_xname, device_xname(sc->bge_dev));
3890
3891 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0)
3892 sc->ethercom.ec_if.if_capabilities |=
3893 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx;
3894 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */
3895 sc->ethercom.ec_if.if_capabilities |=
3896 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
3897 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx;
3898 #endif
3899 sc->ethercom.ec_capabilities |=
3900 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU;
3901 sc->ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING;
3902
3903 if (sc->bge_flags & BGEF_TSO)
3904 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4;
3905
3906 /*
3907 * Do MII setup.
3908 */
3909 DPRINTFN(5, ("mii setup\n"));
3910 mii->mii_ifp = ifp;
3911 mii->mii_readreg = bge_miibus_readreg;
3912 mii->mii_writereg = bge_miibus_writereg;
3913 mii->mii_statchg = bge_miibus_statchg;
3914
3915 /*
3916 * Figure out what sort of media we have by checking the hardware
3917 * config word. Note: on some BCM5700 cards, this value appears to be
3918 * unset. If that's the case, we have to rely on identifying the NIC
3919 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41.
3920 * The SysKonnect SK-9D41 is a 1000baseSX card.
3921 */
3922 if (PCI_PRODUCT(subid) == SK_SUBSYSID_9D41 ||
3923 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
3924 if (BGE_IS_5705_PLUS(sc)) {
3925 sc->bge_flags |= BGEF_FIBER_MII;
3926 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED;
3927 } else
3928 sc->bge_flags |= BGEF_FIBER_TBI;
3929 }
3930
3931 /* Set bge_phy_flags before prop_dictionary_set_uint32() */
3932 if (BGE_IS_JUMBO_CAPABLE(sc))
3933 sc->bge_phy_flags |= BGEPHYF_JUMBO_CAPABLE;
3934
3935 /* set phyflags and chipid before mii_attach() */
3936 dict = device_properties(self);
3937 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_phy_flags);
3938 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid);
3939
3940 macmode = CSR_READ_4(sc, BGE_MAC_MODE);
3941 macmode &= ~BGE_MACMODE_PORTMODE;
3942 /* Initialize ifmedia structures. */
3943 if (sc->bge_flags & BGEF_FIBER_TBI) {
3944 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE,
3945 macmode | BGE_PORTMODE_TBI);
3946 DELAY(40);
3947
3948 struct ifmedia * const ifm = &sc->bge_ifmedia;
3949 sc->ethercom.ec_ifmedia = ifm;
3950
3951 ifmedia_init_with_lock(ifm, IFM_IMASK,
3952 bge_ifmedia_upd, bge_ifmedia_sts, sc->sc_intr_lock);
3953 ifmedia_add(ifm, IFM_ETHER | IFM_1000_SX, 0, NULL);
3954 ifmedia_add(ifm, IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL);
3955 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL);
3956 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO);
3957 /* Pretend the user requested this setting */
3958 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
3959 } else {
3960 uint16_t phyreg;
3961 int rv;
3962 /*
3963 * Do transceiver setup and tell the firmware the
3964 * driver is down so we can try to get access the
3965 * probe if ASF is running. Retry a couple of times
3966 * if we get a conflict with the ASF firmware accessing
3967 * the PHY.
3968 */
3969 if (sc->bge_flags & BGEF_FIBER_MII)
3970 macmode |= BGE_PORTMODE_GMII;
3971 else
3972 macmode |= BGE_PORTMODE_MII;
3973 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, macmode);
3974 DELAY(40);
3975
3976 /*
3977 * Do transceiver setup and tell the firmware the
3978 * driver is down so we can try to get access the
3979 * probe if ASF is running. Retry a couple of times
3980 * if we get a conflict with the ASF firmware accessing
3981 * the PHY.
3982 */
3983 trys = 0;
3984 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3985 sc->ethercom.ec_mii = mii;
3986 ifmedia_init_with_lock(&mii->mii_media, 0, bge_ifmedia_upd,
3987 bge_ifmedia_sts, sc->sc_intr_lock);
3988 mii_flags = MIIF_DOPAUSE;
3989 if (sc->bge_flags & BGEF_FIBER_MII)
3990 mii_flags |= MIIF_HAVEFIBER;
3991 again:
3992 bge_asf_driver_up(sc);
3993 rv = bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr,
3994 MII_BMCR, &phyreg);
3995 if ((rv != 0) || ((phyreg & BMCR_PDOWN) != 0)) {
3996 int i;
3997
3998 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr,
3999 MII_BMCR, BMCR_RESET);
4000 /* Wait up to 500ms for it to complete. */
4001 for (i = 0; i < 500; i++) {
4002 bge_miibus_readreg(sc->bge_dev,
4003 sc->bge_phy_addr, MII_BMCR, &phyreg);
4004 if ((phyreg & BMCR_RESET) == 0)
4005 break;
4006 DELAY(1000);
4007 }
4008 }
4009
4010 mii_attach(sc->bge_dev, mii, capmask, sc->bge_phy_addr,
4011 MII_OFFSET_ANY, mii_flags);
4012
4013 if (LIST_EMPTY(&mii->mii_phys) && (trys++ < 4))
4014 goto again;
4015
4016 if (LIST_EMPTY(&mii->mii_phys)) {
4017 aprint_error_dev(sc->bge_dev, "no PHY found!\n");
4018 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL,
4019 0, NULL);
4020 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL);
4021 } else
4022 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
4023
4024 /*
4025 * Now tell the firmware we are going up after probing the PHY
4026 */
4027 if (sc->bge_asf_mode & ASF_STACKUP)
4028 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4029 }
4030
4031 /*
4032 * Call MI attach routine.
4033 */
4034 DPRINTFN(5, ("if_initialize\n"));
4035 if_initialize(ifp);
4036 ifp->if_percpuq = if_percpuq_create(ifp);
4037 if_deferred_start_init(ifp, NULL);
4038 if_register(ifp);
4039
4040 DPRINTFN(5, ("ether_ifattach\n"));
4041 ether_ifattach(ifp, eaddr);
4042 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb);
4043
4044 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev),
4045 RND_TYPE_NET, RND_FLAG_DEFAULT);
4046 #ifdef BGE_EVENT_COUNTERS
4047 /*
4048 * Attach event counters.
4049 */
4050 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR,
4051 NULL, device_xname(sc->bge_dev), "intr");
4052 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious, EVCNT_TYPE_INTR,
4053 NULL, device_xname(sc->bge_dev), "intr_spurious");
4054 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious2, EVCNT_TYPE_INTR,
4055 NULL, device_xname(sc->bge_dev), "intr_spurious2");
4056 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC,
4057 NULL, device_xname(sc->bge_dev), "tx_xoff");
4058 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC,
4059 NULL, device_xname(sc->bge_dev), "tx_xon");
4060 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC,
4061 NULL, device_xname(sc->bge_dev), "rx_xoff");
4062 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC,
4063 NULL, device_xname(sc->bge_dev), "rx_xon");
4064 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC,
4065 NULL, device_xname(sc->bge_dev), "rx_macctl");
4066 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC,
4067 NULL, device_xname(sc->bge_dev), "xoffentered");
4068 #endif /* BGE_EVENT_COUNTERS */
4069 DPRINTFN(5, ("callout_init\n"));
4070 callout_init(&sc->bge_timeout, CALLOUT_MPSAFE);
4071 callout_setfunc(&sc->bge_timeout, bge_tick, sc);
4072
4073 if (pmf_device_register(self, NULL, NULL))
4074 pmf_class_network_register(self, ifp);
4075 else
4076 aprint_error_dev(self, "couldn't establish power handler\n");
4077
4078 bge_sysctl_init(sc);
4079
4080 #ifdef BGE_DEBUG
4081 bge_debug_info(sc);
4082 #endif
4083 }
4084
4085 /*
4086 * Stop all chip I/O so that the kernel's probe routines don't
4087 * get confused by errant DMAs when rebooting.
4088 */
4089 static int
bge_detach(device_t self,int flags __unused)4090 bge_detach(device_t self, int flags __unused)
4091 {
4092 struct bge_softc * const sc = device_private(self);
4093 struct ifnet * const ifp = &sc->ethercom.ec_if;
4094
4095 IFNET_LOCK(ifp);
4096
4097 /* Stop the interface. Callouts are stopped in it. */
4098 bge_stop(ifp, 1);
4099 sc->bge_detaching = true;
4100
4101 IFNET_UNLOCK(ifp);
4102
4103 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY);
4104
4105 ether_ifdetach(ifp);
4106 if_detach(ifp);
4107
4108 /* Delete all remaining media. */
4109 ifmedia_fini(&sc->bge_mii.mii_media);
4110
4111 bge_release_resources(sc);
4112
4113 return 0;
4114 }
4115
4116 static void
bge_release_resources(struct bge_softc * sc)4117 bge_release_resources(struct bge_softc *sc)
4118 {
4119
4120 /* Detach sysctl */
4121 if (sc->bge_log != NULL)
4122 sysctl_teardown(&sc->bge_log);
4123
4124 #ifdef BGE_EVENT_COUNTERS
4125 /* Detach event counters. */
4126 evcnt_detach(&sc->bge_ev_intr);
4127 evcnt_detach(&sc->bge_ev_intr_spurious);
4128 evcnt_detach(&sc->bge_ev_intr_spurious2);
4129 evcnt_detach(&sc->bge_ev_tx_xoff);
4130 evcnt_detach(&sc->bge_ev_tx_xon);
4131 evcnt_detach(&sc->bge_ev_rx_xoff);
4132 evcnt_detach(&sc->bge_ev_rx_xon);
4133 evcnt_detach(&sc->bge_ev_rx_macctl);
4134 evcnt_detach(&sc->bge_ev_xoffentered);
4135 #endif /* BGE_EVENT_COUNTERS */
4136
4137 /* Disestablish the interrupt handler */
4138 if (sc->bge_intrhand != NULL) {
4139 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand);
4140 pci_intr_release(sc->sc_pc, sc->bge_pihp, 1);
4141 sc->bge_intrhand = NULL;
4142 }
4143
4144 if (sc->bge_cdata.bge_jumbo_buf != NULL)
4145 bge_free_jumbo_mem(sc);
4146
4147 if (sc->bge_dmatag != NULL) {
4148 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map);
4149 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map);
4150 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata,
4151 sizeof(struct bge_ring_data));
4152 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg,
4153 sc->bge_ring_rseg);
4154 }
4155
4156 /* Unmap the device registers */
4157 if (sc->bge_bsize != 0) {
4158 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize);
4159 sc->bge_bsize = 0;
4160 }
4161
4162 /* Unmap the APE registers */
4163 if (sc->bge_apesize != 0) {
4164 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle,
4165 sc->bge_apesize);
4166 sc->bge_apesize = 0;
4167 }
4168 }
4169
4170 static int
bge_reset(struct bge_softc * sc)4171 bge_reset(struct bge_softc *sc)
4172 {
4173 uint32_t cachesize, command;
4174 uint32_t reset, mac_mode, mac_mode_mask;
4175 pcireg_t devctl, reg;
4176 int i, val;
4177 void (*write_op)(struct bge_softc *, int, int);
4178
4179 /* Make mask for BGE_MAC_MODE register. */
4180 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE;
4181 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4182 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
4183 /* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */
4184 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;
4185
4186 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
4187 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) {
4188 if (sc->bge_flags & BGEF_PCIE)
4189 write_op = bge_writemem_direct;
4190 else
4191 write_op = bge_writemem_ind;
4192 } else
4193 write_op = bge_writereg_ind;
4194
4195 /* 57XX step 4 */
4196 /* Acquire the NVM lock */
4197 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0 &&
4198 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 &&
4199 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) {
4200 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
4201 for (i = 0; i < 8000; i++) {
4202 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) &
4203 BGE_NVRAMSWARB_GNT1)
4204 break;
4205 DELAY(20);
4206 }
4207 if (i == 8000) {
4208 printf("%s: NVRAM lock timedout!\n",
4209 device_xname(sc->bge_dev));
4210 }
4211 }
4212
4213 /* Take APE lock when performing reset. */
4214 bge_ape_lock(sc, BGE_APE_LOCK_GRC);
4215
4216 /* 57XX step 3 */
4217 /* Save some important PCI state. */
4218 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ);
4219 /* 5718 reset step 3 */
4220 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD);
4221
4222 /* 5718 reset step 5, 57XX step 5b-5d */
4223 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL,
4224 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4225 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW);
4226
4227 /* XXX ???: Disable fastboot on controllers that support it. */
4228 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 ||
4229 BGE_IS_5755_PLUS(sc))
4230 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0);
4231
4232 /* 5718 reset step 2, 57XX step 6 */
4233 /*
4234 * Write the magic number to SRAM at offset 0xB50.
4235 * When firmware finishes its initialization it will
4236 * write ~BGE_MAGIC_NUMBER to the same location.
4237 */
4238 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
4239
4240 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) {
4241 val = CSR_READ_4(sc, BGE_PCIE_LINKCTL);
4242 val = (val & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN)
4243 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS;
4244 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, val);
4245 }
4246
4247 /* 5718 reset step 6, 57XX step 7 */
4248 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
4249 /*
4250 * XXX: from FreeBSD/Linux; no documentation
4251 */
4252 if (sc->bge_flags & BGEF_PCIE) {
4253 if ((BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) &&
4254 !BGE_IS_57765_PLUS(sc) &&
4255 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) ==
4256 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) {
4257 /* PCI Express 1.0 system */
4258 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG,
4259 BGE_PHY_PCIE_SCRAM_MODE);
4260 }
4261 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
4262 /*
4263 * Prevent PCI Express link training
4264 * during global reset.
4265 */
4266 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
4267 reset |= (1 << 29);
4268 }
4269 }
4270
4271 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) {
4272 i = CSR_READ_4(sc, BGE_VCPU_STATUS);
4273 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
4274 i | BGE_VCPU_STATUS_DRV_RESET);
4275 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
4276 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
4277 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
4278 }
4279
4280 /*
4281 * Set GPHY Power Down Override to leave GPHY
4282 * powered up in D0 uninitialized.
4283 */
4284 if (BGE_IS_5705_PLUS(sc) &&
4285 (sc->bge_flags & BGEF_CPMU_PRESENT) == 0)
4286 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
4287
4288 /* Issue global reset */
4289 write_op(sc, BGE_MISC_CFG, reset);
4290
4291 /* 5718 reset step 7, 57XX step 8 */
4292 if (sc->bge_flags & BGEF_PCIE)
4293 delay(100*1000); /* too big */
4294 else
4295 delay(1000);
4296
4297 if (sc->bge_flags & BGEF_PCIE) {
4298 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
4299 DELAY(500000);
4300 /* XXX: Magic Numbers */
4301 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
4302 BGE_PCI_UNKNOWN0);
4303 pci_conf_write(sc->sc_pc, sc->sc_pcitag,
4304 BGE_PCI_UNKNOWN0,
4305 reg | (1 << 15));
4306 }
4307 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
4308 sc->bge_pciecap + PCIE_DCSR);
4309 /* Clear enable no snoop and disable relaxed ordering. */
4310 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD |
4311 PCIE_DCSR_ENA_NO_SNOOP);
4312
4313 /* Set PCIE max payload size to 128 for older PCIe devices */
4314 if ((sc->bge_flags & BGEF_CPMU_PRESENT) == 0)
4315 devctl &= ~(0x00e0);
4316 /* Clear device status register. Write 1b to clear */
4317 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED
4318 | PCIE_DCSR_NFED | PCIE_DCSR_CED;
4319 pci_conf_write(sc->sc_pc, sc->sc_pcitag,
4320 sc->bge_pciecap + PCIE_DCSR, devctl);
4321 bge_set_max_readrq(sc);
4322 }
4323
4324 /* From Linux: dummy read to flush PCI posted writes */
4325 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD);
4326
4327 /*
4328 * Reset some of the PCI state that got zapped by reset
4329 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be
4330 * set, too.
4331 */
4332 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL,
4333 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4334 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW);
4335 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE;
4336 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 &&
4337 (sc->bge_flags & BGEF_PCIX) != 0)
4338 val |= BGE_PCISTATE_RETRY_SAME_DMA;
4339 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4340 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
4341 BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
4342 BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
4343 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val);
4344 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize);
4345 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command);
4346
4347 /* 57xx step 11: disable PCI-X Relaxed Ordering. */
4348 if (sc->bge_flags & BGEF_PCIX) {
4349 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap
4350 + PCIX_CMD);
4351 /* Set max memory read byte count to 2K */
4352 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) {
4353 reg &= ~PCIX_CMD_BYTECNT_MASK;
4354 reg |= PCIX_CMD_BCNT_2048;
4355 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704){
4356 /*
4357 * For 5704, set max outstanding split transaction
4358 * field to 0 (0 means it supports 1 request)
4359 */
4360 reg &= ~(PCIX_CMD_SPLTRANS_MASK
4361 | PCIX_CMD_BYTECNT_MASK);
4362 reg |= PCIX_CMD_BCNT_2048;
4363 }
4364 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap
4365 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER);
4366 }
4367
4368 /* 5718 reset step 10, 57XX step 12 */
4369 /* Enable memory arbiter. */
4370 if (BGE_IS_5714_FAMILY(sc)) {
4371 val = CSR_READ_4(sc, BGE_MARB_MODE);
4372 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
4373 } else
4374 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4375
4376 /* XXX 5721, 5751 and 5752 */
4377 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) {
4378 /* Step 19: */
4379 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25);
4380 /* Step 20: */
4381 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT);
4382 }
4383
4384 /* 5718 reset step 12, 57XX step 15 and 16 */
4385 /* Fix up byte swapping */
4386 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS);
4387
4388 /* 5718 reset step 13, 57XX step 17 */
4389 /* Poll until the firmware initialization is complete */
4390 bge_poll_fw(sc);
4391
4392 /* 57XX step 21 */
4393 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) {
4394 pcireg_t msidata;
4395
4396 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
4397 BGE_PCI_MSI_DATA);
4398 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16);
4399 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA,
4400 msidata);
4401 }
4402
4403 /* 57XX step 18 */
4404 /* Write mac mode. */
4405 val = CSR_READ_4(sc, BGE_MAC_MODE);
4406 /* Restore mac_mode_mask's bits using mac_mode */
4407 val = (val & ~mac_mode_mask) | mac_mode;
4408 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val);
4409 DELAY(40);
4410
4411 bge_ape_unlock(sc, BGE_APE_LOCK_GRC);
4412
4413 /*
4414 * The 5704 in TBI mode apparently needs some special
4415 * adjustment to insure the SERDES drive level is set
4416 * to 1.2V.
4417 */
4418 if (sc->bge_flags & BGEF_FIBER_TBI &&
4419 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) {
4420 uint32_t serdescfg;
4421
4422 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
4423 serdescfg = (serdescfg & ~0xFFF) | 0x880;
4424 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
4425 }
4426
4427 if (sc->bge_flags & BGEF_PCIE &&
4428 !BGE_IS_57765_PLUS(sc) &&
4429 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
4430 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) {
4431 uint32_t v;
4432
4433 /* Enable PCI Express bug fix */
4434 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG);
4435 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG,
4436 v | BGE_TLP_DATA_FIFO_PROTECT);
4437 }
4438
4439 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720)
4440 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
4441 CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
4442
4443 return 0;
4444 }
4445
4446 /*
4447 * Frame reception handling. This is called if there's a frame
4448 * on the receive return list.
4449 *
4450 * Note: we have to be able to handle two possibilities here:
4451 * 1) the frame is from the jumbo receive ring
4452 * 2) the frame is from the standard receive ring
4453 */
4454
4455 static void
bge_rxeof(struct bge_softc * sc)4456 bge_rxeof(struct bge_softc *sc)
4457 {
4458 struct ifnet * const ifp = &sc->ethercom.ec_if;
4459 uint16_t rx_prod, rx_cons;
4460 int stdcnt = 0, jumbocnt = 0;
4461 bus_dmamap_t dmamap;
4462 bus_addr_t offset, toff;
4463 bus_size_t tlen;
4464 int tosync;
4465
4466 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
4467 offsetof(struct bge_ring_data, bge_status_block),
4468 sizeof(struct bge_status_block),
4469 BUS_DMASYNC_POSTREAD);
4470
4471 rx_cons = sc->bge_rx_saved_considx;
4472 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx;
4473
4474 /* Nothing to do */
4475 if (rx_cons == rx_prod)
4476 return;
4477
4478 offset = offsetof(struct bge_ring_data, bge_rx_return_ring);
4479 tosync = rx_prod - rx_cons;
4480
4481 if (tosync != 0)
4482 rnd_add_uint32(&sc->rnd_source, tosync);
4483
4484 toff = offset + (rx_cons * sizeof(struct bge_rx_bd));
4485
4486 if (tosync < 0) {
4487 tlen = (sc->bge_return_ring_cnt - rx_cons) *
4488 sizeof(struct bge_rx_bd);
4489 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
4490 toff, tlen, BUS_DMASYNC_POSTREAD);
4491 tosync = rx_prod;
4492 toff = offset;
4493 }
4494
4495 if (tosync != 0) {
4496 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
4497 toff, tosync * sizeof(struct bge_rx_bd),
4498 BUS_DMASYNC_POSTREAD);
4499 }
4500
4501 while (rx_cons != rx_prod) {
4502 struct bge_rx_bd *cur_rx;
4503 uint32_t rxidx;
4504 struct mbuf *m = NULL;
4505
4506 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons];
4507
4508 rxidx = cur_rx->bge_idx;
4509 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
4510
4511 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
4512 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4513 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
4514 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
4515 jumbocnt++;
4516 bus_dmamap_sync(sc->bge_dmatag,
4517 sc->bge_cdata.bge_rx_jumbo_map,
4518 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf,
4519 BGE_JLEN, BUS_DMASYNC_POSTREAD);
4520 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4521 if_statinc(ifp, if_ierrors);
4522 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
4523 continue;
4524 }
4525 if (bge_newbuf_jumbo(sc, sc->bge_jumbo,
4526 NULL) == ENOBUFS) {
4527 if_statinc(ifp, if_ierrors);
4528 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
4529 continue;
4530 }
4531 } else {
4532 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
4533 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
4534
4535 stdcnt++;
4536 sc->bge_std_cnt--;
4537
4538 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx];
4539 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0,
4540 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
4541 bus_dmamap_unload(sc->bge_dmatag, dmamap);
4542
4543 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4544 m_free(m);
4545 if_statinc(ifp, if_ierrors);
4546 continue;
4547 }
4548 }
4549
4550 #ifndef __NO_STRICT_ALIGNMENT
4551 /*
4552 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect,
4553 * the Rx buffer has the layer-2 header unaligned.
4554 * If our CPU requires alignment, re-align by copying.
4555 */
4556 if (sc->bge_flags & BGEF_RX_ALIGNBUG) {
4557 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data,
4558 cur_rx->bge_len);
4559 m->m_data += ETHER_ALIGN;
4560 }
4561 #endif
4562
4563 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
4564 m_set_rcvif(m, ifp);
4565
4566 bge_rxcsum(sc, cur_rx, m);
4567
4568 /*
4569 * If we received a packet with a vlan tag, pass it
4570 * to vlan_input() instead of ether_input().
4571 */
4572 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG)
4573 vlan_set_tag(m, cur_rx->bge_vlan_tag);
4574
4575 if_percpuq_enqueue(ifp->if_percpuq, m);
4576 }
4577
4578 sc->bge_rx_saved_considx = rx_cons;
4579 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
4580 if (stdcnt)
4581 bge_fill_rx_ring_std(sc);
4582 if (jumbocnt)
4583 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
4584 }
4585
4586 static void
bge_rxcsum(struct bge_softc * sc,struct bge_rx_bd * cur_rx,struct mbuf * m)4587 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
4588 {
4589
4590 if (BGE_IS_57765_PLUS(sc)) {
4591 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
4592 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0)
4593 m->m_pkthdr.csum_flags = M_CSUM_IPv4;
4594 if ((cur_rx->bge_error_flag &
4595 BGE_RXERRFLAG_IP_CSUM_NOK) != 0)
4596 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD;
4597 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
4598 m->m_pkthdr.csum_data =
4599 cur_rx->bge_tcp_udp_csum;
4600 m->m_pkthdr.csum_flags |=
4601 (M_CSUM_TCPv4 | M_CSUM_UDPv4 |M_CSUM_DATA);
4602 }
4603 }
4604 } else {
4605 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0)
4606 m->m_pkthdr.csum_flags = M_CSUM_IPv4;
4607 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0)
4608 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD;
4609 /*
4610 * Rx transport checksum-offload may also
4611 * have bugs with packets which, when transmitted,
4612 * were `runts' requiring padding.
4613 */
4614 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
4615 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/
4616 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) {
4617 m->m_pkthdr.csum_data =
4618 cur_rx->bge_tcp_udp_csum;
4619 m->m_pkthdr.csum_flags |=
4620 (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_DATA);
4621 }
4622 }
4623 }
4624
4625 static void
bge_txeof(struct bge_softc * sc)4626 bge_txeof(struct bge_softc *sc)
4627 {
4628 struct ifnet * const ifp = &sc->ethercom.ec_if;
4629 struct bge_tx_bd *cur_tx = NULL;
4630 struct txdmamap_pool_entry *dma;
4631 bus_addr_t offset, toff;
4632 bus_size_t tlen;
4633 int tosync;
4634 struct mbuf *m;
4635
4636 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
4637 offsetof(struct bge_ring_data, bge_status_block),
4638 sizeof(struct bge_status_block),
4639 BUS_DMASYNC_POSTREAD);
4640
4641 const uint16_t hw_cons_idx =
4642 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx;
4643 offset = offsetof(struct bge_ring_data, bge_tx_ring);
4644 tosync = hw_cons_idx - sc->bge_tx_saved_considx;
4645
4646 if (tosync != 0)
4647 rnd_add_uint32(&sc->rnd_source, tosync);
4648
4649 toff = offset + (sc->bge_tx_saved_considx * sizeof(struct bge_tx_bd));
4650
4651 if (tosync < 0) {
4652 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) *
4653 sizeof(struct bge_tx_bd);
4654 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
4655 toff, tlen, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4656 tosync = hw_cons_idx;
4657 toff = offset;
4658 }
4659
4660 if (tosync != 0) {
4661 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
4662 toff, tosync * sizeof(struct bge_tx_bd),
4663 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4664 }
4665
4666 /*
4667 * Go through our tx ring and free mbufs for those
4668 * frames that have been sent.
4669 */
4670 while (sc->bge_tx_saved_considx != hw_cons_idx) {
4671 uint32_t idx = sc->bge_tx_saved_considx;
4672 cur_tx = &sc->bge_rdata->bge_tx_ring[idx];
4673 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
4674 if_statinc(ifp, if_opackets);
4675 m = sc->bge_cdata.bge_tx_chain[idx];
4676 if (m != NULL) {
4677 sc->bge_cdata.bge_tx_chain[idx] = NULL;
4678 dma = sc->txdma[idx];
4679 if (dma->is_dma32) {
4680 bus_dmamap_sync(sc->bge_dmatag32, dma->dmamap32,
4681 0, dma->dmamap32->dm_mapsize,
4682 BUS_DMASYNC_POSTWRITE);
4683 bus_dmamap_unload(
4684 sc->bge_dmatag32, dma->dmamap32);
4685 } else {
4686 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap,
4687 0, dma->dmamap->dm_mapsize,
4688 BUS_DMASYNC_POSTWRITE);
4689 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap);
4690 }
4691 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link);
4692 sc->txdma[idx] = NULL;
4693
4694 m_freem(m);
4695 }
4696 sc->bge_txcnt--;
4697 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
4698 sc->bge_tx_sending = false;
4699 }
4700 }
4701
4702 static int
bge_intr(void * xsc)4703 bge_intr(void *xsc)
4704 {
4705 struct bge_softc * const sc = xsc;
4706 struct ifnet * const ifp = &sc->ethercom.ec_if;
4707 uint32_t pcistate, statusword, statustag;
4708 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE;
4709
4710 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */
4711 if (BGE_IS_5717_PLUS(sc))
4712 intrmask = 0;
4713
4714 mutex_enter(sc->sc_intr_lock);
4715 if (sc->bge_txrx_stopping) {
4716 mutex_exit(sc->sc_intr_lock);
4717 return 1;
4718 }
4719
4720 /*
4721 * It is possible for the interrupt to arrive before
4722 * the status block is updated prior to the interrupt.
4723 * Reading the PCI State register will confirm whether the
4724 * interrupt is ours and will flush the status block.
4725 */
4726 pcistate = CSR_READ_4(sc, BGE_PCI_PCISTATE);
4727
4728 /* read status word from status block */
4729 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
4730 offsetof(struct bge_ring_data, bge_status_block),
4731 sizeof(struct bge_status_block),
4732 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4733 statusword = sc->bge_rdata->bge_status_block.bge_status;
4734 statustag = sc->bge_rdata->bge_status_block.bge_status_tag << 24;
4735
4736 if (sc->bge_flags & BGEF_TAGGED_STATUS) {
4737 if (sc->bge_lasttag == statustag &&
4738 (~pcistate & intrmask)) {
4739 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious);
4740 mutex_exit(sc->sc_intr_lock);
4741 return 0;
4742 }
4743 sc->bge_lasttag = statustag;
4744 } else {
4745 if (!(statusword & BGE_STATFLAG_UPDATED) &&
4746 !(~pcistate & intrmask)) {
4747 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious2);
4748 mutex_exit(sc->sc_intr_lock);
4749 return 0;
4750 }
4751 statustag = 0;
4752 }
4753 /* Ack interrupt and stop others from occurring. */
4754 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1);
4755 BGE_EVCNT_INCR(sc->bge_ev_intr);
4756
4757 /* clear status word */
4758 sc->bge_rdata->bge_status_block.bge_status = 0;
4759
4760 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
4761 offsetof(struct bge_ring_data, bge_status_block),
4762 sizeof(struct bge_status_block),
4763 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4764
4765 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 ||
4766 statusword & BGE_STATFLAG_LINKSTATE_CHANGED ||
4767 BGE_STS_BIT(sc, BGE_STS_LINK_EVT))
4768 bge_link_upd(sc);
4769
4770 /* Check RX return ring producer/consumer */
4771 bge_rxeof(sc);
4772
4773 /* Check TX ring producer/consumer */
4774 bge_txeof(sc);
4775
4776 if (sc->bge_pending_rxintr_change) {
4777 uint32_t rx_ticks = sc->bge_rx_coal_ticks;
4778 uint32_t rx_bds = sc->bge_rx_max_coal_bds;
4779
4780 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks);
4781 DELAY(10);
4782 (void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
4783
4784 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds);
4785 DELAY(10);
4786 (void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
4787
4788 sc->bge_pending_rxintr_change = false;
4789 }
4790 bge_handle_events(sc);
4791
4792 /* Re-enable interrupts. */
4793 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, statustag);
4794
4795 if_schedule_deferred_start(ifp);
4796
4797 mutex_exit(sc->sc_intr_lock);
4798
4799 return 1;
4800 }
4801
4802 static void
bge_asf_driver_up(struct bge_softc * sc)4803 bge_asf_driver_up(struct bge_softc *sc)
4804 {
4805 if (sc->bge_asf_mode & ASF_STACKUP) {
4806 /* Send ASF heartbeat approx. every 2s */
4807 if (sc->bge_asf_count)
4808 sc->bge_asf_count --;
4809 else {
4810 sc->bge_asf_count = 2;
4811
4812 bge_wait_for_event_ack(sc);
4813
4814 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
4815 BGE_FW_CMD_DRV_ALIVE3);
4816 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
4817 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
4818 BGE_FW_HB_TIMEOUT_SEC);
4819 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT,
4820 CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
4821 BGE_RX_CPU_DRV_EVENT);
4822 }
4823 }
4824 }
4825
4826 static void
bge_tick(void * xsc)4827 bge_tick(void *xsc)
4828 {
4829 struct bge_softc * const sc = xsc;
4830 struct ifnet * const ifp = &sc->ethercom.ec_if;
4831 struct mii_data * const mii = &sc->bge_mii;
4832
4833 mutex_enter(sc->sc_core_lock);
4834 if (sc->bge_stopping) {
4835 mutex_exit(sc->sc_core_lock);
4836 return;
4837 }
4838
4839 if (BGE_IS_5705_PLUS(sc))
4840 bge_stats_update_regs(sc);
4841 else
4842 bge_stats_update(sc);
4843
4844 if (sc->bge_flags & BGEF_FIBER_TBI) {
4845 /*
4846 * Since in TBI mode auto-polling can't be used we should poll
4847 * link status manually. Here we register pending link event
4848 * and trigger interrupt.
4849 */
4850 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT);
4851 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4852 } else {
4853 /*
4854 * Do not touch PHY if we have link up. This could break
4855 * IPMI/ASF mode or produce extra input errors.
4856 * (extra input errors was reported for bcm5701 & bcm5704).
4857 */
4858 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) {
4859 mutex_enter(sc->sc_intr_lock);
4860 mii_tick(mii);
4861 mutex_exit(sc->sc_intr_lock);
4862 }
4863 }
4864
4865 bge_asf_driver_up(sc);
4866
4867 const bool ok = bge_watchdog_tick(ifp);
4868 if (ok)
4869 callout_schedule(&sc->bge_timeout, hz);
4870
4871 mutex_exit(sc->sc_core_lock);
4872 }
4873
4874 static void
bge_stats_update_regs(struct bge_softc * sc)4875 bge_stats_update_regs(struct bge_softc *sc)
4876 {
4877 struct ifnet * const ifp = &sc->ethercom.ec_if;
4878
4879 net_stat_ref_t nsr = IF_STAT_GETREF(ifp);
4880
4881 if_statadd_ref(nsr, if_collisions,
4882 CSR_READ_4(sc, BGE_MAC_STATS +
4883 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)));
4884
4885 /*
4886 * On BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0,
4887 * RXLP_LOCSTAT_IFIN_DROPS includes unwanted multicast frames
4888 * (silicon bug). There's no reliable workaround so just
4889 * ignore the counter
4890 */
4891 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 &&
4892 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 &&
4893 sc->bge_chipid != BGE_CHIPID_BCM5720_A0) {
4894 if_statadd_ref(nsr, if_ierrors,
4895 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS));
4896 }
4897 if_statadd_ref(nsr, if_ierrors,
4898 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS));
4899 if_statadd_ref(nsr, if_ierrors,
4900 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS));
4901
4902 IF_STAT_PUTREF(ifp);
4903
4904 if (sc->bge_flags & BGEF_RDMA_BUG) {
4905 uint32_t val, ucast, mcast, bcast;
4906
4907 ucast = CSR_READ_4(sc, BGE_MAC_STATS +
4908 offsetof(struct bge_mac_stats_regs, ifHCOutUcastPkts));
4909 mcast = CSR_READ_4(sc, BGE_MAC_STATS +
4910 offsetof(struct bge_mac_stats_regs, ifHCOutMulticastPkts));
4911 bcast = CSR_READ_4(sc, BGE_MAC_STATS +
4912 offsetof(struct bge_mac_stats_regs, ifHCOutBroadcastPkts));
4913
4914 /*
4915 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS
4916 * frames, it's safe to disable workaround for DMA engine's
4917 * miscalculation of TXMBUF space.
4918 */
4919 if (ucast + mcast + bcast > BGE_NUM_RDMA_CHANNELS) {
4920 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
4921 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719)
4922 val &= ~BGE_RDMA_TX_LENGTH_WA_5719;
4923 else
4924 val &= ~BGE_RDMA_TX_LENGTH_WA_5720;
4925 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
4926 sc->bge_flags &= ~BGEF_RDMA_BUG;
4927 }
4928 }
4929 }
4930
4931 static void
bge_stats_update(struct bge_softc * sc)4932 bge_stats_update(struct bge_softc *sc)
4933 {
4934 struct ifnet * const ifp = &sc->ethercom.ec_if;
4935 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
4936
4937 #define READ_STAT(sc, stats, stat) \
4938 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
4939
4940 uint64_t collisions =
4941 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) +
4942 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) +
4943 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) +
4944 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo));
4945
4946 if_statadd(ifp, if_collisions, collisions - sc->bge_if_collisions);
4947 sc->bge_if_collisions = collisions;
4948
4949
4950 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff,
4951 READ_STAT(sc, stats, outXoffSent.bge_addr_lo));
4952 BGE_EVCNT_UPD(sc->bge_ev_tx_xon,
4953 READ_STAT(sc, stats, outXonSent.bge_addr_lo));
4954 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff,
4955 READ_STAT(sc, stats,
4956 xoffPauseFramesReceived.bge_addr_lo));
4957 BGE_EVCNT_UPD(sc->bge_ev_rx_xon,
4958 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo));
4959 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl,
4960 READ_STAT(sc, stats,
4961 macControlFramesReceived.bge_addr_lo));
4962 BGE_EVCNT_UPD(sc->bge_ev_xoffentered,
4963 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo));
4964
4965 #undef READ_STAT
4966 }
4967
4968 /*
4969 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
4970 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
4971 * but when such padded frames employ the bge IP/TCP checksum offload,
4972 * the hardware checksum assist gives incorrect results (possibly
4973 * from incorporating its own padding into the UDP/TCP checksum; who knows).
4974 * If we pad such runts with zeros, the onboard checksum comes out correct.
4975 */
4976 static inline int
bge_cksum_pad(struct mbuf * pkt)4977 bge_cksum_pad(struct mbuf *pkt)
4978 {
4979 struct mbuf *last = NULL;
4980 int padlen;
4981
4982 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len;
4983
4984 /* if there's only the packet-header and we can pad there, use it. */
4985 if (pkt->m_pkthdr.len == pkt->m_len &&
4986 M_TRAILINGSPACE(pkt) >= padlen) {
4987 last = pkt;
4988 } else {
4989 /*
4990 * Walk packet chain to find last mbuf. We will either
4991 * pad there, or append a new mbuf and pad it
4992 * (thus perhaps avoiding the bcm5700 dma-min bug).
4993 */
4994 for (last = pkt; last->m_next != NULL; last = last->m_next) {
4995 continue; /* do nothing */
4996 }
4997
4998 /* `last' now points to last in chain. */
4999 if (M_TRAILINGSPACE(last) < padlen) {
5000 /* Allocate new empty mbuf, pad it. Compact later. */
5001 struct mbuf *n;
5002 MGET(n, M_DONTWAIT, MT_DATA);
5003 if (n == NULL)
5004 return ENOBUFS;
5005 n->m_len = 0;
5006 last->m_next = n;
5007 last = n;
5008 }
5009 }
5010
5011 KDASSERT(!M_READONLY(last));
5012 KDASSERT(M_TRAILINGSPACE(last) >= padlen);
5013
5014 /* Now zero the pad area, to avoid the bge cksum-assist bug */
5015 memset(mtod(last, char *) + last->m_len, 0, padlen);
5016 last->m_len += padlen;
5017 pkt->m_pkthdr.len += padlen;
5018 return 0;
5019 }
5020
5021 /*
5022 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes.
5023 */
5024 static inline int
bge_compact_dma_runt(struct mbuf * pkt)5025 bge_compact_dma_runt(struct mbuf *pkt)
5026 {
5027 struct mbuf *m, *prev;
5028 int totlen;
5029
5030 prev = NULL;
5031 totlen = 0;
5032
5033 for (m = pkt; m != NULL; prev = m, m = m->m_next) {
5034 int mlen = m->m_len;
5035 int shortfall = 8 - mlen ;
5036
5037 totlen += mlen;
5038 if (mlen == 0)
5039 continue;
5040 if (mlen >= 8)
5041 continue;
5042
5043 /*
5044 * If we get here, mbuf data is too small for DMA engine.
5045 * Try to fix by shuffling data to prev or next in chain.
5046 * If that fails, do a compacting deep-copy of the whole chain.
5047 */
5048
5049 /* Internal frag. If fits in prev, copy it there. */
5050 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) {
5051 memcpy(prev->m_data + prev->m_len, m->m_data, mlen);
5052 prev->m_len += mlen;
5053 m->m_len = 0;
5054 /* XXX stitch chain */
5055 prev->m_next = m_free(m);
5056 m = prev;
5057 continue;
5058 } else if (m->m_next != NULL &&
5059 M_TRAILINGSPACE(m) >= shortfall &&
5060 m->m_next->m_len >= (8 + shortfall)) {
5061 /* m is writable and have enough data in next, pull up. */
5062
5063 memcpy(m->m_data + m->m_len, m->m_next->m_data,
5064 shortfall);
5065 m->m_len += shortfall;
5066 m->m_next->m_len -= shortfall;
5067 m->m_next->m_data += shortfall;
5068 } else if (m->m_next == NULL || 1) {
5069 /*
5070 * Got a runt at the very end of the packet.
5071 * borrow data from the tail of the preceding mbuf and
5072 * update its length in-place. (The original data is
5073 * still valid, so we can do this even if prev is not
5074 * writable.)
5075 */
5076
5077 /*
5078 * If we'd make prev a runt, just move all of its data.
5079 */
5080 KASSERT(prev != NULL /*, ("runt but null PREV")*/);
5081 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/);
5082
5083 if ((prev->m_len - shortfall) < 8)
5084 shortfall = prev->m_len;
5085
5086 #ifdef notyet /* just do the safe slow thing for now */
5087 if (!M_READONLY(m)) {
5088 if (M_LEADINGSPACE(m) < shorfall) {
5089 void *m_dat;
5090 m_dat = M_BUFADDR(m);
5091 memmove(m_dat, mtod(m, void*),
5092 m->m_len);
5093 m->m_data = m_dat;
5094 }
5095 } else
5096 #endif /* just do the safe slow thing */
5097 {
5098 struct mbuf * n = NULL;
5099 int newprevlen = prev->m_len - shortfall;
5100
5101 MGET(n, M_NOWAIT, MT_DATA);
5102 if (n == NULL)
5103 return ENOBUFS;
5104 KASSERT(m->m_len + shortfall < MLEN
5105 /*,
5106 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/);
5107
5108 /* first copy the data we're stealing from prev */
5109 memcpy(n->m_data, prev->m_data + newprevlen,
5110 shortfall);
5111
5112 /* update prev->m_len accordingly */
5113 prev->m_len -= shortfall;
5114
5115 /* copy data from runt m */
5116 memcpy(n->m_data + shortfall, m->m_data,
5117 m->m_len);
5118
5119 /* n holds what we stole from prev, plus m */
5120 n->m_len = shortfall + m->m_len;
5121
5122 /* stitch n into chain and free m */
5123 n->m_next = m->m_next;
5124 prev->m_next = n;
5125 /* KASSERT(m->m_next == NULL); */
5126 m->m_next = NULL;
5127 m_free(m);
5128 m = n; /* for continuing loop */
5129 }
5130 }
5131 }
5132 return 0;
5133 }
5134
5135 /*
5136 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
5137 * pointers to descriptors.
5138 */
5139 static int
bge_encap(struct bge_softc * sc,struct mbuf * m_head,uint32_t * txidx)5140 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
5141 {
5142 struct bge_tx_bd *f, *prev_f;
5143 uint32_t frag, cur;
5144 uint16_t csum_flags = 0;
5145 uint16_t txbd_tso_flags = 0;
5146 struct txdmamap_pool_entry *dma;
5147 bus_dmamap_t dmamap;
5148 bus_dma_tag_t dmatag;
5149 int i = 0;
5150 int use_tso, maxsegsize, error;
5151 bool have_vtag;
5152 uint16_t vtag;
5153 bool remap;
5154
5155 if (m_head->m_pkthdr.csum_flags) {
5156 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4)
5157 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
5158 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4 |M_CSUM_UDPv4))
5159 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
5160 }
5161
5162 /*
5163 * If we were asked to do an outboard checksum, and the NIC
5164 * has the bug where it sometimes adds in the Ethernet padding,
5165 * explicitly pad with zeros so the cksum will be correct either way.
5166 * (For now, do this for all chip versions, until newer
5167 * are confirmed to not require the workaround.)
5168 */
5169 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 ||
5170 #ifdef notyet
5171 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||
5172 #endif
5173 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD)
5174 goto check_dma_bug;
5175
5176 if (bge_cksum_pad(m_head) != 0)
5177 return ENOBUFS;
5178
5179 check_dma_bug:
5180 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX))
5181 goto doit;
5182
5183 /*
5184 * bcm5700 Revision B silicon cannot handle DMA descriptors with
5185 * less than eight bytes. If we encounter a teeny mbuf
5186 * at the end of a chain, we can pad. Otherwise, copy.
5187 */
5188 if (bge_compact_dma_runt(m_head) != 0)
5189 return ENOBUFS;
5190
5191 doit:
5192 dma = SLIST_FIRST(&sc->txdma_list);
5193 if (dma == NULL) {
5194 return ENOBUFS;
5195 }
5196 dmamap = dma->dmamap;
5197 dmatag = sc->bge_dmatag;
5198 dma->is_dma32 = false;
5199
5200 /*
5201 * Set up any necessary TSO state before we start packing...
5202 */
5203 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0;
5204 if (!use_tso) {
5205 maxsegsize = 0;
5206 } else { /* TSO setup */
5207 unsigned mss;
5208 struct ether_header *eh;
5209 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset;
5210 unsigned bge_hlen;
5211 struct mbuf * m0 = m_head;
5212 struct ip *ip;
5213 struct tcphdr *th;
5214 int iphl, hlen;
5215
5216 /*
5217 * XXX It would be nice if the mbuf pkthdr had offset
5218 * fields for the protocol headers.
5219 */
5220
5221 eh = mtod(m0, struct ether_header *);
5222 switch (htons(eh->ether_type)) {
5223 case ETHERTYPE_IP:
5224 offset = ETHER_HDR_LEN;
5225 break;
5226
5227 case ETHERTYPE_VLAN:
5228 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
5229 break;
5230
5231 default:
5232 /*
5233 * Don't support this protocol or encapsulation.
5234 */
5235 return ENOBUFS;
5236 }
5237
5238 /*
5239 * TCP/IP headers are in the first mbuf; we can do
5240 * this the easy way.
5241 */
5242 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data);
5243 hlen = iphl + offset;
5244 if (__predict_false(m0->m_len <
5245 (hlen + sizeof(struct tcphdr)))) {
5246
5247 aprint_error_dev(sc->bge_dev,
5248 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd,"
5249 "not handled yet\n",
5250 m0->m_len, hlen+ sizeof(struct tcphdr));
5251 #ifdef NOTYET
5252 /*
5253 * XXX jonathan@NetBSD.org: untested.
5254 * how to force this branch to be taken?
5255 */
5256 BGE_EVCNT_INCR(sc->bge_ev_txtsopain);
5257
5258 m_copydata(m0, offset, sizeof(ip), &ip);
5259 m_copydata(m0, hlen, sizeof(th), &th);
5260
5261 ip.ip_len = 0;
5262
5263 m_copyback(m0, hlen + offsetof(struct ip, ip_len),
5264 sizeof(ip.ip_len), &ip.ip_len);
5265
5266 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr,
5267 ip.ip_dst.s_addr, htons(IPPROTO_TCP));
5268
5269 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum),
5270 sizeof(th.th_sum), &th.th_sum);
5271
5272 hlen += th.th_off << 2;
5273 iptcp_opt_words = hlen;
5274 #else
5275 /*
5276 * if_wm "hard" case not yet supported, can we not
5277 * mandate it out of existence?
5278 */
5279 (void) ip; (void)th; (void) ip_tcp_hlen;
5280
5281 return ENOBUFS;
5282 #endif
5283 } else {
5284 ip = (struct ip *) (mtod(m0, char *) + offset);
5285 th = (struct tcphdr *) (mtod(m0, char *) + hlen);
5286 ip_tcp_hlen = iphl + (th->th_off << 2);
5287
5288 /* Total IP/TCP options, in 32-bit words */
5289 iptcp_opt_words = (ip_tcp_hlen
5290 - sizeof(struct tcphdr)
5291 - sizeof(struct ip)) >> 2;
5292 }
5293 if (BGE_IS_575X_PLUS(sc)) {
5294 th->th_sum = 0;
5295 csum_flags = 0;
5296 } else {
5297 /*
5298 * XXX jonathan@NetBSD.org: 5705 untested.
5299 * Requires TSO firmware patch for 5701/5703/5704.
5300 */
5301 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr,
5302 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
5303 }
5304
5305 mss = m_head->m_pkthdr.segsz;
5306 txbd_tso_flags |=
5307 BGE_TXBDFLAG_CPU_PRE_DMA |
5308 BGE_TXBDFLAG_CPU_POST_DMA;
5309
5310 /*
5311 * Our NIC TSO-assist assumes TSO has standard, optionless
5312 * IPv4 and TCP headers, which total 40 bytes. By default,
5313 * the NIC copies 40 bytes of IP/TCP header from the
5314 * supplied header into the IP/TCP header portion of
5315 * each post-TSO-segment. If the supplied packet has IP or
5316 * TCP options, we need to tell the NIC to copy those extra
5317 * bytes into each post-TSO header, in addition to the normal
5318 * 40-byte IP/TCP header (and to leave space accordingly).
5319 * Unfortunately, the driver encoding of option length
5320 * varies across different ASIC families.
5321 */
5322 tcp_seg_flags = 0;
5323 bge_hlen = ip_tcp_hlen >> 2;
5324 if (BGE_IS_5717_PLUS(sc)) {
5325 tcp_seg_flags = (bge_hlen & 0x3) << 14;
5326 txbd_tso_flags |=
5327 ((bge_hlen & 0xF8) << 7) | ((bge_hlen & 0x4) << 2);
5328 } else if (BGE_IS_5705_PLUS(sc)) {
5329 tcp_seg_flags = bge_hlen << 11;
5330 } else {
5331 /* XXX iptcp_opt_words or bge_hlen ? */
5332 txbd_tso_flags |= iptcp_opt_words << 12;
5333 }
5334 maxsegsize = mss | tcp_seg_flags;
5335 ip->ip_len = htons(mss + ip_tcp_hlen);
5336 ip->ip_sum = 0;
5337
5338 } /* TSO setup */
5339
5340 have_vtag = vlan_has_tag(m_head);
5341 if (have_vtag)
5342 vtag = vlan_get_tag(m_head);
5343
5344 /*
5345 * Start packing the mbufs in this chain into
5346 * the fragment pointers. Stop when we run out
5347 * of fragments or hit the end of the mbuf chain.
5348 */
5349 remap = true;
5350 load_again:
5351 error = bus_dmamap_load_mbuf(dmatag, dmamap, m_head, BUS_DMA_NOWAIT);
5352 if (__predict_false(error)) {
5353 if (error == EFBIG && remap) {
5354 struct mbuf *m;
5355 remap = false;
5356 m = m_defrag(m_head, M_NOWAIT);
5357 if (m != NULL) {
5358 KASSERT(m == m_head);
5359 goto load_again;
5360 }
5361 }
5362 return error;
5363 }
5364 /*
5365 * Sanity check: avoid coming within 16 descriptors
5366 * of the end of the ring.
5367 */
5368 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) {
5369 BGE_TSO_PRINTF(("%s: "
5370 " dmamap_load_mbuf too close to ring wrap\n",
5371 device_xname(sc->bge_dev)));
5372 goto fail_unload;
5373 }
5374
5375 /* Iterate over dmap-map fragments. */
5376 f = prev_f = NULL;
5377 cur = frag = *txidx;
5378
5379 for (i = 0; i < dmamap->dm_nsegs; i++) {
5380 f = &sc->bge_rdata->bge_tx_ring[frag];
5381 if (sc->bge_cdata.bge_tx_chain[frag] != NULL)
5382 break;
5383
5384 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr);
5385 f->bge_len = dmamap->dm_segs[i].ds_len;
5386 if (sizeof(bus_addr_t) > 4 && dma->is_dma32 == false && use_tso && (
5387 (dmamap->dm_segs[i].ds_addr & 0xffffffff00000000) !=
5388 ((dmamap->dm_segs[i].ds_addr + f->bge_len) & 0xffffffff00000000) ||
5389 (prev_f != NULL &&
5390 prev_f->bge_addr.bge_addr_hi != f->bge_addr.bge_addr_hi))
5391 ) {
5392 /*
5393 * watchdog timeout issue was observed with TSO,
5394 * limiting DMA address space to 32bits seems to
5395 * address the issue.
5396 */
5397 bus_dmamap_unload(dmatag, dmamap);
5398 dmatag = sc->bge_dmatag32;
5399 dmamap = dma->dmamap32;
5400 dma->is_dma32 = true;
5401 remap = true;
5402 goto load_again;
5403 }
5404
5405 /*
5406 * For 5751 and follow-ons, for TSO we must turn
5407 * off checksum-assist flag in the tx-descr, and
5408 * supply the ASIC-revision-specific encoding
5409 * of TSO flags and segsize.
5410 */
5411 if (use_tso) {
5412 if (BGE_IS_575X_PLUS(sc) || i == 0) {
5413 f->bge_rsvd = maxsegsize;
5414 f->bge_flags = csum_flags | txbd_tso_flags;
5415 } else {
5416 f->bge_rsvd = 0;
5417 f->bge_flags =
5418 (csum_flags | txbd_tso_flags) & 0x0fff;
5419 }
5420 } else {
5421 f->bge_rsvd = 0;
5422 f->bge_flags = csum_flags;
5423 }
5424
5425 if (have_vtag) {
5426 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
5427 f->bge_vlan_tag = vtag;
5428 } else {
5429 f->bge_vlan_tag = 0;
5430 }
5431 prev_f = f;
5432 cur = frag;
5433 BGE_INC(frag, BGE_TX_RING_CNT);
5434 }
5435
5436 if (i < dmamap->dm_nsegs) {
5437 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n",
5438 device_xname(sc->bge_dev), i, dmamap->dm_nsegs));
5439 goto fail_unload;
5440 }
5441
5442 bus_dmamap_sync(dmatag, dmamap, 0, dmamap->dm_mapsize,
5443 BUS_DMASYNC_PREWRITE);
5444
5445 if (frag == sc->bge_tx_saved_considx) {
5446 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n",
5447 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx));
5448
5449 goto fail_unload;
5450 }
5451
5452 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END;
5453 sc->bge_cdata.bge_tx_chain[cur] = m_head;
5454 SLIST_REMOVE_HEAD(&sc->txdma_list, link);
5455 sc->txdma[cur] = dma;
5456 sc->bge_txcnt += dmamap->dm_nsegs;
5457
5458 *txidx = frag;
5459
5460 return 0;
5461
5462 fail_unload:
5463 bus_dmamap_unload(dmatag, dmamap);
5464
5465 return ENOBUFS;
5466 }
5467
5468
5469 static void
bge_start(struct ifnet * ifp)5470 bge_start(struct ifnet *ifp)
5471 {
5472 struct bge_softc * const sc = ifp->if_softc;
5473
5474 mutex_enter(sc->sc_intr_lock);
5475 if (!sc->bge_txrx_stopping)
5476 bge_start_locked(ifp);
5477 mutex_exit(sc->sc_intr_lock);
5478 }
5479
5480 /*
5481 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5482 * to the mbuf data regions directly in the transmit descriptors.
5483 */
5484 static void
bge_start_locked(struct ifnet * ifp)5485 bge_start_locked(struct ifnet *ifp)
5486 {
5487 struct bge_softc * const sc = ifp->if_softc;
5488 struct mbuf *m_head = NULL;
5489 struct mbuf *m;
5490 uint32_t prodidx;
5491 int pkts = 0;
5492 int error;
5493
5494 KASSERT(mutex_owned(sc->sc_intr_lock));
5495
5496 prodidx = sc->bge_tx_prodidx;
5497
5498 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
5499 IFQ_POLL(&ifp->if_snd, m_head);
5500 if (m_head == NULL)
5501 break;
5502
5503 #if 0
5504 /*
5505 * XXX
5506 * safety overkill. If this is a fragmented packet chain
5507 * with delayed TCP/UDP checksums, then only encapsulate
5508 * it if we have enough descriptors to handle the entire
5509 * chain at once.
5510 * (paranoia -- may not actually be needed)
5511 */
5512 if (m_head->m_flags & M_FIRSTFRAG &&
5513 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
5514 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
5515 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) {
5516 ifp->if_flags |= IFF_OACTIVE;
5517 break;
5518 }
5519 }
5520 #endif
5521
5522 /*
5523 * Pack the data into the transmit ring. If we
5524 * don't have room, set the OACTIVE flag and wait
5525 * for the NIC to drain the ring.
5526 */
5527 error = bge_encap(sc, m_head, &prodidx);
5528 if (__predict_false(error)) {
5529 if (SLIST_EMPTY(&sc->txdma_list)) {
5530 /* just wait for the transmit ring to drain */
5531 break;
5532 }
5533 IFQ_DEQUEUE(&ifp->if_snd, m);
5534 KASSERT(m == m_head);
5535 m_freem(m_head);
5536 continue;
5537 }
5538
5539 /* now we are committed to transmit the packet */
5540 IFQ_DEQUEUE(&ifp->if_snd, m);
5541 KASSERT(m == m_head);
5542 pkts++;
5543
5544 /*
5545 * If there's a BPF listener, bounce a copy of this frame
5546 * to him.
5547 */
5548 bpf_mtap(ifp, m_head, BPF_D_OUT);
5549 }
5550 if (pkts == 0)
5551 return;
5552
5553 /* Transmit */
5554 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5555 /* 5700 b2 errata */
5556 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)
5557 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5558
5559 sc->bge_tx_prodidx = prodidx;
5560 sc->bge_tx_lastsent = time_uptime;
5561 sc->bge_tx_sending = true;
5562 }
5563
5564 static int
bge_init(struct ifnet * ifp)5565 bge_init(struct ifnet *ifp)
5566 {
5567 struct bge_softc * const sc = ifp->if_softc;
5568
5569 KASSERT(IFNET_LOCKED(ifp));
5570
5571 if (sc->bge_detaching)
5572 return ENXIO;
5573
5574 mutex_enter(sc->sc_core_lock);
5575 int ret = bge_init_locked(ifp);
5576 mutex_exit(sc->sc_core_lock);
5577
5578 return ret;
5579 }
5580
5581
5582 static int
bge_init_locked(struct ifnet * ifp)5583 bge_init_locked(struct ifnet *ifp)
5584 {
5585 struct bge_softc * const sc = ifp->if_softc;
5586 const uint16_t *m;
5587 uint32_t mode, reg;
5588 int error = 0;
5589
5590 ASSERT_SLEEPABLE();
5591 KASSERT(IFNET_LOCKED(ifp));
5592 KASSERT(mutex_owned(sc->sc_core_lock));
5593 KASSERT(ifp == &sc->ethercom.ec_if);
5594
5595 /* Cancel pending I/O and flush buffers. */
5596 bge_stop_locked(ifp, false);
5597
5598 bge_stop_fw(sc);
5599 bge_sig_pre_reset(sc, BGE_RESET_START);
5600 bge_reset(sc);
5601 bge_sig_legacy(sc, BGE_RESET_START);
5602
5603 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) {
5604 reg = CSR_READ_4(sc, BGE_CPMU_CTRL);
5605 reg &= ~(BGE_CPMU_CTRL_LINK_AWARE_MODE |
5606 BGE_CPMU_CTRL_LINK_IDLE_MODE);
5607 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg);
5608
5609 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);
5610 reg &= ~BGE_CPMU_LSPD_10MB_CLK;
5611 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25;
5612 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg);
5613
5614 reg = CSR_READ_4(sc, BGE_CPMU_LNK_AWARE_PWRMD);
5615 reg &= ~BGE_CPMU_LNK_AWARE_MACCLK_MASK;
5616 reg |= BGE_CPMU_LNK_AWARE_MACCLK_6_25;
5617 CSR_WRITE_4(sc, BGE_CPMU_LNK_AWARE_PWRMD, reg);
5618
5619 reg = CSR_READ_4(sc, BGE_CPMU_HST_ACC);
5620 reg &= ~BGE_CPMU_HST_ACC_MACCLK_MASK;
5621 reg |= BGE_CPMU_HST_ACC_MACCLK_6_25;
5622 CSR_WRITE_4(sc, BGE_CPMU_HST_ACC, reg);
5623 }
5624
5625 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) {
5626 pcireg_t aercap;
5627
5628 reg = CSR_READ_4(sc, BGE_PCIE_PWRMNG_THRESH);
5629 reg = (reg & ~BGE_PCIE_PWRMNG_L1THRESH_MASK)
5630 | BGE_PCIE_PWRMNG_L1THRESH_4MS
5631 | BGE_PCIE_PWRMNG_EXTASPMTMR_EN;
5632 CSR_WRITE_4(sc, BGE_PCIE_PWRMNG_THRESH, reg);
5633
5634 reg = CSR_READ_4(sc, BGE_PCIE_EIDLE_DELAY);
5635 reg = (reg & ~BGE_PCIE_EIDLE_DELAY_MASK)
5636 | BGE_PCIE_EIDLE_DELAY_13CLK;
5637 CSR_WRITE_4(sc, BGE_PCIE_EIDLE_DELAY, reg);
5638
5639 /* Clear correctable error */
5640 if (pci_get_ext_capability(sc->sc_pc, sc->sc_pcitag,
5641 PCI_EXTCAP_AER, &aercap, NULL) != 0)
5642 pci_conf_write(sc->sc_pc, sc->sc_pcitag,
5643 aercap + PCI_AER_COR_STATUS, 0xffffffff);
5644
5645 reg = CSR_READ_4(sc, BGE_PCIE_LINKCTL);
5646 reg = (reg & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN)
5647 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS;
5648 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, reg);
5649 }
5650
5651 bge_sig_post_reset(sc, BGE_RESET_START);
5652
5653 bge_chipinit(sc);
5654
5655 /*
5656 * Init the various state machines, ring
5657 * control blocks and firmware.
5658 */
5659 error = bge_blockinit(sc);
5660 if (error != 0) {
5661 aprint_error_dev(sc->bge_dev, "initialization error %d\n",
5662 error);
5663 return error;
5664 }
5665
5666 /* 5718 step 25, 57XX step 54 */
5667 /* Specify MTU. */
5668 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
5669 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
5670
5671 /* 5718 step 23 */
5672 /* Load our MAC address. */
5673 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]);
5674 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
5675 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI,
5676 ((uint32_t)htons(m[1]) << 16) | htons(m[2]));
5677
5678 /* Enable or disable promiscuous mode as needed. */
5679 if (ifp->if_flags & IFF_PROMISC)
5680 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
5681 else
5682 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
5683
5684 /* Program multicast filter. */
5685 bge_setmulti(sc);
5686
5687 /* Init RX ring. */
5688 bge_init_rx_ring_std(sc);
5689
5690 /*
5691 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
5692 * memory to insure that the chip has in fact read the first
5693 * entry of the ring.
5694 */
5695 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
5696 u_int i;
5697 for (i = 0; i < 10; i++) {
5698 DELAY(20);
5699 uint32_t v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
5700 if (v == (MCLBYTES - ETHER_ALIGN))
5701 break;
5702 }
5703 if (i == 10)
5704 aprint_error_dev(sc->bge_dev,
5705 "5705 A0 chip failed to load RX ring\n");
5706 }
5707
5708 /* Init jumbo RX ring. */
5709 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
5710 bge_init_rx_ring_jumbo(sc);
5711
5712 /* Init our RX return ring index */
5713 sc->bge_rx_saved_considx = 0;
5714
5715 /* Init TX ring. */
5716 bge_init_tx_ring(sc);
5717
5718 /* 5718 step 63, 57XX step 94 */
5719 /* Enable TX MAC state machine lockup fix. */
5720 mode = CSR_READ_4(sc, BGE_TX_MODE);
5721 if (BGE_IS_5755_PLUS(sc) ||
5722 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
5723 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
5724 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 ||
5725 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) {
5726 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5727 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
5728 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5729 }
5730
5731 /* Turn on transmitter */
5732 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
5733 /* 5718 step 64 */
5734 DELAY(100);
5735
5736 /* 5718 step 65, 57XX step 95 */
5737 /* Turn on receiver */
5738 mode = CSR_READ_4(sc, BGE_RX_MODE);
5739 if (BGE_IS_5755_PLUS(sc))
5740 mode |= BGE_RXMODE_IPV6_ENABLE;
5741 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762)
5742 mode |= BGE_RXMODE_IPV4_FRAG_FIX;
5743 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE);
5744 /* 5718 step 66 */
5745 DELAY(10);
5746
5747 /* 5718 step 12, 57XX step 37 */
5748 /*
5749 * XXX Doucments of 5718 series and 577xx say the recommended value
5750 * is 1, but tg3 set 1 only on 57765 series.
5751 */
5752 if (BGE_IS_57765_PLUS(sc))
5753 reg = 1;
5754 else
5755 reg = 2;
5756 CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg);
5757
5758 /* Tell firmware we're alive. */
5759 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5760
5761 /* Enable host interrupts. */
5762 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
5763 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5764 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0);
5765
5766 mutex_enter(sc->sc_intr_lock);
5767 if ((error = bge_ifmedia_upd(ifp)) == 0) {
5768 sc->bge_stopping = false;
5769 sc->bge_txrx_stopping = false;
5770
5771 /* IFNET_LOCKED asserted above */
5772 ifp->if_flags |= IFF_RUNNING;
5773
5774 callout_schedule(&sc->bge_timeout, hz);
5775 }
5776 mutex_exit(sc->sc_intr_lock);
5777
5778 sc->bge_if_flags = ifp->if_flags;
5779
5780 return error;
5781 }
5782
5783 /*
5784 * Set media options.
5785 */
5786 static int
bge_ifmedia_upd(struct ifnet * ifp)5787 bge_ifmedia_upd(struct ifnet *ifp)
5788 {
5789 struct bge_softc * const sc = ifp->if_softc;
5790 struct mii_data * const mii = &sc->bge_mii;
5791 struct ifmedia * const ifm = &sc->bge_ifmedia;
5792 int rc;
5793
5794 KASSERT(mutex_owned(sc->sc_intr_lock));
5795
5796 /* If this is a 1000baseX NIC, enable the TBI port. */
5797 if (sc->bge_flags & BGEF_FIBER_TBI) {
5798 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
5799 return EINVAL;
5800 switch (IFM_SUBTYPE(ifm->ifm_media)) {
5801 case IFM_AUTO:
5802 /*
5803 * The BCM5704 ASIC appears to have a special
5804 * mechanism for programming the autoneg
5805 * advertisement registers in TBI mode.
5806 */
5807 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) {
5808 uint32_t sgdig;
5809 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
5810 if (sgdig & BGE_SGDIGSTS_DONE) {
5811 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
5812 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
5813 sgdig |= BGE_SGDIGCFG_AUTO |
5814 BGE_SGDIGCFG_PAUSE_CAP |
5815 BGE_SGDIGCFG_ASYM_PAUSE;
5816 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG,
5817 sgdig | BGE_SGDIGCFG_SEND);
5818 DELAY(5);
5819 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG,
5820 sgdig);
5821 }
5822 }
5823 break;
5824 case IFM_1000_SX:
5825 if ((ifm->ifm_media & IFM_FDX) != 0) {
5826 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE,
5827 BGE_MACMODE_HALF_DUPLEX);
5828 } else {
5829 BGE_SETBIT_FLUSH(sc, BGE_MAC_MODE,
5830 BGE_MACMODE_HALF_DUPLEX);
5831 }
5832 DELAY(40);
5833 break;
5834 default:
5835 return EINVAL;
5836 }
5837 /* XXX 802.3x flow control for 1000BASE-SX */
5838 return 0;
5839 }
5840
5841 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784) &&
5842 (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5784_AX)) {
5843 uint32_t reg;
5844
5845 reg = CSR_READ_4(sc, BGE_CPMU_CTRL);
5846 if ((reg & BGE_CPMU_CTRL_GPHY_10MB_RXONLY) != 0) {
5847 reg &= ~BGE_CPMU_CTRL_GPHY_10MB_RXONLY;
5848 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg);
5849 }
5850 }
5851
5852 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT);
5853 if ((rc = mii_mediachg(mii)) == ENXIO)
5854 return 0;
5855
5856 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) {
5857 uint32_t reg;
5858
5859 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_1000MB_CLK);
5860 if ((reg & BGE_CPMU_LSPD_1000MB_MACCLK_MASK)
5861 == (BGE_CPMU_LSPD_1000MB_MACCLK_12_5)) {
5862 reg &= ~BGE_CPMU_LSPD_1000MB_MACCLK_MASK;
5863 delay(40);
5864 CSR_WRITE_4(sc, BGE_CPMU_LSPD_1000MB_CLK, reg);
5865 }
5866 }
5867
5868 /*
5869 * Force an interrupt so that we will call bge_link_upd
5870 * if needed and clear any pending link state attention.
5871 * Without this we are not getting any further interrupts
5872 * for link state changes and thus will not UP the link and
5873 * not be able to send in bge_start. The only way to get
5874 * things working was to receive a packet and get a RX intr.
5875 */
5876 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 ||
5877 sc->bge_flags & BGEF_IS_5788)
5878 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
5879 else
5880 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
5881
5882 return rc;
5883 }
5884
5885 /*
5886 * Report current media status.
5887 */
5888 static void
bge_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)5889 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
5890 {
5891 struct bge_softc * const sc = ifp->if_softc;
5892 struct mii_data * const mii = &sc->bge_mii;
5893
5894 KASSERT(mutex_owned(sc->sc_intr_lock));
5895
5896 if (sc->bge_flags & BGEF_FIBER_TBI) {
5897 ifmr->ifm_status = IFM_AVALID;
5898 ifmr->ifm_active = IFM_ETHER;
5899 if (CSR_READ_4(sc, BGE_MAC_STS) &
5900 BGE_MACSTAT_TBI_PCS_SYNCHED)
5901 ifmr->ifm_status |= IFM_ACTIVE;
5902 ifmr->ifm_active |= IFM_1000_SX;
5903 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
5904 ifmr->ifm_active |= IFM_HDX;
5905 else
5906 ifmr->ifm_active |= IFM_FDX;
5907 return;
5908 }
5909
5910 mii_pollstat(mii);
5911 ifmr->ifm_status = mii->mii_media_status;
5912 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) |
5913 sc->bge_flowflags;
5914 }
5915
5916 static int
bge_ifflags_cb(struct ethercom * ec)5917 bge_ifflags_cb(struct ethercom *ec)
5918 {
5919 struct ifnet * const ifp = &ec->ec_if;
5920 struct bge_softc * const sc = ifp->if_softc;
5921 int ret = 0;
5922
5923 KASSERT(IFNET_LOCKED(ifp));
5924 mutex_enter(sc->sc_core_lock);
5925
5926 u_short change = ifp->if_flags ^ sc->bge_if_flags;
5927
5928 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) {
5929 ret = ENETRESET;
5930 } else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
5931 if ((ifp->if_flags & IFF_PROMISC) == 0)
5932 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
5933 else
5934 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
5935
5936 bge_setmulti(sc);
5937 }
5938
5939 sc->bge_if_flags = ifp->if_flags;
5940 mutex_exit(sc->sc_core_lock);
5941
5942 return ret;
5943 }
5944
5945 static int
bge_ioctl(struct ifnet * ifp,u_long command,void * data)5946 bge_ioctl(struct ifnet *ifp, u_long command, void *data)
5947 {
5948 struct bge_softc * const sc = ifp->if_softc;
5949 struct ifreq * const ifr = (struct ifreq *) data;
5950 int error = 0;
5951
5952 switch (command) {
5953 case SIOCADDMULTI:
5954 case SIOCDELMULTI:
5955 break;
5956 default:
5957 KASSERT(IFNET_LOCKED(ifp));
5958 }
5959
5960 const int s = splnet();
5961
5962 switch (command) {
5963 case SIOCSIFMEDIA:
5964 mutex_enter(sc->sc_core_lock);
5965 /* XXX Flow control is not supported for 1000BASE-SX */
5966 if (sc->bge_flags & BGEF_FIBER_TBI) {
5967 ifr->ifr_media &= ~IFM_ETH_FMASK;
5968 sc->bge_flowflags = 0;
5969 }
5970
5971 /* Flow control requires full-duplex mode. */
5972 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO ||
5973 (ifr->ifr_media & IFM_FDX) == 0) {
5974 ifr->ifr_media &= ~IFM_ETH_FMASK;
5975 }
5976 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) {
5977 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) {
5978 /* We can do both TXPAUSE and RXPAUSE. */
5979 ifr->ifr_media |=
5980 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
5981 }
5982 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK;
5983 }
5984 mutex_exit(sc->sc_core_lock);
5985
5986 if (sc->bge_flags & BGEF_FIBER_TBI) {
5987 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia,
5988 command);
5989 } else {
5990 struct mii_data * const mii = &sc->bge_mii;
5991 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
5992 command);
5993 }
5994 break;
5995 default:
5996 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET)
5997 break;
5998
5999 error = 0;
6000
6001 if (command == SIOCADDMULTI || command == SIOCDELMULTI) {
6002 mutex_enter(sc->sc_core_lock);
6003 if (sc->bge_if_flags & IFF_RUNNING) {
6004 bge_setmulti(sc);
6005 }
6006 mutex_exit(sc->sc_core_lock);
6007 }
6008 break;
6009 }
6010
6011 splx(s);
6012
6013 return error;
6014 }
6015
6016 static bool
bge_watchdog_check(struct bge_softc * const sc)6017 bge_watchdog_check(struct bge_softc * const sc)
6018 {
6019
6020 KASSERT(mutex_owned(sc->sc_core_lock));
6021
6022 if (!sc->bge_tx_sending)
6023 return true;
6024
6025 if (time_uptime - sc->bge_tx_lastsent <= bge_watchdog_timeout)
6026 return true;
6027
6028 /* If pause frames are active then don't reset the hardware. */
6029 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) {
6030 const uint32_t status = CSR_READ_4(sc, BGE_RX_STS);
6031 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) {
6032 /*
6033 * If link partner has us in XOFF state then wait for
6034 * the condition to clear.
6035 */
6036 CSR_WRITE_4(sc, BGE_RX_STS, status);
6037 sc->bge_tx_lastsent = time_uptime;
6038 return true;
6039 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 &&
6040 (status & BGE_RXSTAT_RCVD_XON) != 0) {
6041 /*
6042 * If link partner has us in XOFF state then wait for
6043 * the condition to clear.
6044 */
6045 CSR_WRITE_4(sc, BGE_RX_STS, status);
6046 sc->bge_tx_lastsent = time_uptime;
6047 return true;
6048 }
6049 /*
6050 * Any other condition is unexpected and the controller
6051 * should be reset.
6052 */
6053 }
6054
6055 return false;
6056 }
6057
6058 static bool
bge_watchdog_tick(struct ifnet * ifp)6059 bge_watchdog_tick(struct ifnet *ifp)
6060 {
6061 struct bge_softc * const sc = ifp->if_softc;
6062
6063 KASSERT(mutex_owned(sc->sc_core_lock));
6064
6065 if (!sc->sc_trigger_reset && bge_watchdog_check(sc))
6066 return true;
6067
6068 if (atomic_swap_uint(&sc->sc_reset_pending, 1) == 0)
6069 workqueue_enqueue(sc->sc_reset_wq, &sc->sc_reset_work, NULL);
6070
6071 return false;
6072 }
6073
6074 /*
6075 * Perform an interface watchdog reset.
6076 */
6077 static void
bge_handle_reset_work(struct work * work,void * arg)6078 bge_handle_reset_work(struct work *work, void *arg)
6079 {
6080 struct bge_softc * const sc = arg;
6081 struct ifnet * const ifp = &sc->ethercom.ec_if;
6082
6083 printf("%s: watchdog timeout -- resetting\n", ifp->if_xname);
6084
6085 /* Don't want ioctl operations to happen */
6086 IFNET_LOCK(ifp);
6087
6088 /* reset the interface. */
6089 bge_init(ifp);
6090
6091 IFNET_UNLOCK(ifp);
6092
6093 /*
6094 * There are still some upper layer processing which call
6095 * ifp->if_start(). e.g. ALTQ or one CPU system
6096 */
6097 /* Try to get more packets going. */
6098 ifp->if_start(ifp);
6099
6100 atomic_store_relaxed(&sc->sc_reset_pending, 0);
6101 }
6102
6103 static void
bge_stop_block(struct bge_softc * sc,bus_addr_t reg,uint32_t bit)6104 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit)
6105 {
6106 int i;
6107
6108 BGE_CLRBIT_FLUSH(sc, reg, bit);
6109
6110 for (i = 0; i < 1000; i++) {
6111 delay(100);
6112 if ((CSR_READ_4(sc, reg) & bit) == 0)
6113 return;
6114 }
6115
6116 /*
6117 * Doesn't print only when the register is BGE_SRS_MODE. It occurs
6118 * on some environment (and once after boot?)
6119 */
6120 if (reg != BGE_SRS_MODE)
6121 aprint_error_dev(sc->bge_dev,
6122 "block failed to stop: reg 0x%lx, bit 0x%08x\n",
6123 (u_long)reg, bit);
6124 }
6125
6126
6127 static void
bge_stop(struct ifnet * ifp,int disable)6128 bge_stop(struct ifnet *ifp, int disable)
6129 {
6130 struct bge_softc * const sc = ifp->if_softc;
6131
6132 ASSERT_SLEEPABLE();
6133 KASSERT(IFNET_LOCKED(ifp));
6134
6135 mutex_enter(sc->sc_core_lock);
6136 bge_stop_locked(ifp, disable ? true : false);
6137 mutex_exit(sc->sc_core_lock);
6138 }
6139
6140 /*
6141 * Stop the adapter and free any mbufs allocated to the
6142 * RX and TX lists.
6143 */
6144 static void
bge_stop_locked(struct ifnet * ifp,bool disable)6145 bge_stop_locked(struct ifnet *ifp, bool disable)
6146 {
6147 struct bge_softc * const sc = ifp->if_softc;
6148
6149 ASSERT_SLEEPABLE();
6150 KASSERT(IFNET_LOCKED(ifp));
6151 KASSERT(mutex_owned(sc->sc_core_lock));
6152
6153 sc->bge_stopping = true;
6154
6155 mutex_enter(sc->sc_intr_lock);
6156 sc->bge_txrx_stopping = true;
6157 mutex_exit(sc->sc_intr_lock);
6158
6159 callout_halt(&sc->bge_timeout, sc->sc_core_lock);
6160
6161 /* Disable host interrupts. */
6162 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
6163 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1);
6164
6165 /*
6166 * Tell firmware we're shutting down.
6167 */
6168 bge_stop_fw(sc);
6169 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
6170
6171 /*
6172 * Disable all of the receiver blocks.
6173 */
6174 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
6175 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
6176 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
6177 if (BGE_IS_5700_FAMILY(sc))
6178 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
6179 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
6180 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
6181 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
6182
6183 /*
6184 * Disable all of the transmit blocks.
6185 */
6186 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
6187 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
6188 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
6189 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
6190 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
6191 if (BGE_IS_5700_FAMILY(sc))
6192 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
6193 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
6194
6195 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB);
6196 delay(40);
6197
6198 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
6199
6200 /*
6201 * Shut down all of the memory managers and related
6202 * state machines.
6203 */
6204 /* 5718 step 5a,5b */
6205 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
6206 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
6207 if (BGE_IS_5700_FAMILY(sc))
6208 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
6209
6210 /* 5718 step 5c,5d */
6211 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
6212 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
6213
6214 if (BGE_IS_5700_FAMILY(sc)) {
6215 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
6216 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
6217 }
6218
6219 bge_reset(sc);
6220 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
6221 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
6222
6223 /*
6224 * Keep the ASF firmware running if up.
6225 */
6226 if (sc->bge_asf_mode & ASF_STACKUP)
6227 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6228 else
6229 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6230
6231 /* Free the RX lists. */
6232 bge_free_rx_ring_std(sc);
6233
6234 /* Free jumbo RX list. */
6235 if (BGE_IS_JUMBO_CAPABLE(sc))
6236 bge_free_rx_ring_jumbo(sc);
6237
6238 /* Free TX buffers. */
6239 bge_free_tx_ring(sc, disable);
6240
6241 /*
6242 * Isolate/power down the PHY.
6243 */
6244 if (!(sc->bge_flags & BGEF_FIBER_TBI)) {
6245 mutex_enter(sc->sc_intr_lock);
6246 mii_down(&sc->bge_mii);
6247 mutex_exit(sc->sc_intr_lock);
6248 }
6249
6250 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
6251
6252 /* Clear MAC's link state (PHY may still have link UP). */
6253 BGE_STS_CLRBIT(sc, BGE_STS_LINK);
6254
6255 ifp->if_flags &= ~IFF_RUNNING;
6256
6257 sc->bge_if_flags = ifp->if_flags;
6258 }
6259
6260 static void
bge_link_upd(struct bge_softc * sc)6261 bge_link_upd(struct bge_softc *sc)
6262 {
6263 struct ifnet * const ifp = &sc->ethercom.ec_if;
6264 struct mii_data * const mii = &sc->bge_mii;
6265 uint32_t status;
6266 uint16_t phyval;
6267 int link;
6268
6269 KASSERT(sc->sc_intr_lock);
6270
6271 /* Clear 'pending link event' flag */
6272 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT);
6273
6274 /*
6275 * Process link state changes.
6276 * Grrr. The link status word in the status block does
6277 * not work correctly on the BCM5700 rev AX and BX chips,
6278 * according to all available information. Hence, we have
6279 * to enable MII interrupts in order to properly obtain
6280 * async link changes. Unfortunately, this also means that
6281 * we have to read the MAC status register to detect link
6282 * changes, thereby adding an additional register access to
6283 * the interrupt handler.
6284 */
6285
6286 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) {
6287 status = CSR_READ_4(sc, BGE_MAC_STS);
6288 if (status & BGE_MACSTAT_MI_INTERRUPT) {
6289 mii_pollstat(mii);
6290
6291 if (!BGE_STS_BIT(sc, BGE_STS_LINK) &&
6292 mii->mii_media_status & IFM_ACTIVE &&
6293 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
6294 BGE_STS_SETBIT(sc, BGE_STS_LINK);
6295 else if (BGE_STS_BIT(sc, BGE_STS_LINK) &&
6296 (!(mii->mii_media_status & IFM_ACTIVE) ||
6297 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE))
6298 BGE_STS_CLRBIT(sc, BGE_STS_LINK);
6299
6300 /* Clear the interrupt */
6301 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
6302 BGE_EVTENB_MI_INTERRUPT);
6303 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr,
6304 BRGPHY_MII_ISR, &phyval);
6305 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr,
6306 BRGPHY_MII_IMR, BRGPHY_INTRS);
6307 }
6308 return;
6309 }
6310
6311 if (sc->bge_flags & BGEF_FIBER_TBI) {
6312 status = CSR_READ_4(sc, BGE_MAC_STS);
6313 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
6314 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) {
6315 BGE_STS_SETBIT(sc, BGE_STS_LINK);
6316 if (BGE_ASICREV(sc->bge_chipid)
6317 == BGE_ASICREV_BCM5704) {
6318 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE,
6319 BGE_MACMODE_TBI_SEND_CFGS);
6320 DELAY(40);
6321 }
6322 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
6323 if_link_state_change(ifp, LINK_STATE_UP);
6324 }
6325 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) {
6326 BGE_STS_CLRBIT(sc, BGE_STS_LINK);
6327 if_link_state_change(ifp, LINK_STATE_DOWN);
6328 }
6329 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) {
6330 /*
6331 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED
6332 * bit in status word always set. Workaround this bug by
6333 * reading PHY link status directly.
6334 */
6335 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)?
6336 BGE_STS_LINK : 0;
6337
6338 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) {
6339 mii_pollstat(mii);
6340
6341 if (!BGE_STS_BIT(sc, BGE_STS_LINK) &&
6342 mii->mii_media_status & IFM_ACTIVE &&
6343 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
6344 BGE_STS_SETBIT(sc, BGE_STS_LINK);
6345 else if (BGE_STS_BIT(sc, BGE_STS_LINK) &&
6346 (!(mii->mii_media_status & IFM_ACTIVE) ||
6347 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE))
6348 BGE_STS_CLRBIT(sc, BGE_STS_LINK);
6349 }
6350 } else {
6351 /*
6352 * For controllers that call mii_tick, we have to poll
6353 * link status.
6354 */
6355 mii_pollstat(mii);
6356 }
6357
6358 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) {
6359 uint32_t reg, scale;
6360
6361 reg = CSR_READ_4(sc, BGE_CPMU_CLCK_STAT) &
6362 BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK;
6363 if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5)
6364 scale = 65;
6365 else if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25)
6366 scale = 6;
6367 else
6368 scale = 12;
6369
6370 reg = CSR_READ_4(sc, BGE_MISC_CFG) &
6371 ~BGE_MISCCFG_TIMER_PRESCALER;
6372 reg |= scale << 1;
6373 CSR_WRITE_4(sc, BGE_MISC_CFG, reg);
6374 }
6375 /* Clear the attention */
6376 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
6377 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
6378 BGE_MACSTAT_LINK_CHANGED);
6379 }
6380
6381 static int
bge_sysctl_verify(SYSCTLFN_ARGS)6382 bge_sysctl_verify(SYSCTLFN_ARGS)
6383 {
6384 int error, t;
6385 struct sysctlnode node;
6386
6387 node = *rnode;
6388 t = *(int*)rnode->sysctl_data;
6389 node.sysctl_data = &t;
6390 error = sysctl_lookup(SYSCTLFN_CALL(&node));
6391 if (error || newp == NULL)
6392 return error;
6393
6394 #if 0
6395 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t,
6396 node.sysctl_num, rnode->sysctl_num));
6397 #endif
6398
6399 if (node.sysctl_num == bge_rxthresh_nodenum) {
6400 if (t < 0 || t >= NBGE_RX_THRESH)
6401 return EINVAL;
6402 bge_update_all_threshes(t);
6403 } else
6404 return EINVAL;
6405
6406 *(int*)rnode->sysctl_data = t;
6407
6408 return 0;
6409 }
6410
6411 /*
6412 * Set up sysctl(3) MIB, hw.bge.*.
6413 */
6414 static void
bge_sysctl_init(struct bge_softc * sc)6415 bge_sysctl_init(struct bge_softc *sc)
6416 {
6417 int rc, bge_root_num;
6418 const struct sysctlnode *node;
6419
6420 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node,
6421 0, CTLTYPE_NODE, "bge",
6422 SYSCTL_DESCR("BGE interface controls"),
6423 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) {
6424 goto out;
6425 }
6426
6427 bge_root_num = node->sysctl_num;
6428
6429 /* BGE Rx interrupt mitigation level */
6430 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node,
6431 CTLFLAG_READWRITE,
6432 CTLTYPE_INT, "rx_lvl",
6433 SYSCTL_DESCR("BGE receive interrupt mitigation level"),
6434 bge_sysctl_verify, 0,
6435 &bge_rx_thresh_lvl,
6436 0, CTL_HW, bge_root_num, CTL_CREATE,
6437 CTL_EOL)) != 0) {
6438 goto out;
6439 }
6440
6441 bge_rxthresh_nodenum = node->sysctl_num;
6442
6443 #ifdef BGE_DEBUG
6444 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node,
6445 CTLFLAG_READWRITE,
6446 CTLTYPE_BOOL, "trigger_reset",
6447 SYSCTL_DESCR("Trigger an interface reset"),
6448 NULL, 0, &sc->sc_trigger_reset, 0, CTL_CREATE,
6449 CTL_EOL)) != 0) {
6450 goto out;
6451 }
6452 #endif
6453 return;
6454
6455 out:
6456 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc);
6457 }
6458
6459 #ifdef BGE_DEBUG
6460 void
bge_debug_info(struct bge_softc * sc)6461 bge_debug_info(struct bge_softc *sc)
6462 {
6463
6464 printf("Hardware Flags:\n");
6465 if (BGE_IS_57765_PLUS(sc))
6466 printf(" - 57765 Plus\n");
6467 if (BGE_IS_5717_PLUS(sc))
6468 printf(" - 5717 Plus\n");
6469 if (BGE_IS_5755_PLUS(sc))
6470 printf(" - 5755 Plus\n");
6471 if (BGE_IS_575X_PLUS(sc))
6472 printf(" - 575X Plus\n");
6473 if (BGE_IS_5705_PLUS(sc))
6474 printf(" - 5705 Plus\n");
6475 if (BGE_IS_5714_FAMILY(sc))
6476 printf(" - 5714 Family\n");
6477 if (BGE_IS_5700_FAMILY(sc))
6478 printf(" - 5700 Family\n");
6479 if (sc->bge_flags & BGEF_IS_5788)
6480 printf(" - 5788\n");
6481 if (sc->bge_flags & BGEF_JUMBO_CAPABLE)
6482 printf(" - Supports Jumbo Frames\n");
6483 if (sc->bge_flags & BGEF_NO_EEPROM)
6484 printf(" - No EEPROM\n");
6485 if (sc->bge_flags & BGEF_PCIX)
6486 printf(" - PCI-X Bus\n");
6487 if (sc->bge_flags & BGEF_PCIE)
6488 printf(" - PCI Express Bus\n");
6489 if (sc->bge_flags & BGEF_RX_ALIGNBUG)
6490 printf(" - RX Alignment Bug\n");
6491 if (sc->bge_flags & BGEF_APE)
6492 printf(" - APE\n");
6493 if (sc->bge_flags & BGEF_CPMU_PRESENT)
6494 printf(" - CPMU\n");
6495 if (sc->bge_flags & BGEF_TSO)
6496 printf(" - TSO\n");
6497 if (sc->bge_flags & BGEF_TAGGED_STATUS)
6498 printf(" - TAGGED_STATUS\n");
6499
6500 /* PHY related */
6501 if (sc->bge_phy_flags & BGEPHYF_NO_3LED)
6502 printf(" - No 3 LEDs\n");
6503 if (sc->bge_phy_flags & BGEPHYF_CRC_BUG)
6504 printf(" - CRC bug\n");
6505 if (sc->bge_phy_flags & BGEPHYF_ADC_BUG)
6506 printf(" - ADC bug\n");
6507 if (sc->bge_phy_flags & BGEPHYF_5704_A0_BUG)
6508 printf(" - 5704 A0 bug\n");
6509 if (sc->bge_phy_flags & BGEPHYF_JITTER_BUG)
6510 printf(" - jitter bug\n");
6511 if (sc->bge_phy_flags & BGEPHYF_BER_BUG)
6512 printf(" - BER bug\n");
6513 if (sc->bge_phy_flags & BGEPHYF_ADJUST_TRIM)
6514 printf(" - adjust trim\n");
6515 if (sc->bge_phy_flags & BGEPHYF_NO_WIRESPEED)
6516 printf(" - no wirespeed\n");
6517
6518 /* ASF related */
6519 if (sc->bge_asf_mode & ASF_ENABLE)
6520 printf(" - ASF enable\n");
6521 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE)
6522 printf(" - ASF new handshake\n");
6523 if (sc->bge_asf_mode & ASF_STACKUP)
6524 printf(" - ASF stackup\n");
6525 }
6526 #endif /* BGE_DEBUG */
6527
6528 static int
bge_get_eaddr_fw(struct bge_softc * sc,uint8_t ether_addr[])6529 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
6530 {
6531 prop_dictionary_t dict;
6532 prop_data_t ea;
6533
6534 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0)
6535 return 1;
6536
6537 dict = device_properties(sc->bge_dev);
6538 ea = prop_dictionary_get(dict, "mac-address");
6539 if (ea != NULL) {
6540 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA);
6541 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN);
6542 memcpy(ether_addr, prop_data_value(ea), ETHER_ADDR_LEN);
6543 return 0;
6544 }
6545
6546 return 1;
6547 }
6548
6549 static int
bge_get_eaddr_mem(struct bge_softc * sc,uint8_t ether_addr[])6550 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
6551 {
6552 uint32_t mac_addr;
6553
6554 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB);
6555 if ((mac_addr >> 16) == 0x484b) {
6556 ether_addr[0] = (uint8_t)(mac_addr >> 8);
6557 ether_addr[1] = (uint8_t)mac_addr;
6558 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB);
6559 ether_addr[2] = (uint8_t)(mac_addr >> 24);
6560 ether_addr[3] = (uint8_t)(mac_addr >> 16);
6561 ether_addr[4] = (uint8_t)(mac_addr >> 8);
6562 ether_addr[5] = (uint8_t)mac_addr;
6563 return 0;
6564 }
6565 return 1;
6566 }
6567
6568 static int
bge_get_eaddr_nvram(struct bge_softc * sc,uint8_t ether_addr[])6569 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
6570 {
6571 int mac_offset = BGE_EE_MAC_OFFSET;
6572
6573 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
6574 mac_offset = BGE_EE_MAC_OFFSET_5906;
6575
6576 return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
6577 ETHER_ADDR_LEN));
6578 }
6579
6580 static int
bge_get_eaddr_eeprom(struct bge_softc * sc,uint8_t ether_addr[])6581 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
6582 {
6583
6584 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
6585 return 1;
6586
6587 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
6588 ETHER_ADDR_LEN));
6589 }
6590
6591 static int
bge_get_eaddr(struct bge_softc * sc,uint8_t eaddr[])6592 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
6593 {
6594 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
6595 /* NOTE: Order is critical */
6596 bge_get_eaddr_fw,
6597 bge_get_eaddr_mem,
6598 bge_get_eaddr_nvram,
6599 bge_get_eaddr_eeprom,
6600 NULL
6601 };
6602 const bge_eaddr_fcn_t *func;
6603
6604 for (func = bge_eaddr_funcs; *func != NULL; ++func) {
6605 if ((*func)(sc, eaddr) == 0)
6606 break;
6607 }
6608 return *func == NULL ? ENXIO : 0;
6609 }
6610