1 /* $NetBSD: if_bgevar.h,v 1.6 2011/01/09 13:01:03 jruoho Exp $ */ 2 /* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2001 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_bgereg.h,v 1.1.2.7 2002/11/02 18:17:55 mp Exp $ 35 */ 36 37 /* 38 * BCM570x memory map. The internal memory layout varies somewhat 39 * depending on whether or not we have external SSRAM attached. 40 * The BCM5700 can have up to 16MB of external memory. The BCM5701 41 * is apparently not designed to use external SSRAM. The mappings 42 * up to the first 4 send rings are the same for both internal and 43 * external memory configurations. Note that mini RX ring space is 44 * only available with external SSRAM configurations, which means 45 * the mini RX ring is not supported on the BCM5701. 46 * 47 * The NIC's memory can be accessed by the host in one of 3 ways: 48 * 49 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 50 * registers in PCI config space can be used to read any 32-bit 51 * address within the NIC's memory. 52 * 53 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 54 * space can be used in conjunction with the memory window in the 55 * device register space at offset 0x8000 to read any 32K chunk 56 * of NIC memory. 57 * 58 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 59 * set, the device I/O mapping consumes 32MB of host address space, 60 * allowing all of the registers and internal NIC memory to be 61 * accessed directly. NIC memory addresses are offset by 0x01000000. 62 * Flat mode consumes so much host address space that it is not 63 * recommended. 64 */ 65 66 #ifndef _DEV_PCI_IF_BGEVAR_H_ 67 #define _DEV_PCI_IF_BGEVAR_H_ 68 69 #include <machine/bus.h> 70 #include <net/if_ether.h> 71 #include <dev/pci/pcivar.h> 72 73 #define BGE_HOSTADDR(x, y) \ 74 do { \ 75 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 76 if (sizeof (bus_addr_t) == 8) \ 77 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 78 else \ 79 (x).bge_addr_hi = 0; \ 80 } while(0) 81 82 #define RCB_WRITE_4(sc, rcb, offset, val) \ 83 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 84 rcb + offsetof(struct bge_rcb, offset), val) 85 86 /* 87 * Other utility macros. 88 */ 89 #define BGE_INC(x, y) (x) = (x + 1) % y 90 91 /* 92 * Register access macros. The Tigon always uses memory mapped register 93 * accesses and all registers must be accessed with 32 bit operations. 94 */ 95 96 #define CSR_WRITE_4(sc, reg, val) \ 97 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 98 99 #define CSR_READ_4(sc, reg) \ 100 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 101 102 #define BGE_SETBIT(sc, reg, x) \ 103 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x)) 104 #define BGE_CLRBIT(sc, reg, x) \ 105 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x)) 106 107 #define PCI_SETBIT(pc, tag, reg, x) \ 108 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | x)) 109 #define PCI_CLRBIT(pc, tag, reg, x) \ 110 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~x)) 111 112 /* 113 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 114 * values are tuneable. They control the actual amount of buffers 115 * allocated for the standard, mini and jumbo receive rings. 116 */ 117 118 #define BGE_SSLOTS 256 119 #define BGE_MSLOTS 256 120 #define BGE_JSLOTS 384 121 #define BGE_RSLOTS 256 122 123 #define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 124 #define BGE_JLEN (BGE_JRAWLEN + (sizeof(uint64_t) - \ 125 (BGE_JRAWLEN % sizeof(uint64_t)))) 126 #define BGE_JPAGESZ PAGE_SIZE 127 #define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 128 #define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 129 130 /* 131 * Ring structures. Most of these reside in host memory and we tell 132 * the NIC where they are via the ring control blocks. The exceptions 133 * are the tx and command rings, which live in NIC memory and which 134 * we access via the shared memory window. 135 */ 136 struct bge_ring_data { 137 struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 138 struct bge_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 139 struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 140 struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 141 struct bge_status_block bge_status_block; 142 struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 143 struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 144 struct bge_gib bge_info; 145 }; 146 147 #define BGE_RING_DMA_ADDR(sc, offset) \ 148 ((sc)->bge_ring_map->dm_segs[0].ds_addr + \ 149 offsetof(struct bge_ring_data, offset)) 150 151 /* 152 * Number of DMA segments in a TxCB. Note that this is carefully 153 * chosen to make the total struct size an even power of two. It's 154 * critical that no TxCB be split across a page boundary since 155 * no attempt is made to allocate physically contiguous memory. 156 * 157 */ 158 #if 0 /* pre-TSO values */ 159 #define BGE_TXDMA_MAX ETHER_MAX_LEN_JUMBO 160 #ifdef _LP64 161 #define BGE_NTXSEG 30 162 #else 163 #define BGE_NTXSEG 31 164 #endif 165 #else /* TSO values */ 166 #define BGE_TXDMA_MAX (round_page(IP_MAXPACKET)) /* for TSO */ 167 #ifdef _LP64 168 #define BGE_NTXSEG 120 /* XXX just a guess */ 169 #else 170 #define BGE_NTXSEG 124 /* XXX just a guess */ 171 #endif 172 #endif /* TSO values */ 173 174 175 /* 176 * Mbuf pointers. We need these to keep track of the virtual addresses 177 * of our mbuf chains since we can only convert from physical to virtual, 178 * not the other way around. 179 */ 180 struct bge_chain_data { 181 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 182 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 183 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 184 struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 185 bus_dmamap_t bge_rx_std_map[BGE_STD_RX_RING_CNT]; 186 bus_dmamap_t bge_rx_jumbo_map; 187 /* Stick the jumbo mem management stuff here too. */ 188 void * bge_jslots[BGE_JSLOTS]; 189 void * bge_jumbo_buf; 190 }; 191 192 #define BGE_JUMBO_DMA_ADDR(sc, m) \ 193 ((sc)->bge_cdata.bge_rx_jumbo_map->dm_segs[0].ds_addr + \ 194 (mtod((m), char *) - (char *)(sc)->bge_cdata.bge_jumbo_buf)) 195 196 struct bge_type { 197 uint16_t bge_vid; 198 uint16_t bge_did; 199 char *bge_name; 200 }; 201 202 #define BGE_TIMEOUT 100000 203 #define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 204 205 struct bge_jpool_entry { 206 int slot; 207 SLIST_ENTRY(bge_jpool_entry) jpool_entries; 208 }; 209 210 struct bge_bcom_hack { 211 int reg; 212 int val; 213 }; 214 215 struct txdmamap_pool_entry { 216 bus_dmamap_t dmamap; 217 SLIST_ENTRY(txdmamap_pool_entry) link; 218 }; 219 220 #define ASF_ENABLE 1 221 #define ASF_NEW_HANDSHAKE 2 222 #define ASF_STACKUP 4 223 224 struct bge_softc { 225 device_t bge_dev; 226 struct ethercom ethercom; /* interface info */ 227 bus_space_handle_t bge_bhandle; 228 bus_space_tag_t bge_btag; 229 void *bge_intrhand; 230 pci_chipset_tag_t sc_pc; 231 pcitag_t sc_pcitag; 232 233 struct mii_data bge_mii; 234 struct ifmedia bge_ifmedia; /* media info */ 235 uint32_t bge_return_ring_cnt; 236 uint32_t bge_tx_prodidx; 237 bus_dma_tag_t bge_dmatag; 238 uint32_t bge_pcixcap; 239 uint32_t bge_pciecap; 240 uint32_t bge_chipid; 241 uint32_t bge_local_ctrl_reg; 242 uint8_t bge_asf_mode; 243 uint8_t bge_asf_count; 244 struct bge_ring_data *bge_rdata; /* rings */ 245 struct bge_chain_data bge_cdata; /* mbufs */ 246 bus_dmamap_t bge_ring_map; 247 uint16_t bge_tx_saved_considx; 248 uint16_t bge_rx_saved_considx; 249 uint16_t bge_ev_saved_considx; 250 uint16_t bge_std; /* current std ring head */ 251 uint16_t bge_jumbo; /* current jumo ring head */ 252 SLIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead; 253 SLIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead; 254 uint32_t bge_stat_ticks; 255 uint32_t bge_rx_coal_ticks; 256 uint32_t bge_tx_coal_ticks; 257 uint32_t bge_rx_max_coal_bds; 258 uint32_t bge_tx_max_coal_bds; 259 uint32_t bge_tx_buf_ratio; 260 uint32_t bge_sts; 261 #define BGE_STS_LINK 0x00000001 /* MAC link status */ 262 #define BGE_STS_LINK_EVT 0x00000002 /* pending link event */ 263 #define BGE_STS_AUTOPOLL 0x00000004 /* PHY auto-polling */ 264 #define BGE_STS_BIT(sc, x) ((sc)->bge_sts & (x)) 265 #define BGE_STS_SETBIT(sc, x) ((sc)->bge_sts |= (x)) 266 #define BGE_STS_CLRBIT(sc, x) ((sc)->bge_sts &= ~(x)) 267 int bge_if_flags; 268 uint32_t bge_flags; 269 int bge_flowflags; 270 #ifdef BGE_EVENT_COUNTERS 271 /* 272 * Event counters. 273 */ 274 struct evcnt bge_ev_intr; /* interrupts */ 275 struct evcnt bge_ev_tx_xoff; /* send PAUSE(len>0) packets */ 276 struct evcnt bge_ev_tx_xon; /* send PAUSE(len=0) packets */ 277 struct evcnt bge_ev_rx_xoff; /* receive PAUSE(len>0) packets */ 278 struct evcnt bge_ev_rx_xon; /* receive PAUSE(len=0) packets */ 279 struct evcnt bge_ev_rx_macctl; /* receive MAC control packets */ 280 struct evcnt bge_ev_xoffentered;/* XOFF state entered */ 281 #endif /* BGE_EVENT_COUNTERS */ 282 int bge_txcnt; 283 struct callout bge_timeout; 284 char *bge_vpd_prodname; 285 char *bge_vpd_readonly; 286 int bge_pending_rxintr_change; 287 SLIST_HEAD(, txdmamap_pool_entry) txdma_list; 288 struct txdmamap_pool_entry *txdma[BGE_TX_RING_CNT]; 289 290 struct sysctllog *bge_log; 291 292 #if NRND > 0 293 rndsource_element_t rnd_source; /* random source */ 294 #endif 295 }; 296 297 #endif /* _DEV_PCI_IF_BGEVAR_H_ */ 298