1 /* $NetBSD: if_bnx.c,v 1.42 2011/01/26 00:09:27 dyoung Exp $ */ 2 /* $OpenBSD: if_bnx.c,v 1.85 2009/11/09 14:32:41 dlg Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Broadcom Corporation 6 * David Christensen <davidch@broadcom.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 #if 0 36 __FBSDID("$FreeBSD: src/sys/dev/bce/if_bce.c,v 1.3 2006/04/13 14:12:26 ru Exp $"); 37 #endif 38 __KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.42 2011/01/26 00:09:27 dyoung Exp $"); 39 40 /* 41 * The following controllers are supported by this driver: 42 * BCM5706C A2, A3 43 * BCM5706S A2, A3 44 * BCM5708C B1, B2 45 * BCM5708S B1, B2 46 * BCM5709C A1, C0 47 * BCM5709S A1, C0 48 * BCM5716 C0 49 * 50 * The following controllers are not supported by this driver: 51 * 52 * BCM5706C A0, A1 53 * BCM5706S A0, A1 54 * BCM5708C A0, B0 55 * BCM5708S A0, B0 56 * BCM5709C A0 B0, B1, B2 (pre-production) 57 * BCM5709S A0, B0, B1, B2 (pre-production) 58 */ 59 60 #include <sys/callout.h> 61 #include <sys/mutex.h> 62 63 #include <dev/pci/if_bnxreg.h> 64 #include <dev/pci/if_bnxvar.h> 65 66 #include <dev/microcode/bnx/bnxfw.h> 67 68 /****************************************************************************/ 69 /* BNX Driver Version */ 70 /****************************************************************************/ 71 #define BNX_DRIVER_VERSION "v0.9.6" 72 73 /****************************************************************************/ 74 /* BNX Debug Options */ 75 /****************************************************************************/ 76 #ifdef BNX_DEBUG 77 u_int32_t bnx_debug = /*BNX_WARN*/ BNX_VERBOSE_SEND; 78 79 /* 0 = Never */ 80 /* 1 = 1 in 2,147,483,648 */ 81 /* 256 = 1 in 8,388,608 */ 82 /* 2048 = 1 in 1,048,576 */ 83 /* 65536 = 1 in 32,768 */ 84 /* 1048576 = 1 in 2,048 */ 85 /* 268435456 = 1 in 8 */ 86 /* 536870912 = 1 in 4 */ 87 /* 1073741824 = 1 in 2 */ 88 89 /* Controls how often the l2_fhdr frame error check will fail. */ 90 int bnx_debug_l2fhdr_status_check = 0; 91 92 /* Controls how often the unexpected attention check will fail. */ 93 int bnx_debug_unexpected_attention = 0; 94 95 /* Controls how often to simulate an mbuf allocation failure. */ 96 int bnx_debug_mbuf_allocation_failure = 0; 97 98 /* Controls how often to simulate a DMA mapping failure. */ 99 int bnx_debug_dma_map_addr_failure = 0; 100 101 /* Controls how often to simulate a bootcode failure. */ 102 int bnx_debug_bootcode_running_failure = 0; 103 #endif 104 105 /****************************************************************************/ 106 /* PCI Device ID Table */ 107 /* */ 108 /* Used by bnx_probe() to identify the devices supported by this driver. */ 109 /****************************************************************************/ 110 static const struct bnx_product { 111 pci_vendor_id_t bp_vendor; 112 pci_product_id_t bp_product; 113 pci_vendor_id_t bp_subvendor; 114 pci_product_id_t bp_subproduct; 115 const char *bp_name; 116 } bnx_devices[] = { 117 #ifdef PCI_SUBPRODUCT_HP_NC370T 118 { 119 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 120 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370T, 121 "HP NC370T Multifunction Gigabit Server Adapter" 122 }, 123 #endif 124 #ifdef PCI_SUBPRODUCT_HP_NC370i 125 { 126 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 127 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370i, 128 "HP NC370i Multifunction Gigabit Server Adapter" 129 }, 130 #endif 131 { 132 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 133 0, 0, 134 "Broadcom NetXtreme II BCM5706 1000Base-T" 135 }, 136 #ifdef PCI_SUBPRODUCT_HP_NC370F 137 { 138 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 139 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370F, 140 "HP NC370F Multifunction Gigabit Server Adapter" 141 }, 142 #endif 143 { 144 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 145 0, 0, 146 "Broadcom NetXtreme II BCM5706 1000Base-SX" 147 }, 148 { 149 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708, 150 0, 0, 151 "Broadcom NetXtreme II BCM5708 1000Base-T" 152 }, 153 { 154 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708S, 155 0, 0, 156 "Broadcom NetXtreme II BCM5708 1000Base-SX" 157 }, 158 { 159 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709, 160 0, 0, 161 "Broadcom NetXtreme II BCM5709 1000Base-T" 162 }, 163 { 164 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709S, 165 0, 0, 166 "Broadcom NetXtreme II BCM5709 1000Base-SX" 167 }, 168 { 169 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716, 170 0, 0, 171 "Broadcom NetXtreme II BCM5716 1000Base-T" 172 }, 173 { 174 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716S, 175 0, 0, 176 "Broadcom NetXtreme II BCM5716 1000Base-SX" 177 }, 178 }; 179 180 /****************************************************************************/ 181 /* Supported Flash NVRAM device data. */ 182 /****************************************************************************/ 183 static struct flash_spec flash_table[] = 184 { 185 #define BUFFERED_FLAGS (BNX_NV_BUFFERED | BNX_NV_TRANSLATE) 186 #define NONBUFFERED_FLAGS (BNX_NV_WREN) 187 /* Slow EEPROM */ 188 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 189 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 190 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 191 "EEPROM - slow"}, 192 /* Expansion entry 0001 */ 193 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 194 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 195 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 196 "Entry 0001"}, 197 /* Saifun SA25F010 (non-buffered flash) */ 198 /* strap, cfg1, & write1 need updates */ 199 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 200 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 201 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 202 "Non-buffered flash (128kB)"}, 203 /* Saifun SA25F020 (non-buffered flash) */ 204 /* strap, cfg1, & write1 need updates */ 205 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 206 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 207 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 208 "Non-buffered flash (256kB)"}, 209 /* Expansion entry 0100 */ 210 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 211 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 212 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 213 "Entry 0100"}, 214 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 215 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 216 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 217 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 218 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 219 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 220 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 221 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 222 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 223 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 224 /* Saifun SA25F005 (non-buffered flash) */ 225 /* strap, cfg1, & write1 need updates */ 226 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 227 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 228 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 229 "Non-buffered flash (64kB)"}, 230 /* Fast EEPROM */ 231 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 232 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 233 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 234 "EEPROM - fast"}, 235 /* Expansion entry 1001 */ 236 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 237 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 238 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 239 "Entry 1001"}, 240 /* Expansion entry 1010 */ 241 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 242 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 243 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 244 "Entry 1010"}, 245 /* ATMEL AT45DB011B (buffered flash) */ 246 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 247 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 248 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 249 "Buffered flash (128kB)"}, 250 /* Expansion entry 1100 */ 251 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 252 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 253 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 254 "Entry 1100"}, 255 /* Expansion entry 1101 */ 256 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 257 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 258 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 259 "Entry 1101"}, 260 /* Ateml Expansion entry 1110 */ 261 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 262 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 263 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 264 "Entry 1110 (Atmel)"}, 265 /* ATMEL AT45DB021B (buffered flash) */ 266 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 267 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 268 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 269 "Buffered flash (256kB)"}, 270 }; 271 272 /* 273 * The BCM5709 controllers transparently handle the 274 * differences between Atmel 264 byte pages and all 275 * flash devices which use 256 byte pages, so no 276 * logical-to-physical mapping is required in the 277 * driver. 278 */ 279 static struct flash_spec flash_5709 = { 280 .flags = BNX_NV_BUFFERED, 281 .page_bits = BCM5709_FLASH_PAGE_BITS, 282 .page_size = BCM5709_FLASH_PAGE_SIZE, 283 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 284 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 285 .name = "5709 buffered flash (256kB)", 286 }; 287 288 /****************************************************************************/ 289 /* OpenBSD device entry points. */ 290 /****************************************************************************/ 291 static int bnx_probe(device_t, cfdata_t, void *); 292 void bnx_attach(device_t, device_t, void *); 293 int bnx_detach(device_t, int); 294 295 /****************************************************************************/ 296 /* BNX Debug Data Structure Dump Routines */ 297 /****************************************************************************/ 298 #ifdef BNX_DEBUG 299 void bnx_dump_mbuf(struct bnx_softc *, struct mbuf *); 300 void bnx_dump_tx_mbuf_chain(struct bnx_softc *, int, int); 301 void bnx_dump_rx_mbuf_chain(struct bnx_softc *, int, int); 302 void bnx_dump_txbd(struct bnx_softc *, int, struct tx_bd *); 303 void bnx_dump_rxbd(struct bnx_softc *, int, struct rx_bd *); 304 void bnx_dump_l2fhdr(struct bnx_softc *, int, struct l2_fhdr *); 305 void bnx_dump_tx_chain(struct bnx_softc *, int, int); 306 void bnx_dump_rx_chain(struct bnx_softc *, int, int); 307 void bnx_dump_status_block(struct bnx_softc *); 308 void bnx_dump_stats_block(struct bnx_softc *); 309 void bnx_dump_driver_state(struct bnx_softc *); 310 void bnx_dump_hw_state(struct bnx_softc *); 311 void bnx_breakpoint(struct bnx_softc *); 312 #endif 313 314 /****************************************************************************/ 315 /* BNX Register/Memory Access Routines */ 316 /****************************************************************************/ 317 u_int32_t bnx_reg_rd_ind(struct bnx_softc *, u_int32_t); 318 void bnx_reg_wr_ind(struct bnx_softc *, u_int32_t, u_int32_t); 319 void bnx_ctx_wr(struct bnx_softc *, u_int32_t, u_int32_t, u_int32_t); 320 int bnx_miibus_read_reg(device_t, int, int); 321 void bnx_miibus_write_reg(device_t, int, int, int); 322 void bnx_miibus_statchg(device_t); 323 324 /****************************************************************************/ 325 /* BNX NVRAM Access Routines */ 326 /****************************************************************************/ 327 int bnx_acquire_nvram_lock(struct bnx_softc *); 328 int bnx_release_nvram_lock(struct bnx_softc *); 329 void bnx_enable_nvram_access(struct bnx_softc *); 330 void bnx_disable_nvram_access(struct bnx_softc *); 331 int bnx_nvram_read_dword(struct bnx_softc *, u_int32_t, u_int8_t *, 332 u_int32_t); 333 int bnx_init_nvram(struct bnx_softc *); 334 int bnx_nvram_read(struct bnx_softc *, u_int32_t, u_int8_t *, int); 335 int bnx_nvram_test(struct bnx_softc *); 336 #ifdef BNX_NVRAM_WRITE_SUPPORT 337 int bnx_enable_nvram_write(struct bnx_softc *); 338 void bnx_disable_nvram_write(struct bnx_softc *); 339 int bnx_nvram_erase_page(struct bnx_softc *, u_int32_t); 340 int bnx_nvram_write_dword(struct bnx_softc *, u_int32_t, u_int8_t *, 341 u_int32_t); 342 int bnx_nvram_write(struct bnx_softc *, u_int32_t, u_int8_t *, int); 343 #endif 344 345 /****************************************************************************/ 346 /* */ 347 /****************************************************************************/ 348 void bnx_get_media(struct bnx_softc *); 349 void bnx_init_media(struct bnx_softc *); 350 int bnx_dma_alloc(struct bnx_softc *); 351 void bnx_dma_free(struct bnx_softc *); 352 void bnx_release_resources(struct bnx_softc *); 353 354 /****************************************************************************/ 355 /* BNX Firmware Synchronization and Load */ 356 /****************************************************************************/ 357 int bnx_fw_sync(struct bnx_softc *, u_int32_t); 358 void bnx_load_rv2p_fw(struct bnx_softc *, u_int32_t *, u_int32_t, 359 u_int32_t); 360 void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *, 361 struct fw_info *); 362 void bnx_init_cpus(struct bnx_softc *); 363 364 void bnx_stop(struct ifnet *, int); 365 int bnx_reset(struct bnx_softc *, u_int32_t); 366 int bnx_chipinit(struct bnx_softc *); 367 int bnx_blockinit(struct bnx_softc *); 368 static int bnx_add_buf(struct bnx_softc *, struct mbuf *, u_int16_t *, 369 u_int16_t *, u_int32_t *); 370 int bnx_get_buf(struct bnx_softc *, u_int16_t *, u_int16_t *, u_int32_t *); 371 372 int bnx_init_tx_chain(struct bnx_softc *); 373 void bnx_init_tx_context(struct bnx_softc *); 374 int bnx_init_rx_chain(struct bnx_softc *); 375 void bnx_init_rx_context(struct bnx_softc *); 376 void bnx_free_rx_chain(struct bnx_softc *); 377 void bnx_free_tx_chain(struct bnx_softc *); 378 379 int bnx_tx_encap(struct bnx_softc *, struct mbuf *); 380 void bnx_start(struct ifnet *); 381 int bnx_ioctl(struct ifnet *, u_long, void *); 382 void bnx_watchdog(struct ifnet *); 383 int bnx_init(struct ifnet *); 384 385 void bnx_init_context(struct bnx_softc *); 386 void bnx_get_mac_addr(struct bnx_softc *); 387 void bnx_set_mac_addr(struct bnx_softc *); 388 void bnx_phy_intr(struct bnx_softc *); 389 void bnx_rx_intr(struct bnx_softc *); 390 void bnx_tx_intr(struct bnx_softc *); 391 void bnx_disable_intr(struct bnx_softc *); 392 void bnx_enable_intr(struct bnx_softc *); 393 394 int bnx_intr(void *); 395 void bnx_iff(struct bnx_softc *); 396 void bnx_stats_update(struct bnx_softc *); 397 void bnx_tick(void *); 398 399 struct pool *bnx_tx_pool = NULL; 400 int bnx_alloc_pkts(struct bnx_softc *); 401 402 /****************************************************************************/ 403 /* OpenBSD device dispatch table. */ 404 /****************************************************************************/ 405 CFATTACH_DECL3_NEW(bnx, sizeof(struct bnx_softc), 406 bnx_probe, bnx_attach, bnx_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 407 408 /****************************************************************************/ 409 /* Device probe function. */ 410 /* */ 411 /* Compares the device to the driver's list of supported devices and */ 412 /* reports back to the OS whether this is the right driver for the device. */ 413 /* */ 414 /* Returns: */ 415 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 416 /****************************************************************************/ 417 static const struct bnx_product * 418 bnx_lookup(const struct pci_attach_args *pa) 419 { 420 int i; 421 pcireg_t subid; 422 423 for (i = 0; i < __arraycount(bnx_devices); i++) { 424 if (PCI_VENDOR(pa->pa_id) != bnx_devices[i].bp_vendor || 425 PCI_PRODUCT(pa->pa_id) != bnx_devices[i].bp_product) 426 continue; 427 if (!bnx_devices[i].bp_subvendor) 428 return &bnx_devices[i]; 429 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 430 if (PCI_VENDOR(subid) == bnx_devices[i].bp_subvendor && 431 PCI_PRODUCT(subid) == bnx_devices[i].bp_subproduct) 432 return &bnx_devices[i]; 433 } 434 435 return NULL; 436 } 437 static int 438 bnx_probe(device_t parent, cfdata_t match, void *aux) 439 { 440 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 441 442 if (bnx_lookup(pa) != NULL) 443 return (1); 444 445 return (0); 446 } 447 448 /****************************************************************************/ 449 /* Device attach function. */ 450 /* */ 451 /* Allocates device resources, performs secondary chip identification, */ 452 /* resets and initializes the hardware, and initializes driver instance */ 453 /* variables. */ 454 /* */ 455 /* Returns: */ 456 /* 0 on success, positive value on failure. */ 457 /****************************************************************************/ 458 void 459 bnx_attach(device_t parent, device_t self, void *aux) 460 { 461 const struct bnx_product *bp; 462 struct bnx_softc *sc = device_private(self); 463 prop_dictionary_t dict; 464 struct pci_attach_args *pa = aux; 465 pci_chipset_tag_t pc = pa->pa_pc; 466 pci_intr_handle_t ih; 467 const char *intrstr = NULL; 468 u_int32_t command; 469 struct ifnet *ifp; 470 u_int32_t val; 471 int mii_flags = MIIF_FORCEANEG; 472 pcireg_t memtype; 473 474 if (bnx_tx_pool == NULL) { 475 bnx_tx_pool = malloc(sizeof(*bnx_tx_pool), M_DEVBUF, M_NOWAIT); 476 if (bnx_tx_pool != NULL) { 477 pool_init(bnx_tx_pool, sizeof(struct bnx_pkt), 478 0, 0, 0, "bnxpkts", NULL, IPL_NET); 479 } else { 480 aprint_error(": can't alloc bnx_tx_pool\n"); 481 return; 482 } 483 } 484 485 bp = bnx_lookup(pa); 486 if (bp == NULL) 487 panic("unknown device"); 488 489 sc->bnx_dev = self; 490 491 aprint_naive("\n"); 492 aprint_normal(": %s\n", bp->bp_name); 493 494 sc->bnx_pa = *pa; 495 496 /* 497 * Map control/status registers. 498 */ 499 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 500 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 501 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 502 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 503 504 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 505 aprint_error_dev(sc->bnx_dev, 506 "failed to enable memory mapping!\n"); 507 return; 508 } 509 510 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BNX_PCI_BAR0); 511 if (pci_mapreg_map(pa, BNX_PCI_BAR0, memtype, 0, &sc->bnx_btag, 512 &sc->bnx_bhandle, NULL, &sc->bnx_size)) { 513 aprint_error_dev(sc->bnx_dev, "can't find mem space\n"); 514 return; 515 } 516 517 if (pci_intr_map(pa, &ih)) { 518 aprint_error_dev(sc->bnx_dev, "couldn't map interrupt\n"); 519 goto bnx_attach_fail; 520 } 521 522 intrstr = pci_intr_string(pc, ih); 523 524 /* 525 * Configure byte swap and enable indirect register access. 526 * Rely on CPU to do target byte swapping on big endian systems. 527 * Access to registers outside of PCI configurtion space are not 528 * valid until this is done. 529 */ 530 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 531 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 532 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); 533 534 /* Save ASIC revsion info. */ 535 sc->bnx_chipid = REG_RD(sc, BNX_MISC_ID); 536 537 /* 538 * Find the base address for shared memory access. 539 * Newer versions of bootcode use a signature and offset 540 * while older versions use a fixed address. 541 */ 542 val = REG_RD_IND(sc, BNX_SHM_HDR_SIGNATURE); 543 if ((val & BNX_SHM_HDR_SIGNATURE_SIG_MASK) == BNX_SHM_HDR_SIGNATURE_SIG) 544 sc->bnx_shmem_base = REG_RD_IND(sc, BNX_SHM_HDR_ADDR_0 + 545 (sc->bnx_pa.pa_function << 2)); 546 else 547 sc->bnx_shmem_base = HOST_VIEW_SHMEM_BASE; 548 549 DBPRINT(sc, BNX_INFO, "bnx_shmem_base = 0x%08X\n", sc->bnx_shmem_base); 550 551 /* Set initial device and PHY flags */ 552 sc->bnx_flags = 0; 553 sc->bnx_phy_flags = 0; 554 555 /* Get PCI bus information (speed and type). */ 556 val = REG_RD(sc, BNX_PCICFG_MISC_STATUS); 557 if (val & BNX_PCICFG_MISC_STATUS_PCIX_DET) { 558 u_int32_t clkreg; 559 560 sc->bnx_flags |= BNX_PCIX_FLAG; 561 562 clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS); 563 564 clkreg &= BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 565 switch (clkreg) { 566 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 567 sc->bus_speed_mhz = 133; 568 break; 569 570 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 571 sc->bus_speed_mhz = 100; 572 break; 573 574 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 575 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 576 sc->bus_speed_mhz = 66; 577 break; 578 579 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 580 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 581 sc->bus_speed_mhz = 50; 582 break; 583 584 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 585 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 586 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 587 sc->bus_speed_mhz = 33; 588 break; 589 } 590 } else if (val & BNX_PCICFG_MISC_STATUS_M66EN) 591 sc->bus_speed_mhz = 66; 592 else 593 sc->bus_speed_mhz = 33; 594 595 if (val & BNX_PCICFG_MISC_STATUS_32BIT_DET) 596 sc->bnx_flags |= BNX_PCI_32BIT_FLAG; 597 598 /* Reset the controller. */ 599 if (bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) 600 goto bnx_attach_fail; 601 602 /* Initialize the controller. */ 603 if (bnx_chipinit(sc)) { 604 aprint_error_dev(sc->bnx_dev, 605 "Controller initialization failed!\n"); 606 goto bnx_attach_fail; 607 } 608 609 /* Perform NVRAM test. */ 610 if (bnx_nvram_test(sc)) { 611 aprint_error_dev(sc->bnx_dev, "NVRAM test failed!\n"); 612 goto bnx_attach_fail; 613 } 614 615 /* Fetch the permanent Ethernet MAC address. */ 616 bnx_get_mac_addr(sc); 617 aprint_normal_dev(sc->bnx_dev, "Ethernet address %s\n", 618 ether_sprintf(sc->eaddr)); 619 620 /* 621 * Trip points control how many BDs 622 * should be ready before generating an 623 * interrupt while ticks control how long 624 * a BD can sit in the chain before 625 * generating an interrupt. Set the default 626 * values for the RX and TX rings. 627 */ 628 629 #ifdef BNX_DEBUG 630 /* Force more frequent interrupts. */ 631 sc->bnx_tx_quick_cons_trip_int = 1; 632 sc->bnx_tx_quick_cons_trip = 1; 633 sc->bnx_tx_ticks_int = 0; 634 sc->bnx_tx_ticks = 0; 635 636 sc->bnx_rx_quick_cons_trip_int = 1; 637 sc->bnx_rx_quick_cons_trip = 1; 638 sc->bnx_rx_ticks_int = 0; 639 sc->bnx_rx_ticks = 0; 640 #else 641 sc->bnx_tx_quick_cons_trip_int = 20; 642 sc->bnx_tx_quick_cons_trip = 20; 643 sc->bnx_tx_ticks_int = 80; 644 sc->bnx_tx_ticks = 80; 645 646 sc->bnx_rx_quick_cons_trip_int = 6; 647 sc->bnx_rx_quick_cons_trip = 6; 648 sc->bnx_rx_ticks_int = 18; 649 sc->bnx_rx_ticks = 18; 650 #endif 651 652 /* Update statistics once every second. */ 653 sc->bnx_stats_ticks = 1000000 & 0xffff00; 654 655 /* Find the media type for the adapter. */ 656 bnx_get_media(sc); 657 658 /* 659 * Store config data needed by the PHY driver for 660 * backplane applications 661 */ 662 sc->bnx_shared_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 663 BNX_SHARED_HW_CFG_CONFIG); 664 sc->bnx_port_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 665 BNX_PORT_HW_CFG_CONFIG); 666 667 /* Allocate DMA memory resources. */ 668 sc->bnx_dmatag = pa->pa_dmat; 669 if (bnx_dma_alloc(sc)) { 670 aprint_error_dev(sc->bnx_dev, 671 "DMA resource allocation failed!\n"); 672 goto bnx_attach_fail; 673 } 674 675 /* Initialize the ifnet interface. */ 676 ifp = &sc->bnx_ec.ec_if; 677 ifp->if_softc = sc; 678 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 679 ifp->if_ioctl = bnx_ioctl; 680 ifp->if_stop = bnx_stop; 681 ifp->if_start = bnx_start; 682 ifp->if_init = bnx_init; 683 ifp->if_timer = 0; 684 ifp->if_watchdog = bnx_watchdog; 685 IFQ_SET_MAXLEN(&ifp->if_snd, USABLE_TX_BD - 1); 686 IFQ_SET_READY(&ifp->if_snd); 687 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 688 689 sc->bnx_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU | 690 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 691 692 ifp->if_capabilities |= 693 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 694 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 695 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 696 697 /* Hookup IRQ last. */ 698 sc->bnx_intrhand = pci_intr_establish(pc, ih, IPL_NET, bnx_intr, sc); 699 if (sc->bnx_intrhand == NULL) { 700 aprint_error_dev(self, "couldn't establish interrupt"); 701 if (intrstr != NULL) 702 aprint_error(" at %s", intrstr); 703 aprint_error("\n"); 704 goto bnx_attach_fail; 705 } 706 aprint_normal_dev(sc->bnx_dev, "interrupting at %s\n", intrstr); 707 708 sc->bnx_mii.mii_ifp = ifp; 709 sc->bnx_mii.mii_readreg = bnx_miibus_read_reg; 710 sc->bnx_mii.mii_writereg = bnx_miibus_write_reg; 711 sc->bnx_mii.mii_statchg = bnx_miibus_statchg; 712 713 /* Handle any special PHY initialization for SerDes PHYs. */ 714 bnx_init_media(sc); 715 716 sc->bnx_ec.ec_mii = &sc->bnx_mii; 717 ifmedia_init(&sc->bnx_mii.mii_media, 0, ether_mediachange, 718 ether_mediastatus); 719 720 /* set phyflags before mii_attach() */ 721 dict = device_properties(self); 722 prop_dictionary_set_uint32(dict, "phyflags", sc->bnx_phy_flags); 723 724 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) 725 mii_flags |= MIIF_HAVEFIBER; 726 mii_attach(self, &sc->bnx_mii, 0xffffffff, 727 MII_PHY_ANY, MII_OFFSET_ANY, mii_flags); 728 729 if (LIST_EMPTY(&sc->bnx_mii.mii_phys)) { 730 aprint_error_dev(self, "no PHY found!\n"); 731 ifmedia_add(&sc->bnx_mii.mii_media, 732 IFM_ETHER|IFM_MANUAL, 0, NULL); 733 ifmedia_set(&sc->bnx_mii.mii_media, 734 IFM_ETHER|IFM_MANUAL); 735 } else { 736 ifmedia_set(&sc->bnx_mii.mii_media, 737 IFM_ETHER|IFM_AUTO); 738 } 739 740 /* Attach to the Ethernet interface list. */ 741 if_attach(ifp); 742 ether_ifattach(ifp,sc->eaddr); 743 744 callout_init(&sc->bnx_timeout, 0); 745 746 if (pmf_device_register(self, NULL, NULL)) 747 pmf_class_network_register(self, ifp); 748 else 749 aprint_error_dev(self, "couldn't establish power handler\n"); 750 751 /* Print some important debugging info. */ 752 DBRUN(BNX_INFO, bnx_dump_driver_state(sc)); 753 754 goto bnx_attach_exit; 755 756 bnx_attach_fail: 757 bnx_release_resources(sc); 758 759 bnx_attach_exit: 760 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 761 } 762 763 /****************************************************************************/ 764 /* Device detach function. */ 765 /* */ 766 /* Stops the controller, resets the controller, and releases resources. */ 767 /* */ 768 /* Returns: */ 769 /* 0 on success, positive value on failure. */ 770 /****************************************************************************/ 771 int 772 bnx_detach(device_t dev, int flags) 773 { 774 int s; 775 struct bnx_softc *sc; 776 struct ifnet *ifp; 777 778 sc = device_private(dev); 779 ifp = &sc->bnx_ec.ec_if; 780 781 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 782 783 /* Stop and reset the controller. */ 784 s = splnet(); 785 if (ifp->if_flags & IFF_RUNNING) 786 bnx_stop(ifp, 1); 787 else { 788 /* Disable the transmit/receive blocks. */ 789 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 790 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 791 DELAY(20); 792 bnx_disable_intr(sc); 793 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 794 } 795 796 splx(s); 797 798 pmf_device_deregister(dev); 799 callout_destroy(&sc->bnx_timeout); 800 ether_ifdetach(ifp); 801 802 /* Delete all remaining media. */ 803 ifmedia_delete_instance(&sc->bnx_mii.mii_media, IFM_INST_ANY); 804 805 if_detach(ifp); 806 mii_detach(&sc->bnx_mii, MII_PHY_ANY, MII_OFFSET_ANY); 807 808 /* Release all remaining resources. */ 809 bnx_release_resources(sc); 810 811 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 812 813 return(0); 814 } 815 816 /****************************************************************************/ 817 /* Indirect register read. */ 818 /* */ 819 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 820 /* configuration space. Using this mechanism avoids issues with posted */ 821 /* reads but is much slower than memory-mapped I/O. */ 822 /* */ 823 /* Returns: */ 824 /* The value of the register. */ 825 /****************************************************************************/ 826 u_int32_t 827 bnx_reg_rd_ind(struct bnx_softc *sc, u_int32_t offset) 828 { 829 struct pci_attach_args *pa = &(sc->bnx_pa); 830 831 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 832 offset); 833 #ifdef BNX_DEBUG 834 { 835 u_int32_t val; 836 val = pci_conf_read(pa->pa_pc, pa->pa_tag, 837 BNX_PCICFG_REG_WINDOW); 838 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, " 839 "val = 0x%08X\n", __func__, offset, val); 840 return (val); 841 } 842 #else 843 return pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW); 844 #endif 845 } 846 847 /****************************************************************************/ 848 /* Indirect register write. */ 849 /* */ 850 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 851 /* configuration space. Using this mechanism avoids issues with posted */ 852 /* writes but is muchh slower than memory-mapped I/O. */ 853 /* */ 854 /* Returns: */ 855 /* Nothing. */ 856 /****************************************************************************/ 857 void 858 bnx_reg_wr_ind(struct bnx_softc *sc, u_int32_t offset, u_int32_t val) 859 { 860 struct pci_attach_args *pa = &(sc->bnx_pa); 861 862 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 863 __func__, offset, val); 864 865 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 866 offset); 867 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW, val); 868 } 869 870 /****************************************************************************/ 871 /* Context memory write. */ 872 /* */ 873 /* The NetXtreme II controller uses context memory to track connection */ 874 /* information for L2 and higher network protocols. */ 875 /* */ 876 /* Returns: */ 877 /* Nothing. */ 878 /****************************************************************************/ 879 void 880 bnx_ctx_wr(struct bnx_softc *sc, u_int32_t cid_addr, u_int32_t ctx_offset, 881 u_int32_t ctx_val) 882 { 883 u_int32_t idx, offset = ctx_offset + cid_addr; 884 u_int32_t val, retry_cnt = 5; 885 886 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 887 REG_WR(sc, BNX_CTX_CTX_DATA, ctx_val); 888 REG_WR(sc, BNX_CTX_CTX_CTRL, 889 (offset | BNX_CTX_CTX_CTRL_WRITE_REQ)); 890 891 for (idx = 0; idx < retry_cnt; idx++) { 892 val = REG_RD(sc, BNX_CTX_CTX_CTRL); 893 if ((val & BNX_CTX_CTX_CTRL_WRITE_REQ) == 0) 894 break; 895 DELAY(5); 896 } 897 898 #if 0 899 if (val & BNX_CTX_CTX_CTRL_WRITE_REQ) 900 BNX_PRINTF("%s(%d); Unable to write CTX memory: " 901 "cid_addr = 0x%08X, offset = 0x%08X!\n", 902 __FILE__, __LINE__, cid_addr, ctx_offset); 903 #endif 904 905 } else { 906 REG_WR(sc, BNX_CTX_DATA_ADR, offset); 907 REG_WR(sc, BNX_CTX_DATA, ctx_val); 908 } 909 } 910 911 /****************************************************************************/ 912 /* PHY register read. */ 913 /* */ 914 /* Implements register reads on the MII bus. */ 915 /* */ 916 /* Returns: */ 917 /* The value of the register. */ 918 /****************************************************************************/ 919 int 920 bnx_miibus_read_reg(device_t dev, int phy, int reg) 921 { 922 struct bnx_softc *sc = device_private(dev); 923 u_int32_t val; 924 int i; 925 926 /* Make sure we are accessing the correct PHY address. */ 927 if (phy != sc->bnx_phy_addr) { 928 DBPRINT(sc, BNX_VERBOSE, 929 "Invalid PHY address %d for PHY read!\n", phy); 930 return(0); 931 } 932 933 /* 934 * The BCM5709S PHY is an IEEE Clause 45 PHY 935 * with special mappings to work with IEEE 936 * Clause 22 register accesses. 937 */ 938 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 939 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 940 reg += 0x10; 941 } 942 943 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 944 val = REG_RD(sc, BNX_EMAC_MDIO_MODE); 945 val &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 946 947 REG_WR(sc, BNX_EMAC_MDIO_MODE, val); 948 REG_RD(sc, BNX_EMAC_MDIO_MODE); 949 950 DELAY(40); 951 } 952 953 val = BNX_MIPHY(phy) | BNX_MIREG(reg) | 954 BNX_EMAC_MDIO_COMM_COMMAND_READ | BNX_EMAC_MDIO_COMM_DISEXT | 955 BNX_EMAC_MDIO_COMM_START_BUSY; 956 REG_WR(sc, BNX_EMAC_MDIO_COMM, val); 957 958 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 959 DELAY(10); 960 961 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 962 if (!(val & BNX_EMAC_MDIO_COMM_START_BUSY)) { 963 DELAY(5); 964 965 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 966 val &= BNX_EMAC_MDIO_COMM_DATA; 967 968 break; 969 } 970 } 971 972 if (val & BNX_EMAC_MDIO_COMM_START_BUSY) { 973 BNX_PRINTF(sc, "%s(%d): Error: PHY read timeout! phy = %d, " 974 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 975 val = 0x0; 976 } else 977 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 978 979 DBPRINT(sc, BNX_EXCESSIVE, 980 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", __func__, phy, 981 (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff); 982 983 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 984 val = REG_RD(sc, BNX_EMAC_MDIO_MODE); 985 val |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 986 987 REG_WR(sc, BNX_EMAC_MDIO_MODE, val); 988 REG_RD(sc, BNX_EMAC_MDIO_MODE); 989 990 DELAY(40); 991 } 992 993 return (val & 0xffff); 994 } 995 996 /****************************************************************************/ 997 /* PHY register write. */ 998 /* */ 999 /* Implements register writes on the MII bus. */ 1000 /* */ 1001 /* Returns: */ 1002 /* The value of the register. */ 1003 /****************************************************************************/ 1004 void 1005 bnx_miibus_write_reg(device_t dev, int phy, int reg, int val) 1006 { 1007 struct bnx_softc *sc = device_private(dev); 1008 u_int32_t val1; 1009 int i; 1010 1011 /* Make sure we are accessing the correct PHY address. */ 1012 if (phy != sc->bnx_phy_addr) { 1013 DBPRINT(sc, BNX_WARN, "Invalid PHY address %d for PHY write!\n", 1014 phy); 1015 return; 1016 } 1017 1018 DBPRINT(sc, BNX_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, " 1019 "val = 0x%04X\n", __func__, 1020 phy, (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff); 1021 1022 /* 1023 * The BCM5709S PHY is an IEEE Clause 45 PHY 1024 * with special mappings to work with IEEE 1025 * Clause 22 register accesses. 1026 */ 1027 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1028 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1029 reg += 0x10; 1030 } 1031 1032 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1033 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1034 val1 &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 1035 1036 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1037 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1038 1039 DELAY(40); 1040 } 1041 1042 val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val | 1043 BNX_EMAC_MDIO_COMM_COMMAND_WRITE | 1044 BNX_EMAC_MDIO_COMM_START_BUSY | BNX_EMAC_MDIO_COMM_DISEXT; 1045 REG_WR(sc, BNX_EMAC_MDIO_COMM, val1); 1046 1047 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 1048 DELAY(10); 1049 1050 val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1051 if (!(val1 & BNX_EMAC_MDIO_COMM_START_BUSY)) { 1052 DELAY(5); 1053 break; 1054 } 1055 } 1056 1057 if (val1 & BNX_EMAC_MDIO_COMM_START_BUSY) { 1058 BNX_PRINTF(sc, "%s(%d): PHY write timeout!\n", __FILE__, 1059 __LINE__); 1060 } 1061 1062 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1063 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1064 val1 |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 1065 1066 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1067 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1068 1069 DELAY(40); 1070 } 1071 } 1072 1073 /****************************************************************************/ 1074 /* MII bus status change. */ 1075 /* */ 1076 /* Called by the MII bus driver when the PHY establishes link to set the */ 1077 /* MAC interface registers. */ 1078 /* */ 1079 /* Returns: */ 1080 /* Nothing. */ 1081 /****************************************************************************/ 1082 void 1083 bnx_miibus_statchg(device_t dev) 1084 { 1085 struct bnx_softc *sc = device_private(dev); 1086 struct mii_data *mii = &sc->bnx_mii; 1087 int val; 1088 1089 val = REG_RD(sc, BNX_EMAC_MODE); 1090 val &= ~(BNX_EMAC_MODE_PORT | BNX_EMAC_MODE_HALF_DUPLEX | 1091 BNX_EMAC_MODE_MAC_LOOP | BNX_EMAC_MODE_FORCE_LINK | 1092 BNX_EMAC_MODE_25G); 1093 1094 /* Set MII or GMII interface based on the speed 1095 * negotiated by the PHY. 1096 */ 1097 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1098 case IFM_10_T: 1099 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 1100 DBPRINT(sc, BNX_INFO, "Enabling 10Mb interface.\n"); 1101 val |= BNX_EMAC_MODE_PORT_MII_10; 1102 break; 1103 } 1104 /* FALLTHROUGH */ 1105 case IFM_100_TX: 1106 DBPRINT(sc, BNX_INFO, "Enabling MII interface.\n"); 1107 val |= BNX_EMAC_MODE_PORT_MII; 1108 break; 1109 case IFM_2500_SX: 1110 DBPRINT(sc, BNX_INFO, "Enabling 2.5G MAC mode.\n"); 1111 val |= BNX_EMAC_MODE_25G; 1112 /* FALLTHROUGH */ 1113 case IFM_1000_T: 1114 case IFM_1000_SX: 1115 DBPRINT(sc, BNX_INFO, "Enabling GMII interface.\n"); 1116 val |= BNX_EMAC_MODE_PORT_GMII; 1117 break; 1118 default: 1119 val |= BNX_EMAC_MODE_PORT_GMII; 1120 break; 1121 } 1122 1123 /* Set half or full duplex based on the duplicity 1124 * negotiated by the PHY. 1125 */ 1126 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 1127 DBPRINT(sc, BNX_INFO, "Setting Half-Duplex interface.\n"); 1128 val |= BNX_EMAC_MODE_HALF_DUPLEX; 1129 } else { 1130 DBPRINT(sc, BNX_INFO, "Setting Full-Duplex interface.\n"); 1131 } 1132 1133 REG_WR(sc, BNX_EMAC_MODE, val); 1134 } 1135 1136 /****************************************************************************/ 1137 /* Acquire NVRAM lock. */ 1138 /* */ 1139 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1140 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1141 /* for use by the driver. */ 1142 /* */ 1143 /* Returns: */ 1144 /* 0 on success, positive value on failure. */ 1145 /****************************************************************************/ 1146 int 1147 bnx_acquire_nvram_lock(struct bnx_softc *sc) 1148 { 1149 u_int32_t val; 1150 int j; 1151 1152 DBPRINT(sc, BNX_VERBOSE, "Acquiring NVRAM lock.\n"); 1153 1154 /* Request access to the flash interface. */ 1155 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2); 1156 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1157 val = REG_RD(sc, BNX_NVM_SW_ARB); 1158 if (val & BNX_NVM_SW_ARB_ARB_ARB2) 1159 break; 1160 1161 DELAY(5); 1162 } 1163 1164 if (j >= NVRAM_TIMEOUT_COUNT) { 1165 DBPRINT(sc, BNX_WARN, "Timeout acquiring NVRAM lock!\n"); 1166 return (EBUSY); 1167 } 1168 1169 return (0); 1170 } 1171 1172 /****************************************************************************/ 1173 /* Release NVRAM lock. */ 1174 /* */ 1175 /* When the caller is finished accessing NVRAM the lock must be released. */ 1176 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1177 /* for use by the driver. */ 1178 /* */ 1179 /* Returns: */ 1180 /* 0 on success, positive value on failure. */ 1181 /****************************************************************************/ 1182 int 1183 bnx_release_nvram_lock(struct bnx_softc *sc) 1184 { 1185 int j; 1186 u_int32_t val; 1187 1188 DBPRINT(sc, BNX_VERBOSE, "Releasing NVRAM lock.\n"); 1189 1190 /* Relinquish nvram interface. */ 1191 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2); 1192 1193 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1194 val = REG_RD(sc, BNX_NVM_SW_ARB); 1195 if (!(val & BNX_NVM_SW_ARB_ARB_ARB2)) 1196 break; 1197 1198 DELAY(5); 1199 } 1200 1201 if (j >= NVRAM_TIMEOUT_COUNT) { 1202 DBPRINT(sc, BNX_WARN, "Timeout reeasing NVRAM lock!\n"); 1203 return (EBUSY); 1204 } 1205 1206 return (0); 1207 } 1208 1209 #ifdef BNX_NVRAM_WRITE_SUPPORT 1210 /****************************************************************************/ 1211 /* Enable NVRAM write access. */ 1212 /* */ 1213 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1214 /* */ 1215 /* Returns: */ 1216 /* 0 on success, positive value on failure. */ 1217 /****************************************************************************/ 1218 int 1219 bnx_enable_nvram_write(struct bnx_softc *sc) 1220 { 1221 u_int32_t val; 1222 1223 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM write.\n"); 1224 1225 val = REG_RD(sc, BNX_MISC_CFG); 1226 REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI); 1227 1228 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1229 int j; 1230 1231 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1232 REG_WR(sc, BNX_NVM_COMMAND, 1233 BNX_NVM_COMMAND_WREN | BNX_NVM_COMMAND_DOIT); 1234 1235 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1236 DELAY(5); 1237 1238 val = REG_RD(sc, BNX_NVM_COMMAND); 1239 if (val & BNX_NVM_COMMAND_DONE) 1240 break; 1241 } 1242 1243 if (j >= NVRAM_TIMEOUT_COUNT) { 1244 DBPRINT(sc, BNX_WARN, "Timeout writing NVRAM!\n"); 1245 return (EBUSY); 1246 } 1247 } 1248 1249 return (0); 1250 } 1251 1252 /****************************************************************************/ 1253 /* Disable NVRAM write access. */ 1254 /* */ 1255 /* When the caller is finished writing to NVRAM write access must be */ 1256 /* disabled. */ 1257 /* */ 1258 /* Returns: */ 1259 /* Nothing. */ 1260 /****************************************************************************/ 1261 void 1262 bnx_disable_nvram_write(struct bnx_softc *sc) 1263 { 1264 u_int32_t val; 1265 1266 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM write.\n"); 1267 1268 val = REG_RD(sc, BNX_MISC_CFG); 1269 REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN); 1270 } 1271 #endif 1272 1273 /****************************************************************************/ 1274 /* Enable NVRAM access. */ 1275 /* */ 1276 /* Before accessing NVRAM for read or write operations the caller must */ 1277 /* enabled NVRAM access. */ 1278 /* */ 1279 /* Returns: */ 1280 /* Nothing. */ 1281 /****************************************************************************/ 1282 void 1283 bnx_enable_nvram_access(struct bnx_softc *sc) 1284 { 1285 u_int32_t val; 1286 1287 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM access.\n"); 1288 1289 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1290 /* Enable both bits, even on read. */ 1291 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1292 val | BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN); 1293 } 1294 1295 /****************************************************************************/ 1296 /* Disable NVRAM access. */ 1297 /* */ 1298 /* When the caller is finished accessing NVRAM access must be disabled. */ 1299 /* */ 1300 /* Returns: */ 1301 /* Nothing. */ 1302 /****************************************************************************/ 1303 void 1304 bnx_disable_nvram_access(struct bnx_softc *sc) 1305 { 1306 u_int32_t val; 1307 1308 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM access.\n"); 1309 1310 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1311 1312 /* Disable both bits, even after read. */ 1313 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1314 val & ~(BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN)); 1315 } 1316 1317 #ifdef BNX_NVRAM_WRITE_SUPPORT 1318 /****************************************************************************/ 1319 /* Erase NVRAM page before writing. */ 1320 /* */ 1321 /* Non-buffered flash parts require that a page be erased before it is */ 1322 /* written. */ 1323 /* */ 1324 /* Returns: */ 1325 /* 0 on success, positive value on failure. */ 1326 /****************************************************************************/ 1327 int 1328 bnx_nvram_erase_page(struct bnx_softc *sc, u_int32_t offset) 1329 { 1330 u_int32_t cmd; 1331 int j; 1332 1333 /* Buffered flash doesn't require an erase. */ 1334 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) 1335 return (0); 1336 1337 DBPRINT(sc, BNX_VERBOSE, "Erasing NVRAM page.\n"); 1338 1339 /* Build an erase command. */ 1340 cmd = BNX_NVM_COMMAND_ERASE | BNX_NVM_COMMAND_WR | 1341 BNX_NVM_COMMAND_DOIT; 1342 1343 /* 1344 * Clear the DONE bit separately, set the NVRAM adress to erase, 1345 * and issue the erase command. 1346 */ 1347 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1348 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1349 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1350 1351 /* Wait for completion. */ 1352 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1353 u_int32_t val; 1354 1355 DELAY(5); 1356 1357 val = REG_RD(sc, BNX_NVM_COMMAND); 1358 if (val & BNX_NVM_COMMAND_DONE) 1359 break; 1360 } 1361 1362 if (j >= NVRAM_TIMEOUT_COUNT) { 1363 DBPRINT(sc, BNX_WARN, "Timeout erasing NVRAM.\n"); 1364 return (EBUSY); 1365 } 1366 1367 return (0); 1368 } 1369 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1370 1371 /****************************************************************************/ 1372 /* Read a dword (32 bits) from NVRAM. */ 1373 /* */ 1374 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1375 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1376 /* */ 1377 /* Returns: */ 1378 /* 0 on success and the 32 bit value read, positive value on failure. */ 1379 /****************************************************************************/ 1380 int 1381 bnx_nvram_read_dword(struct bnx_softc *sc, u_int32_t offset, 1382 u_int8_t *ret_val, u_int32_t cmd_flags) 1383 { 1384 u_int32_t cmd; 1385 int i, rc = 0; 1386 1387 /* Build the command word. */ 1388 cmd = BNX_NVM_COMMAND_DOIT | cmd_flags; 1389 1390 /* Calculate the offset for buffered flash if translation is used. */ 1391 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1392 offset = ((offset / sc->bnx_flash_info->page_size) << 1393 sc->bnx_flash_info->page_bits) + 1394 (offset % sc->bnx_flash_info->page_size); 1395 } 1396 1397 /* 1398 * Clear the DONE bit separately, set the address to read, 1399 * and issue the read. 1400 */ 1401 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1402 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1403 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1404 1405 /* Wait for completion. */ 1406 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1407 u_int32_t val; 1408 1409 DELAY(5); 1410 1411 val = REG_RD(sc, BNX_NVM_COMMAND); 1412 if (val & BNX_NVM_COMMAND_DONE) { 1413 val = REG_RD(sc, BNX_NVM_READ); 1414 1415 val = bnx_be32toh(val); 1416 memcpy(ret_val, &val, 4); 1417 break; 1418 } 1419 } 1420 1421 /* Check for errors. */ 1422 if (i >= NVRAM_TIMEOUT_COUNT) { 1423 BNX_PRINTF(sc, "%s(%d): Timeout error reading NVRAM at " 1424 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 1425 rc = EBUSY; 1426 } 1427 1428 return(rc); 1429 } 1430 1431 #ifdef BNX_NVRAM_WRITE_SUPPORT 1432 /****************************************************************************/ 1433 /* Write a dword (32 bits) to NVRAM. */ 1434 /* */ 1435 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1436 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1437 /* enabled NVRAM write access. */ 1438 /* */ 1439 /* Returns: */ 1440 /* 0 on success, positive value on failure. */ 1441 /****************************************************************************/ 1442 int 1443 bnx_nvram_write_dword(struct bnx_softc *sc, u_int32_t offset, u_int8_t *val, 1444 u_int32_t cmd_flags) 1445 { 1446 u_int32_t cmd, val32; 1447 int j; 1448 1449 /* Build the command word. */ 1450 cmd = BNX_NVM_COMMAND_DOIT | BNX_NVM_COMMAND_WR | cmd_flags; 1451 1452 /* Calculate the offset for buffered flash if translation is used. */ 1453 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1454 offset = ((offset / sc->bnx_flash_info->page_size) << 1455 sc->bnx_flash_info->page_bits) + 1456 (offset % sc->bnx_flash_info->page_size); 1457 } 1458 1459 /* 1460 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1461 * set the NVRAM address to write, and issue the write command 1462 */ 1463 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1464 memcpy(&val32, val, 4); 1465 val32 = htobe32(val32); 1466 REG_WR(sc, BNX_NVM_WRITE, val32); 1467 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1468 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1469 1470 /* Wait for completion. */ 1471 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1472 DELAY(5); 1473 1474 if (REG_RD(sc, BNX_NVM_COMMAND) & BNX_NVM_COMMAND_DONE) 1475 break; 1476 } 1477 if (j >= NVRAM_TIMEOUT_COUNT) { 1478 BNX_PRINTF(sc, "%s(%d): Timeout error writing NVRAM at " 1479 "offset 0x%08X\n", __FILE__, __LINE__, offset); 1480 return (EBUSY); 1481 } 1482 1483 return (0); 1484 } 1485 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1486 1487 /****************************************************************************/ 1488 /* Initialize NVRAM access. */ 1489 /* */ 1490 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1491 /* access that device. */ 1492 /* */ 1493 /* Returns: */ 1494 /* 0 on success, positive value on failure. */ 1495 /****************************************************************************/ 1496 int 1497 bnx_init_nvram(struct bnx_softc *sc) 1498 { 1499 u_int32_t val; 1500 int j, entry_count, rc = 0; 1501 struct flash_spec *flash; 1502 1503 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 1504 1505 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1506 sc->bnx_flash_info = &flash_5709; 1507 goto bnx_init_nvram_get_flash_size; 1508 } 1509 1510 /* Determine the selected interface. */ 1511 val = REG_RD(sc, BNX_NVM_CFG1); 1512 1513 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1514 1515 /* 1516 * Flash reconfiguration is required to support additional 1517 * NVRAM devices not directly supported in hardware. 1518 * Check if the flash interface was reconfigured 1519 * by the bootcode. 1520 */ 1521 1522 if (val & 0x40000000) { 1523 /* Flash interface reconfigured by bootcode. */ 1524 1525 DBPRINT(sc,BNX_INFO_LOAD, 1526 "bnx_init_nvram(): Flash WAS reconfigured.\n"); 1527 1528 for (j = 0, flash = &flash_table[0]; j < entry_count; 1529 j++, flash++) { 1530 if ((val & FLASH_BACKUP_STRAP_MASK) == 1531 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 1532 sc->bnx_flash_info = flash; 1533 break; 1534 } 1535 } 1536 } else { 1537 /* Flash interface not yet reconfigured. */ 1538 u_int32_t mask; 1539 1540 DBPRINT(sc,BNX_INFO_LOAD, 1541 "bnx_init_nvram(): Flash was NOT reconfigured.\n"); 1542 1543 if (val & (1 << 23)) 1544 mask = FLASH_BACKUP_STRAP_MASK; 1545 else 1546 mask = FLASH_STRAP_MASK; 1547 1548 /* Look for the matching NVRAM device configuration data. */ 1549 for (j = 0, flash = &flash_table[0]; j < entry_count; 1550 j++, flash++) { 1551 /* Check if the dev matches any of the known devices. */ 1552 if ((val & mask) == (flash->strapping & mask)) { 1553 /* Found a device match. */ 1554 sc->bnx_flash_info = flash; 1555 1556 /* Request access to the flash interface. */ 1557 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1558 return (rc); 1559 1560 /* Reconfigure the flash interface. */ 1561 bnx_enable_nvram_access(sc); 1562 REG_WR(sc, BNX_NVM_CFG1, flash->config1); 1563 REG_WR(sc, BNX_NVM_CFG2, flash->config2); 1564 REG_WR(sc, BNX_NVM_CFG3, flash->config3); 1565 REG_WR(sc, BNX_NVM_WRITE1, flash->write1); 1566 bnx_disable_nvram_access(sc); 1567 bnx_release_nvram_lock(sc); 1568 1569 break; 1570 } 1571 } 1572 } 1573 1574 /* Check if a matching device was found. */ 1575 if (j == entry_count) { 1576 sc->bnx_flash_info = NULL; 1577 BNX_PRINTF(sc, "%s(%d): Unknown Flash NVRAM found!\n", 1578 __FILE__, __LINE__); 1579 rc = ENODEV; 1580 } 1581 1582 bnx_init_nvram_get_flash_size: 1583 /* Write the flash config data to the shared memory interface. */ 1584 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2); 1585 val &= BNX_SHARED_HW_CFG2_NVM_SIZE_MASK; 1586 if (val) 1587 sc->bnx_flash_size = val; 1588 else 1589 sc->bnx_flash_size = sc->bnx_flash_info->total_size; 1590 1591 DBPRINT(sc, BNX_INFO_LOAD, "bnx_init_nvram() flash->total_size = " 1592 "0x%08X\n", sc->bnx_flash_info->total_size); 1593 1594 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 1595 1596 return (rc); 1597 } 1598 1599 /****************************************************************************/ 1600 /* Read an arbitrary range of data from NVRAM. */ 1601 /* */ 1602 /* Prepares the NVRAM interface for access and reads the requested data */ 1603 /* into the supplied buffer. */ 1604 /* */ 1605 /* Returns: */ 1606 /* 0 on success and the data read, positive value on failure. */ 1607 /****************************************************************************/ 1608 int 1609 bnx_nvram_read(struct bnx_softc *sc, u_int32_t offset, u_int8_t *ret_buf, 1610 int buf_size) 1611 { 1612 int rc = 0; 1613 u_int32_t cmd_flags, offset32, len32, extra; 1614 1615 if (buf_size == 0) 1616 return (0); 1617 1618 /* Request access to the flash interface. */ 1619 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1620 return (rc); 1621 1622 /* Enable access to flash interface */ 1623 bnx_enable_nvram_access(sc); 1624 1625 len32 = buf_size; 1626 offset32 = offset; 1627 extra = 0; 1628 1629 cmd_flags = 0; 1630 1631 if (offset32 & 3) { 1632 u_int8_t buf[4]; 1633 u_int32_t pre_len; 1634 1635 offset32 &= ~3; 1636 pre_len = 4 - (offset & 3); 1637 1638 if (pre_len >= len32) { 1639 pre_len = len32; 1640 cmd_flags = 1641 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1642 } else 1643 cmd_flags = BNX_NVM_COMMAND_FIRST; 1644 1645 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1646 1647 if (rc) 1648 return (rc); 1649 1650 memcpy(ret_buf, buf + (offset & 3), pre_len); 1651 1652 offset32 += 4; 1653 ret_buf += pre_len; 1654 len32 -= pre_len; 1655 } 1656 1657 if (len32 & 3) { 1658 extra = 4 - (len32 & 3); 1659 len32 = (len32 + 4) & ~3; 1660 } 1661 1662 if (len32 == 4) { 1663 u_int8_t buf[4]; 1664 1665 if (cmd_flags) 1666 cmd_flags = BNX_NVM_COMMAND_LAST; 1667 else 1668 cmd_flags = 1669 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1670 1671 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1672 1673 memcpy(ret_buf, buf, 4 - extra); 1674 } else if (len32 > 0) { 1675 u_int8_t buf[4]; 1676 1677 /* Read the first word. */ 1678 if (cmd_flags) 1679 cmd_flags = 0; 1680 else 1681 cmd_flags = BNX_NVM_COMMAND_FIRST; 1682 1683 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 1684 1685 /* Advance to the next dword. */ 1686 offset32 += 4; 1687 ret_buf += 4; 1688 len32 -= 4; 1689 1690 while (len32 > 4 && rc == 0) { 1691 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, 0); 1692 1693 /* Advance to the next dword. */ 1694 offset32 += 4; 1695 ret_buf += 4; 1696 len32 -= 4; 1697 } 1698 1699 if (rc) 1700 return (rc); 1701 1702 cmd_flags = BNX_NVM_COMMAND_LAST; 1703 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1704 1705 memcpy(ret_buf, buf, 4 - extra); 1706 } 1707 1708 /* Disable access to flash interface and release the lock. */ 1709 bnx_disable_nvram_access(sc); 1710 bnx_release_nvram_lock(sc); 1711 1712 return (rc); 1713 } 1714 1715 #ifdef BNX_NVRAM_WRITE_SUPPORT 1716 /****************************************************************************/ 1717 /* Write an arbitrary range of data from NVRAM. */ 1718 /* */ 1719 /* Prepares the NVRAM interface for write access and writes the requested */ 1720 /* data from the supplied buffer. The caller is responsible for */ 1721 /* calculating any appropriate CRCs. */ 1722 /* */ 1723 /* Returns: */ 1724 /* 0 on success, positive value on failure. */ 1725 /****************************************************************************/ 1726 int 1727 bnx_nvram_write(struct bnx_softc *sc, u_int32_t offset, u_int8_t *data_buf, 1728 int buf_size) 1729 { 1730 u_int32_t written, offset32, len32; 1731 u_int8_t *buf, start[4], end[4]; 1732 int rc = 0; 1733 int align_start, align_end; 1734 1735 buf = data_buf; 1736 offset32 = offset; 1737 len32 = buf_size; 1738 align_start = align_end = 0; 1739 1740 if ((align_start = (offset32 & 3))) { 1741 offset32 &= ~3; 1742 len32 += align_start; 1743 if ((rc = bnx_nvram_read(sc, offset32, start, 4))) 1744 return (rc); 1745 } 1746 1747 if (len32 & 3) { 1748 if ((len32 > 4) || !align_start) { 1749 align_end = 4 - (len32 & 3); 1750 len32 += align_end; 1751 if ((rc = bnx_nvram_read(sc, offset32 + len32 - 4, 1752 end, 4))) { 1753 return (rc); 1754 } 1755 } 1756 } 1757 1758 if (align_start || align_end) { 1759 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 1760 if (buf == 0) 1761 return (ENOMEM); 1762 1763 if (align_start) 1764 memcpy(buf, start, 4); 1765 1766 if (align_end) 1767 memcpy(buf + len32 - 4, end, 4); 1768 1769 memcpy(buf + align_start, data_buf, buf_size); 1770 } 1771 1772 written = 0; 1773 while ((written < len32) && (rc == 0)) { 1774 u_int32_t page_start, page_end, data_start, data_end; 1775 u_int32_t addr, cmd_flags; 1776 int i; 1777 u_int8_t flash_buffer[264]; 1778 1779 /* Find the page_start addr */ 1780 page_start = offset32 + written; 1781 page_start -= (page_start % sc->bnx_flash_info->page_size); 1782 /* Find the page_end addr */ 1783 page_end = page_start + sc->bnx_flash_info->page_size; 1784 /* Find the data_start addr */ 1785 data_start = (written == 0) ? offset32 : page_start; 1786 /* Find the data_end addr */ 1787 data_end = (page_end > offset32 + len32) ? 1788 (offset32 + len32) : page_end; 1789 1790 /* Request access to the flash interface. */ 1791 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1792 goto nvram_write_end; 1793 1794 /* Enable access to flash interface */ 1795 bnx_enable_nvram_access(sc); 1796 1797 cmd_flags = BNX_NVM_COMMAND_FIRST; 1798 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1799 int j; 1800 1801 /* Read the whole page into the buffer 1802 * (non-buffer flash only) */ 1803 for (j = 0; j < sc->bnx_flash_info->page_size; j += 4) { 1804 if (j == (sc->bnx_flash_info->page_size - 4)) 1805 cmd_flags |= BNX_NVM_COMMAND_LAST; 1806 1807 rc = bnx_nvram_read_dword(sc, 1808 page_start + j, 1809 &flash_buffer[j], 1810 cmd_flags); 1811 1812 if (rc) 1813 goto nvram_write_end; 1814 1815 cmd_flags = 0; 1816 } 1817 } 1818 1819 /* Enable writes to flash interface (unlock write-protect) */ 1820 if ((rc = bnx_enable_nvram_write(sc)) != 0) 1821 goto nvram_write_end; 1822 1823 /* Erase the page */ 1824 if ((rc = bnx_nvram_erase_page(sc, page_start)) != 0) 1825 goto nvram_write_end; 1826 1827 /* Re-enable the write again for the actual write */ 1828 bnx_enable_nvram_write(sc); 1829 1830 /* Loop to write back the buffer data from page_start to 1831 * data_start */ 1832 i = 0; 1833 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1834 for (addr = page_start; addr < data_start; 1835 addr += 4, i += 4) { 1836 1837 rc = bnx_nvram_write_dword(sc, addr, 1838 &flash_buffer[i], cmd_flags); 1839 1840 if (rc != 0) 1841 goto nvram_write_end; 1842 1843 cmd_flags = 0; 1844 } 1845 } 1846 1847 /* Loop to write the new data from data_start to data_end */ 1848 for (addr = data_start; addr < data_end; addr += 4, i++) { 1849 if ((addr == page_end - 4) || 1850 (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED) 1851 && (addr == data_end - 4))) { 1852 1853 cmd_flags |= BNX_NVM_COMMAND_LAST; 1854 } 1855 1856 rc = bnx_nvram_write_dword(sc, addr, buf, cmd_flags); 1857 1858 if (rc != 0) 1859 goto nvram_write_end; 1860 1861 cmd_flags = 0; 1862 buf += 4; 1863 } 1864 1865 /* Loop to write back the buffer data from data_end 1866 * to page_end */ 1867 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1868 for (addr = data_end; addr < page_end; 1869 addr += 4, i += 4) { 1870 1871 if (addr == page_end-4) 1872 cmd_flags = BNX_NVM_COMMAND_LAST; 1873 1874 rc = bnx_nvram_write_dword(sc, addr, 1875 &flash_buffer[i], cmd_flags); 1876 1877 if (rc != 0) 1878 goto nvram_write_end; 1879 1880 cmd_flags = 0; 1881 } 1882 } 1883 1884 /* Disable writes to flash interface (lock write-protect) */ 1885 bnx_disable_nvram_write(sc); 1886 1887 /* Disable access to flash interface */ 1888 bnx_disable_nvram_access(sc); 1889 bnx_release_nvram_lock(sc); 1890 1891 /* Increment written */ 1892 written += data_end - data_start; 1893 } 1894 1895 nvram_write_end: 1896 if (align_start || align_end) 1897 free(buf, M_DEVBUF); 1898 1899 return (rc); 1900 } 1901 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1902 1903 /****************************************************************************/ 1904 /* Verifies that NVRAM is accessible and contains valid data. */ 1905 /* */ 1906 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 1907 /* correct. */ 1908 /* */ 1909 /* Returns: */ 1910 /* 0 on success, positive value on failure. */ 1911 /****************************************************************************/ 1912 int 1913 bnx_nvram_test(struct bnx_softc *sc) 1914 { 1915 u_int32_t buf[BNX_NVRAM_SIZE / 4]; 1916 u_int8_t *data = (u_int8_t *) buf; 1917 int rc = 0; 1918 u_int32_t magic, csum; 1919 1920 /* 1921 * Check that the device NVRAM is valid by reading 1922 * the magic value at offset 0. 1923 */ 1924 if ((rc = bnx_nvram_read(sc, 0, data, 4)) != 0) 1925 goto bnx_nvram_test_done; 1926 1927 magic = bnx_be32toh(buf[0]); 1928 if (magic != BNX_NVRAM_MAGIC) { 1929 rc = ENODEV; 1930 BNX_PRINTF(sc, "%s(%d): Invalid NVRAM magic value! " 1931 "Expected: 0x%08X, Found: 0x%08X\n", 1932 __FILE__, __LINE__, BNX_NVRAM_MAGIC, magic); 1933 goto bnx_nvram_test_done; 1934 } 1935 1936 /* 1937 * Verify that the device NVRAM includes valid 1938 * configuration data. 1939 */ 1940 if ((rc = bnx_nvram_read(sc, 0x100, data, BNX_NVRAM_SIZE)) != 0) 1941 goto bnx_nvram_test_done; 1942 1943 csum = ether_crc32_le(data, 0x100); 1944 if (csum != BNX_CRC32_RESIDUAL) { 1945 rc = ENODEV; 1946 BNX_PRINTF(sc, "%s(%d): Invalid Manufacturing Information " 1947 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 1948 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 1949 goto bnx_nvram_test_done; 1950 } 1951 1952 csum = ether_crc32_le(data + 0x100, 0x100); 1953 if (csum != BNX_CRC32_RESIDUAL) { 1954 BNX_PRINTF(sc, "%s(%d): Invalid Feature Configuration " 1955 "Information NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 1956 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 1957 rc = ENODEV; 1958 } 1959 1960 bnx_nvram_test_done: 1961 return (rc); 1962 } 1963 1964 /****************************************************************************/ 1965 /* Identifies the current media type of the controller and sets the PHY */ 1966 /* address. */ 1967 /* */ 1968 /* Returns: */ 1969 /* Nothing. */ 1970 /****************************************************************************/ 1971 void 1972 bnx_get_media(struct bnx_softc *sc) 1973 { 1974 sc->bnx_phy_addr = 1; 1975 1976 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1977 u_int32_t val = REG_RD(sc, BNX_MISC_DUAL_MEDIA_CTRL); 1978 u_int32_t bond_id = val & BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID; 1979 u_int32_t strap; 1980 1981 /* 1982 * The BCM5709S is software configurable 1983 * for Copper or SerDes operation. 1984 */ 1985 if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 1986 DBPRINT(sc, BNX_INFO_LOAD, 1987 "5709 bonded for copper.\n"); 1988 goto bnx_get_media_exit; 1989 } else if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 1990 DBPRINT(sc, BNX_INFO_LOAD, 1991 "5709 bonded for dual media.\n"); 1992 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 1993 goto bnx_get_media_exit; 1994 } 1995 1996 if (val & BNX_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 1997 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 1998 else { 1999 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) 2000 >> 8; 2001 } 2002 2003 if (sc->bnx_pa.pa_function == 0) { 2004 switch (strap) { 2005 case 0x4: 2006 case 0x5: 2007 case 0x6: 2008 DBPRINT(sc, BNX_INFO_LOAD, 2009 "BCM5709 s/w configured for SerDes.\n"); 2010 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2011 break; 2012 default: 2013 DBPRINT(sc, BNX_INFO_LOAD, 2014 "BCM5709 s/w configured for Copper.\n"); 2015 } 2016 } else { 2017 switch (strap) { 2018 case 0x1: 2019 case 0x2: 2020 case 0x4: 2021 DBPRINT(sc, BNX_INFO_LOAD, 2022 "BCM5709 s/w configured for SerDes.\n"); 2023 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2024 break; 2025 default: 2026 DBPRINT(sc, BNX_INFO_LOAD, 2027 "BCM5709 s/w configured for Copper.\n"); 2028 } 2029 } 2030 2031 } else if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) 2032 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2033 2034 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) { 2035 u_int32_t val; 2036 2037 sc->bnx_flags |= BNX_NO_WOL_FLAG; 2038 2039 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) 2040 sc->bnx_phy_flags |= BNX_PHY_IEEE_CLAUSE_45_FLAG; 2041 2042 /* 2043 * The BCM5708S, BCM5709S, and BCM5716S controllers use a 2044 * separate PHY for SerDes. 2045 */ 2046 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 2047 sc->bnx_phy_addr = 2; 2048 val = REG_RD_IND(sc, sc->bnx_shmem_base + 2049 BNX_SHARED_HW_CFG_CONFIG); 2050 if (val & BNX_SHARED_HW_CFG_PHY_2_5G) { 2051 sc->bnx_phy_flags |= BNX_PHY_2_5G_CAPABLE_FLAG; 2052 DBPRINT(sc, BNX_INFO_LOAD, 2053 "Found 2.5Gb capable adapter\n"); 2054 } 2055 } 2056 } else if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) || 2057 (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708)) 2058 sc->bnx_phy_flags |= BNX_PHY_CRC_FIX_FLAG; 2059 2060 bnx_get_media_exit: 2061 DBPRINT(sc, (BNX_INFO_LOAD), 2062 "Using PHY address %d.\n", sc->bnx_phy_addr); 2063 } 2064 2065 /****************************************************************************/ 2066 /* Performs PHY initialization required before MII drivers access the */ 2067 /* device. */ 2068 /* */ 2069 /* Returns: */ 2070 /* Nothing. */ 2071 /****************************************************************************/ 2072 void 2073 bnx_init_media(struct bnx_softc *sc) 2074 { 2075 if (sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) { 2076 /* 2077 * Configure the BCM5709S / BCM5716S PHYs to use traditional 2078 * IEEE Clause 22 method. Otherwise we have no way to attach 2079 * the PHY to the mii(4) layer. PHY specific configuration 2080 * is done by the mii(4) layer. 2081 */ 2082 2083 /* Select auto-negotiation MMD of the PHY. */ 2084 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2085 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 2086 2087 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2088 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 2089 2090 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2091 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 2092 } 2093 } 2094 2095 /****************************************************************************/ 2096 /* Free any DMA memory owned by the driver. */ 2097 /* */ 2098 /* Scans through each data structre that requires DMA memory and frees */ 2099 /* the memory if allocated. */ 2100 /* */ 2101 /* Returns: */ 2102 /* Nothing. */ 2103 /****************************************************************************/ 2104 void 2105 bnx_dma_free(struct bnx_softc *sc) 2106 { 2107 int i; 2108 2109 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2110 2111 /* Destroy the status block. */ 2112 if (sc->status_block != NULL && sc->status_map != NULL) { 2113 bus_dmamap_unload(sc->bnx_dmatag, sc->status_map); 2114 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->status_block, 2115 BNX_STATUS_BLK_SZ); 2116 bus_dmamem_free(sc->bnx_dmatag, &sc->status_seg, 2117 sc->status_rseg); 2118 bus_dmamap_destroy(sc->bnx_dmatag, sc->status_map); 2119 sc->status_block = NULL; 2120 sc->status_map = NULL; 2121 } 2122 2123 /* Destroy the statistics block. */ 2124 if (sc->stats_block != NULL && sc->stats_map != NULL) { 2125 bus_dmamap_unload(sc->bnx_dmatag, sc->stats_map); 2126 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->stats_block, 2127 BNX_STATS_BLK_SZ); 2128 bus_dmamem_free(sc->bnx_dmatag, &sc->stats_seg, 2129 sc->stats_rseg); 2130 bus_dmamap_destroy(sc->bnx_dmatag, sc->stats_map); 2131 sc->stats_block = NULL; 2132 sc->stats_map = NULL; 2133 } 2134 2135 /* Free, unmap and destroy all context memory pages. */ 2136 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2137 for (i = 0; i < sc->ctx_pages; i++) { 2138 if (sc->ctx_block[i] != NULL) { 2139 bus_dmamap_unload(sc->bnx_dmatag, 2140 sc->ctx_map[i]); 2141 bus_dmamem_unmap(sc->bnx_dmatag, 2142 (void *)sc->ctx_block[i], 2143 BCM_PAGE_SIZE); 2144 bus_dmamem_free(sc->bnx_dmatag, 2145 &sc->ctx_segs[i], sc->ctx_rsegs[i]); 2146 bus_dmamap_destroy(sc->bnx_dmatag, 2147 sc->ctx_map[i]); 2148 sc->ctx_block[i] = NULL; 2149 } 2150 } 2151 } 2152 2153 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 2154 for (i = 0; i < TX_PAGES; i++ ) { 2155 if (sc->tx_bd_chain[i] != NULL && 2156 sc->tx_bd_chain_map[i] != NULL) { 2157 bus_dmamap_unload(sc->bnx_dmatag, 2158 sc->tx_bd_chain_map[i]); 2159 bus_dmamem_unmap(sc->bnx_dmatag, 2160 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); 2161 bus_dmamem_free(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2162 sc->tx_bd_chain_rseg[i]); 2163 bus_dmamap_destroy(sc->bnx_dmatag, 2164 sc->tx_bd_chain_map[i]); 2165 sc->tx_bd_chain[i] = NULL; 2166 sc->tx_bd_chain_map[i] = NULL; 2167 } 2168 } 2169 2170 /* Destroy the TX dmamaps. */ 2171 /* This isn't necessary since we dont allocate them up front */ 2172 2173 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 2174 for (i = 0; i < RX_PAGES; i++ ) { 2175 if (sc->rx_bd_chain[i] != NULL && 2176 sc->rx_bd_chain_map[i] != NULL) { 2177 bus_dmamap_unload(sc->bnx_dmatag, 2178 sc->rx_bd_chain_map[i]); 2179 bus_dmamem_unmap(sc->bnx_dmatag, 2180 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 2181 bus_dmamem_free(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2182 sc->rx_bd_chain_rseg[i]); 2183 2184 bus_dmamap_destroy(sc->bnx_dmatag, 2185 sc->rx_bd_chain_map[i]); 2186 sc->rx_bd_chain[i] = NULL; 2187 sc->rx_bd_chain_map[i] = NULL; 2188 } 2189 } 2190 2191 /* Unload and destroy the RX mbuf maps. */ 2192 for (i = 0; i < TOTAL_RX_BD; i++) { 2193 if (sc->rx_mbuf_map[i] != NULL) { 2194 bus_dmamap_unload(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2195 bus_dmamap_destroy(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2196 } 2197 } 2198 2199 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2200 } 2201 2202 /****************************************************************************/ 2203 /* Allocate any DMA memory needed by the driver. */ 2204 /* */ 2205 /* Allocates DMA memory needed for the various global structures needed by */ 2206 /* hardware. */ 2207 /* */ 2208 /* Returns: */ 2209 /* 0 for success, positive value for failure. */ 2210 /****************************************************************************/ 2211 int 2212 bnx_dma_alloc(struct bnx_softc *sc) 2213 { 2214 int i, rc = 0; 2215 2216 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2217 2218 /* 2219 * Allocate DMA memory for the status block, map the memory into DMA 2220 * space, and fetch the physical address of the block. 2221 */ 2222 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1, 2223 BNX_STATUS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->status_map)) { 2224 aprint_error_dev(sc->bnx_dev, 2225 "Could not create status block DMA map!\n"); 2226 rc = ENOMEM; 2227 goto bnx_dma_alloc_exit; 2228 } 2229 2230 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 2231 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->status_seg, 1, 2232 &sc->status_rseg, BUS_DMA_NOWAIT)) { 2233 aprint_error_dev(sc->bnx_dev, 2234 "Could not allocate status block DMA memory!\n"); 2235 rc = ENOMEM; 2236 goto bnx_dma_alloc_exit; 2237 } 2238 2239 if (bus_dmamem_map(sc->bnx_dmatag, &sc->status_seg, sc->status_rseg, 2240 BNX_STATUS_BLK_SZ, (void **)&sc->status_block, BUS_DMA_NOWAIT)) { 2241 aprint_error_dev(sc->bnx_dev, 2242 "Could not map status block DMA memory!\n"); 2243 rc = ENOMEM; 2244 goto bnx_dma_alloc_exit; 2245 } 2246 2247 if (bus_dmamap_load(sc->bnx_dmatag, sc->status_map, 2248 sc->status_block, BNX_STATUS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2249 aprint_error_dev(sc->bnx_dev, 2250 "Could not load status block DMA memory!\n"); 2251 rc = ENOMEM; 2252 goto bnx_dma_alloc_exit; 2253 } 2254 2255 sc->status_block_paddr = sc->status_map->dm_segs[0].ds_addr; 2256 memset(sc->status_block, 0, BNX_STATUS_BLK_SZ); 2257 2258 /* DRC - Fix for 64 bit addresses. */ 2259 DBPRINT(sc, BNX_INFO, "status_block_paddr = 0x%08X\n", 2260 (u_int32_t) sc->status_block_paddr); 2261 2262 /* BCM5709 uses host memory as cache for context memory. */ 2263 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2264 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 2265 if (sc->ctx_pages == 0) 2266 sc->ctx_pages = 1; 2267 if (sc->ctx_pages > 4) /* XXX */ 2268 sc->ctx_pages = 4; 2269 2270 DBRUNIF((sc->ctx_pages > 512), 2271 BNX_PRINTF(sc, "%s(%d): Too many CTX pages! %d > 512\n", 2272 __FILE__, __LINE__, sc->ctx_pages)); 2273 2274 2275 for (i = 0; i < sc->ctx_pages; i++) { 2276 if (bus_dmamap_create(sc->bnx_dmatag, BCM_PAGE_SIZE, 2277 1, BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, 2278 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2279 &sc->ctx_map[i]) != 0) { 2280 rc = ENOMEM; 2281 goto bnx_dma_alloc_exit; 2282 } 2283 2284 if (bus_dmamem_alloc(sc->bnx_dmatag, BCM_PAGE_SIZE, 2285 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->ctx_segs[i], 2286 1, &sc->ctx_rsegs[i], BUS_DMA_NOWAIT) != 0) { 2287 rc = ENOMEM; 2288 goto bnx_dma_alloc_exit; 2289 } 2290 2291 if (bus_dmamem_map(sc->bnx_dmatag, &sc->ctx_segs[i], 2292 sc->ctx_rsegs[i], BCM_PAGE_SIZE, 2293 &sc->ctx_block[i], BUS_DMA_NOWAIT) != 0) { 2294 rc = ENOMEM; 2295 goto bnx_dma_alloc_exit; 2296 } 2297 2298 if (bus_dmamap_load(sc->bnx_dmatag, sc->ctx_map[i], 2299 sc->ctx_block[i], BCM_PAGE_SIZE, NULL, 2300 BUS_DMA_NOWAIT) != 0) { 2301 rc = ENOMEM; 2302 goto bnx_dma_alloc_exit; 2303 } 2304 2305 bzero(sc->ctx_block[i], BCM_PAGE_SIZE); 2306 } 2307 } 2308 2309 /* 2310 * Allocate DMA memory for the statistics block, map the memory into 2311 * DMA space, and fetch the physical address of the block. 2312 */ 2313 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 1, 2314 BNX_STATS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->stats_map)) { 2315 aprint_error_dev(sc->bnx_dev, 2316 "Could not create stats block DMA map!\n"); 2317 rc = ENOMEM; 2318 goto bnx_dma_alloc_exit; 2319 } 2320 2321 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 2322 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->stats_seg, 1, 2323 &sc->stats_rseg, BUS_DMA_NOWAIT)) { 2324 aprint_error_dev(sc->bnx_dev, 2325 "Could not allocate stats block DMA memory!\n"); 2326 rc = ENOMEM; 2327 goto bnx_dma_alloc_exit; 2328 } 2329 2330 if (bus_dmamem_map(sc->bnx_dmatag, &sc->stats_seg, sc->stats_rseg, 2331 BNX_STATS_BLK_SZ, (void **)&sc->stats_block, BUS_DMA_NOWAIT)) { 2332 aprint_error_dev(sc->bnx_dev, 2333 "Could not map stats block DMA memory!\n"); 2334 rc = ENOMEM; 2335 goto bnx_dma_alloc_exit; 2336 } 2337 2338 if (bus_dmamap_load(sc->bnx_dmatag, sc->stats_map, 2339 sc->stats_block, BNX_STATS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2340 aprint_error_dev(sc->bnx_dev, 2341 "Could not load status block DMA memory!\n"); 2342 rc = ENOMEM; 2343 goto bnx_dma_alloc_exit; 2344 } 2345 2346 sc->stats_block_paddr = sc->stats_map->dm_segs[0].ds_addr; 2347 memset(sc->stats_block, 0, BNX_STATS_BLK_SZ); 2348 2349 /* DRC - Fix for 64 bit address. */ 2350 DBPRINT(sc,BNX_INFO, "stats_block_paddr = 0x%08X\n", 2351 (u_int32_t) sc->stats_block_paddr); 2352 2353 /* 2354 * Allocate DMA memory for the TX buffer descriptor chain, 2355 * and fetch the physical address of the block. 2356 */ 2357 for (i = 0; i < TX_PAGES; i++) { 2358 if (bus_dmamap_create(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 1, 2359 BNX_TX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2360 &sc->tx_bd_chain_map[i])) { 2361 aprint_error_dev(sc->bnx_dev, 2362 "Could not create Tx desc %d DMA map!\n", i); 2363 rc = ENOMEM; 2364 goto bnx_dma_alloc_exit; 2365 } 2366 2367 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 2368 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->tx_bd_chain_seg[i], 1, 2369 &sc->tx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2370 aprint_error_dev(sc->bnx_dev, 2371 "Could not allocate TX desc %d DMA memory!\n", 2372 i); 2373 rc = ENOMEM; 2374 goto bnx_dma_alloc_exit; 2375 } 2376 2377 if (bus_dmamem_map(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2378 sc->tx_bd_chain_rseg[i], BNX_TX_CHAIN_PAGE_SZ, 2379 (void **)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT)) { 2380 aprint_error_dev(sc->bnx_dev, 2381 "Could not map TX desc %d DMA memory!\n", i); 2382 rc = ENOMEM; 2383 goto bnx_dma_alloc_exit; 2384 } 2385 2386 if (bus_dmamap_load(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 2387 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ, NULL, 2388 BUS_DMA_NOWAIT)) { 2389 aprint_error_dev(sc->bnx_dev, 2390 "Could not load TX desc %d DMA memory!\n", i); 2391 rc = ENOMEM; 2392 goto bnx_dma_alloc_exit; 2393 } 2394 2395 sc->tx_bd_chain_paddr[i] = 2396 sc->tx_bd_chain_map[i]->dm_segs[0].ds_addr; 2397 2398 /* DRC - Fix for 64 bit systems. */ 2399 DBPRINT(sc, BNX_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 2400 i, (u_int32_t) sc->tx_bd_chain_paddr[i]); 2401 } 2402 2403 /* 2404 * Create lists to hold TX mbufs. 2405 */ 2406 TAILQ_INIT(&sc->tx_free_pkts); 2407 TAILQ_INIT(&sc->tx_used_pkts); 2408 sc->tx_pkt_count = 0; 2409 mutex_init(&sc->tx_pkt_mtx, MUTEX_DEFAULT, IPL_NET); 2410 2411 /* 2412 * Allocate DMA memory for the Rx buffer descriptor chain, 2413 * and fetch the physical address of the block. 2414 */ 2415 for (i = 0; i < RX_PAGES; i++) { 2416 if (bus_dmamap_create(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 1, 2417 BNX_RX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2418 &sc->rx_bd_chain_map[i])) { 2419 aprint_error_dev(sc->bnx_dev, 2420 "Could not create Rx desc %d DMA map!\n", i); 2421 rc = ENOMEM; 2422 goto bnx_dma_alloc_exit; 2423 } 2424 2425 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 2426 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->rx_bd_chain_seg[i], 1, 2427 &sc->rx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2428 aprint_error_dev(sc->bnx_dev, 2429 "Could not allocate Rx desc %d DMA memory!\n", i); 2430 rc = ENOMEM; 2431 goto bnx_dma_alloc_exit; 2432 } 2433 2434 if (bus_dmamem_map(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2435 sc->rx_bd_chain_rseg[i], BNX_RX_CHAIN_PAGE_SZ, 2436 (void **)&sc->rx_bd_chain[i], BUS_DMA_NOWAIT)) { 2437 aprint_error_dev(sc->bnx_dev, 2438 "Could not map Rx desc %d DMA memory!\n", i); 2439 rc = ENOMEM; 2440 goto bnx_dma_alloc_exit; 2441 } 2442 2443 if (bus_dmamap_load(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2444 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ, NULL, 2445 BUS_DMA_NOWAIT)) { 2446 aprint_error_dev(sc->bnx_dev, 2447 "Could not load Rx desc %d DMA memory!\n", i); 2448 rc = ENOMEM; 2449 goto bnx_dma_alloc_exit; 2450 } 2451 2452 memset(sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 2453 sc->rx_bd_chain_paddr[i] = 2454 sc->rx_bd_chain_map[i]->dm_segs[0].ds_addr; 2455 2456 /* DRC - Fix for 64 bit systems. */ 2457 DBPRINT(sc, BNX_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 2458 i, (u_int32_t) sc->rx_bd_chain_paddr[i]); 2459 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2460 0, BNX_RX_CHAIN_PAGE_SZ, 2461 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2462 } 2463 2464 /* 2465 * Create DMA maps for the Rx buffer mbufs. 2466 */ 2467 for (i = 0; i < TOTAL_RX_BD; i++) { 2468 if (bus_dmamap_create(sc->bnx_dmatag, BNX_MAX_JUMBO_MRU, 2469 BNX_MAX_SEGMENTS, BNX_MAX_JUMBO_MRU, 0, BUS_DMA_NOWAIT, 2470 &sc->rx_mbuf_map[i])) { 2471 aprint_error_dev(sc->bnx_dev, 2472 "Could not create Rx mbuf %d DMA map!\n", i); 2473 rc = ENOMEM; 2474 goto bnx_dma_alloc_exit; 2475 } 2476 } 2477 2478 bnx_dma_alloc_exit: 2479 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2480 2481 return(rc); 2482 } 2483 2484 /****************************************************************************/ 2485 /* Release all resources used by the driver. */ 2486 /* */ 2487 /* Releases all resources acquired by the driver including interrupts, */ 2488 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 2489 /* */ 2490 /* Returns: */ 2491 /* Nothing. */ 2492 /****************************************************************************/ 2493 void 2494 bnx_release_resources(struct bnx_softc *sc) 2495 { 2496 struct pci_attach_args *pa = &(sc->bnx_pa); 2497 2498 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2499 2500 bnx_dma_free(sc); 2501 2502 if (sc->bnx_intrhand != NULL) 2503 pci_intr_disestablish(pa->pa_pc, sc->bnx_intrhand); 2504 2505 if (sc->bnx_size) 2506 bus_space_unmap(sc->bnx_btag, sc->bnx_bhandle, sc->bnx_size); 2507 2508 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2509 } 2510 2511 /****************************************************************************/ 2512 /* Firmware synchronization. */ 2513 /* */ 2514 /* Before performing certain events such as a chip reset, synchronize with */ 2515 /* the firmware first. */ 2516 /* */ 2517 /* Returns: */ 2518 /* 0 for success, positive value for failure. */ 2519 /****************************************************************************/ 2520 int 2521 bnx_fw_sync(struct bnx_softc *sc, u_int32_t msg_data) 2522 { 2523 int i, rc = 0; 2524 u_int32_t val; 2525 2526 /* Don't waste any time if we've timed out before. */ 2527 if (sc->bnx_fw_timed_out) { 2528 rc = EBUSY; 2529 goto bnx_fw_sync_exit; 2530 } 2531 2532 /* Increment the message sequence number. */ 2533 sc->bnx_fw_wr_seq++; 2534 msg_data |= sc->bnx_fw_wr_seq; 2535 2536 DBPRINT(sc, BNX_VERBOSE, "bnx_fw_sync(): msg_data = 0x%08X\n", 2537 msg_data); 2538 2539 /* Send the message to the bootcode driver mailbox. */ 2540 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2541 2542 /* Wait for the bootcode to acknowledge the message. */ 2543 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 2544 /* Check for a response in the bootcode firmware mailbox. */ 2545 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB); 2546 if ((val & BNX_FW_MSG_ACK) == (msg_data & BNX_DRV_MSG_SEQ)) 2547 break; 2548 DELAY(1000); 2549 } 2550 2551 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 2552 if (((val & BNX_FW_MSG_ACK) != (msg_data & BNX_DRV_MSG_SEQ)) && 2553 ((msg_data & BNX_DRV_MSG_DATA) != BNX_DRV_MSG_DATA_WAIT0)) { 2554 BNX_PRINTF(sc, "%s(%d): Firmware synchronization timeout! " 2555 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 2556 2557 msg_data &= ~BNX_DRV_MSG_CODE; 2558 msg_data |= BNX_DRV_MSG_CODE_FW_TIMEOUT; 2559 2560 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2561 2562 sc->bnx_fw_timed_out = 1; 2563 rc = EBUSY; 2564 } 2565 2566 bnx_fw_sync_exit: 2567 return (rc); 2568 } 2569 2570 /****************************************************************************/ 2571 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 2572 /* */ 2573 /* Returns: */ 2574 /* Nothing. */ 2575 /****************************************************************************/ 2576 void 2577 bnx_load_rv2p_fw(struct bnx_softc *sc, u_int32_t *rv2p_code, 2578 u_int32_t rv2p_code_len, u_int32_t rv2p_proc) 2579 { 2580 int i; 2581 u_int32_t val; 2582 2583 /* Set the page size used by RV2P. */ 2584 if (rv2p_proc == RV2P_PROC2) { 2585 BNX_RV2P_PROC2_CHG_MAX_BD_PAGE(rv2p_code, 2586 USABLE_RX_BD_PER_PAGE); 2587 } 2588 2589 for (i = 0; i < rv2p_code_len; i += 8) { 2590 REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code); 2591 rv2p_code++; 2592 REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code); 2593 rv2p_code++; 2594 2595 if (rv2p_proc == RV2P_PROC1) { 2596 val = (i / 8) | BNX_RV2P_PROC1_ADDR_CMD_RDWR; 2597 REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val); 2598 } else { 2599 val = (i / 8) | BNX_RV2P_PROC2_ADDR_CMD_RDWR; 2600 REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val); 2601 } 2602 } 2603 2604 /* Reset the processor, un-stall is done later. */ 2605 if (rv2p_proc == RV2P_PROC1) 2606 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET); 2607 else 2608 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET); 2609 } 2610 2611 /****************************************************************************/ 2612 /* Load RISC processor firmware. */ 2613 /* */ 2614 /* Loads firmware from the file if_bnxfw.h into the scratchpad memory */ 2615 /* associated with a particular processor. */ 2616 /* */ 2617 /* Returns: */ 2618 /* Nothing. */ 2619 /****************************************************************************/ 2620 void 2621 bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg, 2622 struct fw_info *fw) 2623 { 2624 u_int32_t offset; 2625 u_int32_t val; 2626 2627 /* Halt the CPU. */ 2628 val = REG_RD_IND(sc, cpu_reg->mode); 2629 val |= cpu_reg->mode_value_halt; 2630 REG_WR_IND(sc, cpu_reg->mode, val); 2631 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2632 2633 /* Load the Text area. */ 2634 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2635 if (fw->text) { 2636 int j; 2637 2638 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) 2639 REG_WR_IND(sc, offset, fw->text[j]); 2640 } 2641 2642 /* Load the Data area. */ 2643 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 2644 if (fw->data) { 2645 int j; 2646 2647 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) 2648 REG_WR_IND(sc, offset, fw->data[j]); 2649 } 2650 2651 /* Load the SBSS area. */ 2652 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 2653 if (fw->sbss) { 2654 int j; 2655 2656 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) 2657 REG_WR_IND(sc, offset, fw->sbss[j]); 2658 } 2659 2660 /* Load the BSS area. */ 2661 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 2662 if (fw->bss) { 2663 int j; 2664 2665 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) 2666 REG_WR_IND(sc, offset, fw->bss[j]); 2667 } 2668 2669 /* Load the Read-Only area. */ 2670 offset = cpu_reg->spad_base + 2671 (fw->rodata_addr - cpu_reg->mips_view_base); 2672 if (fw->rodata) { 2673 int j; 2674 2675 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) 2676 REG_WR_IND(sc, offset, fw->rodata[j]); 2677 } 2678 2679 /* Clear the pre-fetch instruction. */ 2680 REG_WR_IND(sc, cpu_reg->inst, 0); 2681 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 2682 2683 /* Start the CPU. */ 2684 val = REG_RD_IND(sc, cpu_reg->mode); 2685 val &= ~cpu_reg->mode_value_halt; 2686 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2687 REG_WR_IND(sc, cpu_reg->mode, val); 2688 } 2689 2690 /****************************************************************************/ 2691 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ 2692 /* */ 2693 /* Loads the firmware for each CPU and starts the CPU. */ 2694 /* */ 2695 /* Returns: */ 2696 /* Nothing. */ 2697 /****************************************************************************/ 2698 void 2699 bnx_init_cpus(struct bnx_softc *sc) 2700 { 2701 struct cpu_reg cpu_reg; 2702 struct fw_info fw; 2703 2704 switch(BNX_CHIP_NUM(sc)) { 2705 case BNX_CHIP_NUM_5709: 2706 /* Initialize the RV2P processor. */ 2707 if (BNX_CHIP_REV(sc) == BNX_CHIP_REV_Ax) { 2708 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc1, 2709 sizeof(bnx_xi90_rv2p_proc1), RV2P_PROC1); 2710 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc2, 2711 sizeof(bnx_xi90_rv2p_proc2), RV2P_PROC2); 2712 } else { 2713 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc1, 2714 sizeof(bnx_xi_rv2p_proc1), RV2P_PROC1); 2715 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc2, 2716 sizeof(bnx_xi_rv2p_proc2), RV2P_PROC2); 2717 } 2718 2719 /* Initialize the RX Processor. */ 2720 cpu_reg.mode = BNX_RXP_CPU_MODE; 2721 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 2722 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 2723 cpu_reg.state = BNX_RXP_CPU_STATE; 2724 cpu_reg.state_value_clear = 0xffffff; 2725 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 2726 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 2727 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 2728 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 2729 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 2730 cpu_reg.spad_base = BNX_RXP_SCRATCH; 2731 cpu_reg.mips_view_base = 0x8000000; 2732 2733 fw.ver_major = bnx_RXP_b09FwReleaseMajor; 2734 fw.ver_minor = bnx_RXP_b09FwReleaseMinor; 2735 fw.ver_fix = bnx_RXP_b09FwReleaseFix; 2736 fw.start_addr = bnx_RXP_b09FwStartAddr; 2737 2738 fw.text_addr = bnx_RXP_b09FwTextAddr; 2739 fw.text_len = bnx_RXP_b09FwTextLen; 2740 fw.text_index = 0; 2741 fw.text = bnx_RXP_b09FwText; 2742 2743 fw.data_addr = bnx_RXP_b09FwDataAddr; 2744 fw.data_len = bnx_RXP_b09FwDataLen; 2745 fw.data_index = 0; 2746 fw.data = bnx_RXP_b09FwData; 2747 2748 fw.sbss_addr = bnx_RXP_b09FwSbssAddr; 2749 fw.sbss_len = bnx_RXP_b09FwSbssLen; 2750 fw.sbss_index = 0; 2751 fw.sbss = bnx_RXP_b09FwSbss; 2752 2753 fw.bss_addr = bnx_RXP_b09FwBssAddr; 2754 fw.bss_len = bnx_RXP_b09FwBssLen; 2755 fw.bss_index = 0; 2756 fw.bss = bnx_RXP_b09FwBss; 2757 2758 fw.rodata_addr = bnx_RXP_b09FwRodataAddr; 2759 fw.rodata_len = bnx_RXP_b09FwRodataLen; 2760 fw.rodata_index = 0; 2761 fw.rodata = bnx_RXP_b09FwRodata; 2762 2763 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 2764 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2765 2766 /* Initialize the TX Processor. */ 2767 cpu_reg.mode = BNX_TXP_CPU_MODE; 2768 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 2769 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 2770 cpu_reg.state = BNX_TXP_CPU_STATE; 2771 cpu_reg.state_value_clear = 0xffffff; 2772 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 2773 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 2774 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 2775 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 2776 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 2777 cpu_reg.spad_base = BNX_TXP_SCRATCH; 2778 cpu_reg.mips_view_base = 0x8000000; 2779 2780 fw.ver_major = bnx_TXP_b09FwReleaseMajor; 2781 fw.ver_minor = bnx_TXP_b09FwReleaseMinor; 2782 fw.ver_fix = bnx_TXP_b09FwReleaseFix; 2783 fw.start_addr = bnx_TXP_b09FwStartAddr; 2784 2785 fw.text_addr = bnx_TXP_b09FwTextAddr; 2786 fw.text_len = bnx_TXP_b09FwTextLen; 2787 fw.text_index = 0; 2788 fw.text = bnx_TXP_b09FwText; 2789 2790 fw.data_addr = bnx_TXP_b09FwDataAddr; 2791 fw.data_len = bnx_TXP_b09FwDataLen; 2792 fw.data_index = 0; 2793 fw.data = bnx_TXP_b09FwData; 2794 2795 fw.sbss_addr = bnx_TXP_b09FwSbssAddr; 2796 fw.sbss_len = bnx_TXP_b09FwSbssLen; 2797 fw.sbss_index = 0; 2798 fw.sbss = bnx_TXP_b09FwSbss; 2799 2800 fw.bss_addr = bnx_TXP_b09FwBssAddr; 2801 fw.bss_len = bnx_TXP_b09FwBssLen; 2802 fw.bss_index = 0; 2803 fw.bss = bnx_TXP_b09FwBss; 2804 2805 fw.rodata_addr = bnx_TXP_b09FwRodataAddr; 2806 fw.rodata_len = bnx_TXP_b09FwRodataLen; 2807 fw.rodata_index = 0; 2808 fw.rodata = bnx_TXP_b09FwRodata; 2809 2810 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 2811 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2812 2813 /* Initialize the TX Patch-up Processor. */ 2814 cpu_reg.mode = BNX_TPAT_CPU_MODE; 2815 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 2816 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 2817 cpu_reg.state = BNX_TPAT_CPU_STATE; 2818 cpu_reg.state_value_clear = 0xffffff; 2819 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 2820 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 2821 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 2822 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 2823 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 2824 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 2825 cpu_reg.mips_view_base = 0x8000000; 2826 2827 fw.ver_major = bnx_TPAT_b09FwReleaseMajor; 2828 fw.ver_minor = bnx_TPAT_b09FwReleaseMinor; 2829 fw.ver_fix = bnx_TPAT_b09FwReleaseFix; 2830 fw.start_addr = bnx_TPAT_b09FwStartAddr; 2831 2832 fw.text_addr = bnx_TPAT_b09FwTextAddr; 2833 fw.text_len = bnx_TPAT_b09FwTextLen; 2834 fw.text_index = 0; 2835 fw.text = bnx_TPAT_b09FwText; 2836 2837 fw.data_addr = bnx_TPAT_b09FwDataAddr; 2838 fw.data_len = bnx_TPAT_b09FwDataLen; 2839 fw.data_index = 0; 2840 fw.data = bnx_TPAT_b09FwData; 2841 2842 fw.sbss_addr = bnx_TPAT_b09FwSbssAddr; 2843 fw.sbss_len = bnx_TPAT_b09FwSbssLen; 2844 fw.sbss_index = 0; 2845 fw.sbss = bnx_TPAT_b09FwSbss; 2846 2847 fw.bss_addr = bnx_TPAT_b09FwBssAddr; 2848 fw.bss_len = bnx_TPAT_b09FwBssLen; 2849 fw.bss_index = 0; 2850 fw.bss = bnx_TPAT_b09FwBss; 2851 2852 fw.rodata_addr = bnx_TPAT_b09FwRodataAddr; 2853 fw.rodata_len = bnx_TPAT_b09FwRodataLen; 2854 fw.rodata_index = 0; 2855 fw.rodata = bnx_TPAT_b09FwRodata; 2856 2857 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 2858 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2859 2860 /* Initialize the Completion Processor. */ 2861 cpu_reg.mode = BNX_COM_CPU_MODE; 2862 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 2863 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 2864 cpu_reg.state = BNX_COM_CPU_STATE; 2865 cpu_reg.state_value_clear = 0xffffff; 2866 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 2867 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 2868 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 2869 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 2870 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 2871 cpu_reg.spad_base = BNX_COM_SCRATCH; 2872 cpu_reg.mips_view_base = 0x8000000; 2873 2874 fw.ver_major = bnx_COM_b09FwReleaseMajor; 2875 fw.ver_minor = bnx_COM_b09FwReleaseMinor; 2876 fw.ver_fix = bnx_COM_b09FwReleaseFix; 2877 fw.start_addr = bnx_COM_b09FwStartAddr; 2878 2879 fw.text_addr = bnx_COM_b09FwTextAddr; 2880 fw.text_len = bnx_COM_b09FwTextLen; 2881 fw.text_index = 0; 2882 fw.text = bnx_COM_b09FwText; 2883 2884 fw.data_addr = bnx_COM_b09FwDataAddr; 2885 fw.data_len = bnx_COM_b09FwDataLen; 2886 fw.data_index = 0; 2887 fw.data = bnx_COM_b09FwData; 2888 2889 fw.sbss_addr = bnx_COM_b09FwSbssAddr; 2890 fw.sbss_len = bnx_COM_b09FwSbssLen; 2891 fw.sbss_index = 0; 2892 fw.sbss = bnx_COM_b09FwSbss; 2893 2894 fw.bss_addr = bnx_COM_b09FwBssAddr; 2895 fw.bss_len = bnx_COM_b09FwBssLen; 2896 fw.bss_index = 0; 2897 fw.bss = bnx_COM_b09FwBss; 2898 2899 fw.rodata_addr = bnx_COM_b09FwRodataAddr; 2900 fw.rodata_len = bnx_COM_b09FwRodataLen; 2901 fw.rodata_index = 0; 2902 fw.rodata = bnx_COM_b09FwRodata; 2903 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 2904 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2905 break; 2906 default: 2907 /* Initialize the RV2P processor. */ 2908 bnx_load_rv2p_fw(sc, bnx_rv2p_proc1, sizeof(bnx_rv2p_proc1), 2909 RV2P_PROC1); 2910 bnx_load_rv2p_fw(sc, bnx_rv2p_proc2, sizeof(bnx_rv2p_proc2), 2911 RV2P_PROC2); 2912 2913 /* Initialize the RX Processor. */ 2914 cpu_reg.mode = BNX_RXP_CPU_MODE; 2915 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 2916 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 2917 cpu_reg.state = BNX_RXP_CPU_STATE; 2918 cpu_reg.state_value_clear = 0xffffff; 2919 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 2920 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 2921 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 2922 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 2923 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 2924 cpu_reg.spad_base = BNX_RXP_SCRATCH; 2925 cpu_reg.mips_view_base = 0x8000000; 2926 2927 fw.ver_major = bnx_RXP_b06FwReleaseMajor; 2928 fw.ver_minor = bnx_RXP_b06FwReleaseMinor; 2929 fw.ver_fix = bnx_RXP_b06FwReleaseFix; 2930 fw.start_addr = bnx_RXP_b06FwStartAddr; 2931 2932 fw.text_addr = bnx_RXP_b06FwTextAddr; 2933 fw.text_len = bnx_RXP_b06FwTextLen; 2934 fw.text_index = 0; 2935 fw.text = bnx_RXP_b06FwText; 2936 2937 fw.data_addr = bnx_RXP_b06FwDataAddr; 2938 fw.data_len = bnx_RXP_b06FwDataLen; 2939 fw.data_index = 0; 2940 fw.data = bnx_RXP_b06FwData; 2941 2942 fw.sbss_addr = bnx_RXP_b06FwSbssAddr; 2943 fw.sbss_len = bnx_RXP_b06FwSbssLen; 2944 fw.sbss_index = 0; 2945 fw.sbss = bnx_RXP_b06FwSbss; 2946 2947 fw.bss_addr = bnx_RXP_b06FwBssAddr; 2948 fw.bss_len = bnx_RXP_b06FwBssLen; 2949 fw.bss_index = 0; 2950 fw.bss = bnx_RXP_b06FwBss; 2951 2952 fw.rodata_addr = bnx_RXP_b06FwRodataAddr; 2953 fw.rodata_len = bnx_RXP_b06FwRodataLen; 2954 fw.rodata_index = 0; 2955 fw.rodata = bnx_RXP_b06FwRodata; 2956 2957 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 2958 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2959 2960 /* Initialize the TX Processor. */ 2961 cpu_reg.mode = BNX_TXP_CPU_MODE; 2962 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 2963 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 2964 cpu_reg.state = BNX_TXP_CPU_STATE; 2965 cpu_reg.state_value_clear = 0xffffff; 2966 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 2967 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 2968 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 2969 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 2970 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 2971 cpu_reg.spad_base = BNX_TXP_SCRATCH; 2972 cpu_reg.mips_view_base = 0x8000000; 2973 2974 fw.ver_major = bnx_TXP_b06FwReleaseMajor; 2975 fw.ver_minor = bnx_TXP_b06FwReleaseMinor; 2976 fw.ver_fix = bnx_TXP_b06FwReleaseFix; 2977 fw.start_addr = bnx_TXP_b06FwStartAddr; 2978 2979 fw.text_addr = bnx_TXP_b06FwTextAddr; 2980 fw.text_len = bnx_TXP_b06FwTextLen; 2981 fw.text_index = 0; 2982 fw.text = bnx_TXP_b06FwText; 2983 2984 fw.data_addr = bnx_TXP_b06FwDataAddr; 2985 fw.data_len = bnx_TXP_b06FwDataLen; 2986 fw.data_index = 0; 2987 fw.data = bnx_TXP_b06FwData; 2988 2989 fw.sbss_addr = bnx_TXP_b06FwSbssAddr; 2990 fw.sbss_len = bnx_TXP_b06FwSbssLen; 2991 fw.sbss_index = 0; 2992 fw.sbss = bnx_TXP_b06FwSbss; 2993 2994 fw.bss_addr = bnx_TXP_b06FwBssAddr; 2995 fw.bss_len = bnx_TXP_b06FwBssLen; 2996 fw.bss_index = 0; 2997 fw.bss = bnx_TXP_b06FwBss; 2998 2999 fw.rodata_addr = bnx_TXP_b06FwRodataAddr; 3000 fw.rodata_len = bnx_TXP_b06FwRodataLen; 3001 fw.rodata_index = 0; 3002 fw.rodata = bnx_TXP_b06FwRodata; 3003 3004 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 3005 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3006 3007 /* Initialize the TX Patch-up Processor. */ 3008 cpu_reg.mode = BNX_TPAT_CPU_MODE; 3009 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 3010 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 3011 cpu_reg.state = BNX_TPAT_CPU_STATE; 3012 cpu_reg.state_value_clear = 0xffffff; 3013 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 3014 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 3015 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 3016 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 3017 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 3018 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 3019 cpu_reg.mips_view_base = 0x8000000; 3020 3021 fw.ver_major = bnx_TPAT_b06FwReleaseMajor; 3022 fw.ver_minor = bnx_TPAT_b06FwReleaseMinor; 3023 fw.ver_fix = bnx_TPAT_b06FwReleaseFix; 3024 fw.start_addr = bnx_TPAT_b06FwStartAddr; 3025 3026 fw.text_addr = bnx_TPAT_b06FwTextAddr; 3027 fw.text_len = bnx_TPAT_b06FwTextLen; 3028 fw.text_index = 0; 3029 fw.text = bnx_TPAT_b06FwText; 3030 3031 fw.data_addr = bnx_TPAT_b06FwDataAddr; 3032 fw.data_len = bnx_TPAT_b06FwDataLen; 3033 fw.data_index = 0; 3034 fw.data = bnx_TPAT_b06FwData; 3035 3036 fw.sbss_addr = bnx_TPAT_b06FwSbssAddr; 3037 fw.sbss_len = bnx_TPAT_b06FwSbssLen; 3038 fw.sbss_index = 0; 3039 fw.sbss = bnx_TPAT_b06FwSbss; 3040 3041 fw.bss_addr = bnx_TPAT_b06FwBssAddr; 3042 fw.bss_len = bnx_TPAT_b06FwBssLen; 3043 fw.bss_index = 0; 3044 fw.bss = bnx_TPAT_b06FwBss; 3045 3046 fw.rodata_addr = bnx_TPAT_b06FwRodataAddr; 3047 fw.rodata_len = bnx_TPAT_b06FwRodataLen; 3048 fw.rodata_index = 0; 3049 fw.rodata = bnx_TPAT_b06FwRodata; 3050 3051 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 3052 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3053 3054 /* Initialize the Completion Processor. */ 3055 cpu_reg.mode = BNX_COM_CPU_MODE; 3056 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 3057 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 3058 cpu_reg.state = BNX_COM_CPU_STATE; 3059 cpu_reg.state_value_clear = 0xffffff; 3060 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 3061 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 3062 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 3063 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 3064 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 3065 cpu_reg.spad_base = BNX_COM_SCRATCH; 3066 cpu_reg.mips_view_base = 0x8000000; 3067 3068 fw.ver_major = bnx_COM_b06FwReleaseMajor; 3069 fw.ver_minor = bnx_COM_b06FwReleaseMinor; 3070 fw.ver_fix = bnx_COM_b06FwReleaseFix; 3071 fw.start_addr = bnx_COM_b06FwStartAddr; 3072 3073 fw.text_addr = bnx_COM_b06FwTextAddr; 3074 fw.text_len = bnx_COM_b06FwTextLen; 3075 fw.text_index = 0; 3076 fw.text = bnx_COM_b06FwText; 3077 3078 fw.data_addr = bnx_COM_b06FwDataAddr; 3079 fw.data_len = bnx_COM_b06FwDataLen; 3080 fw.data_index = 0; 3081 fw.data = bnx_COM_b06FwData; 3082 3083 fw.sbss_addr = bnx_COM_b06FwSbssAddr; 3084 fw.sbss_len = bnx_COM_b06FwSbssLen; 3085 fw.sbss_index = 0; 3086 fw.sbss = bnx_COM_b06FwSbss; 3087 3088 fw.bss_addr = bnx_COM_b06FwBssAddr; 3089 fw.bss_len = bnx_COM_b06FwBssLen; 3090 fw.bss_index = 0; 3091 fw.bss = bnx_COM_b06FwBss; 3092 3093 fw.rodata_addr = bnx_COM_b06FwRodataAddr; 3094 fw.rodata_len = bnx_COM_b06FwRodataLen; 3095 fw.rodata_index = 0; 3096 fw.rodata = bnx_COM_b06FwRodata; 3097 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 3098 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3099 break; 3100 } 3101 } 3102 3103 /****************************************************************************/ 3104 /* Initialize context memory. */ 3105 /* */ 3106 /* Clears the memory associated with each Context ID (CID). */ 3107 /* */ 3108 /* Returns: */ 3109 /* Nothing. */ 3110 /****************************************************************************/ 3111 void 3112 bnx_init_context(struct bnx_softc *sc) 3113 { 3114 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3115 /* DRC: Replace this constant value with a #define. */ 3116 int i, retry_cnt = 10; 3117 u_int32_t val; 3118 3119 /* 3120 * BCM5709 context memory may be cached 3121 * in host memory so prepare the host memory 3122 * for access. 3123 */ 3124 val = BNX_CTX_COMMAND_ENABLED | BNX_CTX_COMMAND_MEM_INIT 3125 | (1 << 12); 3126 val |= (BCM_PAGE_BITS - 8) << 16; 3127 REG_WR(sc, BNX_CTX_COMMAND, val); 3128 3129 /* Wait for mem init command to complete. */ 3130 for (i = 0; i < retry_cnt; i++) { 3131 val = REG_RD(sc, BNX_CTX_COMMAND); 3132 if (!(val & BNX_CTX_COMMAND_MEM_INIT)) 3133 break; 3134 DELAY(2); 3135 } 3136 3137 3138 /* ToDo: Consider returning an error here. */ 3139 3140 for (i = 0; i < sc->ctx_pages; i++) { 3141 int j; 3142 3143 3144 /* Set the physaddr of the context memory cache. */ 3145 val = (u_int32_t)(sc->ctx_segs[i].ds_addr); 3146 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA0, val | 3147 BNX_CTX_HOST_PAGE_TBL_DATA0_VALID); 3148 val = (u_int32_t) 3149 ((u_int64_t)sc->ctx_segs[i].ds_addr >> 32); 3150 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA1, val); 3151 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_CTRL, i | 3152 BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 3153 3154 3155 /* Verify that the context memory write was successful. */ 3156 for (j = 0; j < retry_cnt; j++) { 3157 val = REG_RD(sc, BNX_CTX_HOST_PAGE_TBL_CTRL); 3158 if ((val & BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 3159 break; 3160 DELAY(5); 3161 } 3162 3163 /* ToDo: Consider returning an error here. */ 3164 } 3165 } else { 3166 u_int32_t vcid_addr, offset; 3167 3168 /* 3169 * For the 5706/5708, context memory is local to 3170 * the controller, so initialize the controller 3171 * context memory. 3172 */ 3173 3174 vcid_addr = GET_CID_ADDR(96); 3175 while (vcid_addr) { 3176 3177 vcid_addr -= BNX_PHY_CTX_SIZE; 3178 3179 REG_WR(sc, BNX_CTX_VIRT_ADDR, 0); 3180 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3181 3182 for(offset = 0; offset < BNX_PHY_CTX_SIZE; offset += 4) { 3183 CTX_WR(sc, 0x00, offset, 0); 3184 } 3185 3186 REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr); 3187 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3188 } 3189 } 3190 } 3191 3192 /****************************************************************************/ 3193 /* Fetch the permanent MAC address of the controller. */ 3194 /* */ 3195 /* Returns: */ 3196 /* Nothing. */ 3197 /****************************************************************************/ 3198 void 3199 bnx_get_mac_addr(struct bnx_softc *sc) 3200 { 3201 u_int32_t mac_lo = 0, mac_hi = 0; 3202 3203 /* 3204 * The NetXtreme II bootcode populates various NIC 3205 * power-on and runtime configuration items in a 3206 * shared memory area. The factory configured MAC 3207 * address is available from both NVRAM and the 3208 * shared memory area so we'll read the value from 3209 * shared memory for speed. 3210 */ 3211 3212 mac_hi = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_UPPER); 3213 mac_lo = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_LOWER); 3214 3215 if ((mac_lo == 0) && (mac_hi == 0)) { 3216 BNX_PRINTF(sc, "%s(%d): Invalid Ethernet address!\n", 3217 __FILE__, __LINE__); 3218 } else { 3219 sc->eaddr[0] = (u_char)(mac_hi >> 8); 3220 sc->eaddr[1] = (u_char)(mac_hi >> 0); 3221 sc->eaddr[2] = (u_char)(mac_lo >> 24); 3222 sc->eaddr[3] = (u_char)(mac_lo >> 16); 3223 sc->eaddr[4] = (u_char)(mac_lo >> 8); 3224 sc->eaddr[5] = (u_char)(mac_lo >> 0); 3225 } 3226 3227 DBPRINT(sc, BNX_INFO, "Permanent Ethernet address = " 3228 "%s\n", ether_sprintf(sc->eaddr)); 3229 } 3230 3231 /****************************************************************************/ 3232 /* Program the MAC address. */ 3233 /* */ 3234 /* Returns: */ 3235 /* Nothing. */ 3236 /****************************************************************************/ 3237 void 3238 bnx_set_mac_addr(struct bnx_softc *sc) 3239 { 3240 u_int32_t val; 3241 const u_int8_t *mac_addr = CLLADDR(sc->bnx_ec.ec_if.if_sadl); 3242 3243 DBPRINT(sc, BNX_INFO, "Setting Ethernet address = " 3244 "%s\n", ether_sprintf(sc->eaddr)); 3245 3246 val = (mac_addr[0] << 8) | mac_addr[1]; 3247 3248 REG_WR(sc, BNX_EMAC_MAC_MATCH0, val); 3249 3250 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 3251 (mac_addr[4] << 8) | mac_addr[5]; 3252 3253 REG_WR(sc, BNX_EMAC_MAC_MATCH1, val); 3254 } 3255 3256 /****************************************************************************/ 3257 /* Stop the controller. */ 3258 /* */ 3259 /* Returns: */ 3260 /* Nothing. */ 3261 /****************************************************************************/ 3262 void 3263 bnx_stop(struct ifnet *ifp, int disable) 3264 { 3265 struct bnx_softc *sc = ifp->if_softc; 3266 3267 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3268 3269 if ((ifp->if_flags & IFF_RUNNING) == 0) 3270 return; 3271 3272 callout_stop(&sc->bnx_timeout); 3273 3274 mii_down(&sc->bnx_mii); 3275 3276 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3277 3278 /* Disable the transmit/receive blocks. */ 3279 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 3280 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3281 DELAY(20); 3282 3283 bnx_disable_intr(sc); 3284 3285 /* Tell firmware that the driver is going away. */ 3286 if (disable) 3287 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 3288 else 3289 bnx_reset(sc, BNX_DRV_MSG_CODE_SUSPEND_NO_WOL); 3290 3291 /* Free RX buffers. */ 3292 bnx_free_rx_chain(sc); 3293 3294 /* Free TX buffers. */ 3295 bnx_free_tx_chain(sc); 3296 3297 ifp->if_timer = 0; 3298 3299 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3300 3301 } 3302 3303 int 3304 bnx_reset(struct bnx_softc *sc, u_int32_t reset_code) 3305 { 3306 struct pci_attach_args *pa = &(sc->bnx_pa); 3307 u_int32_t val; 3308 int i, rc = 0; 3309 3310 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3311 3312 /* Wait for pending PCI transactions to complete. */ 3313 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 3314 BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 3315 BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 3316 BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 3317 BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 3318 val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3319 DELAY(5); 3320 3321 /* Disable DMA */ 3322 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3323 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3324 val &= ~BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3325 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3326 } 3327 3328 /* Assume bootcode is running. */ 3329 sc->bnx_fw_timed_out = 0; 3330 3331 /* Give the firmware a chance to prepare for the reset. */ 3332 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT0 | reset_code); 3333 if (rc) 3334 goto bnx_reset_exit; 3335 3336 /* Set a firmware reminder that this is a soft reset. */ 3337 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_RESET_SIGNATURE, 3338 BNX_DRV_RESET_SIGNATURE_MAGIC); 3339 3340 /* Dummy read to force the chip to complete all current transactions. */ 3341 val = REG_RD(sc, BNX_MISC_ID); 3342 3343 /* Chip reset. */ 3344 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3345 REG_WR(sc, BNX_MISC_COMMAND, BNX_MISC_COMMAND_SW_RESET); 3346 REG_RD(sc, BNX_MISC_COMMAND); 3347 DELAY(5); 3348 3349 val = BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3350 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3351 3352 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 3353 val); 3354 } else { 3355 val = BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3356 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3357 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3358 REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val); 3359 3360 /* Allow up to 30us for reset to complete. */ 3361 for (i = 0; i < 10; i++) { 3362 val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG); 3363 if ((val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3364 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 3365 break; 3366 } 3367 DELAY(10); 3368 } 3369 3370 /* Check that reset completed successfully. */ 3371 if (val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3372 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 3373 BNX_PRINTF(sc, "%s(%d): Reset failed!\n", 3374 __FILE__, __LINE__); 3375 rc = EBUSY; 3376 goto bnx_reset_exit; 3377 } 3378 } 3379 3380 /* Make sure byte swapping is properly configured. */ 3381 val = REG_RD(sc, BNX_PCI_SWAP_DIAG0); 3382 if (val != 0x01020304) { 3383 BNX_PRINTF(sc, "%s(%d): Byte swap is incorrect!\n", 3384 __FILE__, __LINE__); 3385 rc = ENODEV; 3386 goto bnx_reset_exit; 3387 } 3388 3389 /* Just completed a reset, assume that firmware is running again. */ 3390 sc->bnx_fw_timed_out = 0; 3391 3392 /* Wait for the firmware to finish its initialization. */ 3393 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT1 | reset_code); 3394 if (rc) 3395 BNX_PRINTF(sc, "%s(%d): Firmware did not complete " 3396 "initialization!\n", __FILE__, __LINE__); 3397 3398 bnx_reset_exit: 3399 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3400 3401 return (rc); 3402 } 3403 3404 int 3405 bnx_chipinit(struct bnx_softc *sc) 3406 { 3407 struct pci_attach_args *pa = &(sc->bnx_pa); 3408 u_int32_t val; 3409 int rc = 0; 3410 3411 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3412 3413 /* Make sure the interrupt is not active. */ 3414 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 3415 3416 /* Initialize DMA byte/word swapping, configure the number of DMA */ 3417 /* channels and PCI clock compensation delay. */ 3418 val = BNX_DMA_CONFIG_DATA_BYTE_SWAP | 3419 BNX_DMA_CONFIG_DATA_WORD_SWAP | 3420 #if BYTE_ORDER == BIG_ENDIAN 3421 BNX_DMA_CONFIG_CNTL_BYTE_SWAP | 3422 #endif 3423 BNX_DMA_CONFIG_CNTL_WORD_SWAP | 3424 DMA_READ_CHANS << 12 | 3425 DMA_WRITE_CHANS << 16; 3426 3427 val |= (0x2 << 20) | BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY; 3428 3429 if ((sc->bnx_flags & BNX_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 3430 val |= BNX_DMA_CONFIG_PCI_FAST_CLK_CMP; 3431 3432 /* 3433 * This setting resolves a problem observed on certain Intel PCI 3434 * chipsets that cannot handle multiple outstanding DMA operations. 3435 * See errata E9_5706A1_65. 3436 */ 3437 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 3438 (BNX_CHIP_ID(sc) != BNX_CHIP_ID_5706_A0) && 3439 !(sc->bnx_flags & BNX_PCIX_FLAG)) 3440 val |= BNX_DMA_CONFIG_CNTL_PING_PONG_DMA; 3441 3442 REG_WR(sc, BNX_DMA_CONFIG, val); 3443 3444 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ 3445 if (sc->bnx_flags & BNX_PCIX_FLAG) { 3446 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD); 3447 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD, 3448 val & ~0x20000); 3449 } 3450 3451 /* Enable the RX_V2P and Context state machines before access. */ 3452 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3453 BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 3454 BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 3455 BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 3456 3457 /* Initialize context mapping and zero out the quick contexts. */ 3458 bnx_init_context(sc); 3459 3460 /* Initialize the on-boards CPUs */ 3461 bnx_init_cpus(sc); 3462 3463 /* Prepare NVRAM for access. */ 3464 if (bnx_init_nvram(sc)) { 3465 rc = ENODEV; 3466 goto bnx_chipinit_exit; 3467 } 3468 3469 /* Set the kernel bypass block size */ 3470 val = REG_RD(sc, BNX_MQ_CONFIG); 3471 val &= ~BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE; 3472 val |= BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 3473 3474 /* Enable bins used on the 5709. */ 3475 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3476 val |= BNX_MQ_CONFIG_BIN_MQ_MODE; 3477 if (BNX_CHIP_ID(sc) == BNX_CHIP_ID_5709_A1) 3478 val |= BNX_MQ_CONFIG_HALT_DIS; 3479 } 3480 3481 REG_WR(sc, BNX_MQ_CONFIG, val); 3482 3483 val = 0x10000 + (MAX_CID_CNT * BNX_MB_KERNEL_CTX_SIZE); 3484 REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val); 3485 REG_WR(sc, BNX_MQ_KNL_WIND_END, val); 3486 3487 val = (BCM_PAGE_BITS - 8) << 24; 3488 REG_WR(sc, BNX_RV2P_CONFIG, val); 3489 3490 /* Configure page size. */ 3491 val = REG_RD(sc, BNX_TBDR_CONFIG); 3492 val &= ~BNX_TBDR_CONFIG_PAGE_SIZE; 3493 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 3494 REG_WR(sc, BNX_TBDR_CONFIG, val); 3495 3496 #if 0 3497 /* Set the perfect match control register to default. */ 3498 REG_WR_IND(sc, BNX_RXP_PM_CTRL, 0); 3499 #endif 3500 3501 bnx_chipinit_exit: 3502 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3503 3504 return(rc); 3505 } 3506 3507 /****************************************************************************/ 3508 /* Initialize the controller in preparation to send/receive traffic. */ 3509 /* */ 3510 /* Returns: */ 3511 /* 0 for success, positive value for failure. */ 3512 /****************************************************************************/ 3513 int 3514 bnx_blockinit(struct bnx_softc *sc) 3515 { 3516 u_int32_t reg, val; 3517 int rc = 0; 3518 3519 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3520 3521 /* Load the hardware default MAC address. */ 3522 bnx_set_mac_addr(sc); 3523 3524 /* Set the Ethernet backoff seed value */ 3525 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) + 3526 (sc->eaddr[3]) + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 3527 REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val); 3528 3529 sc->last_status_idx = 0; 3530 sc->rx_mode = BNX_EMAC_RX_MODE_SORT_MODE; 3531 3532 /* Set up link change interrupt generation. */ 3533 REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK); 3534 REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3535 3536 /* Program the physical address of the status block. */ 3537 REG_WR(sc, BNX_HC_STATUS_ADDR_L, (u_int32_t)(sc->status_block_paddr)); 3538 REG_WR(sc, BNX_HC_STATUS_ADDR_H, 3539 (u_int32_t)((u_int64_t)sc->status_block_paddr >> 32)); 3540 3541 /* Program the physical address of the statistics block. */ 3542 REG_WR(sc, BNX_HC_STATISTICS_ADDR_L, 3543 (u_int32_t)(sc->stats_block_paddr)); 3544 REG_WR(sc, BNX_HC_STATISTICS_ADDR_H, 3545 (u_int32_t)((u_int64_t)sc->stats_block_paddr >> 32)); 3546 3547 /* Program various host coalescing parameters. */ 3548 REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int 3549 << 16) | sc->bnx_tx_quick_cons_trip); 3550 REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int 3551 << 16) | sc->bnx_rx_quick_cons_trip); 3552 REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) | 3553 sc->bnx_comp_prod_trip); 3554 REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) | 3555 sc->bnx_tx_ticks); 3556 REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) | 3557 sc->bnx_rx_ticks); 3558 REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) | 3559 sc->bnx_com_ticks); 3560 REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) | 3561 sc->bnx_cmd_ticks); 3562 REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00)); 3563 REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 3564 REG_WR(sc, BNX_HC_CONFIG, 3565 (BNX_HC_CONFIG_RX_TMR_MODE | BNX_HC_CONFIG_TX_TMR_MODE | 3566 BNX_HC_CONFIG_COLLECT_STATS)); 3567 3568 /* Clear the internal statistics counters. */ 3569 REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW); 3570 3571 /* Verify that bootcode is running. */ 3572 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE); 3573 3574 DBRUNIF(DB_RANDOMTRUE(bnx_debug_bootcode_running_failure), 3575 BNX_PRINTF(sc, "%s(%d): Simulating bootcode failure.\n", 3576 __FILE__, __LINE__); reg = 0); 3577 3578 if ((reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK) != 3579 BNX_DEV_INFO_SIGNATURE_MAGIC) { 3580 BNX_PRINTF(sc, "%s(%d): Bootcode not running! Found: 0x%08X, " 3581 "Expected: 08%08X\n", __FILE__, __LINE__, 3582 (reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK), 3583 BNX_DEV_INFO_SIGNATURE_MAGIC); 3584 rc = ENODEV; 3585 goto bnx_blockinit_exit; 3586 } 3587 3588 /* Check if any management firmware is running. */ 3589 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE); 3590 if (reg & (BNX_PORT_FEATURE_ASF_ENABLED | 3591 BNX_PORT_FEATURE_IMD_ENABLED)) { 3592 DBPRINT(sc, BNX_INFO, "Management F/W Enabled.\n"); 3593 sc->bnx_flags |= BNX_MFW_ENABLE_FLAG; 3594 } 3595 3596 sc->bnx_fw_ver = REG_RD_IND(sc, sc->bnx_shmem_base + 3597 BNX_DEV_INFO_BC_REV); 3598 3599 DBPRINT(sc, BNX_INFO, "bootcode rev = 0x%08X\n", sc->bnx_fw_ver); 3600 3601 /* Enable DMA */ 3602 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3603 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3604 val |= BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3605 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3606 } 3607 3608 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 3609 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT2 | BNX_DRV_MSG_CODE_RESET); 3610 3611 /* Enable link state change interrupt generation. */ 3612 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3613 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3614 BNX_MISC_ENABLE_DEFAULT_XI); 3615 } else 3616 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, BNX_MISC_ENABLE_DEFAULT); 3617 3618 /* Enable all remaining blocks in the MAC. */ 3619 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 0x5ffffff); 3620 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 3621 DELAY(20); 3622 3623 bnx_blockinit_exit: 3624 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3625 3626 return (rc); 3627 } 3628 3629 static int 3630 bnx_add_buf(struct bnx_softc *sc, struct mbuf *m_new, u_int16_t *prod, 3631 u_int16_t *chain_prod, u_int32_t *prod_bseq) 3632 { 3633 bus_dmamap_t map; 3634 struct rx_bd *rxbd; 3635 u_int32_t addr; 3636 int i; 3637 #ifdef BNX_DEBUG 3638 u_int16_t debug_chain_prod = *chain_prod; 3639 #endif 3640 u_int16_t first_chain_prod; 3641 3642 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3643 3644 /* Map the mbuf cluster into device memory. */ 3645 map = sc->rx_mbuf_map[*chain_prod]; 3646 first_chain_prod = *chain_prod; 3647 if (bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m_new, BUS_DMA_NOWAIT)) { 3648 BNX_PRINTF(sc, "%s(%d): Error mapping mbuf into RX chain!\n", 3649 __FILE__, __LINE__); 3650 3651 m_freem(m_new); 3652 3653 DBRUNIF(1, sc->rx_mbuf_alloc--); 3654 3655 return ENOBUFS; 3656 } 3657 /* Make sure there is room in the receive chain. */ 3658 if (map->dm_nsegs > sc->free_rx_bd) { 3659 bus_dmamap_unload(sc->bnx_dmatag, map); 3660 m_freem(m_new); 3661 return EFBIG; 3662 } 3663 #ifdef BNX_DEBUG 3664 /* Track the distribution of buffer segments. */ 3665 sc->rx_mbuf_segs[map->dm_nsegs]++; 3666 #endif 3667 3668 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 3669 BUS_DMASYNC_PREREAD); 3670 3671 /* Update some debug statistics counters */ 3672 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3673 sc->rx_low_watermark = sc->free_rx_bd); 3674 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++); 3675 3676 /* 3677 * Setup the rx_bd for the first segment 3678 */ 3679 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3680 3681 addr = (u_int32_t)map->dm_segs[0].ds_addr; 3682 rxbd->rx_bd_haddr_lo = addr; 3683 addr = (u_int32_t)((u_int64_t)map->dm_segs[0].ds_addr >> 32); 3684 rxbd->rx_bd_haddr_hi = addr; 3685 rxbd->rx_bd_len = map->dm_segs[0].ds_len; 3686 rxbd->rx_bd_flags = RX_BD_FLAGS_START; 3687 *prod_bseq += map->dm_segs[0].ds_len; 3688 bus_dmamap_sync(sc->bnx_dmatag, 3689 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3690 sizeof(struct rx_bd) * RX_IDX(*chain_prod), sizeof(struct rx_bd), 3691 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3692 3693 for (i = 1; i < map->dm_nsegs; i++) { 3694 *prod = NEXT_RX_BD(*prod); 3695 *chain_prod = RX_CHAIN_IDX(*prod); 3696 3697 rxbd = 3698 &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3699 3700 addr = (u_int32_t)map->dm_segs[i].ds_addr; 3701 rxbd->rx_bd_haddr_lo = addr; 3702 addr = (u_int32_t)((u_int64_t)map->dm_segs[i].ds_addr >> 32); 3703 rxbd->rx_bd_haddr_hi = addr; 3704 rxbd->rx_bd_len = map->dm_segs[i].ds_len; 3705 rxbd->rx_bd_flags = 0; 3706 *prod_bseq += map->dm_segs[i].ds_len; 3707 bus_dmamap_sync(sc->bnx_dmatag, 3708 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3709 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3710 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3711 } 3712 3713 rxbd->rx_bd_flags |= RX_BD_FLAGS_END; 3714 bus_dmamap_sync(sc->bnx_dmatag, 3715 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3716 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3717 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3718 3719 /* 3720 * Save the mbuf, ajust the map pointer (swap map for first and 3721 * last rx_bd entry to that rx_mbuf_ptr and rx_mbuf_map matches) 3722 * and update counter. 3723 */ 3724 sc->rx_mbuf_ptr[*chain_prod] = m_new; 3725 sc->rx_mbuf_map[first_chain_prod] = sc->rx_mbuf_map[*chain_prod]; 3726 sc->rx_mbuf_map[*chain_prod] = map; 3727 sc->free_rx_bd -= map->dm_nsegs; 3728 3729 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_mbuf_chain(sc, debug_chain_prod, 3730 map->dm_nsegs)); 3731 *prod = NEXT_RX_BD(*prod); 3732 *chain_prod = RX_CHAIN_IDX(*prod); 3733 3734 return 0; 3735 } 3736 3737 /****************************************************************************/ 3738 /* Encapsulate an mbuf cluster into the rx_bd chain. */ 3739 /* */ 3740 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ 3741 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */ 3742 /* necessary. */ 3743 /* */ 3744 /* Returns: */ 3745 /* 0 for success, positive value for failure. */ 3746 /****************************************************************************/ 3747 int 3748 bnx_get_buf(struct bnx_softc *sc, u_int16_t *prod, 3749 u_int16_t *chain_prod, u_int32_t *prod_bseq) 3750 { 3751 struct mbuf *m_new = NULL; 3752 int rc = 0; 3753 u_int16_t min_free_bd; 3754 3755 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Entering %s()\n", 3756 __func__); 3757 3758 /* Make sure the inputs are valid. */ 3759 DBRUNIF((*chain_prod > MAX_RX_BD), 3760 aprint_error_dev(sc->bnx_dev, 3761 "RX producer out of range: 0x%04X > 0x%04X\n", 3762 *chain_prod, (u_int16_t)MAX_RX_BD)); 3763 3764 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = " 3765 "0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, 3766 *prod_bseq); 3767 3768 /* try to get in as many mbufs as possible */ 3769 if (sc->mbuf_alloc_size == MCLBYTES) 3770 min_free_bd = (MCLBYTES + PAGE_SIZE - 1) / PAGE_SIZE; 3771 else 3772 min_free_bd = (BNX_MAX_JUMBO_MRU + PAGE_SIZE - 1) / PAGE_SIZE; 3773 while (sc->free_rx_bd >= min_free_bd) { 3774 /* Simulate an mbuf allocation failure. */ 3775 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3776 aprint_error_dev(sc->bnx_dev, 3777 "Simulating mbuf allocation failure.\n"); 3778 sc->mbuf_sim_alloc_failed++; 3779 rc = ENOBUFS; 3780 goto bnx_get_buf_exit); 3781 3782 /* This is a new mbuf allocation. */ 3783 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3784 if (m_new == NULL) { 3785 DBPRINT(sc, BNX_WARN, 3786 "%s(%d): RX mbuf header allocation failed!\n", 3787 __FILE__, __LINE__); 3788 3789 sc->mbuf_alloc_failed++; 3790 3791 rc = ENOBUFS; 3792 goto bnx_get_buf_exit; 3793 } 3794 3795 DBRUNIF(1, sc->rx_mbuf_alloc++); 3796 3797 /* Simulate an mbuf cluster allocation failure. */ 3798 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3799 m_freem(m_new); 3800 sc->rx_mbuf_alloc--; 3801 sc->mbuf_alloc_failed++; 3802 sc->mbuf_sim_alloc_failed++; 3803 rc = ENOBUFS; 3804 goto bnx_get_buf_exit); 3805 3806 if (sc->mbuf_alloc_size == MCLBYTES) 3807 MCLGET(m_new, M_DONTWAIT); 3808 else 3809 MEXTMALLOC(m_new, sc->mbuf_alloc_size, 3810 M_DONTWAIT); 3811 if (!(m_new->m_flags & M_EXT)) { 3812 DBPRINT(sc, BNX_WARN, 3813 "%s(%d): RX mbuf chain allocation failed!\n", 3814 __FILE__, __LINE__); 3815 3816 m_freem(m_new); 3817 3818 DBRUNIF(1, sc->rx_mbuf_alloc--); 3819 sc->mbuf_alloc_failed++; 3820 3821 rc = ENOBUFS; 3822 goto bnx_get_buf_exit; 3823 } 3824 3825 rc = bnx_add_buf(sc, m_new, prod, chain_prod, prod_bseq); 3826 if (rc != 0) 3827 goto bnx_get_buf_exit; 3828 } 3829 3830 bnx_get_buf_exit: 3831 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod " 3832 "= 0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, 3833 *chain_prod, *prod_bseq); 3834 3835 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Exiting %s()\n", 3836 __func__); 3837 3838 return(rc); 3839 } 3840 3841 int 3842 bnx_alloc_pkts(struct bnx_softc *sc) 3843 { 3844 struct ifnet *ifp = &sc->bnx_ec.ec_if; 3845 struct bnx_pkt *pkt; 3846 int i; 3847 3848 for (i = 0; i < 4; i++) { /* magic! */ 3849 pkt = pool_get(bnx_tx_pool, PR_NOWAIT); 3850 if (pkt == NULL) 3851 break; 3852 3853 if (bus_dmamap_create(sc->bnx_dmatag, 3854 MCLBYTES * BNX_MAX_SEGMENTS, USABLE_TX_BD, 3855 MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 3856 &pkt->pkt_dmamap) != 0) 3857 goto put; 3858 3859 if (!ISSET(ifp->if_flags, IFF_UP)) 3860 goto stopping; 3861 3862 mutex_enter(&sc->tx_pkt_mtx); 3863 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 3864 sc->tx_pkt_count++; 3865 mutex_exit(&sc->tx_pkt_mtx); 3866 } 3867 3868 return (i == 0) ? ENOMEM : 0; 3869 3870 stopping: 3871 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 3872 put: 3873 pool_put(bnx_tx_pool, pkt); 3874 return (i == 0) ? ENOMEM : 0; 3875 } 3876 3877 /****************************************************************************/ 3878 /* Initialize the TX context memory. */ 3879 /* */ 3880 /* Returns: */ 3881 /* Nothing */ 3882 /****************************************************************************/ 3883 void 3884 bnx_init_tx_context(struct bnx_softc *sc) 3885 { 3886 u_int32_t val; 3887 3888 /* Initialize the context ID for an L2 TX chain. */ 3889 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3890 /* Set the CID type to support an L2 connection. */ 3891 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 3892 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE_XI, val); 3893 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 3894 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE_XI, val); 3895 3896 /* Point the hardware to the first page in the chain. */ 3897 val = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[0] >> 32); 3898 CTX_WR(sc, GET_CID_ADDR(TX_CID), 3899 BNX_L2CTX_TBDR_BHADDR_HI_XI, val); 3900 val = (u_int32_t)(sc->tx_bd_chain_paddr[0]); 3901 CTX_WR(sc, GET_CID_ADDR(TX_CID), 3902 BNX_L2CTX_TBDR_BHADDR_LO_XI, val); 3903 } else { 3904 /* Set the CID type to support an L2 connection. */ 3905 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 3906 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE, val); 3907 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 3908 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE, val); 3909 3910 /* Point the hardware to the first page in the chain. */ 3911 val = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[0] >> 32); 3912 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_HI, val); 3913 val = (u_int32_t)(sc->tx_bd_chain_paddr[0]); 3914 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_LO, val); 3915 } 3916 } 3917 3918 3919 /****************************************************************************/ 3920 /* Allocate memory and initialize the TX data structures. */ 3921 /* */ 3922 /* Returns: */ 3923 /* 0 for success, positive value for failure. */ 3924 /****************************************************************************/ 3925 int 3926 bnx_init_tx_chain(struct bnx_softc *sc) 3927 { 3928 struct tx_bd *txbd; 3929 u_int32_t addr; 3930 int i, rc = 0; 3931 3932 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3933 3934 /* Force an allocation of some dmamaps for tx up front */ 3935 bnx_alloc_pkts(sc); 3936 3937 /* Set the initial TX producer/consumer indices. */ 3938 sc->tx_prod = 0; 3939 sc->tx_cons = 0; 3940 sc->tx_prod_bseq = 0; 3941 sc->used_tx_bd = 0; 3942 sc->max_tx_bd = USABLE_TX_BD; 3943 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); 3944 DBRUNIF(1, sc->tx_full_count = 0); 3945 3946 /* 3947 * The NetXtreme II supports a linked-list structure called 3948 * a Buffer Descriptor Chain (or BD chain). A BD chain 3949 * consists of a series of 1 or more chain pages, each of which 3950 * consists of a fixed number of BD entries. 3951 * The last BD entry on each page is a pointer to the next page 3952 * in the chain, and the last pointer in the BD chain 3953 * points back to the beginning of the chain. 3954 */ 3955 3956 /* Set the TX next pointer chain entries. */ 3957 for (i = 0; i < TX_PAGES; i++) { 3958 int j; 3959 3960 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 3961 3962 /* Check if we've reached the last page. */ 3963 if (i == (TX_PAGES - 1)) 3964 j = 0; 3965 else 3966 j = i + 1; 3967 3968 addr = (u_int32_t)sc->tx_bd_chain_paddr[j]; 3969 txbd->tx_bd_haddr_lo = addr; 3970 addr = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[j] >> 32); 3971 txbd->tx_bd_haddr_hi = addr; 3972 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 3973 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 3974 } 3975 3976 /* 3977 * Initialize the context ID for an L2 TX chain. 3978 */ 3979 bnx_init_tx_context(sc); 3980 3981 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3982 3983 return(rc); 3984 } 3985 3986 /****************************************************************************/ 3987 /* Free memory and clear the TX data structures. */ 3988 /* */ 3989 /* Returns: */ 3990 /* Nothing. */ 3991 /****************************************************************************/ 3992 void 3993 bnx_free_tx_chain(struct bnx_softc *sc) 3994 { 3995 struct bnx_pkt *pkt; 3996 int i; 3997 3998 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3999 4000 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 4001 mutex_enter(&sc->tx_pkt_mtx); 4002 while ((pkt = TAILQ_FIRST(&sc->tx_used_pkts)) != NULL) { 4003 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4004 mutex_exit(&sc->tx_pkt_mtx); 4005 4006 bus_dmamap_sync(sc->bnx_dmatag, pkt->pkt_dmamap, 0, 4007 pkt->pkt_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4008 bus_dmamap_unload(sc->bnx_dmatag, pkt->pkt_dmamap); 4009 4010 m_freem(pkt->pkt_mbuf); 4011 DBRUNIF(1, sc->tx_mbuf_alloc--); 4012 4013 mutex_enter(&sc->tx_pkt_mtx); 4014 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4015 } 4016 4017 /* Destroy all the dmamaps we allocated for TX */ 4018 while ((pkt = TAILQ_FIRST(&sc->tx_free_pkts)) != NULL) { 4019 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 4020 sc->tx_pkt_count--; 4021 mutex_exit(&sc->tx_pkt_mtx); 4022 4023 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 4024 pool_put(bnx_tx_pool, pkt); 4025 4026 mutex_enter(&sc->tx_pkt_mtx); 4027 } 4028 mutex_exit(&sc->tx_pkt_mtx); 4029 4030 4031 4032 /* Clear each TX chain page. */ 4033 for (i = 0; i < TX_PAGES; i++) { 4034 memset((char *)sc->tx_bd_chain[i], 0, BNX_TX_CHAIN_PAGE_SZ); 4035 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 4036 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 4037 } 4038 4039 sc->used_tx_bd = 0; 4040 4041 /* Check if we lost any mbufs in the process. */ 4042 DBRUNIF((sc->tx_mbuf_alloc), 4043 aprint_error_dev(sc->bnx_dev, 4044 "Memory leak! Lost %d mbufs from tx chain!\n", 4045 sc->tx_mbuf_alloc)); 4046 4047 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4048 } 4049 4050 /****************************************************************************/ 4051 /* Initialize the RX context memory. */ 4052 /* */ 4053 /* Returns: */ 4054 /* Nothing */ 4055 /****************************************************************************/ 4056 void 4057 bnx_init_rx_context(struct bnx_softc *sc) 4058 { 4059 u_int32_t val; 4060 4061 /* Initialize the context ID for an L2 RX chain. */ 4062 val = BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 4063 BNX_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8); 4064 4065 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4066 u_int32_t lo_water, hi_water; 4067 4068 lo_water = BNX_L2CTX_RX_LO_WATER_MARK_DEFAULT; 4069 hi_water = USABLE_RX_BD / 4; 4070 4071 lo_water /= BNX_L2CTX_RX_LO_WATER_MARK_SCALE; 4072 hi_water /= BNX_L2CTX_RX_HI_WATER_MARK_SCALE; 4073 4074 if (hi_water > 0xf) 4075 hi_water = 0xf; 4076 else if (hi_water == 0) 4077 lo_water = 0; 4078 val |= lo_water | 4079 (hi_water << BNX_L2CTX_RX_HI_WATER_MARK_SHIFT); 4080 } 4081 4082 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_CTX_TYPE, val); 4083 4084 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 4085 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4086 val = REG_RD(sc, BNX_MQ_MAP_L2_5); 4087 REG_WR(sc, BNX_MQ_MAP_L2_5, val | BNX_MQ_MAP_L2_5_ARM); 4088 } 4089 4090 /* Point the hardware to the first page in the chain. */ 4091 val = (u_int32_t)((u_int64_t)sc->rx_bd_chain_paddr[0] >> 32); 4092 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_HI, val); 4093 val = (u_int32_t)(sc->rx_bd_chain_paddr[0]); 4094 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_LO, val); 4095 } 4096 4097 /****************************************************************************/ 4098 /* Allocate memory and initialize the RX data structures. */ 4099 /* */ 4100 /* Returns: */ 4101 /* 0 for success, positive value for failure. */ 4102 /****************************************************************************/ 4103 int 4104 bnx_init_rx_chain(struct bnx_softc *sc) 4105 { 4106 struct rx_bd *rxbd; 4107 int i, rc = 0; 4108 u_int16_t prod, chain_prod; 4109 u_int32_t prod_bseq, addr; 4110 4111 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4112 4113 /* Initialize the RX producer and consumer indices. */ 4114 sc->rx_prod = 0; 4115 sc->rx_cons = 0; 4116 sc->rx_prod_bseq = 0; 4117 sc->free_rx_bd = USABLE_RX_BD; 4118 sc->max_rx_bd = USABLE_RX_BD; 4119 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); 4120 DBRUNIF(1, sc->rx_empty_count = 0); 4121 4122 /* Initialize the RX next pointer chain entries. */ 4123 for (i = 0; i < RX_PAGES; i++) { 4124 int j; 4125 4126 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 4127 4128 /* Check if we've reached the last page. */ 4129 if (i == (RX_PAGES - 1)) 4130 j = 0; 4131 else 4132 j = i + 1; 4133 4134 /* Setup the chain page pointers. */ 4135 addr = (u_int32_t)((u_int64_t)sc->rx_bd_chain_paddr[j] >> 32); 4136 rxbd->rx_bd_haddr_hi = addr; 4137 addr = (u_int32_t)sc->rx_bd_chain_paddr[j]; 4138 rxbd->rx_bd_haddr_lo = addr; 4139 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 4140 0, BNX_RX_CHAIN_PAGE_SZ, 4141 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4142 } 4143 4144 /* Allocate mbuf clusters for the rx_bd chain. */ 4145 prod = prod_bseq = 0; 4146 chain_prod = RX_CHAIN_IDX(prod); 4147 if (bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq)) { 4148 BNX_PRINTF(sc, 4149 "Error filling RX chain: rx_bd[0x%04X]!\n", chain_prod); 4150 } 4151 4152 /* Save the RX chain producer index. */ 4153 sc->rx_prod = prod; 4154 sc->rx_prod_bseq = prod_bseq; 4155 4156 for (i = 0; i < RX_PAGES; i++) 4157 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 0, 4158 sc->rx_bd_chain_map[i]->dm_mapsize, 4159 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4160 4161 /* Tell the chip about the waiting rx_bd's. */ 4162 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4163 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4164 4165 bnx_init_rx_context(sc); 4166 4167 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 4168 4169 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4170 4171 return(rc); 4172 } 4173 4174 /****************************************************************************/ 4175 /* Free memory and clear the RX data structures. */ 4176 /* */ 4177 /* Returns: */ 4178 /* Nothing. */ 4179 /****************************************************************************/ 4180 void 4181 bnx_free_rx_chain(struct bnx_softc *sc) 4182 { 4183 int i; 4184 4185 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4186 4187 /* Free any mbufs still in the RX mbuf chain. */ 4188 for (i = 0; i < TOTAL_RX_BD; i++) { 4189 if (sc->rx_mbuf_ptr[i] != NULL) { 4190 if (sc->rx_mbuf_map[i] != NULL) { 4191 bus_dmamap_sync(sc->bnx_dmatag, 4192 sc->rx_mbuf_map[i], 0, 4193 sc->rx_mbuf_map[i]->dm_mapsize, 4194 BUS_DMASYNC_POSTREAD); 4195 bus_dmamap_unload(sc->bnx_dmatag, 4196 sc->rx_mbuf_map[i]); 4197 } 4198 m_freem(sc->rx_mbuf_ptr[i]); 4199 sc->rx_mbuf_ptr[i] = NULL; 4200 DBRUNIF(1, sc->rx_mbuf_alloc--); 4201 } 4202 } 4203 4204 /* Clear each RX chain page. */ 4205 for (i = 0; i < RX_PAGES; i++) 4206 memset((char *)sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 4207 4208 sc->free_rx_bd = sc->max_rx_bd; 4209 4210 /* Check if we lost any mbufs in the process. */ 4211 DBRUNIF((sc->rx_mbuf_alloc), 4212 aprint_error_dev(sc->bnx_dev, 4213 "Memory leak! Lost %d mbufs from rx chain!\n", 4214 sc->rx_mbuf_alloc)); 4215 4216 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4217 } 4218 4219 /****************************************************************************/ 4220 /* Handles PHY generated interrupt events. */ 4221 /* */ 4222 /* Returns: */ 4223 /* Nothing. */ 4224 /****************************************************************************/ 4225 void 4226 bnx_phy_intr(struct bnx_softc *sc) 4227 { 4228 u_int32_t new_link_state, old_link_state; 4229 4230 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4231 BUS_DMASYNC_POSTREAD); 4232 new_link_state = sc->status_block->status_attn_bits & 4233 STATUS_ATTN_BITS_LINK_STATE; 4234 old_link_state = sc->status_block->status_attn_bits_ack & 4235 STATUS_ATTN_BITS_LINK_STATE; 4236 4237 /* Handle any changes if the link state has changed. */ 4238 if (new_link_state != old_link_state) { 4239 DBRUN(BNX_VERBOSE_INTR, bnx_dump_status_block(sc)); 4240 4241 callout_stop(&sc->bnx_timeout); 4242 bnx_tick(sc); 4243 4244 /* Update the status_attn_bits_ack field in the status block. */ 4245 if (new_link_state) { 4246 REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD, 4247 STATUS_ATTN_BITS_LINK_STATE); 4248 DBPRINT(sc, BNX_INFO, "Link is now UP.\n"); 4249 } else { 4250 REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD, 4251 STATUS_ATTN_BITS_LINK_STATE); 4252 DBPRINT(sc, BNX_INFO, "Link is now DOWN.\n"); 4253 } 4254 } 4255 4256 /* Acknowledge the link change interrupt. */ 4257 REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE); 4258 } 4259 4260 /****************************************************************************/ 4261 /* Handles received frame interrupt events. */ 4262 /* */ 4263 /* Returns: */ 4264 /* Nothing. */ 4265 /****************************************************************************/ 4266 void 4267 bnx_rx_intr(struct bnx_softc *sc) 4268 { 4269 struct status_block *sblk = sc->status_block; 4270 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4271 u_int16_t hw_cons, sw_cons, sw_chain_cons; 4272 u_int16_t sw_prod, sw_chain_prod; 4273 u_int32_t sw_prod_bseq; 4274 struct l2_fhdr *l2fhdr; 4275 int i; 4276 4277 DBRUNIF(1, sc->rx_interrupts++); 4278 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4279 BUS_DMASYNC_POSTREAD); 4280 4281 /* Prepare the RX chain pages to be accessed by the host CPU. */ 4282 for (i = 0; i < RX_PAGES; i++) 4283 bus_dmamap_sync(sc->bnx_dmatag, 4284 sc->rx_bd_chain_map[i], 0, 4285 sc->rx_bd_chain_map[i]->dm_mapsize, 4286 BUS_DMASYNC_POSTWRITE); 4287 4288 /* Get the hardware's view of the RX consumer index. */ 4289 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 4290 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 4291 hw_cons++; 4292 4293 /* Get working copies of the driver's view of the RX indices. */ 4294 sw_cons = sc->rx_cons; 4295 sw_prod = sc->rx_prod; 4296 sw_prod_bseq = sc->rx_prod_bseq; 4297 4298 DBPRINT(sc, BNX_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " 4299 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", 4300 __func__, sw_prod, sw_cons, sw_prod_bseq); 4301 4302 /* Prevent speculative reads from getting ahead of the status block. */ 4303 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4304 BUS_SPACE_BARRIER_READ); 4305 4306 /* Update some debug statistics counters */ 4307 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 4308 sc->rx_low_watermark = sc->free_rx_bd); 4309 DBRUNIF((sc->free_rx_bd == USABLE_RX_BD), sc->rx_empty_count++); 4310 4311 /* 4312 * Scan through the receive chain as long 4313 * as there is work to do. 4314 */ 4315 while (sw_cons != hw_cons) { 4316 struct mbuf *m; 4317 struct rx_bd *rxbd; 4318 unsigned int len; 4319 u_int32_t status; 4320 4321 /* Convert the producer/consumer indices to an actual 4322 * rx_bd index. 4323 */ 4324 sw_chain_cons = RX_CHAIN_IDX(sw_cons); 4325 sw_chain_prod = RX_CHAIN_IDX(sw_prod); 4326 4327 /* Get the used rx_bd. */ 4328 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; 4329 sc->free_rx_bd++; 4330 4331 DBRUN(BNX_VERBOSE_RECV, aprint_error("%s(): ", __func__); 4332 bnx_dump_rxbd(sc, sw_chain_cons, rxbd)); 4333 4334 /* The mbuf is stored with the last rx_bd entry of a packet. */ 4335 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { 4336 #ifdef DIAGNOSTIC 4337 /* Validate that this is the last rx_bd. */ 4338 if ((rxbd->rx_bd_flags & RX_BD_FLAGS_END) == 0) { 4339 printf("%s: Unexpected mbuf found in " 4340 "rx_bd[0x%04X]!\n", device_xname(sc->bnx_dev), 4341 sw_chain_cons); 4342 } 4343 #endif 4344 4345 /* DRC - ToDo: If the received packet is small, say less 4346 * than 128 bytes, allocate a new mbuf here, 4347 * copy the data to that mbuf, and recycle 4348 * the mapped jumbo frame. 4349 */ 4350 4351 /* Unmap the mbuf from DMA space. */ 4352 #ifdef DIAGNOSTIC 4353 if (sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize == 0) { 4354 printf("invalid map sw_cons 0x%x " 4355 "sw_prod 0x%x " 4356 "sw_chain_cons 0x%x " 4357 "sw_chain_prod 0x%x " 4358 "hw_cons 0x%x " 4359 "TOTAL_RX_BD_PER_PAGE 0x%x " 4360 "TOTAL_RX_BD 0x%x\n", 4361 sw_cons, sw_prod, sw_chain_cons, sw_chain_prod, 4362 hw_cons, 4363 (int)TOTAL_RX_BD_PER_PAGE, (int)TOTAL_RX_BD); 4364 } 4365 #endif 4366 bus_dmamap_sync(sc->bnx_dmatag, 4367 sc->rx_mbuf_map[sw_chain_cons], 0, 4368 sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize, 4369 BUS_DMASYNC_POSTREAD); 4370 bus_dmamap_unload(sc->bnx_dmatag, 4371 sc->rx_mbuf_map[sw_chain_cons]); 4372 4373 /* Remove the mbuf from the driver's chain. */ 4374 m = sc->rx_mbuf_ptr[sw_chain_cons]; 4375 sc->rx_mbuf_ptr[sw_chain_cons] = NULL; 4376 4377 /* 4378 * Frames received on the NetXteme II are prepended 4379 * with the l2_fhdr structure which provides status 4380 * information about the received frame (including 4381 * VLAN tags and checksum info) and are also 4382 * automatically adjusted to align the IP header 4383 * (i.e. two null bytes are inserted before the 4384 * Ethernet header). 4385 */ 4386 l2fhdr = mtod(m, struct l2_fhdr *); 4387 4388 len = l2fhdr->l2_fhdr_pkt_len; 4389 status = l2fhdr->l2_fhdr_status; 4390 4391 DBRUNIF(DB_RANDOMTRUE(bnx_debug_l2fhdr_status_check), 4392 aprint_error("Simulating l2_fhdr status error.\n"); 4393 status = status | L2_FHDR_ERRORS_PHY_DECODE); 4394 4395 /* Watch for unusual sized frames. */ 4396 DBRUNIF(((len < BNX_MIN_MTU) || 4397 (len > BNX_MAX_JUMBO_ETHER_MTU_VLAN)), 4398 aprint_error_dev(sc->bnx_dev, 4399 "Unusual frame size found. " 4400 "Min(%d), Actual(%d), Max(%d)\n", 4401 (int)BNX_MIN_MTU, len, 4402 (int)BNX_MAX_JUMBO_ETHER_MTU_VLAN); 4403 4404 bnx_dump_mbuf(sc, m); 4405 bnx_breakpoint(sc)); 4406 4407 len -= ETHER_CRC_LEN; 4408 4409 /* Check the received frame for errors. */ 4410 if ((status & (L2_FHDR_ERRORS_BAD_CRC | 4411 L2_FHDR_ERRORS_PHY_DECODE | 4412 L2_FHDR_ERRORS_ALIGNMENT | 4413 L2_FHDR_ERRORS_TOO_SHORT | 4414 L2_FHDR_ERRORS_GIANT_FRAME)) || 4415 len < (BNX_MIN_MTU - ETHER_CRC_LEN) || 4416 len > 4417 (BNX_MAX_JUMBO_ETHER_MTU_VLAN - ETHER_CRC_LEN)) { 4418 ifp->if_ierrors++; 4419 DBRUNIF(1, sc->l2fhdr_status_errors++); 4420 4421 /* Reuse the mbuf for a new frame. */ 4422 if (bnx_add_buf(sc, m, &sw_prod, 4423 &sw_chain_prod, &sw_prod_bseq)) { 4424 DBRUNIF(1, bnx_breakpoint(sc)); 4425 panic("%s: Can't reuse RX mbuf!\n", 4426 device_xname(sc->bnx_dev)); 4427 } 4428 continue; 4429 } 4430 4431 /* 4432 * Get a new mbuf for the rx_bd. If no new 4433 * mbufs are available then reuse the current mbuf, 4434 * log an ierror on the interface, and generate 4435 * an error in the system log. 4436 */ 4437 if (bnx_get_buf(sc, &sw_prod, &sw_chain_prod, 4438 &sw_prod_bseq)) { 4439 DBRUN(BNX_WARN, aprint_debug_dev(sc->bnx_dev, 4440 "Failed to allocate " 4441 "new mbuf, incoming frame dropped!\n")); 4442 4443 ifp->if_ierrors++; 4444 4445 /* Try and reuse the exisitng mbuf. */ 4446 if (bnx_add_buf(sc, m, &sw_prod, 4447 &sw_chain_prod, &sw_prod_bseq)) { 4448 DBRUNIF(1, bnx_breakpoint(sc)); 4449 panic("%s: Double mbuf allocation " 4450 "failure!", 4451 device_xname(sc->bnx_dev)); 4452 } 4453 continue; 4454 } 4455 4456 /* Skip over the l2_fhdr when passing the data up 4457 * the stack. 4458 */ 4459 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); 4460 4461 /* Adjust the pckt length to match the received data. */ 4462 m->m_pkthdr.len = m->m_len = len; 4463 4464 /* Send the packet to the appropriate interface. */ 4465 m->m_pkthdr.rcvif = ifp; 4466 4467 DBRUN(BNX_VERBOSE_RECV, 4468 struct ether_header *eh; 4469 eh = mtod(m, struct ether_header *); 4470 aprint_error("%s: to: %s, from: %s, type: 0x%04X\n", 4471 __func__, ether_sprintf(eh->ether_dhost), 4472 ether_sprintf(eh->ether_shost), 4473 htons(eh->ether_type))); 4474 4475 /* Validate the checksum. */ 4476 4477 /* Check for an IP datagram. */ 4478 if (status & L2_FHDR_STATUS_IP_DATAGRAM) { 4479 /* Check if the IP checksum is valid. */ 4480 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) 4481 == 0) 4482 m->m_pkthdr.csum_flags |= 4483 M_CSUM_IPv4; 4484 #ifdef BNX_DEBUG 4485 else 4486 DBPRINT(sc, BNX_WARN_SEND, 4487 "%s(): Invalid IP checksum " 4488 "= 0x%04X!\n", 4489 __func__, 4490 l2fhdr->l2_fhdr_ip_xsum 4491 ); 4492 #endif 4493 } 4494 4495 /* Check for a valid TCP/UDP frame. */ 4496 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 4497 L2_FHDR_STATUS_UDP_DATAGRAM)) { 4498 /* Check for a good TCP/UDP checksum. */ 4499 if ((status & 4500 (L2_FHDR_ERRORS_TCP_XSUM | 4501 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 4502 m->m_pkthdr.csum_flags |= 4503 M_CSUM_TCPv4 | 4504 M_CSUM_UDPv4; 4505 } else { 4506 DBPRINT(sc, BNX_WARN_SEND, 4507 "%s(): Invalid TCP/UDP " 4508 "checksum = 0x%04X!\n", 4509 __func__, 4510 l2fhdr->l2_fhdr_tcp_udp_xsum); 4511 } 4512 } 4513 4514 /* 4515 * If we received a packet with a vlan tag, 4516 * attach that information to the packet. 4517 */ 4518 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 4519 !(sc->rx_mode & BNX_EMAC_RX_MODE_KEEP_VLAN_TAG)) { 4520 VLAN_INPUT_TAG(ifp, m, 4521 l2fhdr->l2_fhdr_vlan_tag, 4522 continue); 4523 } 4524 4525 /* 4526 * Handle BPF listeners. Let the BPF 4527 * user see the packet. 4528 */ 4529 bpf_mtap(ifp, m); 4530 4531 /* Pass the mbuf off to the upper layers. */ 4532 ifp->if_ipackets++; 4533 DBPRINT(sc, BNX_VERBOSE_RECV, 4534 "%s(): Passing received frame up.\n", __func__); 4535 (*ifp->if_input)(ifp, m); 4536 DBRUNIF(1, sc->rx_mbuf_alloc--); 4537 4538 } 4539 4540 sw_cons = NEXT_RX_BD(sw_cons); 4541 4542 /* Refresh hw_cons to see if there's new work */ 4543 if (sw_cons == hw_cons) { 4544 hw_cons = sc->hw_rx_cons = 4545 sblk->status_rx_quick_consumer_index0; 4546 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == 4547 USABLE_RX_BD_PER_PAGE) 4548 hw_cons++; 4549 } 4550 4551 /* Prevent speculative reads from getting ahead of 4552 * the status block. 4553 */ 4554 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4555 BUS_SPACE_BARRIER_READ); 4556 } 4557 4558 for (i = 0; i < RX_PAGES; i++) 4559 bus_dmamap_sync(sc->bnx_dmatag, 4560 sc->rx_bd_chain_map[i], 0, 4561 sc->rx_bd_chain_map[i]->dm_mapsize, 4562 BUS_DMASYNC_PREWRITE); 4563 4564 sc->rx_cons = sw_cons; 4565 sc->rx_prod = sw_prod; 4566 sc->rx_prod_bseq = sw_prod_bseq; 4567 4568 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4569 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4570 4571 DBPRINT(sc, BNX_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " 4572 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 4573 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 4574 } 4575 4576 /****************************************************************************/ 4577 /* Handles transmit completion interrupt events. */ 4578 /* */ 4579 /* Returns: */ 4580 /* Nothing. */ 4581 /****************************************************************************/ 4582 void 4583 bnx_tx_intr(struct bnx_softc *sc) 4584 { 4585 struct status_block *sblk = sc->status_block; 4586 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4587 struct bnx_pkt *pkt; 4588 bus_dmamap_t map; 4589 u_int16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 4590 4591 DBRUNIF(1, sc->tx_interrupts++); 4592 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4593 BUS_DMASYNC_POSTREAD); 4594 4595 /* Get the hardware's view of the TX consumer index. */ 4596 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 4597 4598 /* Skip to the next entry if this is a chain page pointer. */ 4599 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4600 hw_tx_cons++; 4601 4602 sw_tx_cons = sc->tx_cons; 4603 4604 /* Prevent speculative reads from getting ahead of the status block. */ 4605 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4606 BUS_SPACE_BARRIER_READ); 4607 4608 /* Cycle through any completed TX chain page entries. */ 4609 while (sw_tx_cons != hw_tx_cons) { 4610 #ifdef BNX_DEBUG 4611 struct tx_bd *txbd = NULL; 4612 #endif 4613 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 4614 4615 DBPRINT(sc, BNX_INFO_SEND, "%s(): hw_tx_cons = 0x%04X, " 4616 "sw_tx_cons = 0x%04X, sw_tx_chain_cons = 0x%04X\n", 4617 __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 4618 4619 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 4620 aprint_error_dev(sc->bnx_dev, 4621 "TX chain consumer out of range! 0x%04X > 0x%04X\n", 4622 sw_tx_chain_cons, (int)MAX_TX_BD); bnx_breakpoint(sc)); 4623 4624 DBRUNIF(1, txbd = &sc->tx_bd_chain 4625 [TX_PAGE(sw_tx_chain_cons)][TX_IDX(sw_tx_chain_cons)]); 4626 4627 DBRUNIF((txbd == NULL), 4628 aprint_error_dev(sc->bnx_dev, 4629 "Unexpected NULL tx_bd[0x%04X]!\n", sw_tx_chain_cons); 4630 bnx_breakpoint(sc)); 4631 4632 DBRUN(BNX_INFO_SEND, aprint_debug("%s: ", __func__); 4633 bnx_dump_txbd(sc, sw_tx_chain_cons, txbd)); 4634 4635 4636 mutex_enter(&sc->tx_pkt_mtx); 4637 pkt = TAILQ_FIRST(&sc->tx_used_pkts); 4638 if (pkt != NULL && pkt->pkt_end_desc == sw_tx_chain_cons) { 4639 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4640 mutex_exit(&sc->tx_pkt_mtx); 4641 /* 4642 * Free the associated mbuf. Remember 4643 * that only the last tx_bd of a packet 4644 * has an mbuf pointer and DMA map. 4645 */ 4646 map = pkt->pkt_dmamap; 4647 bus_dmamap_sync(sc->bnx_dmatag, map, 0, 4648 map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4649 bus_dmamap_unload(sc->bnx_dmatag, map); 4650 4651 m_freem(pkt->pkt_mbuf); 4652 DBRUNIF(1, sc->tx_mbuf_alloc--); 4653 4654 ifp->if_opackets++; 4655 4656 mutex_enter(&sc->tx_pkt_mtx); 4657 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4658 } 4659 mutex_exit(&sc->tx_pkt_mtx); 4660 4661 sc->used_tx_bd--; 4662 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 4663 __FILE__, __LINE__, sc->used_tx_bd); 4664 4665 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 4666 4667 /* Refresh hw_cons to see if there's new work. */ 4668 hw_tx_cons = sc->hw_tx_cons = 4669 sblk->status_tx_quick_consumer_index0; 4670 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == 4671 USABLE_TX_BD_PER_PAGE) 4672 hw_tx_cons++; 4673 4674 /* Prevent speculative reads from getting ahead of 4675 * the status block. 4676 */ 4677 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4678 BUS_SPACE_BARRIER_READ); 4679 } 4680 4681 /* Clear the TX timeout timer. */ 4682 ifp->if_timer = 0; 4683 4684 /* Clear the tx hardware queue full flag. */ 4685 if (sc->used_tx_bd < sc->max_tx_bd) { 4686 DBRUNIF((ifp->if_flags & IFF_OACTIVE), 4687 aprint_debug_dev(sc->bnx_dev, 4688 "Open TX chain! %d/%d (used/total)\n", 4689 sc->used_tx_bd, sc->max_tx_bd)); 4690 ifp->if_flags &= ~IFF_OACTIVE; 4691 } 4692 4693 sc->tx_cons = sw_tx_cons; 4694 } 4695 4696 /****************************************************************************/ 4697 /* Disables interrupt generation. */ 4698 /* */ 4699 /* Returns: */ 4700 /* Nothing. */ 4701 /****************************************************************************/ 4702 void 4703 bnx_disable_intr(struct bnx_softc *sc) 4704 { 4705 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4706 REG_RD(sc, BNX_PCICFG_INT_ACK_CMD); 4707 } 4708 4709 /****************************************************************************/ 4710 /* Enables interrupt generation. */ 4711 /* */ 4712 /* Returns: */ 4713 /* Nothing. */ 4714 /****************************************************************************/ 4715 void 4716 bnx_enable_intr(struct bnx_softc *sc) 4717 { 4718 u_int32_t val; 4719 4720 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4721 BNX_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 4722 4723 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4724 sc->last_status_idx); 4725 4726 val = REG_RD(sc, BNX_HC_COMMAND); 4727 REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW); 4728 } 4729 4730 /****************************************************************************/ 4731 /* Handles controller initialization. */ 4732 /* */ 4733 /****************************************************************************/ 4734 int 4735 bnx_init(struct ifnet *ifp) 4736 { 4737 struct bnx_softc *sc = ifp->if_softc; 4738 u_int32_t ether_mtu; 4739 int s, error = 0; 4740 4741 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4742 4743 s = splnet(); 4744 4745 bnx_stop(ifp, 0); 4746 4747 if ((error = bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) != 0) { 4748 aprint_error_dev(sc->bnx_dev, 4749 "Controller reset failed!\n"); 4750 goto bnx_init_exit; 4751 } 4752 4753 if ((error = bnx_chipinit(sc)) != 0) { 4754 aprint_error_dev(sc->bnx_dev, 4755 "Controller initialization failed!\n"); 4756 goto bnx_init_exit; 4757 } 4758 4759 if ((error = bnx_blockinit(sc)) != 0) { 4760 aprint_error_dev(sc->bnx_dev, 4761 "Block initialization failed!\n"); 4762 goto bnx_init_exit; 4763 } 4764 4765 /* Calculate and program the Ethernet MRU size. */ 4766 if (ifp->if_mtu <= ETHERMTU) { 4767 ether_mtu = BNX_MAX_STD_ETHER_MTU_VLAN; 4768 sc->mbuf_alloc_size = MCLBYTES; 4769 } else { 4770 ether_mtu = BNX_MAX_JUMBO_ETHER_MTU_VLAN; 4771 sc->mbuf_alloc_size = BNX_MAX_JUMBO_MRU; 4772 } 4773 4774 4775 DBPRINT(sc, BNX_INFO, "%s(): setting MRU = %d\n", 4776 __func__, ether_mtu); 4777 4778 /* 4779 * Program the MRU and enable Jumbo frame 4780 * support. 4781 */ 4782 REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu | 4783 BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA); 4784 4785 /* Calculate the RX Ethernet frame size for rx_bd's. */ 4786 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; 4787 4788 DBPRINT(sc, BNX_INFO, "%s(): mclbytes = %d, mbuf_alloc_size = %d, " 4789 "max_frame_size = %d\n", __func__, (int)MCLBYTES, 4790 sc->mbuf_alloc_size, sc->max_frame_size); 4791 4792 /* Program appropriate promiscuous/multicast filtering. */ 4793 bnx_iff(sc); 4794 4795 /* Init RX buffer descriptor chain. */ 4796 bnx_init_rx_chain(sc); 4797 4798 /* Init TX buffer descriptor chain. */ 4799 bnx_init_tx_chain(sc); 4800 4801 /* Enable host interrupts. */ 4802 bnx_enable_intr(sc); 4803 4804 if ((error = ether_mediachange(ifp)) != 0) 4805 goto bnx_init_exit; 4806 4807 ifp->if_flags |= IFF_RUNNING; 4808 ifp->if_flags &= ~IFF_OACTIVE; 4809 4810 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 4811 4812 bnx_init_exit: 4813 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4814 4815 splx(s); 4816 4817 return(error); 4818 } 4819 4820 /****************************************************************************/ 4821 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 4822 /* memory visible to the controller. */ 4823 /* */ 4824 /* Returns: */ 4825 /* 0 for success, positive value for failure. */ 4826 /****************************************************************************/ 4827 int 4828 bnx_tx_encap(struct bnx_softc *sc, struct mbuf *m) 4829 { 4830 struct bnx_pkt *pkt; 4831 bus_dmamap_t map; 4832 struct tx_bd *txbd = NULL; 4833 u_int16_t vlan_tag = 0, flags = 0; 4834 u_int16_t chain_prod, prod; 4835 #ifdef BNX_DEBUG 4836 u_int16_t debug_prod; 4837 #endif 4838 u_int32_t addr, prod_bseq; 4839 int i, error; 4840 struct m_tag *mtag; 4841 4842 again: 4843 mutex_enter(&sc->tx_pkt_mtx); 4844 pkt = TAILQ_FIRST(&sc->tx_free_pkts); 4845 if (pkt == NULL) { 4846 if (!ISSET(sc->bnx_ec.ec_if.if_flags, IFF_UP)) { 4847 mutex_exit(&sc->tx_pkt_mtx); 4848 return ENETDOWN; 4849 } 4850 if (sc->tx_pkt_count <= TOTAL_TX_BD) { 4851 mutex_exit(&sc->tx_pkt_mtx); 4852 if (bnx_alloc_pkts(sc) == 0) 4853 goto again; 4854 } else { 4855 mutex_exit(&sc->tx_pkt_mtx); 4856 } 4857 return (ENOMEM); 4858 } 4859 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 4860 mutex_exit(&sc->tx_pkt_mtx); 4861 4862 /* Transfer any checksum offload flags to the bd. */ 4863 if (m->m_pkthdr.csum_flags) { 4864 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 4865 flags |= TX_BD_FLAGS_IP_CKSUM; 4866 if (m->m_pkthdr.csum_flags & 4867 (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 4868 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 4869 } 4870 4871 /* Transfer any VLAN tags to the bd. */ 4872 mtag = VLAN_OUTPUT_TAG(&sc->bnx_ec, m); 4873 if (mtag != NULL) { 4874 flags |= TX_BD_FLAGS_VLAN_TAG; 4875 vlan_tag = VLAN_TAG_VALUE(mtag); 4876 } 4877 4878 /* Map the mbuf into DMAable memory. */ 4879 prod = sc->tx_prod; 4880 chain_prod = TX_CHAIN_IDX(prod); 4881 map = pkt->pkt_dmamap; 4882 4883 /* Map the mbuf into our DMA address space. */ 4884 error = bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m, BUS_DMA_NOWAIT); 4885 if (error != 0) { 4886 aprint_error_dev(sc->bnx_dev, 4887 "Error mapping mbuf into TX chain!\n"); 4888 sc->tx_dma_map_failures++; 4889 goto maperr; 4890 } 4891 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 4892 BUS_DMASYNC_PREWRITE); 4893 /* Make sure there's room in the chain */ 4894 if (map->dm_nsegs > (sc->max_tx_bd - sc->used_tx_bd)) 4895 goto nospace; 4896 4897 /* prod points to an empty tx_bd at this point. */ 4898 prod_bseq = sc->tx_prod_bseq; 4899 #ifdef BNX_DEBUG 4900 debug_prod = chain_prod; 4901 #endif 4902 DBPRINT(sc, BNX_INFO_SEND, 4903 "%s(): Start: prod = 0x%04X, chain_prod = %04X, " 4904 "prod_bseq = 0x%08X\n", 4905 __func__, prod, chain_prod, prod_bseq); 4906 4907 /* 4908 * Cycle through each mbuf segment that makes up 4909 * the outgoing frame, gathering the mapping info 4910 * for that segment and creating a tx_bd for the 4911 * mbuf. 4912 */ 4913 for (i = 0; i < map->dm_nsegs ; i++) { 4914 chain_prod = TX_CHAIN_IDX(prod); 4915 txbd = &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 4916 4917 addr = (u_int32_t)map->dm_segs[i].ds_addr; 4918 txbd->tx_bd_haddr_lo = addr; 4919 addr = (u_int32_t)((u_int64_t)map->dm_segs[i].ds_addr >> 32); 4920 txbd->tx_bd_haddr_hi = addr; 4921 txbd->tx_bd_mss_nbytes = map->dm_segs[i].ds_len; 4922 txbd->tx_bd_vlan_tag = vlan_tag; 4923 txbd->tx_bd_flags = flags; 4924 prod_bseq += map->dm_segs[i].ds_len; 4925 if (i == 0) 4926 txbd->tx_bd_flags |= TX_BD_FLAGS_START; 4927 prod = NEXT_TX_BD(prod); 4928 } 4929 /* Set the END flag on the last TX buffer descriptor. */ 4930 txbd->tx_bd_flags |= TX_BD_FLAGS_END; 4931 4932 DBRUN(BNX_INFO_SEND, bnx_dump_tx_chain(sc, debug_prod, map->dm_nsegs)); 4933 4934 DBPRINT(sc, BNX_INFO_SEND, 4935 "%s(): End: prod = 0x%04X, chain_prod = %04X, " 4936 "prod_bseq = 0x%08X\n", 4937 __func__, prod, chain_prod, prod_bseq); 4938 4939 pkt->pkt_mbuf = m; 4940 pkt->pkt_end_desc = chain_prod; 4941 4942 mutex_enter(&sc->tx_pkt_mtx); 4943 TAILQ_INSERT_TAIL(&sc->tx_used_pkts, pkt, pkt_entry); 4944 mutex_exit(&sc->tx_pkt_mtx); 4945 4946 sc->used_tx_bd += map->dm_nsegs; 4947 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 4948 __FILE__, __LINE__, sc->used_tx_bd); 4949 4950 /* Update some debug statistics counters */ 4951 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 4952 sc->tx_hi_watermark = sc->used_tx_bd); 4953 DBRUNIF(sc->used_tx_bd == sc->max_tx_bd, sc->tx_full_count++); 4954 DBRUNIF(1, sc->tx_mbuf_alloc++); 4955 4956 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_mbuf_chain(sc, chain_prod, 4957 map->dm_nsegs)); 4958 4959 /* prod points to the next free tx_bd at this point. */ 4960 sc->tx_prod = prod; 4961 sc->tx_prod_bseq = prod_bseq; 4962 4963 return (0); 4964 4965 4966 nospace: 4967 bus_dmamap_unload(sc->bnx_dmatag, map); 4968 maperr: 4969 mutex_enter(&sc->tx_pkt_mtx); 4970 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4971 mutex_exit(&sc->tx_pkt_mtx); 4972 4973 return (ENOMEM); 4974 } 4975 4976 /****************************************************************************/ 4977 /* Main transmit routine. */ 4978 /* */ 4979 /* Returns: */ 4980 /* Nothing. */ 4981 /****************************************************************************/ 4982 void 4983 bnx_start(struct ifnet *ifp) 4984 { 4985 struct bnx_softc *sc = ifp->if_softc; 4986 struct mbuf *m_head = NULL; 4987 int count = 0; 4988 u_int16_t tx_prod, tx_chain_prod; 4989 4990 /* If there's no link or the transmit queue is empty then just exit. */ 4991 if ((ifp->if_flags & (IFF_OACTIVE|IFF_RUNNING)) != IFF_RUNNING) { 4992 DBPRINT(sc, BNX_INFO_SEND, 4993 "%s(): output active or device not running.\n", __func__); 4994 goto bnx_start_exit; 4995 } 4996 4997 /* prod points to the next free tx_bd. */ 4998 tx_prod = sc->tx_prod; 4999 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 5000 5001 DBPRINT(sc, BNX_INFO_SEND, "%s(): Start: tx_prod = 0x%04X, " 5002 "tx_chain_prod = %04X, tx_prod_bseq = 0x%08X, " 5003 "used_tx %d max_tx %d\n", 5004 __func__, tx_prod, tx_chain_prod, sc->tx_prod_bseq, 5005 sc->used_tx_bd, sc->max_tx_bd); 5006 5007 /* 5008 * Keep adding entries while there is space in the ring. 5009 */ 5010 while (sc->used_tx_bd < sc->max_tx_bd) { 5011 /* Check for any frames to send. */ 5012 IFQ_POLL(&ifp->if_snd, m_head); 5013 if (m_head == NULL) 5014 break; 5015 5016 /* 5017 * Pack the data into the transmit ring. If we 5018 * don't have room, set the OACTIVE flag to wait 5019 * for the NIC to drain the chain. 5020 */ 5021 if (bnx_tx_encap(sc, m_head)) { 5022 ifp->if_flags |= IFF_OACTIVE; 5023 DBPRINT(sc, BNX_INFO_SEND, "TX chain is closed for " 5024 "business! Total tx_bd used = %d\n", 5025 sc->used_tx_bd); 5026 break; 5027 } 5028 5029 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5030 count++; 5031 5032 /* Send a copy of the frame to any BPF listeners. */ 5033 bpf_mtap(ifp, m_head); 5034 } 5035 5036 if (count == 0) { 5037 /* no packets were dequeued */ 5038 DBPRINT(sc, BNX_VERBOSE_SEND, 5039 "%s(): No packets were dequeued\n", __func__); 5040 goto bnx_start_exit; 5041 } 5042 5043 /* Update the driver's counters. */ 5044 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5045 5046 DBPRINT(sc, BNX_INFO_SEND, "%s(): End: tx_prod = 0x%04X, tx_chain_prod " 5047 "= 0x%04X, tx_prod_bseq = 0x%08X\n", __func__, tx_prod, 5048 tx_chain_prod, sc->tx_prod_bseq); 5049 5050 /* Start the transmit. */ 5051 REG_WR16(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BIDX, sc->tx_prod); 5052 REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 5053 5054 /* Set the tx timeout. */ 5055 ifp->if_timer = BNX_TX_TIMEOUT; 5056 5057 bnx_start_exit: 5058 return; 5059 } 5060 5061 /****************************************************************************/ 5062 /* Handles any IOCTL calls from the operating system. */ 5063 /* */ 5064 /* Returns: */ 5065 /* 0 for success, positive value for failure. */ 5066 /****************************************************************************/ 5067 int 5068 bnx_ioctl(struct ifnet *ifp, u_long command, void *data) 5069 { 5070 struct bnx_softc *sc = ifp->if_softc; 5071 struct ifreq *ifr = (struct ifreq *) data; 5072 struct mii_data *mii = &sc->bnx_mii; 5073 int s, error = 0; 5074 5075 s = splnet(); 5076 5077 switch (command) { 5078 case SIOCSIFFLAGS: 5079 if ((error = ifioctl_common(ifp, command, data)) != 0) 5080 break; 5081 /* XXX set an ifflags callback and let ether_ioctl 5082 * handle all of this. 5083 */ 5084 if (ifp->if_flags & IFF_UP) { 5085 if (ifp->if_flags & IFF_RUNNING) 5086 error = ENETRESET; 5087 else 5088 bnx_init(ifp); 5089 } else if (ifp->if_flags & IFF_RUNNING) 5090 bnx_stop(ifp, 1); 5091 break; 5092 5093 case SIOCSIFMEDIA: 5094 case SIOCGIFMEDIA: 5095 DBPRINT(sc, BNX_VERBOSE, "bnx_phy_flags = 0x%08X\n", 5096 sc->bnx_phy_flags); 5097 5098 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 5099 break; 5100 5101 default: 5102 error = ether_ioctl(ifp, command, data); 5103 } 5104 5105 if (error == ENETRESET) { 5106 if (ifp->if_flags & IFF_RUNNING) 5107 bnx_iff(sc); 5108 error = 0; 5109 } 5110 5111 splx(s); 5112 return (error); 5113 } 5114 5115 /****************************************************************************/ 5116 /* Transmit timeout handler. */ 5117 /* */ 5118 /* Returns: */ 5119 /* Nothing. */ 5120 /****************************************************************************/ 5121 void 5122 bnx_watchdog(struct ifnet *ifp) 5123 { 5124 struct bnx_softc *sc = ifp->if_softc; 5125 5126 DBRUN(BNX_WARN_SEND, bnx_dump_driver_state(sc); 5127 bnx_dump_status_block(sc)); 5128 /* 5129 * If we are in this routine because of pause frames, then 5130 * don't reset the hardware. 5131 */ 5132 if (REG_RD(sc, BNX_EMAC_TX_STATUS) & BNX_EMAC_TX_STATUS_XOFFED) 5133 return; 5134 5135 aprint_error_dev(sc->bnx_dev, "Watchdog timeout -- resetting!\n"); 5136 5137 /* DBRUN(BNX_FATAL, bnx_breakpoint(sc)); */ 5138 5139 bnx_init(ifp); 5140 5141 ifp->if_oerrors++; 5142 } 5143 5144 /* 5145 * Interrupt handler. 5146 */ 5147 /****************************************************************************/ 5148 /* Main interrupt entry point. Verifies that the controller generated the */ 5149 /* interrupt and then calls a separate routine for handle the various */ 5150 /* interrupt causes (PHY, TX, RX). */ 5151 /* */ 5152 /* Returns: */ 5153 /* 0 for success, positive value for failure. */ 5154 /****************************************************************************/ 5155 int 5156 bnx_intr(void *xsc) 5157 { 5158 struct bnx_softc *sc; 5159 struct ifnet *ifp; 5160 u_int32_t status_attn_bits; 5161 const struct status_block *sblk; 5162 5163 sc = xsc; 5164 5165 ifp = &sc->bnx_ec.ec_if; 5166 5167 if (!device_is_active(sc->bnx_dev) || 5168 (ifp->if_flags & IFF_RUNNING) == 0) 5169 return 0; 5170 5171 DBRUNIF(1, sc->interrupts_generated++); 5172 5173 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5174 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 5175 5176 /* 5177 * If the hardware status block index 5178 * matches the last value read by the 5179 * driver and we haven't asserted our 5180 * interrupt then there's nothing to do. 5181 */ 5182 if ((sc->status_block->status_idx == sc->last_status_idx) && 5183 (REG_RD(sc, BNX_PCICFG_MISC_STATUS) & 5184 BNX_PCICFG_MISC_STATUS_INTA_VALUE)) 5185 return (0); 5186 5187 /* Ack the interrupt and stop others from occuring. */ 5188 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5189 BNX_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 5190 BNX_PCICFG_INT_ACK_CMD_MASK_INT); 5191 5192 /* Keep processing data as long as there is work to do. */ 5193 for (;;) { 5194 sblk = sc->status_block; 5195 status_attn_bits = sblk->status_attn_bits; 5196 5197 DBRUNIF(DB_RANDOMTRUE(bnx_debug_unexpected_attention), 5198 aprint_debug("Simulating unexpected status attention bit set."); 5199 status_attn_bits = status_attn_bits | 5200 STATUS_ATTN_BITS_PARITY_ERROR); 5201 5202 /* Was it a link change interrupt? */ 5203 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 5204 (sblk->status_attn_bits_ack & 5205 STATUS_ATTN_BITS_LINK_STATE)) 5206 bnx_phy_intr(sc); 5207 5208 /* If any other attention is asserted then the chip is toast. */ 5209 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 5210 (sblk->status_attn_bits_ack & 5211 ~STATUS_ATTN_BITS_LINK_STATE))) { 5212 DBRUN(1, sc->unexpected_attentions++); 5213 5214 BNX_PRINTF(sc, 5215 "Fatal attention detected: 0x%08X\n", 5216 sblk->status_attn_bits); 5217 5218 DBRUN(BNX_FATAL, 5219 if (bnx_debug_unexpected_attention == 0) 5220 bnx_breakpoint(sc)); 5221 5222 bnx_init(ifp); 5223 return (1); 5224 } 5225 5226 /* Check for any completed RX frames. */ 5227 if (sblk->status_rx_quick_consumer_index0 != 5228 sc->hw_rx_cons) 5229 bnx_rx_intr(sc); 5230 5231 /* Check for any completed TX frames. */ 5232 if (sblk->status_tx_quick_consumer_index0 != 5233 sc->hw_tx_cons) 5234 bnx_tx_intr(sc); 5235 5236 /* Save the status block index value for use during the 5237 * next interrupt. 5238 */ 5239 sc->last_status_idx = sblk->status_idx; 5240 5241 /* Prevent speculative reads from getting ahead of the 5242 * status block. 5243 */ 5244 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 5245 BUS_SPACE_BARRIER_READ); 5246 5247 /* If there's no work left then exit the isr. */ 5248 if ((sblk->status_rx_quick_consumer_index0 == 5249 sc->hw_rx_cons) && 5250 (sblk->status_tx_quick_consumer_index0 == 5251 sc->hw_tx_cons)) 5252 break; 5253 } 5254 5255 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5256 sc->status_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 5257 5258 /* Re-enable interrupts. */ 5259 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5260 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx | 5261 BNX_PCICFG_INT_ACK_CMD_MASK_INT); 5262 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5263 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 5264 5265 /* Handle any frames that arrived while handling the interrupt. */ 5266 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 5267 bnx_start(ifp); 5268 5269 return (1); 5270 } 5271 5272 /****************************************************************************/ 5273 /* Programs the various packet receive modes (broadcast and multicast). */ 5274 /* */ 5275 /* Returns: */ 5276 /* Nothing. */ 5277 /****************************************************************************/ 5278 void 5279 bnx_iff(struct bnx_softc *sc) 5280 { 5281 struct ethercom *ec = &sc->bnx_ec; 5282 struct ifnet *ifp = &ec->ec_if; 5283 struct ether_multi *enm; 5284 struct ether_multistep step; 5285 u_int32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 5286 u_int32_t rx_mode, sort_mode; 5287 int h, i; 5288 5289 /* Initialize receive mode default settings. */ 5290 rx_mode = sc->rx_mode & ~(BNX_EMAC_RX_MODE_PROMISCUOUS | 5291 BNX_EMAC_RX_MODE_KEEP_VLAN_TAG); 5292 sort_mode = 1 | BNX_RPM_SORT_USER0_BC_EN; 5293 ifp->if_flags &= ~IFF_ALLMULTI; 5294 5295 /* 5296 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 5297 * be enbled. 5298 */ 5299 if (!(sc->bnx_flags & BNX_MFW_ENABLE_FLAG)) 5300 rx_mode |= BNX_EMAC_RX_MODE_KEEP_VLAN_TAG; 5301 5302 /* 5303 * Check for promiscuous, all multicast, or selected 5304 * multicast address filtering. 5305 */ 5306 if (ifp->if_flags & IFF_PROMISC) { 5307 DBPRINT(sc, BNX_INFO, "Enabling promiscuous mode.\n"); 5308 5309 ifp->if_flags |= IFF_ALLMULTI; 5310 /* Enable promiscuous mode. */ 5311 rx_mode |= BNX_EMAC_RX_MODE_PROMISCUOUS; 5312 sort_mode |= BNX_RPM_SORT_USER0_PROM_EN; 5313 } else if (ifp->if_flags & IFF_ALLMULTI) { 5314 allmulti: 5315 DBPRINT(sc, BNX_INFO, "Enabling all multicast mode.\n"); 5316 5317 ifp->if_flags |= IFF_ALLMULTI; 5318 /* Enable all multicast addresses. */ 5319 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5320 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5321 0xffffffff); 5322 sort_mode |= BNX_RPM_SORT_USER0_MC_EN; 5323 } else { 5324 /* Accept one or more multicast(s). */ 5325 DBPRINT(sc, BNX_INFO, "Enabling selective multicast mode.\n"); 5326 5327 ETHER_FIRST_MULTI(step, ec, enm); 5328 while (enm != NULL) { 5329 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 5330 ETHER_ADDR_LEN)) { 5331 goto allmulti; 5332 } 5333 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 5334 0xFF; 5335 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 5336 ETHER_NEXT_MULTI(step, enm); 5337 } 5338 5339 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5340 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5341 hashes[i]); 5342 5343 sort_mode |= BNX_RPM_SORT_USER0_MC_HSH_EN; 5344 } 5345 5346 /* Only make changes if the recive mode has actually changed. */ 5347 if (rx_mode != sc->rx_mode) { 5348 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 5349 rx_mode); 5350 5351 sc->rx_mode = rx_mode; 5352 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 5353 } 5354 5355 /* Disable and clear the exisitng sort before enabling a new sort. */ 5356 REG_WR(sc, BNX_RPM_SORT_USER0, 0x0); 5357 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode); 5358 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA); 5359 } 5360 5361 /****************************************************************************/ 5362 /* Called periodically to updates statistics from the controllers */ 5363 /* statistics block. */ 5364 /* */ 5365 /* Returns: */ 5366 /* Nothing. */ 5367 /****************************************************************************/ 5368 void 5369 bnx_stats_update(struct bnx_softc *sc) 5370 { 5371 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5372 struct statistics_block *stats; 5373 5374 DBPRINT(sc, BNX_EXCESSIVE, "Entering %s()\n", __func__); 5375 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5376 BUS_DMASYNC_POSTREAD); 5377 5378 stats = (struct statistics_block *)sc->stats_block; 5379 5380 /* 5381 * Update the interface statistics from the 5382 * hardware statistics. 5383 */ 5384 ifp->if_collisions = (u_long)stats->stat_EtherStatsCollisions; 5385 5386 ifp->if_ierrors = (u_long)stats->stat_EtherStatsUndersizePkts + 5387 (u_long)stats->stat_EtherStatsOverrsizePkts + 5388 (u_long)stats->stat_IfInMBUFDiscards + 5389 (u_long)stats->stat_Dot3StatsAlignmentErrors + 5390 (u_long)stats->stat_Dot3StatsFCSErrors; 5391 5392 ifp->if_oerrors = (u_long) 5393 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 5394 (u_long)stats->stat_Dot3StatsExcessiveCollisions + 5395 (u_long)stats->stat_Dot3StatsLateCollisions; 5396 5397 /* 5398 * Certain controllers don't report 5399 * carrier sense errors correctly. 5400 * See errata E11_5708CA0_1165. 5401 */ 5402 if (!(BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 5403 !(BNX_CHIP_ID(sc) == BNX_CHIP_ID_5708_A0)) 5404 ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 5405 5406 /* 5407 * Update the sysctl statistics from the 5408 * hardware statistics. 5409 */ 5410 sc->stat_IfHCInOctets = ((u_int64_t)stats->stat_IfHCInOctets_hi << 32) + 5411 (u_int64_t) stats->stat_IfHCInOctets_lo; 5412 5413 sc->stat_IfHCInBadOctets = 5414 ((u_int64_t) stats->stat_IfHCInBadOctets_hi << 32) + 5415 (u_int64_t) stats->stat_IfHCInBadOctets_lo; 5416 5417 sc->stat_IfHCOutOctets = 5418 ((u_int64_t) stats->stat_IfHCOutOctets_hi << 32) + 5419 (u_int64_t) stats->stat_IfHCOutOctets_lo; 5420 5421 sc->stat_IfHCOutBadOctets = 5422 ((u_int64_t) stats->stat_IfHCOutBadOctets_hi << 32) + 5423 (u_int64_t) stats->stat_IfHCOutBadOctets_lo; 5424 5425 sc->stat_IfHCInUcastPkts = 5426 ((u_int64_t) stats->stat_IfHCInUcastPkts_hi << 32) + 5427 (u_int64_t) stats->stat_IfHCInUcastPkts_lo; 5428 5429 sc->stat_IfHCInMulticastPkts = 5430 ((u_int64_t) stats->stat_IfHCInMulticastPkts_hi << 32) + 5431 (u_int64_t) stats->stat_IfHCInMulticastPkts_lo; 5432 5433 sc->stat_IfHCInBroadcastPkts = 5434 ((u_int64_t) stats->stat_IfHCInBroadcastPkts_hi << 32) + 5435 (u_int64_t) stats->stat_IfHCInBroadcastPkts_lo; 5436 5437 sc->stat_IfHCOutUcastPkts = 5438 ((u_int64_t) stats->stat_IfHCOutUcastPkts_hi << 32) + 5439 (u_int64_t) stats->stat_IfHCOutUcastPkts_lo; 5440 5441 sc->stat_IfHCOutMulticastPkts = 5442 ((u_int64_t) stats->stat_IfHCOutMulticastPkts_hi << 32) + 5443 (u_int64_t) stats->stat_IfHCOutMulticastPkts_lo; 5444 5445 sc->stat_IfHCOutBroadcastPkts = 5446 ((u_int64_t) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 5447 (u_int64_t) stats->stat_IfHCOutBroadcastPkts_lo; 5448 5449 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 5450 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 5451 5452 sc->stat_Dot3StatsCarrierSenseErrors = 5453 stats->stat_Dot3StatsCarrierSenseErrors; 5454 5455 sc->stat_Dot3StatsFCSErrors = stats->stat_Dot3StatsFCSErrors; 5456 5457 sc->stat_Dot3StatsAlignmentErrors = 5458 stats->stat_Dot3StatsAlignmentErrors; 5459 5460 sc->stat_Dot3StatsSingleCollisionFrames = 5461 stats->stat_Dot3StatsSingleCollisionFrames; 5462 5463 sc->stat_Dot3StatsMultipleCollisionFrames = 5464 stats->stat_Dot3StatsMultipleCollisionFrames; 5465 5466 sc->stat_Dot3StatsDeferredTransmissions = 5467 stats->stat_Dot3StatsDeferredTransmissions; 5468 5469 sc->stat_Dot3StatsExcessiveCollisions = 5470 stats->stat_Dot3StatsExcessiveCollisions; 5471 5472 sc->stat_Dot3StatsLateCollisions = stats->stat_Dot3StatsLateCollisions; 5473 5474 sc->stat_EtherStatsCollisions = stats->stat_EtherStatsCollisions; 5475 5476 sc->stat_EtherStatsFragments = stats->stat_EtherStatsFragments; 5477 5478 sc->stat_EtherStatsJabbers = stats->stat_EtherStatsJabbers; 5479 5480 sc->stat_EtherStatsUndersizePkts = stats->stat_EtherStatsUndersizePkts; 5481 5482 sc->stat_EtherStatsOverrsizePkts = stats->stat_EtherStatsOverrsizePkts; 5483 5484 sc->stat_EtherStatsPktsRx64Octets = 5485 stats->stat_EtherStatsPktsRx64Octets; 5486 5487 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 5488 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 5489 5490 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 5491 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 5492 5493 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 5494 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 5495 5496 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 5497 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 5498 5499 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 5500 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 5501 5502 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 5503 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 5504 5505 sc->stat_EtherStatsPktsTx64Octets = 5506 stats->stat_EtherStatsPktsTx64Octets; 5507 5508 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 5509 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 5510 5511 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 5512 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 5513 5514 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 5515 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 5516 5517 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 5518 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 5519 5520 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 5521 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 5522 5523 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 5524 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 5525 5526 sc->stat_XonPauseFramesReceived = stats->stat_XonPauseFramesReceived; 5527 5528 sc->stat_XoffPauseFramesReceived = stats->stat_XoffPauseFramesReceived; 5529 5530 sc->stat_OutXonSent = stats->stat_OutXonSent; 5531 5532 sc->stat_OutXoffSent = stats->stat_OutXoffSent; 5533 5534 sc->stat_FlowControlDone = stats->stat_FlowControlDone; 5535 5536 sc->stat_MacControlFramesReceived = 5537 stats->stat_MacControlFramesReceived; 5538 5539 sc->stat_XoffStateEntered = stats->stat_XoffStateEntered; 5540 5541 sc->stat_IfInFramesL2FilterDiscards = 5542 stats->stat_IfInFramesL2FilterDiscards; 5543 5544 sc->stat_IfInRuleCheckerDiscards = stats->stat_IfInRuleCheckerDiscards; 5545 5546 sc->stat_IfInFTQDiscards = stats->stat_IfInFTQDiscards; 5547 5548 sc->stat_IfInMBUFDiscards = stats->stat_IfInMBUFDiscards; 5549 5550 sc->stat_IfInRuleCheckerP4Hit = stats->stat_IfInRuleCheckerP4Hit; 5551 5552 sc->stat_CatchupInRuleCheckerDiscards = 5553 stats->stat_CatchupInRuleCheckerDiscards; 5554 5555 sc->stat_CatchupInFTQDiscards = stats->stat_CatchupInFTQDiscards; 5556 5557 sc->stat_CatchupInMBUFDiscards = stats->stat_CatchupInMBUFDiscards; 5558 5559 sc->stat_CatchupInRuleCheckerP4Hit = 5560 stats->stat_CatchupInRuleCheckerP4Hit; 5561 5562 DBPRINT(sc, BNX_EXCESSIVE, "Exiting %s()\n", __func__); 5563 } 5564 5565 void 5566 bnx_tick(void *xsc) 5567 { 5568 struct bnx_softc *sc = xsc; 5569 struct mii_data *mii; 5570 u_int32_t msg; 5571 u_int16_t prod, chain_prod; 5572 u_int32_t prod_bseq; 5573 int s = splnet(); 5574 5575 /* Tell the firmware that the driver is still running. */ 5576 #ifdef BNX_DEBUG 5577 msg = (u_int32_t)BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE; 5578 #else 5579 msg = (u_int32_t)++sc->bnx_fw_drv_pulse_wr_seq; 5580 #endif 5581 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_PULSE_MB, msg); 5582 5583 /* Update the statistics from the hardware statistics block. */ 5584 bnx_stats_update(sc); 5585 5586 /* Schedule the next tick. */ 5587 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 5588 5589 mii = &sc->bnx_mii; 5590 mii_tick(mii); 5591 5592 /* try to get more RX buffers, just in case */ 5593 prod = sc->rx_prod; 5594 prod_bseq = sc->rx_prod_bseq; 5595 chain_prod = RX_CHAIN_IDX(prod); 5596 bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq); 5597 sc->rx_prod = prod; 5598 sc->rx_prod_bseq = prod_bseq; 5599 splx(s); 5600 return; 5601 } 5602 5603 /****************************************************************************/ 5604 /* BNX Debug Routines */ 5605 /****************************************************************************/ 5606 #ifdef BNX_DEBUG 5607 5608 /****************************************************************************/ 5609 /* Prints out information about an mbuf. */ 5610 /* */ 5611 /* Returns: */ 5612 /* Nothing. */ 5613 /****************************************************************************/ 5614 void 5615 bnx_dump_mbuf(struct bnx_softc *sc, struct mbuf *m) 5616 { 5617 struct mbuf *mp = m; 5618 5619 if (m == NULL) { 5620 /* Index out of range. */ 5621 aprint_error("mbuf ptr is null!\n"); 5622 return; 5623 } 5624 5625 while (mp) { 5626 aprint_debug("mbuf: vaddr = %p, m_len = %d, m_flags = ", 5627 mp, mp->m_len); 5628 5629 if (mp->m_flags & M_EXT) 5630 aprint_debug("M_EXT "); 5631 if (mp->m_flags & M_PKTHDR) 5632 aprint_debug("M_PKTHDR "); 5633 aprint_debug("\n"); 5634 5635 if (mp->m_flags & M_EXT) 5636 aprint_debug("- m_ext: vaddr = %p, ext_size = 0x%04zX\n", 5637 mp, mp->m_ext.ext_size); 5638 5639 mp = mp->m_next; 5640 } 5641 } 5642 5643 /****************************************************************************/ 5644 /* Prints out the mbufs in the TX mbuf chain. */ 5645 /* */ 5646 /* Returns: */ 5647 /* Nothing. */ 5648 /****************************************************************************/ 5649 void 5650 bnx_dump_tx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5651 { 5652 #if 0 5653 struct mbuf *m; 5654 int i; 5655 5656 aprint_debug_dev(sc->bnx_dev, 5657 "----------------------------" 5658 " tx mbuf data " 5659 "----------------------------\n"); 5660 5661 for (i = 0; i < count; i++) { 5662 m = sc->tx_mbuf_ptr[chain_prod]; 5663 BNX_PRINTF(sc, "txmbuf[%d]\n", chain_prod); 5664 bnx_dump_mbuf(sc, m); 5665 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 5666 } 5667 5668 aprint_debug_dev(sc->bnx_dev, 5669 "--------------------------------------------" 5670 "----------------------------\n"); 5671 #endif 5672 } 5673 5674 /* 5675 * This routine prints the RX mbuf chain. 5676 */ 5677 void 5678 bnx_dump_rx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5679 { 5680 struct mbuf *m; 5681 int i; 5682 5683 aprint_debug_dev(sc->bnx_dev, 5684 "----------------------------" 5685 " rx mbuf data " 5686 "----------------------------\n"); 5687 5688 for (i = 0; i < count; i++) { 5689 m = sc->rx_mbuf_ptr[chain_prod]; 5690 BNX_PRINTF(sc, "rxmbuf[0x%04X]\n", chain_prod); 5691 bnx_dump_mbuf(sc, m); 5692 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 5693 } 5694 5695 5696 aprint_debug_dev(sc->bnx_dev, 5697 "--------------------------------------------" 5698 "----------------------------\n"); 5699 } 5700 5701 void 5702 bnx_dump_txbd(struct bnx_softc *sc, int idx, struct tx_bd *txbd) 5703 { 5704 if (idx > MAX_TX_BD) 5705 /* Index out of range. */ 5706 BNX_PRINTF(sc, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 5707 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 5708 /* TX Chain page pointer. */ 5709 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain " 5710 "page pointer\n", idx, txbd->tx_bd_haddr_hi, 5711 txbd->tx_bd_haddr_lo); 5712 else 5713 /* Normal tx_bd entry. */ 5714 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5715 "0x%08X, vlan tag = 0x%4X, flags = 0x%08X\n", idx, 5716 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 5717 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 5718 txbd->tx_bd_flags); 5719 } 5720 5721 void 5722 bnx_dump_rxbd(struct bnx_softc *sc, int idx, struct rx_bd *rxbd) 5723 { 5724 if (idx > MAX_RX_BD) 5725 /* Index out of range. */ 5726 BNX_PRINTF(sc, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 5727 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 5728 /* TX Chain page pointer. */ 5729 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 5730 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 5731 rxbd->rx_bd_haddr_lo); 5732 else 5733 /* Normal tx_bd entry. */ 5734 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5735 "0x%08X, flags = 0x%08X\n", idx, 5736 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 5737 rxbd->rx_bd_len, rxbd->rx_bd_flags); 5738 } 5739 5740 void 5741 bnx_dump_l2fhdr(struct bnx_softc *sc, int idx, struct l2_fhdr *l2fhdr) 5742 { 5743 BNX_PRINTF(sc, "l2_fhdr[0x%04X]: status = 0x%08X, " 5744 "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " 5745 "tcp_udp_xsum = 0x%04X\n", idx, 5746 l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, 5747 l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, 5748 l2fhdr->l2_fhdr_tcp_udp_xsum); 5749 } 5750 5751 /* 5752 * This routine prints the TX chain. 5753 */ 5754 void 5755 bnx_dump_tx_chain(struct bnx_softc *sc, int tx_prod, int count) 5756 { 5757 struct tx_bd *txbd; 5758 int i; 5759 5760 /* First some info about the tx_bd chain structure. */ 5761 aprint_debug_dev(sc->bnx_dev, 5762 "----------------------------" 5763 " tx_bd chain " 5764 "----------------------------\n"); 5765 5766 BNX_PRINTF(sc, 5767 "page size = 0x%08X, tx chain pages = 0x%08X\n", 5768 (u_int32_t)BCM_PAGE_SIZE, (u_int32_t) TX_PAGES); 5769 5770 BNX_PRINTF(sc, 5771 "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 5772 (u_int32_t)TOTAL_TX_BD_PER_PAGE, (u_int32_t)USABLE_TX_BD_PER_PAGE); 5773 5774 BNX_PRINTF(sc, "total tx_bd = 0x%08X\n", TOTAL_TX_BD); 5775 5776 aprint_error_dev(sc->bnx_dev, "" 5777 "-----------------------------" 5778 " tx_bd data " 5779 "-----------------------------\n"); 5780 5781 /* Now print out the tx_bd's themselves. */ 5782 for (i = 0; i < count; i++) { 5783 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 5784 bnx_dump_txbd(sc, tx_prod, txbd); 5785 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); 5786 } 5787 5788 aprint_debug_dev(sc->bnx_dev, 5789 "-----------------------------" 5790 "--------------" 5791 "-----------------------------\n"); 5792 } 5793 5794 /* 5795 * This routine prints the RX chain. 5796 */ 5797 void 5798 bnx_dump_rx_chain(struct bnx_softc *sc, int rx_prod, int count) 5799 { 5800 struct rx_bd *rxbd; 5801 int i; 5802 5803 /* First some info about the tx_bd chain structure. */ 5804 aprint_debug_dev(sc->bnx_dev, 5805 "----------------------------" 5806 " rx_bd chain " 5807 "----------------------------\n"); 5808 5809 aprint_debug_dev(sc->bnx_dev, "----- RX_BD Chain -----\n"); 5810 5811 BNX_PRINTF(sc, 5812 "page size = 0x%08X, rx chain pages = 0x%08X\n", 5813 (u_int32_t)BCM_PAGE_SIZE, (u_int32_t)RX_PAGES); 5814 5815 BNX_PRINTF(sc, 5816 "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 5817 (u_int32_t)TOTAL_RX_BD_PER_PAGE, (u_int32_t)USABLE_RX_BD_PER_PAGE); 5818 5819 BNX_PRINTF(sc, "total rx_bd = 0x%08X\n", TOTAL_RX_BD); 5820 5821 aprint_error_dev(sc->bnx_dev, 5822 "----------------------------" 5823 " rx_bd data " 5824 "----------------------------\n"); 5825 5826 /* Now print out the rx_bd's themselves. */ 5827 for (i = 0; i < count; i++) { 5828 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 5829 bnx_dump_rxbd(sc, rx_prod, rxbd); 5830 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); 5831 } 5832 5833 aprint_debug_dev(sc->bnx_dev, 5834 "----------------------------" 5835 "--------------" 5836 "----------------------------\n"); 5837 } 5838 5839 /* 5840 * This routine prints the status block. 5841 */ 5842 void 5843 bnx_dump_status_block(struct bnx_softc *sc) 5844 { 5845 struct status_block *sblk; 5846 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5847 BUS_DMASYNC_POSTREAD); 5848 5849 sblk = sc->status_block; 5850 5851 aprint_debug_dev(sc->bnx_dev, "----------------------------- Status Block " 5852 "-----------------------------\n"); 5853 5854 BNX_PRINTF(sc, 5855 "attn_bits = 0x%08X, attn_bits_ack = 0x%08X, index = 0x%04X\n", 5856 sblk->status_attn_bits, sblk->status_attn_bits_ack, 5857 sblk->status_idx); 5858 5859 BNX_PRINTF(sc, "rx_cons0 = 0x%08X, tx_cons0 = 0x%08X\n", 5860 sblk->status_rx_quick_consumer_index0, 5861 sblk->status_tx_quick_consumer_index0); 5862 5863 BNX_PRINTF(sc, "status_idx = 0x%04X\n", sblk->status_idx); 5864 5865 /* Theses indices are not used for normal L2 drivers. */ 5866 if (sblk->status_rx_quick_consumer_index1 || 5867 sblk->status_tx_quick_consumer_index1) 5868 BNX_PRINTF(sc, "rx_cons1 = 0x%08X, tx_cons1 = 0x%08X\n", 5869 sblk->status_rx_quick_consumer_index1, 5870 sblk->status_tx_quick_consumer_index1); 5871 5872 if (sblk->status_rx_quick_consumer_index2 || 5873 sblk->status_tx_quick_consumer_index2) 5874 BNX_PRINTF(sc, "rx_cons2 = 0x%08X, tx_cons2 = 0x%08X\n", 5875 sblk->status_rx_quick_consumer_index2, 5876 sblk->status_tx_quick_consumer_index2); 5877 5878 if (sblk->status_rx_quick_consumer_index3 || 5879 sblk->status_tx_quick_consumer_index3) 5880 BNX_PRINTF(sc, "rx_cons3 = 0x%08X, tx_cons3 = 0x%08X\n", 5881 sblk->status_rx_quick_consumer_index3, 5882 sblk->status_tx_quick_consumer_index3); 5883 5884 if (sblk->status_rx_quick_consumer_index4 || 5885 sblk->status_rx_quick_consumer_index5) 5886 BNX_PRINTF(sc, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 5887 sblk->status_rx_quick_consumer_index4, 5888 sblk->status_rx_quick_consumer_index5); 5889 5890 if (sblk->status_rx_quick_consumer_index6 || 5891 sblk->status_rx_quick_consumer_index7) 5892 BNX_PRINTF(sc, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 5893 sblk->status_rx_quick_consumer_index6, 5894 sblk->status_rx_quick_consumer_index7); 5895 5896 if (sblk->status_rx_quick_consumer_index8 || 5897 sblk->status_rx_quick_consumer_index9) 5898 BNX_PRINTF(sc, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 5899 sblk->status_rx_quick_consumer_index8, 5900 sblk->status_rx_quick_consumer_index9); 5901 5902 if (sblk->status_rx_quick_consumer_index10 || 5903 sblk->status_rx_quick_consumer_index11) 5904 BNX_PRINTF(sc, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 5905 sblk->status_rx_quick_consumer_index10, 5906 sblk->status_rx_quick_consumer_index11); 5907 5908 if (sblk->status_rx_quick_consumer_index12 || 5909 sblk->status_rx_quick_consumer_index13) 5910 BNX_PRINTF(sc, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 5911 sblk->status_rx_quick_consumer_index12, 5912 sblk->status_rx_quick_consumer_index13); 5913 5914 if (sblk->status_rx_quick_consumer_index14 || 5915 sblk->status_rx_quick_consumer_index15) 5916 BNX_PRINTF(sc, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 5917 sblk->status_rx_quick_consumer_index14, 5918 sblk->status_rx_quick_consumer_index15); 5919 5920 if (sblk->status_completion_producer_index || 5921 sblk->status_cmd_consumer_index) 5922 BNX_PRINTF(sc, "com_prod = 0x%08X, cmd_cons = 0x%08X\n", 5923 sblk->status_completion_producer_index, 5924 sblk->status_cmd_consumer_index); 5925 5926 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 5927 "-----------------------------\n"); 5928 } 5929 5930 /* 5931 * This routine prints the statistics block. 5932 */ 5933 void 5934 bnx_dump_stats_block(struct bnx_softc *sc) 5935 { 5936 struct statistics_block *sblk; 5937 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5938 BUS_DMASYNC_POSTREAD); 5939 5940 sblk = sc->stats_block; 5941 5942 aprint_debug_dev(sc->bnx_dev, "" 5943 "-----------------------------" 5944 " Stats Block " 5945 "-----------------------------\n"); 5946 5947 BNX_PRINTF(sc, "IfHcInOctets = 0x%08X:%08X, " 5948 "IfHcInBadOctets = 0x%08X:%08X\n", 5949 sblk->stat_IfHCInOctets_hi, sblk->stat_IfHCInOctets_lo, 5950 sblk->stat_IfHCInBadOctets_hi, sblk->stat_IfHCInBadOctets_lo); 5951 5952 BNX_PRINTF(sc, "IfHcOutOctets = 0x%08X:%08X, " 5953 "IfHcOutBadOctets = 0x%08X:%08X\n", 5954 sblk->stat_IfHCOutOctets_hi, sblk->stat_IfHCOutOctets_lo, 5955 sblk->stat_IfHCOutBadOctets_hi, sblk->stat_IfHCOutBadOctets_lo); 5956 5957 BNX_PRINTF(sc, "IfHcInUcastPkts = 0x%08X:%08X, " 5958 "IfHcInMulticastPkts = 0x%08X:%08X\n", 5959 sblk->stat_IfHCInUcastPkts_hi, sblk->stat_IfHCInUcastPkts_lo, 5960 sblk->stat_IfHCInMulticastPkts_hi, 5961 sblk->stat_IfHCInMulticastPkts_lo); 5962 5963 BNX_PRINTF(sc, "IfHcInBroadcastPkts = 0x%08X:%08X, " 5964 "IfHcOutUcastPkts = 0x%08X:%08X\n", 5965 sblk->stat_IfHCInBroadcastPkts_hi, 5966 sblk->stat_IfHCInBroadcastPkts_lo, 5967 sblk->stat_IfHCOutUcastPkts_hi, 5968 sblk->stat_IfHCOutUcastPkts_lo); 5969 5970 BNX_PRINTF(sc, "IfHcOutMulticastPkts = 0x%08X:%08X, " 5971 "IfHcOutBroadcastPkts = 0x%08X:%08X\n", 5972 sblk->stat_IfHCOutMulticastPkts_hi, 5973 sblk->stat_IfHCOutMulticastPkts_lo, 5974 sblk->stat_IfHCOutBroadcastPkts_hi, 5975 sblk->stat_IfHCOutBroadcastPkts_lo); 5976 5977 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 5978 BNX_PRINTF(sc, "0x%08X : " 5979 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 5980 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 5981 5982 if (sblk->stat_Dot3StatsCarrierSenseErrors) 5983 BNX_PRINTF(sc, "0x%08X : Dot3StatsCarrierSenseErrors\n", 5984 sblk->stat_Dot3StatsCarrierSenseErrors); 5985 5986 if (sblk->stat_Dot3StatsFCSErrors) 5987 BNX_PRINTF(sc, "0x%08X : Dot3StatsFCSErrors\n", 5988 sblk->stat_Dot3StatsFCSErrors); 5989 5990 if (sblk->stat_Dot3StatsAlignmentErrors) 5991 BNX_PRINTF(sc, "0x%08X : Dot3StatsAlignmentErrors\n", 5992 sblk->stat_Dot3StatsAlignmentErrors); 5993 5994 if (sblk->stat_Dot3StatsSingleCollisionFrames) 5995 BNX_PRINTF(sc, "0x%08X : Dot3StatsSingleCollisionFrames\n", 5996 sblk->stat_Dot3StatsSingleCollisionFrames); 5997 5998 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 5999 BNX_PRINTF(sc, "0x%08X : Dot3StatsMultipleCollisionFrames\n", 6000 sblk->stat_Dot3StatsMultipleCollisionFrames); 6001 6002 if (sblk->stat_Dot3StatsDeferredTransmissions) 6003 BNX_PRINTF(sc, "0x%08X : Dot3StatsDeferredTransmissions\n", 6004 sblk->stat_Dot3StatsDeferredTransmissions); 6005 6006 if (sblk->stat_Dot3StatsExcessiveCollisions) 6007 BNX_PRINTF(sc, "0x%08X : Dot3StatsExcessiveCollisions\n", 6008 sblk->stat_Dot3StatsExcessiveCollisions); 6009 6010 if (sblk->stat_Dot3StatsLateCollisions) 6011 BNX_PRINTF(sc, "0x%08X : Dot3StatsLateCollisions\n", 6012 sblk->stat_Dot3StatsLateCollisions); 6013 6014 if (sblk->stat_EtherStatsCollisions) 6015 BNX_PRINTF(sc, "0x%08X : EtherStatsCollisions\n", 6016 sblk->stat_EtherStatsCollisions); 6017 6018 if (sblk->stat_EtherStatsFragments) 6019 BNX_PRINTF(sc, "0x%08X : EtherStatsFragments\n", 6020 sblk->stat_EtherStatsFragments); 6021 6022 if (sblk->stat_EtherStatsJabbers) 6023 BNX_PRINTF(sc, "0x%08X : EtherStatsJabbers\n", 6024 sblk->stat_EtherStatsJabbers); 6025 6026 if (sblk->stat_EtherStatsUndersizePkts) 6027 BNX_PRINTF(sc, "0x%08X : EtherStatsUndersizePkts\n", 6028 sblk->stat_EtherStatsUndersizePkts); 6029 6030 if (sblk->stat_EtherStatsOverrsizePkts) 6031 BNX_PRINTF(sc, "0x%08X : EtherStatsOverrsizePkts\n", 6032 sblk->stat_EtherStatsOverrsizePkts); 6033 6034 if (sblk->stat_EtherStatsPktsRx64Octets) 6035 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx64Octets\n", 6036 sblk->stat_EtherStatsPktsRx64Octets); 6037 6038 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 6039 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 6040 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 6041 6042 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 6043 BNX_PRINTF(sc, "0x%08X : " 6044 "EtherStatsPktsRx128Octetsto255Octets\n", 6045 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 6046 6047 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 6048 BNX_PRINTF(sc, "0x%08X : " 6049 "EtherStatsPktsRx256Octetsto511Octets\n", 6050 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 6051 6052 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 6053 BNX_PRINTF(sc, "0x%08X : " 6054 "EtherStatsPktsRx512Octetsto1023Octets\n", 6055 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 6056 6057 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 6058 BNX_PRINTF(sc, "0x%08X : " 6059 "EtherStatsPktsRx1024Octetsto1522Octets\n", 6060 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 6061 6062 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 6063 BNX_PRINTF(sc, "0x%08X : " 6064 "EtherStatsPktsRx1523Octetsto9022Octets\n", 6065 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 6066 6067 if (sblk->stat_EtherStatsPktsTx64Octets) 6068 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx64Octets\n", 6069 sblk->stat_EtherStatsPktsTx64Octets); 6070 6071 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 6072 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 6073 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 6074 6075 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 6076 BNX_PRINTF(sc, "0x%08X : " 6077 "EtherStatsPktsTx128Octetsto255Octets\n", 6078 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 6079 6080 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 6081 BNX_PRINTF(sc, "0x%08X : " 6082 "EtherStatsPktsTx256Octetsto511Octets\n", 6083 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 6084 6085 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 6086 BNX_PRINTF(sc, "0x%08X : " 6087 "EtherStatsPktsTx512Octetsto1023Octets\n", 6088 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 6089 6090 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 6091 BNX_PRINTF(sc, "0x%08X : " 6092 "EtherStatsPktsTx1024Octetsto1522Octets\n", 6093 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 6094 6095 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 6096 BNX_PRINTF(sc, "0x%08X : " 6097 "EtherStatsPktsTx1523Octetsto9022Octets\n", 6098 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 6099 6100 if (sblk->stat_XonPauseFramesReceived) 6101 BNX_PRINTF(sc, "0x%08X : XonPauseFramesReceived\n", 6102 sblk->stat_XonPauseFramesReceived); 6103 6104 if (sblk->stat_XoffPauseFramesReceived) 6105 BNX_PRINTF(sc, "0x%08X : XoffPauseFramesReceived\n", 6106 sblk->stat_XoffPauseFramesReceived); 6107 6108 if (sblk->stat_OutXonSent) 6109 BNX_PRINTF(sc, "0x%08X : OutXonSent\n", 6110 sblk->stat_OutXonSent); 6111 6112 if (sblk->stat_OutXoffSent) 6113 BNX_PRINTF(sc, "0x%08X : OutXoffSent\n", 6114 sblk->stat_OutXoffSent); 6115 6116 if (sblk->stat_FlowControlDone) 6117 BNX_PRINTF(sc, "0x%08X : FlowControlDone\n", 6118 sblk->stat_FlowControlDone); 6119 6120 if (sblk->stat_MacControlFramesReceived) 6121 BNX_PRINTF(sc, "0x%08X : MacControlFramesReceived\n", 6122 sblk->stat_MacControlFramesReceived); 6123 6124 if (sblk->stat_XoffStateEntered) 6125 BNX_PRINTF(sc, "0x%08X : XoffStateEntered\n", 6126 sblk->stat_XoffStateEntered); 6127 6128 if (sblk->stat_IfInFramesL2FilterDiscards) 6129 BNX_PRINTF(sc, "0x%08X : IfInFramesL2FilterDiscards\n", 6130 sblk->stat_IfInFramesL2FilterDiscards); 6131 6132 if (sblk->stat_IfInRuleCheckerDiscards) 6133 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerDiscards\n", 6134 sblk->stat_IfInRuleCheckerDiscards); 6135 6136 if (sblk->stat_IfInFTQDiscards) 6137 BNX_PRINTF(sc, "0x%08X : IfInFTQDiscards\n", 6138 sblk->stat_IfInFTQDiscards); 6139 6140 if (sblk->stat_IfInMBUFDiscards) 6141 BNX_PRINTF(sc, "0x%08X : IfInMBUFDiscards\n", 6142 sblk->stat_IfInMBUFDiscards); 6143 6144 if (sblk->stat_IfInRuleCheckerP4Hit) 6145 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerP4Hit\n", 6146 sblk->stat_IfInRuleCheckerP4Hit); 6147 6148 if (sblk->stat_CatchupInRuleCheckerDiscards) 6149 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerDiscards\n", 6150 sblk->stat_CatchupInRuleCheckerDiscards); 6151 6152 if (sblk->stat_CatchupInFTQDiscards) 6153 BNX_PRINTF(sc, "0x%08X : CatchupInFTQDiscards\n", 6154 sblk->stat_CatchupInFTQDiscards); 6155 6156 if (sblk->stat_CatchupInMBUFDiscards) 6157 BNX_PRINTF(sc, "0x%08X : CatchupInMBUFDiscards\n", 6158 sblk->stat_CatchupInMBUFDiscards); 6159 6160 if (sblk->stat_CatchupInRuleCheckerP4Hit) 6161 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerP4Hit\n", 6162 sblk->stat_CatchupInRuleCheckerP4Hit); 6163 6164 aprint_debug_dev(sc->bnx_dev, 6165 "-----------------------------" 6166 "--------------" 6167 "-----------------------------\n"); 6168 } 6169 6170 void 6171 bnx_dump_driver_state(struct bnx_softc *sc) 6172 { 6173 aprint_debug_dev(sc->bnx_dev, 6174 "-----------------------------" 6175 " Driver State " 6176 "-----------------------------\n"); 6177 6178 BNX_PRINTF(sc, "%p - (sc) driver softc structure virtual " 6179 "address\n", sc); 6180 6181 BNX_PRINTF(sc, "%p - (sc->status_block) status block virtual address\n", 6182 sc->status_block); 6183 6184 BNX_PRINTF(sc, "%p - (sc->stats_block) statistics block virtual " 6185 "address\n", sc->stats_block); 6186 6187 BNX_PRINTF(sc, "%p - (sc->tx_bd_chain) tx_bd chain virtual " 6188 "adddress\n", sc->tx_bd_chain); 6189 6190 #if 0 6191 BNX_PRINTF(sc, "%p - (sc->rx_bd_chain) rx_bd chain virtual address\n", 6192 sc->rx_bd_chain); 6193 6194 BNX_PRINTF(sc, "%p - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 6195 sc->tx_mbuf_ptr); 6196 #endif 6197 6198 BNX_PRINTF(sc, "%p - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 6199 sc->rx_mbuf_ptr); 6200 6201 BNX_PRINTF(sc, 6202 " 0x%08X - (sc->interrupts_generated) h/w intrs\n", 6203 sc->interrupts_generated); 6204 6205 BNX_PRINTF(sc, 6206 " 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 6207 sc->rx_interrupts); 6208 6209 BNX_PRINTF(sc, 6210 " 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 6211 sc->tx_interrupts); 6212 6213 BNX_PRINTF(sc, 6214 " 0x%08X - (sc->last_status_idx) status block index\n", 6215 sc->last_status_idx); 6216 6217 BNX_PRINTF(sc, " 0x%08X - (sc->tx_prod) tx producer index\n", 6218 sc->tx_prod); 6219 6220 BNX_PRINTF(sc, " 0x%08X - (sc->tx_cons) tx consumer index\n", 6221 sc->tx_cons); 6222 6223 BNX_PRINTF(sc, 6224 " 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 6225 sc->tx_prod_bseq); 6226 BNX_PRINTF(sc, 6227 " 0x%08X - (sc->tx_mbuf_alloc) tx mbufs allocated\n", 6228 sc->tx_mbuf_alloc); 6229 6230 BNX_PRINTF(sc, 6231 " 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 6232 sc->used_tx_bd); 6233 6234 BNX_PRINTF(sc, 6235 " 0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 6236 sc->tx_hi_watermark, sc->max_tx_bd); 6237 6238 6239 BNX_PRINTF(sc, " 0x%08X - (sc->rx_prod) rx producer index\n", 6240 sc->rx_prod); 6241 6242 BNX_PRINTF(sc, " 0x%08X - (sc->rx_cons) rx consumer index\n", 6243 sc->rx_cons); 6244 6245 BNX_PRINTF(sc, 6246 " 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 6247 sc->rx_prod_bseq); 6248 6249 BNX_PRINTF(sc, 6250 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 6251 sc->rx_mbuf_alloc); 6252 6253 BNX_PRINTF(sc, " 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 6254 sc->free_rx_bd); 6255 6256 BNX_PRINTF(sc, 6257 "0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", 6258 sc->rx_low_watermark, sc->max_rx_bd); 6259 6260 BNX_PRINTF(sc, 6261 " 0x%08X - (sc->mbuf_alloc_failed) " 6262 "mbuf alloc failures\n", 6263 sc->mbuf_alloc_failed); 6264 6265 BNX_PRINTF(sc, 6266 " 0x%0X - (sc->mbuf_sim_allocated_failed) " 6267 "simulated mbuf alloc failures\n", 6268 sc->mbuf_sim_alloc_failed); 6269 6270 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 6271 "-----------------------------\n"); 6272 } 6273 6274 void 6275 bnx_dump_hw_state(struct bnx_softc *sc) 6276 { 6277 u_int32_t val1; 6278 int i; 6279 6280 aprint_debug_dev(sc->bnx_dev, 6281 "----------------------------" 6282 " Hardware State " 6283 "----------------------------\n"); 6284 6285 BNX_PRINTF(sc, "0x%08X : bootcode version\n", sc->bnx_fw_ver); 6286 6287 val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS); 6288 BNX_PRINTF(sc, "0x%08X : (0x%04X) misc_enable_status_bits\n", 6289 val1, BNX_MISC_ENABLE_STATUS_BITS); 6290 6291 val1 = REG_RD(sc, BNX_DMA_STATUS); 6292 BNX_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BNX_DMA_STATUS); 6293 6294 val1 = REG_RD(sc, BNX_CTX_STATUS); 6295 BNX_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BNX_CTX_STATUS); 6296 6297 val1 = REG_RD(sc, BNX_EMAC_STATUS); 6298 BNX_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1, 6299 BNX_EMAC_STATUS); 6300 6301 val1 = REG_RD(sc, BNX_RPM_STATUS); 6302 BNX_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BNX_RPM_STATUS); 6303 6304 val1 = REG_RD(sc, BNX_TBDR_STATUS); 6305 BNX_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1, 6306 BNX_TBDR_STATUS); 6307 6308 val1 = REG_RD(sc, BNX_TDMA_STATUS); 6309 BNX_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1, 6310 BNX_TDMA_STATUS); 6311 6312 val1 = REG_RD(sc, BNX_HC_STATUS); 6313 BNX_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BNX_HC_STATUS); 6314 6315 aprint_debug_dev(sc->bnx_dev, 6316 "----------------------------" 6317 "----------------" 6318 "----------------------------\n"); 6319 6320 aprint_debug_dev(sc->bnx_dev, 6321 "----------------------------" 6322 " Register Dump " 6323 "----------------------------\n"); 6324 6325 for (i = 0x400; i < 0x8000; i += 0x10) 6326 BNX_PRINTF(sc, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 6327 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 6328 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 6329 6330 aprint_debug_dev(sc->bnx_dev, 6331 "----------------------------" 6332 "----------------" 6333 "----------------------------\n"); 6334 } 6335 6336 void 6337 bnx_breakpoint(struct bnx_softc *sc) 6338 { 6339 /* Unreachable code to shut the compiler up about unused functions. */ 6340 if (0) { 6341 bnx_dump_txbd(sc, 0, NULL); 6342 bnx_dump_rxbd(sc, 0, NULL); 6343 bnx_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 6344 bnx_dump_rx_mbuf_chain(sc, 0, sc->max_rx_bd); 6345 bnx_dump_l2fhdr(sc, 0, NULL); 6346 bnx_dump_tx_chain(sc, 0, USABLE_TX_BD); 6347 bnx_dump_rx_chain(sc, 0, sc->max_rx_bd); 6348 bnx_dump_status_block(sc); 6349 bnx_dump_stats_block(sc); 6350 bnx_dump_driver_state(sc); 6351 bnx_dump_hw_state(sc); 6352 } 6353 6354 bnx_dump_driver_state(sc); 6355 /* Print the important status block fields. */ 6356 bnx_dump_status_block(sc); 6357 6358 #if 0 6359 /* Call the debugger. */ 6360 breakpoint(); 6361 #endif 6362 6363 return; 6364 } 6365 #endif 6366