1 /* $NetBSD: if_cas.c,v 1.13 2011/01/07 11:17:22 jmcneill Exp $ */ 2 /* $OpenBSD: if_cas.c,v 1.29 2009/11/29 16:19:38 kettenis Exp $ */ 3 4 /* 5 * 6 * Copyright (C) 2007 Mark Kettenis. 7 * Copyright (C) 2001 Eduardo Horvath. 8 * All rights reserved. 9 * 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 /* 35 * Driver for Sun Cassini ethernet controllers. 36 * 37 * There are basically two variants of this chip: Cassini and 38 * Cassini+. We can distinguish between the two by revision: 0x10 and 39 * up are Cassini+. The most important difference is that Cassini+ 40 * has a second RX descriptor ring. Cassini+ will not work without 41 * configuring that second ring. However, since we don't use it we 42 * don't actually fill the descriptors, and only hand off the first 43 * four to the chip. 44 */ 45 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: if_cas.c,v 1.13 2011/01/07 11:17:22 jmcneill Exp $"); 48 49 #ifndef _MODULE 50 #include "opt_inet.h" 51 #endif 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/callout.h> 56 #include <sys/mbuf.h> 57 #include <sys/syslog.h> 58 #include <sys/malloc.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 #include <sys/ioctl.h> 62 #include <sys/errno.h> 63 #include <sys/device.h> 64 #include <sys/module.h> 65 66 #include <machine/endian.h> 67 68 #include <net/if.h> 69 #include <net/if_dl.h> 70 #include <net/if_media.h> 71 #include <net/if_ether.h> 72 73 #ifdef INET 74 #include <netinet/in.h> 75 #include <netinet/in_systm.h> 76 #include <netinet/in_var.h> 77 #include <netinet/ip.h> 78 #include <netinet/tcp.h> 79 #include <netinet/udp.h> 80 #endif 81 82 #include <net/bpf.h> 83 84 #include <sys/bus.h> 85 #include <sys/intr.h> 86 87 #include <dev/mii/mii.h> 88 #include <dev/mii/miivar.h> 89 #include <dev/mii/mii_bitbang.h> 90 91 #include <dev/pci/pcivar.h> 92 #include <dev/pci/pcireg.h> 93 #include <dev/pci/pcidevs.h> 94 #include <prop/proplib.h> 95 96 #include <dev/pci/if_casreg.h> 97 #include <dev/pci/if_casvar.h> 98 99 #define TRIES 10000 100 101 static bool cas_estintr(struct cas_softc *sc, int); 102 bool cas_shutdown(device_t, int); 103 static bool cas_suspend(device_t, const pmf_qual_t *); 104 static bool cas_resume(device_t, const pmf_qual_t *); 105 static int cas_detach(device_t, int); 106 static void cas_partial_detach(struct cas_softc *, enum cas_attach_stage); 107 108 int cas_match(device_t, cfdata_t, void *); 109 void cas_attach(device_t, device_t, void *); 110 111 112 CFATTACH_DECL3_NEW(cas, sizeof(struct cas_softc), 113 cas_match, cas_attach, cas_detach, NULL, NULL, NULL, 114 DVF_DETACH_SHUTDOWN); 115 116 int cas_pci_enaddr(struct cas_softc *, struct pci_attach_args *, uint8_t *); 117 118 void cas_config(struct cas_softc *, const uint8_t *); 119 void cas_start(struct ifnet *); 120 void cas_stop(struct ifnet *, int); 121 int cas_ioctl(struct ifnet *, u_long, void *); 122 void cas_tick(void *); 123 void cas_watchdog(struct ifnet *); 124 int cas_init(struct ifnet *); 125 void cas_init_regs(struct cas_softc *); 126 int cas_ringsize(int); 127 int cas_cringsize(int); 128 int cas_meminit(struct cas_softc *); 129 void cas_mifinit(struct cas_softc *); 130 int cas_bitwait(struct cas_softc *, bus_space_handle_t, int, 131 u_int32_t, u_int32_t); 132 void cas_reset(struct cas_softc *); 133 int cas_reset_rx(struct cas_softc *); 134 int cas_reset_tx(struct cas_softc *); 135 int cas_disable_rx(struct cas_softc *); 136 int cas_disable_tx(struct cas_softc *); 137 void cas_rxdrain(struct cas_softc *); 138 int cas_add_rxbuf(struct cas_softc *, int idx); 139 void cas_iff(struct cas_softc *); 140 int cas_encap(struct cas_softc *, struct mbuf *, u_int32_t *); 141 142 /* MII methods & callbacks */ 143 int cas_mii_readreg(device_t, int, int); 144 void cas_mii_writereg(device_t, int, int, int); 145 void cas_mii_statchg(device_t); 146 int cas_pcs_readreg(device_t, int, int); 147 void cas_pcs_writereg(device_t, int, int, int); 148 149 int cas_mediachange(struct ifnet *); 150 void cas_mediastatus(struct ifnet *, struct ifmediareq *); 151 152 int cas_eint(struct cas_softc *, u_int); 153 int cas_rint(struct cas_softc *); 154 int cas_tint(struct cas_softc *, u_int32_t); 155 int cas_pint(struct cas_softc *); 156 int cas_intr(void *); 157 158 #ifdef CAS_DEBUG 159 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 160 printf x 161 #else 162 #define DPRINTF(sc, x) /* nothing */ 163 #endif 164 165 int 166 cas_match(device_t parent, cfdata_t cf, void *aux) 167 { 168 struct pci_attach_args *pa = aux; 169 170 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN && 171 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_CASSINI)) 172 return 1; 173 174 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS && 175 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NS_SATURN)) 176 return 1; 177 178 return 0; 179 } 180 181 #define PROMHDR_PTR_DATA 0x18 182 #define PROMDATA_PTR_VPD 0x08 183 #define PROMDATA_DATA2 0x0a 184 185 static const u_int8_t cas_promhdr[] = { 0x55, 0xaa }; 186 static const u_int8_t cas_promdat[] = { 187 'P', 'C', 'I', 'R', 188 PCI_VENDOR_SUN & 0xff, PCI_VENDOR_SUN >> 8, 189 PCI_PRODUCT_SUN_CASSINI & 0xff, PCI_PRODUCT_SUN_CASSINI >> 8 190 }; 191 static const u_int8_t cas_promdat_ns[] = { 192 'P', 'C', 'I', 'R', 193 PCI_VENDOR_NS & 0xff, PCI_VENDOR_NS >> 8, 194 PCI_PRODUCT_NS_SATURN & 0xff, PCI_PRODUCT_NS_SATURN >> 8 195 }; 196 197 static const u_int8_t cas_promdat2[] = { 198 0x18, 0x00, /* structure length */ 199 0x00, /* structure revision */ 200 0x00, /* interface revision */ 201 PCI_SUBCLASS_NETWORK_ETHERNET, /* subclass code */ 202 PCI_CLASS_NETWORK /* class code */ 203 }; 204 205 int 206 cas_pci_enaddr(struct cas_softc *sc, struct pci_attach_args *pa, 207 uint8_t *enaddr) 208 { 209 struct pci_vpd_largeres *res; 210 struct pci_vpd *vpd; 211 bus_space_handle_t romh; 212 bus_space_tag_t romt; 213 bus_size_t romsize = 0; 214 u_int8_t buf[32], *desc; 215 pcireg_t address; 216 int dataoff, vpdoff, len; 217 int rv = -1; 218 219 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_MEM, 0, 220 &romt, &romh, NULL, &romsize)) 221 return (-1); 222 223 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START); 224 address |= PCI_MAPREG_ROM_ENABLE; 225 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START, address); 226 227 bus_space_read_region_1(romt, romh, 0, buf, sizeof(buf)); 228 if (bcmp(buf, cas_promhdr, sizeof(cas_promhdr))) 229 goto fail; 230 231 dataoff = buf[PROMHDR_PTR_DATA] | (buf[PROMHDR_PTR_DATA + 1] << 8); 232 if (dataoff < 0x1c) 233 goto fail; 234 235 bus_space_read_region_1(romt, romh, dataoff, buf, sizeof(buf)); 236 if ((bcmp(buf, cas_promdat, sizeof(cas_promdat)) && 237 bcmp(buf, cas_promdat_ns, sizeof(cas_promdat_ns))) || 238 bcmp(buf + PROMDATA_DATA2, cas_promdat2, sizeof(cas_promdat2))) 239 goto fail; 240 241 vpdoff = buf[PROMDATA_PTR_VPD] | (buf[PROMDATA_PTR_VPD + 1] << 8); 242 if (vpdoff < 0x1c) 243 goto fail; 244 245 next: 246 bus_space_read_region_1(romt, romh, vpdoff, buf, sizeof(buf)); 247 if (!PCI_VPDRES_ISLARGE(buf[0])) 248 goto fail; 249 250 res = (struct pci_vpd_largeres *)buf; 251 vpdoff += sizeof(*res); 252 253 len = ((res->vpdres_len_msb << 8) + res->vpdres_len_lsb); 254 switch(PCI_VPDRES_LARGE_NAME(res->vpdres_byte0)) { 255 case PCI_VPDRES_TYPE_IDENTIFIER_STRING: 256 /* Skip identifier string. */ 257 vpdoff += len; 258 goto next; 259 260 case PCI_VPDRES_TYPE_VPD: 261 while (len > 0) { 262 bus_space_read_region_1(romt, romh, vpdoff, 263 buf, sizeof(buf)); 264 265 vpd = (struct pci_vpd *)buf; 266 vpdoff += sizeof(*vpd) + vpd->vpd_len; 267 len -= sizeof(*vpd) + vpd->vpd_len; 268 269 /* 270 * We're looking for an "Enhanced" VPD... 271 */ 272 if (vpd->vpd_key0 != 'Z') 273 continue; 274 275 desc = buf + sizeof(*vpd); 276 277 /* 278 * ...which is an instance property... 279 */ 280 if (desc[0] != 'I') 281 continue; 282 desc += 3; 283 284 /* 285 * ...that's a byte array with the proper 286 * length for a MAC address... 287 */ 288 if (desc[0] != 'B' || desc[1] != ETHER_ADDR_LEN) 289 continue; 290 desc += 2; 291 292 /* 293 * ...named "local-mac-address". 294 */ 295 if (strcmp(desc, "local-mac-address") != 0) 296 continue; 297 desc += strlen("local-mac-address") + 1; 298 299 memcpy(enaddr, desc, ETHER_ADDR_LEN); 300 rv = 0; 301 } 302 break; 303 304 default: 305 goto fail; 306 } 307 308 fail: 309 if (romsize != 0) 310 bus_space_unmap(romt, romh, romsize); 311 312 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM); 313 address &= ~PCI_MAPREG_ROM_ENABLE; 314 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, address); 315 316 return (rv); 317 } 318 319 void 320 cas_attach(device_t parent, device_t self, void *aux) 321 { 322 struct pci_attach_args *pa = aux; 323 struct cas_softc *sc = device_private(self); 324 char devinfo[256]; 325 prop_data_t data; 326 uint8_t enaddr[ETHER_ADDR_LEN]; 327 328 sc->sc_dev = self; 329 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 330 sc->sc_rev = PCI_REVISION(pa->pa_class); 331 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, sc->sc_rev); 332 sc->sc_dmatag = pa->pa_dmat; 333 334 #define PCI_CAS_BASEADDR 0x10 335 if (pci_mapreg_map(pa, PCI_CAS_BASEADDR, PCI_MAPREG_TYPE_MEM, 0, 336 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_size) != 0) { 337 aprint_error_dev(sc->sc_dev, 338 "unable to map device registers\n"); 339 return; 340 } 341 342 if ((data = prop_dictionary_get(device_properties(sc->sc_dev), 343 "mac-address")) != NULL) 344 memcpy(enaddr, prop_data_data_nocopy(data), ETHER_ADDR_LEN); 345 else if (cas_pci_enaddr(sc, pa, enaddr) != 0) { 346 aprint_error_dev(sc->sc_dev, "no Ethernet address found\n"); 347 memset(enaddr, 0, sizeof(enaddr)); 348 } 349 350 sc->sc_burst = 16; /* XXX */ 351 352 sc->sc_att_stage = CAS_ATT_BACKEND_0; 353 354 if (pci_intr_map(pa, &sc->sc_handle) != 0) { 355 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 356 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 357 return; 358 } 359 sc->sc_pc = pa->pa_pc; 360 if (!cas_estintr(sc, CAS_INTR_PCI)) { 361 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 362 aprint_error_dev(sc->sc_dev, "unable to establish interrupt\n"); 363 return; 364 } 365 366 sc->sc_att_stage = CAS_ATT_BACKEND_1; 367 368 /* 369 * call the main configure 370 */ 371 cas_config(sc, enaddr); 372 373 if (pmf_device_register1(sc->sc_dev, 374 cas_suspend, cas_resume, cas_shutdown)) 375 pmf_class_network_register(sc->sc_dev, &sc->sc_ethercom.ec_if); 376 else 377 aprint_error_dev(sc->sc_dev, 378 "could not establish power handlers\n"); 379 380 sc->sc_att_stage = CAS_ATT_FINISHED; 381 /*FALLTHROUGH*/ 382 } 383 384 /* 385 * cas_config: 386 * 387 * Attach a Cassini interface to the system. 388 */ 389 void 390 cas_config(struct cas_softc *sc, const uint8_t *enaddr) 391 { 392 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 393 struct mii_data *mii = &sc->sc_mii; 394 struct mii_softc *child; 395 int i, error; 396 397 /* Make sure the chip is stopped. */ 398 ifp->if_softc = sc; 399 cas_reset(sc); 400 401 /* 402 * Allocate the control data structures, and create and load the 403 * DMA map for it. 404 */ 405 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 406 sizeof(struct cas_control_data), CAS_PAGE_SIZE, 0, &sc->sc_cdseg, 407 1, &sc->sc_cdnseg, 0)) != 0) { 408 aprint_error_dev(sc->sc_dev, 409 "unable to allocate control data, error = %d\n", 410 error); 411 cas_partial_detach(sc, CAS_ATT_0); 412 } 413 414 /* XXX should map this in with correct endianness */ 415 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 416 sizeof(struct cas_control_data), (void **)&sc->sc_control_data, 417 BUS_DMA_COHERENT)) != 0) { 418 aprint_error_dev(sc->sc_dev, 419 "unable to map control data, error = %d\n", error); 420 cas_partial_detach(sc, CAS_ATT_1); 421 } 422 423 if ((error = bus_dmamap_create(sc->sc_dmatag, 424 sizeof(struct cas_control_data), 1, 425 sizeof(struct cas_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 426 aprint_error_dev(sc->sc_dev, 427 "unable to create control data DMA map, error = %d\n", error); 428 cas_partial_detach(sc, CAS_ATT_2); 429 } 430 431 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 432 sc->sc_control_data, sizeof(struct cas_control_data), NULL, 433 0)) != 0) { 434 aprint_error_dev(sc->sc_dev, 435 "unable to load control data DMA map, error = %d\n", 436 error); 437 cas_partial_detach(sc, CAS_ATT_3); 438 } 439 440 memset(sc->sc_control_data, 0, sizeof(struct cas_control_data)); 441 442 /* 443 * Create the receive buffer DMA maps. 444 */ 445 for (i = 0; i < CAS_NRXDESC; i++) { 446 bus_dma_segment_t seg; 447 char *kva; 448 int rseg; 449 450 if ((error = bus_dmamem_alloc(sc->sc_dmatag, CAS_PAGE_SIZE, 451 CAS_PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 452 aprint_error_dev(sc->sc_dev, 453 "unable to alloc rx DMA mem %d, error = %d\n", 454 i, error); 455 cas_partial_detach(sc, CAS_ATT_5); 456 } 457 sc->sc_rxsoft[i].rxs_dmaseg = seg; 458 459 if ((error = bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 460 CAS_PAGE_SIZE, (void **)&kva, BUS_DMA_NOWAIT)) != 0) { 461 aprint_error_dev(sc->sc_dev, 462 "unable to alloc rx DMA mem %d, error = %d\n", 463 i, error); 464 cas_partial_detach(sc, CAS_ATT_5); 465 } 466 sc->sc_rxsoft[i].rxs_kva = kva; 467 468 if ((error = bus_dmamap_create(sc->sc_dmatag, CAS_PAGE_SIZE, 1, 469 CAS_PAGE_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 470 aprint_error_dev(sc->sc_dev, 471 "unable to create rx DMA map %d, error = %d\n", 472 i, error); 473 cas_partial_detach(sc, CAS_ATT_5); 474 } 475 476 if ((error = bus_dmamap_load(sc->sc_dmatag, 477 sc->sc_rxsoft[i].rxs_dmamap, kva, CAS_PAGE_SIZE, NULL, 478 BUS_DMA_NOWAIT)) != 0) { 479 aprint_error_dev(sc->sc_dev, 480 "unable to load rx DMA map %d, error = %d\n", 481 i, error); 482 cas_partial_detach(sc, CAS_ATT_5); 483 } 484 } 485 486 /* 487 * Create the transmit buffer DMA maps. 488 */ 489 for (i = 0; i < CAS_NTXDESC; i++) { 490 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 491 CAS_NTXSEGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 492 &sc->sc_txd[i].sd_map)) != 0) { 493 aprint_error_dev(sc->sc_dev, 494 "unable to create tx DMA map %d, error = %d\n", 495 i, error); 496 cas_partial_detach(sc, CAS_ATT_6); 497 } 498 sc->sc_txd[i].sd_mbuf = NULL; 499 } 500 501 /* 502 * From this point forward, the attachment cannot fail. A failure 503 * before this point releases all resources that may have been 504 * allocated. 505 */ 506 507 /* Announce ourselves. */ 508 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 509 ether_sprintf(enaddr)); 510 aprint_naive(": Ethernet controller\n"); 511 512 /* Get RX FIFO size */ 513 sc->sc_rxfifosize = 16 * 1024; 514 515 /* Initialize ifnet structure. */ 516 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 517 ifp->if_softc = sc; 518 ifp->if_flags = 519 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 520 ifp->if_start = cas_start; 521 ifp->if_ioctl = cas_ioctl; 522 ifp->if_watchdog = cas_watchdog; 523 ifp->if_stop = cas_stop; 524 ifp->if_init = cas_init; 525 IFQ_SET_MAXLEN(&ifp->if_snd, CAS_NTXDESC - 1); 526 IFQ_SET_READY(&ifp->if_snd); 527 528 /* Initialize ifmedia structures and MII info */ 529 mii->mii_ifp = ifp; 530 mii->mii_readreg = cas_mii_readreg; 531 mii->mii_writereg = cas_mii_writereg; 532 mii->mii_statchg = cas_mii_statchg; 533 534 ifmedia_init(&mii->mii_media, 0, cas_mediachange, cas_mediastatus); 535 sc->sc_ethercom.ec_mii = mii; 536 537 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_MII_DATAPATH_MODE, 0); 538 539 cas_mifinit(sc); 540 541 if (sc->sc_mif_config & CAS_MIF_CONFIG_MDI1) { 542 sc->sc_mif_config |= CAS_MIF_CONFIG_PHY_SEL; 543 bus_space_write_4(sc->sc_memt, sc->sc_memh, 544 CAS_MIF_CONFIG, sc->sc_mif_config); 545 } 546 547 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 548 MII_OFFSET_ANY, 0); 549 550 child = LIST_FIRST(&mii->mii_phys); 551 if (child == NULL && 552 sc->sc_mif_config & (CAS_MIF_CONFIG_MDI0|CAS_MIF_CONFIG_MDI1)) { 553 /* 554 * Try the external PCS SERDES if we didn't find any 555 * MII devices. 556 */ 557 bus_space_write_4(sc->sc_memt, sc->sc_memh, 558 CAS_MII_DATAPATH_MODE, CAS_MII_DATAPATH_SERDES); 559 560 bus_space_write_4(sc->sc_memt, sc->sc_memh, 561 CAS_MII_CONFIG, CAS_MII_CONFIG_ENABLE); 562 563 mii->mii_readreg = cas_pcs_readreg; 564 mii->mii_writereg = cas_pcs_writereg; 565 566 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 567 MII_OFFSET_ANY, MIIF_NOISOLATE); 568 } 569 570 child = LIST_FIRST(&mii->mii_phys); 571 if (child == NULL) { 572 /* No PHY attached */ 573 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 574 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 575 } else { 576 /* 577 * Walk along the list of attached MII devices and 578 * establish an `MII instance' to `phy number' 579 * mapping. We'll use this mapping in media change 580 * requests to determine which phy to use to program 581 * the MIF configuration register. 582 */ 583 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 584 /* 585 * Note: we support just two PHYs: the built-in 586 * internal device and an external on the MII 587 * connector. 588 */ 589 if (child->mii_phy > 1 || child->mii_inst > 1) { 590 aprint_error_dev(sc->sc_dev, 591 "cannot accommodate MII device %s" 592 " at phy %d, instance %d\n", 593 device_xname(child->mii_dev), 594 child->mii_phy, child->mii_inst); 595 continue; 596 } 597 598 sc->sc_phys[child->mii_inst] = child->mii_phy; 599 } 600 601 /* 602 * XXX - we can really do the following ONLY if the 603 * phy indeed has the auto negotiation capability!! 604 */ 605 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 606 } 607 608 /* claim 802.1q capability */ 609 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 610 611 /* Attach the interface. */ 612 if_attach(ifp); 613 ether_ifattach(ifp, enaddr); 614 615 #if NRND > 0 616 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 617 RND_TYPE_NET, 0); 618 #endif 619 620 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 621 NULL, device_xname(sc->sc_dev), "interrupts"); 622 623 callout_init(&sc->sc_tick_ch, 0); 624 625 return; 626 } 627 628 int 629 cas_detach(device_t self, int flags) 630 { 631 int i; 632 struct cas_softc *sc = device_private(self); 633 bus_space_tag_t t = sc->sc_memt; 634 bus_space_handle_t h = sc->sc_memh; 635 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 636 637 /* 638 * Free any resources we've allocated during the failed attach 639 * attempt. Do this in reverse order and fall through. 640 */ 641 switch (sc->sc_att_stage) { 642 case CAS_ATT_FINISHED: 643 bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0); 644 pmf_device_deregister(self); 645 cas_stop(&sc->sc_ethercom.ec_if, 1); 646 evcnt_detach(&sc->sc_ev_intr); 647 648 #if NRND > 0 649 rnd_detach_source(&sc->rnd_source); 650 #endif 651 652 ether_ifdetach(ifp); 653 if_detach(ifp); 654 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 655 656 callout_destroy(&sc->sc_tick_ch); 657 658 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 659 660 /*FALLTHROUGH*/ 661 case CAS_ATT_MII: 662 case CAS_ATT_7: 663 case CAS_ATT_6: 664 for (i = 0; i < CAS_NTXDESC; i++) { 665 if (sc->sc_txd[i].sd_map != NULL) 666 bus_dmamap_destroy(sc->sc_dmatag, 667 sc->sc_txd[i].sd_map); 668 } 669 /*FALLTHROUGH*/ 670 case CAS_ATT_5: 671 for (i = 0; i < CAS_NRXDESC; i++) { 672 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 673 bus_dmamap_unload(sc->sc_dmatag, 674 sc->sc_rxsoft[i].rxs_dmamap); 675 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 676 bus_dmamap_destroy(sc->sc_dmatag, 677 sc->sc_rxsoft[i].rxs_dmamap); 678 if (sc->sc_rxsoft[i].rxs_kva != NULL) 679 bus_dmamem_unmap(sc->sc_dmatag, 680 sc->sc_rxsoft[i].rxs_kva, CAS_PAGE_SIZE); 681 /* XXX need to check that bus_dmamem_alloc suceeded 682 if (sc->sc_rxsoft[i].rxs_dmaseg != NULL) 683 */ 684 bus_dmamem_free(sc->sc_dmatag, 685 &(sc->sc_rxsoft[i].rxs_dmaseg), 1); 686 } 687 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 688 /*FALLTHROUGH*/ 689 case CAS_ATT_4: 690 case CAS_ATT_3: 691 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 692 /*FALLTHROUGH*/ 693 case CAS_ATT_2: 694 bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data, 695 sizeof(struct cas_control_data)); 696 /*FALLTHROUGH*/ 697 case CAS_ATT_1: 698 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 699 /*FALLTHROUGH*/ 700 case CAS_ATT_0: 701 sc->sc_att_stage = CAS_ATT_0; 702 /*FALLTHROUGH*/ 703 case CAS_ATT_BACKEND_2: 704 case CAS_ATT_BACKEND_1: 705 if (sc->sc_ih != NULL) { 706 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 707 sc->sc_ih = NULL; 708 } 709 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 710 /*FALLTHROUGH*/ 711 case CAS_ATT_BACKEND_0: 712 break; 713 } 714 return 0; 715 } 716 717 static void 718 cas_partial_detach(struct cas_softc *sc, enum cas_attach_stage stage) 719 { 720 cfattach_t ca = device_cfattach(sc->sc_dev); 721 722 sc->sc_att_stage = stage; 723 (*ca->ca_detach)(sc->sc_dev, 0); 724 } 725 726 void 727 cas_tick(void *arg) 728 { 729 struct cas_softc *sc = arg; 730 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 731 bus_space_tag_t t = sc->sc_memt; 732 bus_space_handle_t mac = sc->sc_memh; 733 int s; 734 u_int32_t v; 735 736 /* unload collisions counters */ 737 v = bus_space_read_4(t, mac, CAS_MAC_EXCESS_COLL_CNT) + 738 bus_space_read_4(t, mac, CAS_MAC_LATE_COLL_CNT); 739 ifp->if_collisions += v + 740 bus_space_read_4(t, mac, CAS_MAC_NORM_COLL_CNT) + 741 bus_space_read_4(t, mac, CAS_MAC_FIRST_COLL_CNT); 742 ifp->if_oerrors += v; 743 744 /* read error counters */ 745 ifp->if_ierrors += 746 bus_space_read_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT) + 747 bus_space_read_4(t, mac, CAS_MAC_RX_ALIGN_ERR) + 748 bus_space_read_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT) + 749 bus_space_read_4(t, mac, CAS_MAC_RX_CODE_VIOL); 750 751 /* clear the hardware counters */ 752 bus_space_write_4(t, mac, CAS_MAC_NORM_COLL_CNT, 0); 753 bus_space_write_4(t, mac, CAS_MAC_FIRST_COLL_CNT, 0); 754 bus_space_write_4(t, mac, CAS_MAC_EXCESS_COLL_CNT, 0); 755 bus_space_write_4(t, mac, CAS_MAC_LATE_COLL_CNT, 0); 756 bus_space_write_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT, 0); 757 bus_space_write_4(t, mac, CAS_MAC_RX_ALIGN_ERR, 0); 758 bus_space_write_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT, 0); 759 bus_space_write_4(t, mac, CAS_MAC_RX_CODE_VIOL, 0); 760 761 s = splnet(); 762 mii_tick(&sc->sc_mii); 763 splx(s); 764 765 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 766 } 767 768 int 769 cas_bitwait(struct cas_softc *sc, bus_space_handle_t h, int r, 770 u_int32_t clr, u_int32_t set) 771 { 772 int i; 773 u_int32_t reg; 774 775 for (i = TRIES; i--; DELAY(100)) { 776 reg = bus_space_read_4(sc->sc_memt, h, r); 777 if ((reg & clr) == 0 && (reg & set) == set) 778 return (1); 779 } 780 781 return (0); 782 } 783 784 void 785 cas_reset(struct cas_softc *sc) 786 { 787 bus_space_tag_t t = sc->sc_memt; 788 bus_space_handle_t h = sc->sc_memh; 789 int s; 790 791 s = splnet(); 792 DPRINTF(sc, ("%s: cas_reset\n", device_xname(sc->sc_dev))); 793 cas_reset_rx(sc); 794 cas_reset_tx(sc); 795 796 /* Disable interrupts */ 797 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_INTMASK, ~(uint32_t)0); 798 799 /* Do a full reset */ 800 bus_space_write_4(t, h, CAS_RESET, 801 CAS_RESET_RX | CAS_RESET_TX | CAS_RESET_BLOCK_PCS); 802 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) 803 aprint_error_dev(sc->sc_dev, "cannot reset device\n"); 804 splx(s); 805 } 806 807 808 /* 809 * cas_rxdrain: 810 * 811 * Drain the receive queue. 812 */ 813 void 814 cas_rxdrain(struct cas_softc *sc) 815 { 816 /* Nothing to do yet. */ 817 } 818 819 /* 820 * Reset the whole thing. 821 */ 822 void 823 cas_stop(struct ifnet *ifp, int disable) 824 { 825 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 826 struct cas_sxd *sd; 827 u_int32_t i; 828 829 DPRINTF(sc, ("%s: cas_stop\n", device_xname(sc->sc_dev))); 830 831 callout_stop(&sc->sc_tick_ch); 832 833 /* 834 * Mark the interface down and cancel the watchdog timer. 835 */ 836 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 837 ifp->if_timer = 0; 838 839 mii_down(&sc->sc_mii); 840 841 cas_reset_rx(sc); 842 cas_reset_tx(sc); 843 844 /* 845 * Release any queued transmit buffers. 846 */ 847 for (i = 0; i < CAS_NTXDESC; i++) { 848 sd = &sc->sc_txd[i]; 849 if (sd->sd_mbuf != NULL) { 850 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 851 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 852 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 853 m_freem(sd->sd_mbuf); 854 sd->sd_mbuf = NULL; 855 } 856 } 857 sc->sc_tx_cnt = sc->sc_tx_prod = sc->sc_tx_cons = 0; 858 859 if (disable) 860 cas_rxdrain(sc); 861 } 862 863 864 /* 865 * Reset the receiver 866 */ 867 int 868 cas_reset_rx(struct cas_softc *sc) 869 { 870 bus_space_tag_t t = sc->sc_memt; 871 bus_space_handle_t h = sc->sc_memh; 872 873 /* 874 * Resetting while DMA is in progress can cause a bus hang, so we 875 * disable DMA first. 876 */ 877 cas_disable_rx(sc); 878 bus_space_write_4(t, h, CAS_RX_CONFIG, 0); 879 /* Wait till it finishes */ 880 if (!cas_bitwait(sc, h, CAS_RX_CONFIG, 1, 0)) 881 aprint_error_dev(sc->sc_dev, "cannot disable rx dma\n"); 882 /* Wait 5ms extra. */ 883 delay(5000); 884 885 /* Finally, reset the ERX */ 886 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_RX); 887 /* Wait till it finishes */ 888 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX, 0)) { 889 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 890 return (1); 891 } 892 return (0); 893 } 894 895 896 /* 897 * Reset the transmitter 898 */ 899 int 900 cas_reset_tx(struct cas_softc *sc) 901 { 902 bus_space_tag_t t = sc->sc_memt; 903 bus_space_handle_t h = sc->sc_memh; 904 905 /* 906 * Resetting while DMA is in progress can cause a bus hang, so we 907 * disable DMA first. 908 */ 909 cas_disable_tx(sc); 910 bus_space_write_4(t, h, CAS_TX_CONFIG, 0); 911 /* Wait till it finishes */ 912 if (!cas_bitwait(sc, h, CAS_TX_CONFIG, 1, 0)) 913 aprint_error_dev(sc->sc_dev, "cannot disable tx dma\n"); 914 /* Wait 5ms extra. */ 915 delay(5000); 916 917 /* Finally, reset the ETX */ 918 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_TX); 919 /* Wait till it finishes */ 920 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_TX, 0)) { 921 aprint_error_dev(sc->sc_dev, "cannot reset transmitter\n"); 922 return (1); 923 } 924 return (0); 925 } 926 927 /* 928 * Disable receiver. 929 */ 930 int 931 cas_disable_rx(struct cas_softc *sc) 932 { 933 bus_space_tag_t t = sc->sc_memt; 934 bus_space_handle_t h = sc->sc_memh; 935 u_int32_t cfg; 936 937 /* Flip the enable bit */ 938 cfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 939 cfg &= ~CAS_MAC_RX_ENABLE; 940 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, cfg); 941 942 /* Wait for it to finish */ 943 return (cas_bitwait(sc, h, CAS_MAC_RX_CONFIG, CAS_MAC_RX_ENABLE, 0)); 944 } 945 946 /* 947 * Disable transmitter. 948 */ 949 int 950 cas_disable_tx(struct cas_softc *sc) 951 { 952 bus_space_tag_t t = sc->sc_memt; 953 bus_space_handle_t h = sc->sc_memh; 954 u_int32_t cfg; 955 956 /* Flip the enable bit */ 957 cfg = bus_space_read_4(t, h, CAS_MAC_TX_CONFIG); 958 cfg &= ~CAS_MAC_TX_ENABLE; 959 bus_space_write_4(t, h, CAS_MAC_TX_CONFIG, cfg); 960 961 /* Wait for it to finish */ 962 return (cas_bitwait(sc, h, CAS_MAC_TX_CONFIG, CAS_MAC_TX_ENABLE, 0)); 963 } 964 965 /* 966 * Initialize interface. 967 */ 968 int 969 cas_meminit(struct cas_softc *sc) 970 { 971 struct cas_rxsoft *rxs; 972 int i, error; 973 974 rxs = (void *)&error; 975 976 /* 977 * Initialize the transmit descriptor ring. 978 */ 979 for (i = 0; i < CAS_NTXDESC; i++) { 980 sc->sc_txdescs[i].cd_flags = 0; 981 sc->sc_txdescs[i].cd_addr = 0; 982 } 983 CAS_CDTXSYNC(sc, 0, CAS_NTXDESC, 984 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 985 986 /* 987 * Initialize the receive descriptor and receive job 988 * descriptor rings. 989 */ 990 for (i = 0; i < CAS_NRXDESC; i++) 991 CAS_INIT_RXDESC(sc, i, i); 992 sc->sc_rxdptr = 0; 993 sc->sc_rxptr = 0; 994 995 /* 996 * Initialize the receive completion ring. 997 */ 998 for (i = 0; i < CAS_NRXCOMP; i++) { 999 sc->sc_rxcomps[i].cc_word[0] = 0; 1000 sc->sc_rxcomps[i].cc_word[1] = 0; 1001 sc->sc_rxcomps[i].cc_word[2] = 0; 1002 sc->sc_rxcomps[i].cc_word[3] = CAS_DMA_WRITE(CAS_RC3_OWN); 1003 CAS_CDRXCSYNC(sc, i, 1004 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1005 } 1006 1007 return (0); 1008 } 1009 1010 int 1011 cas_ringsize(int sz) 1012 { 1013 switch (sz) { 1014 case 32: 1015 return CAS_RING_SZ_32; 1016 case 64: 1017 return CAS_RING_SZ_64; 1018 case 128: 1019 return CAS_RING_SZ_128; 1020 case 256: 1021 return CAS_RING_SZ_256; 1022 case 512: 1023 return CAS_RING_SZ_512; 1024 case 1024: 1025 return CAS_RING_SZ_1024; 1026 case 2048: 1027 return CAS_RING_SZ_2048; 1028 case 4096: 1029 return CAS_RING_SZ_4096; 1030 case 8192: 1031 return CAS_RING_SZ_8192; 1032 default: 1033 aprint_error("cas: invalid Receive Descriptor ring size %d\n", 1034 sz); 1035 return CAS_RING_SZ_32; 1036 } 1037 } 1038 1039 int 1040 cas_cringsize(int sz) 1041 { 1042 int i; 1043 1044 for (i = 0; i < 9; i++) 1045 if (sz == (128 << i)) 1046 return i; 1047 1048 aprint_error("cas: invalid completion ring size %d\n", sz); 1049 return 128; 1050 } 1051 1052 /* 1053 * Initialization of interface; set up initialization block 1054 * and transmit/receive descriptor rings. 1055 */ 1056 int 1057 cas_init(struct ifnet *ifp) 1058 { 1059 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 1060 bus_space_tag_t t = sc->sc_memt; 1061 bus_space_handle_t h = sc->sc_memh; 1062 int s; 1063 u_int max_frame_size; 1064 u_int32_t v; 1065 1066 s = splnet(); 1067 1068 DPRINTF(sc, ("%s: cas_init: calling stop\n", device_xname(sc->sc_dev))); 1069 /* 1070 * Initialization sequence. The numbered steps below correspond 1071 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1072 * Channel Engine manual (part of the PCIO manual). 1073 * See also the STP2002-STQ document from Sun Microsystems. 1074 */ 1075 1076 /* step 1 & 2. Reset the Ethernet Channel */ 1077 cas_stop(ifp, 0); 1078 cas_reset(sc); 1079 DPRINTF(sc, ("%s: cas_init: restarting\n", device_xname(sc->sc_dev))); 1080 1081 /* Re-initialize the MIF */ 1082 cas_mifinit(sc); 1083 1084 /* step 3. Setup data structures in host memory */ 1085 cas_meminit(sc); 1086 1087 /* step 4. TX MAC registers & counters */ 1088 cas_init_regs(sc); 1089 max_frame_size = ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN; 1090 v = (max_frame_size) | (0x2000 << 16) /* Burst size */; 1091 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1092 1093 /* step 5. RX MAC registers & counters */ 1094 cas_iff(sc); 1095 1096 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1097 KASSERT((CAS_CDTXADDR(sc, 0) & 0x1fff) == 0); 1098 bus_space_write_4(t, h, CAS_TX_RING_PTR_HI, 1099 (((uint64_t)CAS_CDTXADDR(sc,0)) >> 32)); 1100 bus_space_write_4(t, h, CAS_TX_RING_PTR_LO, CAS_CDTXADDR(sc, 0)); 1101 1102 KASSERT((CAS_CDRXADDR(sc, 0) & 0x1fff) == 0); 1103 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI, 1104 (((uint64_t)CAS_CDRXADDR(sc,0)) >> 32)); 1105 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO, CAS_CDRXADDR(sc, 0)); 1106 1107 KASSERT((CAS_CDRXCADDR(sc, 0) & 0x1fff) == 0); 1108 bus_space_write_4(t, h, CAS_RX_CRING_PTR_HI, 1109 (((uint64_t)CAS_CDRXCADDR(sc,0)) >> 32)); 1110 bus_space_write_4(t, h, CAS_RX_CRING_PTR_LO, CAS_CDRXCADDR(sc, 0)); 1111 1112 if (CAS_PLUS(sc)) { 1113 KASSERT((CAS_CDRXADDR2(sc, 0) & 0x1fff) == 0); 1114 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI2, 1115 (((uint64_t)CAS_CDRXADDR2(sc,0)) >> 32)); 1116 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO2, 1117 CAS_CDRXADDR2(sc, 0)); 1118 } 1119 1120 /* step 8. Global Configuration & Interrupt Mask */ 1121 cas_estintr(sc, CAS_INTR_REG); 1122 1123 /* step 9. ETX Configuration: use mostly default values */ 1124 1125 /* Enable DMA */ 1126 v = cas_ringsize(CAS_NTXDESC /*XXX*/) << 10; 1127 bus_space_write_4(t, h, CAS_TX_CONFIG, 1128 v|CAS_TX_CONFIG_TXDMA_EN|(1<<24)|(1<<29)); 1129 bus_space_write_4(t, h, CAS_TX_KICK, 0); 1130 1131 /* step 10. ERX Configuration */ 1132 1133 /* Encode Receive Descriptor ring size */ 1134 v = cas_ringsize(CAS_NRXDESC) << CAS_RX_CONFIG_RXDRNG_SZ_SHIFT; 1135 if (CAS_PLUS(sc)) 1136 v |= cas_ringsize(32) << CAS_RX_CONFIG_RXDRNG2_SZ_SHIFT; 1137 1138 /* Encode Receive Completion ring size */ 1139 v |= cas_cringsize(CAS_NRXCOMP) << CAS_RX_CONFIG_RXCRNG_SZ_SHIFT; 1140 1141 /* Enable DMA */ 1142 bus_space_write_4(t, h, CAS_RX_CONFIG, 1143 v|(2<<CAS_RX_CONFIG_FBOFF_SHFT)|CAS_RX_CONFIG_RXDMA_EN); 1144 1145 /* 1146 * The following value is for an OFF Threshold of about 3/4 full 1147 * and an ON Threshold of 1/4 full. 1148 */ 1149 bus_space_write_4(t, h, CAS_RX_PAUSE_THRESH, 1150 (3 * sc->sc_rxfifosize / 256) | 1151 ((sc->sc_rxfifosize / 256) << 12)); 1152 bus_space_write_4(t, h, CAS_RX_BLANKING, (6 << 12) | 6); 1153 1154 /* step 11. Configure Media */ 1155 mii_ifmedia_change(&sc->sc_mii); 1156 1157 /* step 12. RX_MAC Configuration Register */ 1158 v = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1159 v |= CAS_MAC_RX_ENABLE | CAS_MAC_RX_STRIP_CRC; 1160 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, v); 1161 1162 /* step 14. Issue Transmit Pending command */ 1163 1164 /* step 15. Give the receiver a swift kick */ 1165 bus_space_write_4(t, h, CAS_RX_KICK, CAS_NRXDESC-4); 1166 if (CAS_PLUS(sc)) 1167 bus_space_write_4(t, h, CAS_RX_KICK2, 4); 1168 1169 /* Start the one second timer. */ 1170 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 1171 1172 ifp->if_flags |= IFF_RUNNING; 1173 ifp->if_flags &= ~IFF_OACTIVE; 1174 ifp->if_timer = 0; 1175 splx(s); 1176 1177 return (0); 1178 } 1179 1180 void 1181 cas_init_regs(struct cas_softc *sc) 1182 { 1183 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1184 bus_space_tag_t t = sc->sc_memt; 1185 bus_space_handle_t h = sc->sc_memh; 1186 const u_char *laddr = CLLADDR(ifp->if_sadl); 1187 u_int32_t v, r; 1188 1189 /* These regs are not cleared on reset */ 1190 sc->sc_inited = 0; 1191 if (!sc->sc_inited) { 1192 /* Load recommended values */ 1193 bus_space_write_4(t, h, CAS_MAC_IPG0, 0x00); 1194 bus_space_write_4(t, h, CAS_MAC_IPG1, 0x08); 1195 bus_space_write_4(t, h, CAS_MAC_IPG2, 0x04); 1196 1197 bus_space_write_4(t, h, CAS_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1198 /* Max frame and max burst size */ 1199 v = ETHER_MAX_LEN | (0x2000 << 16) /* Burst size */; 1200 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1201 1202 bus_space_write_4(t, h, CAS_MAC_PREAMBLE_LEN, 0x07); 1203 bus_space_write_4(t, h, CAS_MAC_JAM_SIZE, 0x04); 1204 bus_space_write_4(t, h, CAS_MAC_ATTEMPT_LIMIT, 0x10); 1205 bus_space_write_4(t, h, CAS_MAC_CONTROL_TYPE, 0x8088); 1206 bus_space_write_4(t, h, CAS_MAC_RANDOM_SEED, 1207 ((laddr[5]<<8)|laddr[4])&0x3ff); 1208 1209 /* Secondary MAC addresses set to 0:0:0:0:0:0 */ 1210 for (r = CAS_MAC_ADDR3; r < CAS_MAC_ADDR42; r += 4) 1211 bus_space_write_4(t, h, r, 0); 1212 1213 /* MAC control addr set to 0:1:c2:0:1:80 */ 1214 bus_space_write_4(t, h, CAS_MAC_ADDR42, 0x0001); 1215 bus_space_write_4(t, h, CAS_MAC_ADDR43, 0xc200); 1216 bus_space_write_4(t, h, CAS_MAC_ADDR44, 0x0180); 1217 1218 /* MAC filter addr set to 0:0:0:0:0:0 */ 1219 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER0, 0); 1220 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER1, 0); 1221 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER2, 0); 1222 1223 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK1_2, 0); 1224 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK0, 0); 1225 1226 /* Hash table initialized to 0 */ 1227 for (r = CAS_MAC_HASH0; r <= CAS_MAC_HASH15; r += 4) 1228 bus_space_write_4(t, h, r, 0); 1229 1230 sc->sc_inited = 1; 1231 } 1232 1233 /* Counters need to be zeroed */ 1234 bus_space_write_4(t, h, CAS_MAC_NORM_COLL_CNT, 0); 1235 bus_space_write_4(t, h, CAS_MAC_FIRST_COLL_CNT, 0); 1236 bus_space_write_4(t, h, CAS_MAC_EXCESS_COLL_CNT, 0); 1237 bus_space_write_4(t, h, CAS_MAC_LATE_COLL_CNT, 0); 1238 bus_space_write_4(t, h, CAS_MAC_DEFER_TMR_CNT, 0); 1239 bus_space_write_4(t, h, CAS_MAC_PEAK_ATTEMPTS, 0); 1240 bus_space_write_4(t, h, CAS_MAC_RX_FRAME_COUNT, 0); 1241 bus_space_write_4(t, h, CAS_MAC_RX_LEN_ERR_CNT, 0); 1242 bus_space_write_4(t, h, CAS_MAC_RX_ALIGN_ERR, 0); 1243 bus_space_write_4(t, h, CAS_MAC_RX_CRC_ERR_CNT, 0); 1244 bus_space_write_4(t, h, CAS_MAC_RX_CODE_VIOL, 0); 1245 1246 /* Un-pause stuff */ 1247 bus_space_write_4(t, h, CAS_MAC_SEND_PAUSE_CMD, 0); 1248 1249 /* 1250 * Set the station address. 1251 */ 1252 bus_space_write_4(t, h, CAS_MAC_ADDR0, (laddr[4]<<8) | laddr[5]); 1253 bus_space_write_4(t, h, CAS_MAC_ADDR1, (laddr[2]<<8) | laddr[3]); 1254 bus_space_write_4(t, h, CAS_MAC_ADDR2, (laddr[0]<<8) | laddr[1]); 1255 } 1256 1257 /* 1258 * Receive interrupt. 1259 */ 1260 int 1261 cas_rint(struct cas_softc *sc) 1262 { 1263 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1264 bus_space_tag_t t = sc->sc_memt; 1265 bus_space_handle_t h = sc->sc_memh; 1266 struct cas_rxsoft *rxs; 1267 struct mbuf *m; 1268 u_int64_t word[4]; 1269 int len, off, idx; 1270 int i, skip; 1271 void *cp; 1272 1273 for (i = sc->sc_rxptr;; i = CAS_NEXTRX(i + skip)) { 1274 CAS_CDRXCSYNC(sc, i, 1275 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1276 1277 word[0] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[0]); 1278 word[1] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[1]); 1279 word[2] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[2]); 1280 word[3] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[3]); 1281 1282 /* Stop if the hardware still owns the descriptor. */ 1283 if ((word[0] & CAS_RC0_TYPE) == 0 || word[3] & CAS_RC3_OWN) 1284 break; 1285 1286 len = CAS_RC1_HDR_LEN(word[1]); 1287 if (len > 0) { 1288 off = CAS_RC1_HDR_OFF(word[1]); 1289 idx = CAS_RC1_HDR_IDX(word[1]); 1290 rxs = &sc->sc_rxsoft[idx]; 1291 1292 DPRINTF(sc, ("hdr at idx %d, off %d, len %d\n", 1293 idx, off, len)); 1294 1295 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1296 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1297 1298 cp = rxs->rxs_kva + off * 256 + ETHER_ALIGN; 1299 m = m_devget(cp, len, 0, ifp, NULL); 1300 1301 if (word[0] & CAS_RC0_RELEASE_HDR) 1302 cas_add_rxbuf(sc, idx); 1303 1304 if (m != NULL) { 1305 1306 /* 1307 * Pass this up to any BPF listeners, but only 1308 * pass it up the stack if its for us. 1309 */ 1310 bpf_mtap(ifp, m); 1311 1312 ifp->if_ipackets++; 1313 m->m_pkthdr.csum_flags = 0; 1314 (*ifp->if_input)(ifp, m); 1315 } else 1316 ifp->if_ierrors++; 1317 } 1318 1319 len = CAS_RC0_DATA_LEN(word[0]); 1320 if (len > 0) { 1321 off = CAS_RC0_DATA_OFF(word[0]); 1322 idx = CAS_RC0_DATA_IDX(word[0]); 1323 rxs = &sc->sc_rxsoft[idx]; 1324 1325 DPRINTF(sc, ("data at idx %d, off %d, len %d\n", 1326 idx, off, len)); 1327 1328 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1329 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1330 1331 /* XXX We should not be copying the packet here. */ 1332 cp = rxs->rxs_kva + off + ETHER_ALIGN; 1333 m = m_devget(cp, len, 0, ifp, NULL); 1334 1335 if (word[0] & CAS_RC0_RELEASE_DATA) 1336 cas_add_rxbuf(sc, idx); 1337 1338 if (m != NULL) { 1339 /* 1340 * Pass this up to any BPF listeners, but only 1341 * pass it up the stack if its for us. 1342 */ 1343 bpf_mtap(ifp, m); 1344 1345 ifp->if_ipackets++; 1346 m->m_pkthdr.csum_flags = 0; 1347 (*ifp->if_input)(ifp, m); 1348 } else 1349 ifp->if_ierrors++; 1350 } 1351 1352 if (word[0] & CAS_RC0_SPLIT) 1353 aprint_error_dev(sc->sc_dev, "split packet\n"); 1354 1355 skip = CAS_RC0_SKIP(word[0]); 1356 } 1357 1358 while (sc->sc_rxptr != i) { 1359 sc->sc_rxcomps[sc->sc_rxptr].cc_word[0] = 0; 1360 sc->sc_rxcomps[sc->sc_rxptr].cc_word[1] = 0; 1361 sc->sc_rxcomps[sc->sc_rxptr].cc_word[2] = 0; 1362 sc->sc_rxcomps[sc->sc_rxptr].cc_word[3] = 1363 CAS_DMA_WRITE(CAS_RC3_OWN); 1364 CAS_CDRXCSYNC(sc, sc->sc_rxptr, 1365 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1366 1367 sc->sc_rxptr = CAS_NEXTRX(sc->sc_rxptr); 1368 } 1369 1370 bus_space_write_4(t, h, CAS_RX_COMP_TAIL, sc->sc_rxptr); 1371 1372 DPRINTF(sc, ("cas_rint: done sc->rxptr %d, complete %d\n", 1373 sc->sc_rxptr, bus_space_read_4(t, h, CAS_RX_COMPLETION))); 1374 1375 return (1); 1376 } 1377 1378 /* 1379 * cas_add_rxbuf: 1380 * 1381 * Add a receive buffer to the indicated descriptor. 1382 */ 1383 int 1384 cas_add_rxbuf(struct cas_softc *sc, int idx) 1385 { 1386 bus_space_tag_t t = sc->sc_memt; 1387 bus_space_handle_t h = sc->sc_memh; 1388 1389 CAS_INIT_RXDESC(sc, sc->sc_rxdptr, idx); 1390 1391 if ((sc->sc_rxdptr % 4) == 0) 1392 bus_space_write_4(t, h, CAS_RX_KICK, sc->sc_rxdptr); 1393 1394 if (++sc->sc_rxdptr == CAS_NRXDESC) 1395 sc->sc_rxdptr = 0; 1396 1397 return (0); 1398 } 1399 1400 int 1401 cas_eint(struct cas_softc *sc, u_int status) 1402 { 1403 char bits[128]; 1404 if ((status & CAS_INTR_MIF) != 0) { 1405 DPRINTF(sc, ("%s: link status changed\n", 1406 device_xname(sc->sc_dev))); 1407 return (1); 1408 } 1409 1410 snprintb(bits, sizeof(bits), CAS_INTR_BITS, status); 1411 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 1412 return (1); 1413 } 1414 1415 int 1416 cas_pint(struct cas_softc *sc) 1417 { 1418 bus_space_tag_t t = sc->sc_memt; 1419 bus_space_handle_t seb = sc->sc_memh; 1420 u_int32_t status; 1421 1422 status = bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1423 status |= bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1424 #ifdef CAS_DEBUG 1425 if (status) 1426 printf("%s: link status changed\n", device_xname(sc->sc_dev)); 1427 #endif 1428 return (1); 1429 } 1430 1431 int 1432 cas_intr(void *v) 1433 { 1434 struct cas_softc *sc = (struct cas_softc *)v; 1435 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1436 bus_space_tag_t t = sc->sc_memt; 1437 bus_space_handle_t seb = sc->sc_memh; 1438 u_int32_t status; 1439 int r = 0; 1440 #ifdef CAS_DEBUG 1441 char bits[128]; 1442 #endif 1443 1444 sc->sc_ev_intr.ev_count++; 1445 1446 status = bus_space_read_4(t, seb, CAS_STATUS); 1447 #ifdef CAS_DEBUG 1448 snprintb(bits, sizeof(bits), CAS_INTR_BITS, status); 1449 #endif 1450 DPRINTF(sc, ("%s: cas_intr: cplt %x status %s\n", 1451 device_xname(sc->sc_dev), (status>>19), bits)); 1452 1453 if ((status & CAS_INTR_PCS) != 0) 1454 r |= cas_pint(sc); 1455 1456 if ((status & (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR | 1457 CAS_INTR_RX_COMP_FULL | CAS_INTR_BERR)) != 0) 1458 r |= cas_eint(sc, status); 1459 1460 if ((status & (CAS_INTR_TX_EMPTY | CAS_INTR_TX_INTME)) != 0) 1461 r |= cas_tint(sc, status); 1462 1463 if ((status & (CAS_INTR_RX_DONE | CAS_INTR_RX_NOBUF)) != 0) 1464 r |= cas_rint(sc); 1465 1466 /* We should eventually do more than just print out error stats. */ 1467 if (status & CAS_INTR_TX_MAC) { 1468 int txstat = bus_space_read_4(t, seb, CAS_MAC_TX_STATUS); 1469 #ifdef CAS_DEBUG 1470 if (txstat & ~CAS_MAC_TX_XMIT_DONE) 1471 printf("%s: MAC tx fault, status %x\n", 1472 device_xname(sc->sc_dev), txstat); 1473 #endif 1474 if (txstat & (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_PKT_TOO_LONG)) 1475 cas_init(ifp); 1476 } 1477 if (status & CAS_INTR_RX_MAC) { 1478 int rxstat = bus_space_read_4(t, seb, CAS_MAC_RX_STATUS); 1479 #ifdef CAS_DEBUG 1480 if (rxstat & ~CAS_MAC_RX_DONE) 1481 printf("%s: MAC rx fault, status %x\n", 1482 device_xname(sc->sc_dev), rxstat); 1483 #endif 1484 /* 1485 * On some chip revisions CAS_MAC_RX_OVERFLOW happen often 1486 * due to a silicon bug so handle them silently. 1487 */ 1488 if (rxstat & CAS_MAC_RX_OVERFLOW) { 1489 ifp->if_ierrors++; 1490 cas_init(ifp); 1491 } 1492 #ifdef CAS_DEBUG 1493 else if (rxstat & ~(CAS_MAC_RX_DONE | CAS_MAC_RX_FRAME_CNT)) 1494 printf("%s: MAC rx fault, status %x\n", 1495 device_xname(sc->sc_dev), rxstat); 1496 #endif 1497 } 1498 #if NRND > 0 1499 rnd_add_uint32(&sc->rnd_source, status); 1500 #endif 1501 return (r); 1502 } 1503 1504 1505 void 1506 cas_watchdog(struct ifnet *ifp) 1507 { 1508 struct cas_softc *sc = ifp->if_softc; 1509 1510 DPRINTF(sc, ("cas_watchdog: CAS_RX_CONFIG %x CAS_MAC_RX_STATUS %x " 1511 "CAS_MAC_RX_CONFIG %x\n", 1512 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_RX_CONFIG), 1513 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_STATUS), 1514 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_CONFIG))); 1515 1516 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1517 ++ifp->if_oerrors; 1518 1519 /* Try to get more packets going. */ 1520 cas_init(ifp); 1521 } 1522 1523 /* 1524 * Initialize the MII Management Interface 1525 */ 1526 void 1527 cas_mifinit(struct cas_softc *sc) 1528 { 1529 bus_space_tag_t t = sc->sc_memt; 1530 bus_space_handle_t mif = sc->sc_memh; 1531 1532 /* Configure the MIF in frame mode */ 1533 sc->sc_mif_config = bus_space_read_4(t, mif, CAS_MIF_CONFIG); 1534 sc->sc_mif_config &= ~CAS_MIF_CONFIG_BB_ENA; 1535 bus_space_write_4(t, mif, CAS_MIF_CONFIG, sc->sc_mif_config); 1536 } 1537 1538 /* 1539 * MII interface 1540 * 1541 * The Cassini MII interface supports at least three different operating modes: 1542 * 1543 * Bitbang mode is implemented using data, clock and output enable registers. 1544 * 1545 * Frame mode is implemented by loading a complete frame into the frame 1546 * register and polling the valid bit for completion. 1547 * 1548 * Polling mode uses the frame register but completion is indicated by 1549 * an interrupt. 1550 * 1551 */ 1552 int 1553 cas_mii_readreg(device_t self, int phy, int reg) 1554 { 1555 struct cas_softc *sc = device_private(self); 1556 bus_space_tag_t t = sc->sc_memt; 1557 bus_space_handle_t mif = sc->sc_memh; 1558 int n; 1559 u_int32_t v; 1560 1561 #ifdef CAS_DEBUG 1562 if (sc->sc_debug) 1563 printf("cas_mii_readreg: phy %d reg %d\n", phy, reg); 1564 #endif 1565 1566 /* Construct the frame command */ 1567 v = (reg << CAS_MIF_REG_SHIFT) | (phy << CAS_MIF_PHY_SHIFT) | 1568 CAS_MIF_FRAME_READ; 1569 1570 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1571 for (n = 0; n < 100; n++) { 1572 DELAY(1); 1573 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1574 if (v & CAS_MIF_FRAME_TA0) 1575 return (v & CAS_MIF_FRAME_DATA); 1576 } 1577 1578 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 1579 return (0); 1580 } 1581 1582 void 1583 cas_mii_writereg(device_t self, int phy, int reg, int val) 1584 { 1585 struct cas_softc *sc = device_private(self); 1586 bus_space_tag_t t = sc->sc_memt; 1587 bus_space_handle_t mif = sc->sc_memh; 1588 int n; 1589 u_int32_t v; 1590 1591 #ifdef CAS_DEBUG 1592 if (sc->sc_debug) 1593 printf("cas_mii_writereg: phy %d reg %d val %x\n", 1594 phy, reg, val); 1595 #endif 1596 1597 /* Construct the frame command */ 1598 v = CAS_MIF_FRAME_WRITE | 1599 (phy << CAS_MIF_PHY_SHIFT) | 1600 (reg << CAS_MIF_REG_SHIFT) | 1601 (val & CAS_MIF_FRAME_DATA); 1602 1603 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1604 for (n = 0; n < 100; n++) { 1605 DELAY(1); 1606 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1607 if (v & CAS_MIF_FRAME_TA0) 1608 return; 1609 } 1610 1611 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 1612 } 1613 1614 void 1615 cas_mii_statchg(device_t self) 1616 { 1617 struct cas_softc *sc = device_private(self); 1618 #ifdef CAS_DEBUG 1619 int instance = IFM_INST(sc->sc_media.ifm_cur->ifm_media); 1620 #endif 1621 bus_space_tag_t t = sc->sc_memt; 1622 bus_space_handle_t mac = sc->sc_memh; 1623 u_int32_t v; 1624 1625 #ifdef CAS_DEBUG 1626 if (sc->sc_debug) 1627 printf("cas_mii_statchg: status change: phy = %d\n", 1628 sc->sc_phys[instance]); 1629 #endif 1630 1631 /* Set tx full duplex options */ 1632 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, 0); 1633 delay(10000); /* reg must be cleared and delay before changing. */ 1634 v = CAS_MAC_TX_ENA_IPG0|CAS_MAC_TX_NGU|CAS_MAC_TX_NGU_LIMIT| 1635 CAS_MAC_TX_ENABLE; 1636 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1637 v |= CAS_MAC_TX_IGN_CARRIER|CAS_MAC_TX_IGN_COLLIS; 1638 } 1639 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, v); 1640 1641 /* XIF Configuration */ 1642 v = CAS_MAC_XIF_TX_MII_ENA; 1643 v |= CAS_MAC_XIF_LINK_LED; 1644 1645 /* MII needs echo disable if half duplex. */ 1646 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1647 /* turn on full duplex LED */ 1648 v |= CAS_MAC_XIF_FDPLX_LED; 1649 else 1650 /* half duplex -- disable echo */ 1651 v |= CAS_MAC_XIF_ECHO_DISABL; 1652 1653 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 1654 case IFM_1000_T: /* Gigabit using GMII interface */ 1655 case IFM_1000_SX: 1656 v |= CAS_MAC_XIF_GMII_MODE; 1657 break; 1658 default: 1659 v &= ~CAS_MAC_XIF_GMII_MODE; 1660 } 1661 bus_space_write_4(t, mac, CAS_MAC_XIF_CONFIG, v); 1662 } 1663 1664 int 1665 cas_pcs_readreg(device_t self, int phy, int reg) 1666 { 1667 struct cas_softc *sc = device_private(self); 1668 bus_space_tag_t t = sc->sc_memt; 1669 bus_space_handle_t pcs = sc->sc_memh; 1670 1671 #ifdef CAS_DEBUG 1672 if (sc->sc_debug) 1673 printf("cas_pcs_readreg: phy %d reg %d\n", phy, reg); 1674 #endif 1675 1676 if (phy != CAS_PHYAD_EXTERNAL) 1677 return (0); 1678 1679 switch (reg) { 1680 case MII_BMCR: 1681 reg = CAS_MII_CONTROL; 1682 break; 1683 case MII_BMSR: 1684 reg = CAS_MII_STATUS; 1685 break; 1686 case MII_ANAR: 1687 reg = CAS_MII_ANAR; 1688 break; 1689 case MII_ANLPAR: 1690 reg = CAS_MII_ANLPAR; 1691 break; 1692 case MII_EXTSR: 1693 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 1694 default: 1695 return (0); 1696 } 1697 1698 return bus_space_read_4(t, pcs, reg); 1699 } 1700 1701 void 1702 cas_pcs_writereg(device_t self, int phy, int reg, int val) 1703 { 1704 struct cas_softc *sc = device_private(self); 1705 bus_space_tag_t t = sc->sc_memt; 1706 bus_space_handle_t pcs = sc->sc_memh; 1707 int reset = 0; 1708 1709 #ifdef CAS_DEBUG 1710 if (sc->sc_debug) 1711 printf("cas_pcs_writereg: phy %d reg %d val %x\n", 1712 phy, reg, val); 1713 #endif 1714 1715 if (phy != CAS_PHYAD_EXTERNAL) 1716 return; 1717 1718 if (reg == MII_ANAR) 1719 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 0); 1720 1721 switch (reg) { 1722 case MII_BMCR: 1723 reset = (val & CAS_MII_CONTROL_RESET); 1724 reg = CAS_MII_CONTROL; 1725 break; 1726 case MII_BMSR: 1727 reg = CAS_MII_STATUS; 1728 break; 1729 case MII_ANAR: 1730 reg = CAS_MII_ANAR; 1731 break; 1732 case MII_ANLPAR: 1733 reg = CAS_MII_ANLPAR; 1734 break; 1735 default: 1736 return; 1737 } 1738 1739 bus_space_write_4(t, pcs, reg, val); 1740 1741 if (reset) 1742 cas_bitwait(sc, pcs, CAS_MII_CONTROL, CAS_MII_CONTROL_RESET, 0); 1743 1744 if (reg == CAS_MII_ANAR || reset) 1745 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 1746 CAS_MII_CONFIG_ENABLE); 1747 } 1748 1749 int 1750 cas_mediachange(struct ifnet *ifp) 1751 { 1752 struct cas_softc *sc = ifp->if_softc; 1753 struct mii_data *mii = &sc->sc_mii; 1754 1755 if (mii->mii_instance) { 1756 struct mii_softc *miisc; 1757 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1758 mii_phy_reset(miisc); 1759 } 1760 1761 return (mii_mediachg(&sc->sc_mii)); 1762 } 1763 1764 void 1765 cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1766 { 1767 struct cas_softc *sc = ifp->if_softc; 1768 1769 mii_pollstat(&sc->sc_mii); 1770 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1771 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1772 } 1773 1774 /* 1775 * Process an ioctl request. 1776 */ 1777 int 1778 cas_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1779 { 1780 struct cas_softc *sc = ifp->if_softc; 1781 int s, error = 0; 1782 1783 s = splnet(); 1784 1785 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1786 error = 0; 1787 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1788 ; 1789 else if (ifp->if_flags & IFF_RUNNING) { 1790 /* 1791 * Multicast list has changed; set the hardware filter 1792 * accordingly. 1793 */ 1794 cas_iff(sc); 1795 } 1796 } 1797 1798 splx(s); 1799 return (error); 1800 } 1801 1802 static bool 1803 cas_suspend(device_t self, const pmf_qual_t *qual) 1804 { 1805 struct cas_softc *sc = device_private(self); 1806 bus_space_tag_t t = sc->sc_memt; 1807 bus_space_handle_t h = sc->sc_memh; 1808 1809 bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0); 1810 if (sc->sc_ih != NULL) { 1811 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 1812 sc->sc_ih = NULL; 1813 } 1814 1815 return true; 1816 } 1817 1818 static bool 1819 cas_resume(device_t self, const pmf_qual_t *qual) 1820 { 1821 struct cas_softc *sc = device_private(self); 1822 1823 return cas_estintr(sc, CAS_INTR_PCI | CAS_INTR_REG); 1824 } 1825 1826 static bool 1827 cas_estintr(struct cas_softc *sc, int what) 1828 { 1829 bus_space_tag_t t = sc->sc_memt; 1830 bus_space_handle_t h = sc->sc_memh; 1831 const char *intrstr = NULL; 1832 1833 /* PCI interrupts */ 1834 if (what & CAS_INTR_PCI) { 1835 intrstr = pci_intr_string(sc->sc_pc, sc->sc_handle); 1836 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->sc_handle, 1837 IPL_NET, cas_intr, sc); 1838 if (sc->sc_ih == NULL) { 1839 aprint_error_dev(sc->sc_dev, 1840 "unable to establish interrupt"); 1841 if (intrstr != NULL) 1842 aprint_error(" at %s", intrstr); 1843 aprint_error("\n"); 1844 return false; 1845 } 1846 1847 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1848 } 1849 1850 /* Interrupt register */ 1851 if (what & CAS_INTR_REG) { 1852 bus_space_write_4(t, h, CAS_INTMASK, 1853 ~(CAS_INTR_TX_INTME|CAS_INTR_TX_EMPTY| 1854 CAS_INTR_TX_TAG_ERR| 1855 CAS_INTR_RX_DONE|CAS_INTR_RX_NOBUF| 1856 CAS_INTR_RX_TAG_ERR| 1857 CAS_INTR_RX_COMP_FULL|CAS_INTR_PCS| 1858 CAS_INTR_MAC_CONTROL|CAS_INTR_MIF| 1859 CAS_INTR_BERR)); 1860 bus_space_write_4(t, h, CAS_MAC_RX_MASK, 1861 CAS_MAC_RX_DONE|CAS_MAC_RX_FRAME_CNT); 1862 bus_space_write_4(t, h, CAS_MAC_TX_MASK, CAS_MAC_TX_XMIT_DONE); 1863 bus_space_write_4(t, h, CAS_MAC_CONTROL_MASK, 0); /* XXXX */ 1864 } 1865 return true; 1866 } 1867 1868 bool 1869 cas_shutdown(device_t self, int howto) 1870 { 1871 struct cas_softc *sc = device_private(self); 1872 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1873 1874 cas_stop(ifp, 1); 1875 1876 return true; 1877 } 1878 1879 void 1880 cas_iff(struct cas_softc *sc) 1881 { 1882 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1883 struct ethercom *ec = &sc->sc_ethercom; 1884 struct ether_multi *enm; 1885 struct ether_multistep step; 1886 bus_space_tag_t t = sc->sc_memt; 1887 bus_space_handle_t h = sc->sc_memh; 1888 u_int32_t crc, hash[16], rxcfg; 1889 int i; 1890 1891 rxcfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1892 rxcfg &= ~(CAS_MAC_RX_HASH_FILTER | CAS_MAC_RX_PROMISCUOUS | 1893 CAS_MAC_RX_PROMISC_GRP); 1894 ifp->if_flags &= ~IFF_ALLMULTI; 1895 1896 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 1897 ifp->if_flags |= IFF_ALLMULTI; 1898 if (ifp->if_flags & IFF_PROMISC) 1899 rxcfg |= CAS_MAC_RX_PROMISCUOUS; 1900 else 1901 rxcfg |= CAS_MAC_RX_PROMISC_GRP; 1902 } else { 1903 /* 1904 * Set up multicast address filter by passing all multicast 1905 * addresses through a crc generator, and then using the 1906 * high order 8 bits as an index into the 256 bit logical 1907 * address filter. The high order 4 bits selects the word, 1908 * while the other 4 bits select the bit within the word 1909 * (where bit 0 is the MSB). 1910 */ 1911 1912 rxcfg |= CAS_MAC_RX_HASH_FILTER; 1913 1914 /* Clear hash table */ 1915 for (i = 0; i < 16; i++) 1916 hash[i] = 0; 1917 1918 ETHER_FIRST_MULTI(step, ec, enm); 1919 while (enm != NULL) { 1920 crc = ether_crc32_le(enm->enm_addrlo, 1921 ETHER_ADDR_LEN); 1922 1923 /* Just want the 8 most significant bits. */ 1924 crc >>= 24; 1925 1926 /* Set the corresponding bit in the filter. */ 1927 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 1928 1929 ETHER_NEXT_MULTI(step, enm); 1930 } 1931 1932 /* Now load the hash table into the chip (if we are using it) */ 1933 for (i = 0; i < 16; i++) { 1934 bus_space_write_4(t, h, 1935 CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0), 1936 hash[i]); 1937 } 1938 } 1939 1940 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, rxcfg); 1941 } 1942 1943 int 1944 cas_encap(struct cas_softc *sc, struct mbuf *mhead, u_int32_t *bixp) 1945 { 1946 u_int64_t flags; 1947 u_int32_t cur, frag, i; 1948 bus_dmamap_t map; 1949 1950 cur = frag = *bixp; 1951 map = sc->sc_txd[cur].sd_map; 1952 1953 if (bus_dmamap_load_mbuf(sc->sc_dmatag, map, mhead, 1954 BUS_DMA_NOWAIT) != 0) { 1955 return (ENOBUFS); 1956 } 1957 1958 if ((sc->sc_tx_cnt + map->dm_nsegs) > (CAS_NTXDESC - 2)) { 1959 bus_dmamap_unload(sc->sc_dmatag, map); 1960 return (ENOBUFS); 1961 } 1962 1963 bus_dmamap_sync(sc->sc_dmatag, map, 0, map->dm_mapsize, 1964 BUS_DMASYNC_PREWRITE); 1965 1966 for (i = 0; i < map->dm_nsegs; i++) { 1967 sc->sc_txdescs[frag].cd_addr = 1968 CAS_DMA_WRITE(map->dm_segs[i].ds_addr); 1969 flags = (map->dm_segs[i].ds_len & CAS_TD_BUFSIZE) | 1970 (i == 0 ? CAS_TD_START_OF_PACKET : 0) | 1971 ((i == (map->dm_nsegs - 1)) ? CAS_TD_END_OF_PACKET : 0); 1972 sc->sc_txdescs[frag].cd_flags = CAS_DMA_WRITE(flags); 1973 bus_dmamap_sync(sc->sc_dmatag, sc->sc_cddmamap, 1974 CAS_CDTXOFF(frag), sizeof(struct cas_desc), 1975 BUS_DMASYNC_PREWRITE); 1976 cur = frag; 1977 if (++frag == CAS_NTXDESC) 1978 frag = 0; 1979 } 1980 1981 sc->sc_tx_cnt += map->dm_nsegs; 1982 sc->sc_txd[*bixp].sd_map = sc->sc_txd[cur].sd_map; 1983 sc->sc_txd[cur].sd_map = map; 1984 sc->sc_txd[cur].sd_mbuf = mhead; 1985 1986 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_TX_KICK, frag); 1987 1988 *bixp = frag; 1989 1990 /* sync descriptors */ 1991 1992 return (0); 1993 } 1994 1995 /* 1996 * Transmit interrupt. 1997 */ 1998 int 1999 cas_tint(struct cas_softc *sc, u_int32_t status) 2000 { 2001 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2002 struct cas_sxd *sd; 2003 u_int32_t cons, comp; 2004 2005 comp = bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_TX_COMPLETION); 2006 cons = sc->sc_tx_cons; 2007 while (cons != comp) { 2008 sd = &sc->sc_txd[cons]; 2009 if (sd->sd_mbuf != NULL) { 2010 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 2011 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2012 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 2013 m_freem(sd->sd_mbuf); 2014 sd->sd_mbuf = NULL; 2015 ifp->if_opackets++; 2016 } 2017 sc->sc_tx_cnt--; 2018 if (++cons == CAS_NTXDESC) 2019 cons = 0; 2020 } 2021 sc->sc_tx_cons = cons; 2022 2023 if (sc->sc_tx_cnt < CAS_NTXDESC - 2) 2024 ifp->if_flags &= ~IFF_OACTIVE; 2025 if (sc->sc_tx_cnt == 0) 2026 ifp->if_timer = 0; 2027 2028 cas_start(ifp); 2029 2030 return (1); 2031 } 2032 2033 void 2034 cas_start(struct ifnet *ifp) 2035 { 2036 struct cas_softc *sc = ifp->if_softc; 2037 struct mbuf *m; 2038 u_int32_t bix; 2039 2040 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2041 return; 2042 2043 bix = sc->sc_tx_prod; 2044 while (sc->sc_txd[bix].sd_mbuf == NULL) { 2045 IFQ_POLL(&ifp->if_snd, m); 2046 if (m == NULL) 2047 break; 2048 2049 /* 2050 * If BPF is listening on this interface, let it see the 2051 * packet before we commit it to the wire. 2052 */ 2053 bpf_mtap(ifp, m); 2054 2055 /* 2056 * Encapsulate this packet and start it going... 2057 * or fail... 2058 */ 2059 if (cas_encap(sc, m, &bix)) { 2060 ifp->if_flags |= IFF_OACTIVE; 2061 break; 2062 } 2063 2064 IFQ_DEQUEUE(&ifp->if_snd, m); 2065 ifp->if_timer = 5; 2066 } 2067 2068 sc->sc_tx_prod = bix; 2069 } 2070 2071 MODULE(MODULE_CLASS_DRIVER, if_cas, NULL); 2072 2073 #ifdef _MODULE 2074 #include "ioconf.c" 2075 #endif 2076 2077 static int 2078 if_cas_modcmd(modcmd_t cmd, void *opaque) 2079 { 2080 int error = 0; 2081 2082 switch (cmd) { 2083 case MODULE_CMD_INIT: 2084 #ifdef _MODULE 2085 error = config_init_component(cfdriver_ioconf_cas, 2086 cfattach_ioconf_cas, cfdata_ioconf_cas); 2087 #endif 2088 return error; 2089 case MODULE_CMD_FINI: 2090 #ifdef _MODULE 2091 error = config_fini_component(cfdriver_ioconf_cas, 2092 cfattach_ioconf_cas, cfdata_ioconf_cas); 2093 #endif 2094 return error; 2095 default: 2096 return ENOTTY; 2097 } 2098 } 2099